JP4240435B2 - Image display device and device provided with the image display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to an image display apparatus using an LCD (Liquid Crystal Device) or the like that displays an image by driving display pixels arranged in a matrix on a screen by image data sequentially read from a VRAM, and relates to a CRT (Cathode Ray Tube). The present invention relates to a graphic display device that displays image information (image data) such as characters and patterns on a display device using a display device, etc.
[0002]
[Prior art]
  In an image display device that drives display pixels arranged in a matrix on a screen at a binary level (performs on / off or lighting / non-lighting operation), it can be roughly classified as a method for performing pseudo gradation display. There are an area (space) gradation method and a frame rate control (FRC) method. In the former, on / off of pixels included in a unit space of a screen in which display pixels are arranged in a matrix is controlled based on gradation data, and gradation is expressed by changing the average brightness of the space. However, there is a problem that the display resolution is lowered. The latter controls the on / off of the target pixel (or pixel group included in the target area) for each image frame displayed one after another based on the gradation data, and average brightness within a predetermined time (number of frames). The gradation is expressed by changing the brightness, but flicker called so-called flicker occurs and deteriorates the display quality particularly when pixels with intermediate gradation are displayed with the same gradation in a large area. Have the problem.
[0003]
  In order to solve such problems, an invention disclosed in Japanese Patent No. 2784005 (Japanese Patent Laid-Open No. 1-222597) has been proposed. According to the present invention, one screen of the display device is divided into a plurality of sections, each section has N pixels, and the number of pixels N is the same as the number of steps capable of gradation display, and the area ( When the (space) gradation method is used and the gradation display of the section is set to gradation M, a plurality of different phases with different phases prepared corresponding to gradation M are provided over a plurality of frames.Lighting pattern (hereinafter referred to as on / off pattern)Are sequentially given to perform gradation display by FRC control. Therefore, even in the case where the gradation M does not change, in each section for each frameOn / off patternThus, flicker can be eliminated without causing a decrease in display resolution.
[0004]
[Problems to be solved by the invention]
  However, in the conventional example described above, the sameON / OFFAs a countermeasure against flicker that occurs when FRC control is performed with a pattern,ON / OFFAlthough it is stated that the pattern is controlled on a frame-by-frame basis, the same gradation block within one frameON / OFFThere is no mention about the point of controlling the pattern, and the moving phenomenon that deteriorates the image quality like flicker (for example, all the blocks of the same gradation in one frame are the same)ON / OFFWhen a pattern is displayed and it covers a wide area, it looks like the pattern moves in a certain direction when visually observing this area, so this is usually called "moving phenomenon"). is there.
[0005]
  On the other hand, in the conventional method proposed as a countermeasure for such a moving phenomenon, the gradation data read for each dot unit from the storage location of the displayed gradation data is compared with the random number data generated by the random number generator. However, some display devices are driven based on the comparison result. According to this method, the gradation data is converted into binary values based on the random number data, so that the moving phenomenon can be prevented.
  However, since this method uses random numbers, if attention is paid to a specific pixel, for example, the FRC control is not always completed every three frames. Although it seems to be effective in suppressing the moving phenomenon in a wide display area, there is a high possibility that a problem of gradation shift and flicker will occur in a narrow range of several dots. Moreover, the occurrence of flicker and moving phenomenon is affected by the liquid crystal material used in the liquid crystal display element, the cell configuration, the type of polarizing film, the display color, the driving conditions, etc., and in many cases, optimization is necessary. However, adjustment for this is difficult. According to the prior art, it is difficult to solve this problem even if the structure of the random number generator is changed.
[0006]
  The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to suppress flicker and moving phenomenon without deterioration in image quality with a simple configuration, thereby enabling pseudo gradation display. Providing an image display device for improving the quality of an image and a device having the image display device in an operation unit (for example, a device having an image display device on an input operation panel and allowing a user to perform an input operation according to a display screen) There is to do.
[0007]
[Means for Solving the Problems]
  According to the first aspect of the present invention, an image frame including pixels arranged in a matrix is divided into blocks of a predetermined size, and driving of each pixel included in the block is turned on / off over a predetermined number of image frames. In an image display device which enables pseudo gradation display for each block by controlling, a register storing a basic on / off pattern for each gradation, and pixels in the block from the basic on / off pattern Generating means for generating a plurality of different on / off patterns representing the same gradation as the on / off patterns for driving the same, and using the plurality of different on / off patterns, the same spatially adjacent The gradation blocks are driven with different on / off patterns, and the same arrangement of blocks over the predetermined number of image frames is also different on / off. An image display device being characterized in that so as to drive the turn.
  According to a second aspect of the present invention, in the image display device according to the first aspect, the plurality of different on / off patterns are:The basic on / off patternIt is generated by performing a rotation process.
  According to a third aspect of the present invention, in the image display device according to the second aspect, the rotation process is generated by counting a timing signal of a display operation from a basic on / off pattern stored in a register. According to the present invention, the selection is performed by the selector selecting on / off pattern lighting data in accordance with the address, the intra-block image address, and the frame period.
  According to a fourth aspect of the present invention, in the image display device according to any one of the first to third aspects, the different on / off patterns for displaying the same gradation are displayed on each block by a display operation over a predetermined number of image frames. It is characterized in that the pattern is arranged so that the number of times of lighting of each pixel is made uniform.
  According to a fifth aspect of the present invention, in the image display device according to any one of the first to fourth aspects, the pixel is a pixel of each color constituting a color image, and the on / off pattern used for each color is the same frame and the same. It is characterized by not making the same pattern in a block.
  According to a sixth aspect of the present invention, in the image display device according to the fifth aspect, when the basic on / off pattern is rotated, the phase of the on / off pattern displayed in one cycle of each color is different. By setting in this way, the on / off pattern used for each color is prevented from being the same pattern in the same frame and the same block.
  A seventh aspect of the invention is an apparatus including the image display device according to the first to sixth aspects.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
  In the present invention, an image frame is configured by pixels arranged in a matrix and driven at a binary level (on / off or lighting / non-lighting operation), and the pixels arranged on the frame have a predetermined size. By dividing into blocks, and controlling the driving of the pixels in the block, the intermediate gradation can be expressed in units of blocks. In addition, during pixel drive control, even if the adjacent blocks have the same gradation,On / off patternShould not be the same. For this reason, it becomes the basis of each gradation that is stored in advance in a register corresponding to a plurality of gradation displays.On / off patternThe gradation display is temporally and spatially uniformed by an operation of rotating the image to change the pattern for each block and rotating between the blocks for each frame.
[0009]
  The present invention will be described in detail with reference to the following examples shown with the accompanying drawings.
  FIG. 1 is a block diagram of a display control circuit in an embodiment of an image display device according to the present invention. This embodiment relates to an image display apparatus used for an image for monochrome display.
  In FIG. 1, displayed image data is stored in the VRAM 103. The timing controller 101 outputs a signal for controlling the timing of the display operation to each operation part. The VRAM controller 102 performs control to sequentially read image data from the VRAM 103 in accordance with the synchronization signal from the timing controller 101.
  The dot counter 104 counts the synchronization signal from the timing controller 101 and outputs the pixel address in the horizontal direction (main scanning direction) to the selector 108. The line counter 105 counts the synchronization signal from the timing controller 101 and outputs the pixel address in the vertical direction (sub-scanning direction) to the selector 108. The frame counter 106 counts the synchronization signal from the timing controller 101 and outputs a timing signal according to the frame period to the selector 108.
[0010]
  On / off patternThe register 107 is the basicOn / off pattern(Details will be described later) are written from a control circuit (not shown). The selector 108 is based on the gradation data input from the VRAM 103, the horizontal pixel address, the vertical pixel address, the frame period, and the block address (vertical / horizontal) counted by them.On / off patternThe lighting data in the register 107 is selected and output to the format converter 109. The operations so far are processed in units of pixels. The format converter 109 converts the data into an interface format such as an LCD display and outputs display data to the display 110.
[0011]
  In the present invention, the pixels arranged on the display screen are divided into blocks of a predetermined size, and gradation can be expressed in units of blocks. In addition, spatially, even if adjacent blocks have the same gradation,On / off patternGradation processing is performed so that the patterns are not the same. Furthermore, in time (in FRC control), the blocks at the same positionOn / off patternBetween blocks so that they are not identical.On / off patternRotate.
  2 to 29,On / off patternEach basic data written and held in the register 107On / off pattern, Each basicOn / off pattern4x4 pixel block and 4x4 pixel block generated fromOn / off patternIs a 4 × 4 block unit in which the pattern is changed for each block by rotating.
  30 to 33 show 4 × 4 block unit.On / off patternThis shows an example of a screen displayed by repeating the above, and shows a part of frame transition when FRC control is performed with 16 frames as one cycle.
[0012]
  With reference to FIGS. 2 to 33, the gradation display of this embodiment will be described in detail.
  In this embodiment, halftones are displayed with 4 × 4 pixels formed by pixels that perform a binary (on / off or lighting / non-lighting) operation as one block. Therefore, 16 gradations can be expressed.
  Taking 2/16 gradation as an example, it becomes basic as shown in FIG.On / off pattern(On / off patternStored in the register 107) is four types of patterns GRAPA1 to 1 per gradation.
GRAPA4 is prepared. Since the pattern is 2/16 gradation, it has two lit pixels (data ‘1’ is lit), and GRAPA1 to GRAPA4 each have two different locations in 16 pixels as ‘1’.On / off patternIt expresses by.
[0013]
  Here, four different gradationsOn / off patternThe basicOn / off patternAs a result, a 4 × 4 pixel block is generated. In the 4 × 4 pixel block, as shown in FIG. 3, GRAPA1 is applied to blocks 0 to 3 (B0 to B3). The block B0 is generated by sequentially developing the GRAPA1 pattern in the 4 × 4 pixel matrix. In this embodiment, the block B0 is rotated 90 degrees to the right.On / off patternBlock B1 and rotated 90 degrees to the rightOn / off patternB2 and rotated 90 degrees to the rightOn / off patternIs B3. In this way, four 4 × 4 pixel blocks are generated based on GRAPA1.
  Applying GRAPA2 to blocks B4 to B7, GRAPA3 to blocks B8 to BB, and GRAPA4 to blocks BC to BF, each generates 4 4 × 4 pixel blocks in the same way as above. A 4 × 4 block unit of key is constructed.
[0014]
  The case of 3/16 gradation is shown in FIGS. In this case, as shown in FIG.On / off patternThere is a difference in that data corresponding to 3/16 gradation is prepared as GRAPA1 to GRAPA4, but four other 4 × 4 pixel blocks are generated, and each pattern is based on GRAPA1 to GRAPA4. The procedure for generating different 4 × 4 block units can be performed in the same manner as the 2/16 gradation described above.
  6/16 for the 4/16 gradation, FIGS. 8 and 9 for the 5/16 gradation, and FIGS. 10 and 11 for the 6/16 gradation, for the 7/16 gradation. FIG. 12 and FIG. 13, FIG. 14 and FIG. 15 for 8/16 gradation, FIG. 16 and FIG. 17 for 9/16 gradation, and FIG. 18 and FIG. 19 for 10/16 gradation, 20 and 21 for the 11/16 gradation, FIGS. 22 and 23 for the 12/16 gradation, FIGS. 24 and 25 for the 13/16 gradation, and the 14/16 gradation for the 16/16 gradation. 26 and FIG. 27, as shown in FIGS. 28 and 29 for the 15/16 gradation, the 4 × 4 pixels and the 4 × 4 block unit of each gradation are the same as the 2/16 gradation described above. Can be generated.
[0015]
  An example of FRC control performed on display pixels in units of 4 × 4 blocks obtained by the above generation process will be described.
  In the FRC control according to the present invention, the same block position is set during the FRC control cycle.On / off patternIn order to make the gray level of each pixel subject to FRC control uniform between the blocks for each frame.On / off patternRotation is done. For this reason, in this embodiment, between 16 blocks included in a 4 × 4 block unit.On / off patternTherefore, the FRC control cycle requires the number of frames that make a round of 16 blocks, that is, 16 frames.
[0016]
  FIG. 30 shows a 4 × 4 block unit.On / off patternThe state in the frame period 0 of the screen displayed by repeating is shown. This screen shows a case where the image area of the same gradation covers a wider area than the display pixels of 4 × 4 block units obtained by the above generation process, and the 4 × 4 block units are arranged in the matrix direction. By repeating the above, the screen is displayed in two dimensions.
  In the frame period 0, the arrangement is as shown in FIG. 30, and FIGS. 3, 5, 7, 9, 11, 13, 15, 15, 17, 19, 21, 23, 25, and 25, FIG. 27 and the unit of 4 × 4 blocks shown in FIG.On / off patternbecome.
  In the frame period 1, the selector 108 operates to change between 16 blocks included in a 4 × 4 block unit as shown in FIG. 31.On / off pattern, That is, an arrangement that shifts the arrangement of the display blocks is selected. Similarly, the arrangement of blocks in the frame period 14 and the frame period 15 is the pattern shown in FIGS. 32 and 33. Although not shown for the frame periods 2 to 13, the selector 108 similarly performs an operation for shifting the phase.
[0017]
  By performing the FRC control as described above, each pixel is equal in 16 frames, and a desired gradation display can be performed. Also, even if attention is given to a certain frame, it is desired within one block of 4 × 4 pixels. The so-called spatial modulation for performing the gradation display is achieved. In addition, each blockOn / off patternThe pattern can be different from adjacent blocks.
[0018]
  The embodiment described above relates to an image display apparatus used for an image for monochrome display, but the image display apparatus described below relates to an apparatus for an image for color display.
  FIG. 34 is a block diagram of a display control circuit in an embodiment of a color-compatible image display device according to the present invention.
  The image display apparatus according to the present embodiment is color-compatible, and basically the gradation in the monochrome-compatible image display apparatus shown in FIG. Process the display data. Accordingly, the same processing means as in FIG. 1 is used for R data, which is one of the three colors of data, and therefore the same reference numerals are used for the same elements as in FIG. (No.) is attached and the description is not repeated, and the description of the color corresponding part is supplemented below.
[0019]
  As for color-corresponding portions peculiar to the image display apparatus of this embodiment, with reference to FIG. 34, image data to be displayed in color is stored in the VRAM 103 as R, G, B data, and each data In accordance with the synchronization signal from the timing controller 101, control for sequentially reading image data (gradation data) is performed. As data selectors, R, G, and B data selectors 108, 113, and 116 are provided, and each selector receives a block address from the address converter 117, a horizontal pixel address in the block, and a vertical pixel address in the block, and a frame. A frame period is input from the counter 106.
  On / off patternThe register 107 is the basicOn / off patternHowever, although it is written from a control circuit (not shown), it is sufficient to prepare one pattern for R for R, G, B, and this pattern is stored in the R, G, B data selectors 108, 113, 116. Supply.
  Further, a G phase register 111 and a B phase register 114 are provided, in which respective phase shifts with respect to R data used by each are written from a control circuit (not shown). , 116, and the data selectors 113, 116 perform a selection operation using a pattern whose phase is shifted in accordance with the set data.
[0020]
  The selector 108 is based on the R gradation data input from the VRAM 103, the frame period, the block address (vertical / horizontal), the horizontal pixel address in the block, and the vertical pixel address.On / off patternThe lighting data in the register 107 is selected and output to the format converter 109.
  When performing the same operation, the selector 113 receives the G gradation data input from the VRAM 103, the frame period, the block address (vertical / horizontal), the horizontal pixel address in the block, the vertical pixel address, and the G phase. From the G phase data set in the register 111,On / off patternThe lighting data of the register 107 is selected and output to the format converter 109, and the phase of the pixel array in the block is shifted with respect to R in the same frame.
  When performing the same operation, the selector 116 receives the B gradation data input from the VRAM 103, the frame period, the block address (vertical / horizontal), the horizontal pixel address in the block, the vertical pixel address, and From the B phase data set in the B phase register 114,On / off patternThe lighting data of the register 107 is selected and output to the format converter 109, and the phase of the pixel array in the block is shifted with respect to R (also G) in the same frame. The operations so far are processed in units of pixels.
[0021]
  The gradation display operation by the color-compatible image display device of this embodiment will be described.
  The process of generating gradation display data of R, G, and B colors for displaying a color image is basically different from the process of generating monochrome gradation display data described above with reference to FIGS. There is no place. In other words, the pixels arranged on the display screen are divided into blocks of a predetermined size so that gradation can be expressed in units of blocks, and in addition, spatially, adjacent blocks have the same gradation. Also,On / off patternPerform patterning processing so that they are not identical. Furthermore, in time (in FRC control), the same (in the same position) blockOn / off patternBetween blocks so that they are not identical.On / off patternRotate.
[0022]
  A new requirement for gradation display of a color image is the relationship between gradation display data of each color, and each of R, G, and B colors in the same frame and the same block.On / off patternThe gradation display data that does not have the same pattern is used, and the lighting timing is distributed for each of the R, G, and B colors.
  Specifically, the R data, which is one of the three color data, can be implemented by using the process of generating monochrome gradation display data described with reference to FIGS. 2 to 33 as it is. That is,On / off patternBasics written and held in register 107On / off pattern4x4 pixel block and 4x4 pixel block generated fromOn / off patternIs rotated to generate a display screen of one frame in units of 4 × 4 blocks in which the pattern is changed for each block (see FIGS. 2 to 29). FRC control is performed between 16 blocks included in a 4 × 4 block unit for each frame.On / off patternThe FRC control is performed with 16 frames as one cycle (see FIGS. 30 to 33).
[0023]
  In the display of G data, each color of R, G, B in the same frame and the same blockOn / off patternSince it is necessary to generate gradation display data under conditions that do not result in the same pattern, a phase shift with respect to the R data is given at the time of generation. The phase shift is set for the G data selector 113 by the G phase register 111.
  The phase shift is between 16 blocks included in a 4 × 4 block unit.On / off patternBy shifting the arrangement of blocks by the set phase data. For example, when the G phase data set in the G phase register 111 is 1, the arrangement of the display blocks of G data in the frame period 0 is only 1 in the arrangement of the display blocks of the R data (FIG. 30) in the frame period 0. The shifted data, that is, the arrangement shown in FIG. The arrangement of the display blocks of G data in the frame period 13 is as shown in FIG. Similarly, the arrangement of each block of G data in the frame period 14 is as shown in FIG.
[0024]
  In the display of B data as well, the colors of R, G, and B in the same frame and the same block are the same as described above.On / off patternSince it is necessary to generate gradation display data under conditions that do not result in the same pattern, a phase shift with respect to the B data is given at the time of generation. The phase shift is set for the B data selector 116 by the B phase register 114.
  The phase shift is between 16 blocks included in a 4 × 4 block unit.On / off patternBy shifting the arrangement of blocks by the set phase data. For example, when the B phase data set in the B phase register 114 is 15, the arrangement of the display blocks of B data in the frame period 0 is only the arrangement of 15 display blocks of the R data (FIG. 30) in the frame period 0. The shifted data, that is, the arrangement shown in FIG. The arrangement of the display blocks of B data in the frame period 15 is as shown in FIG. Similarly, the arrangement of each block of B data in the frame period 1 is as shown in FIG.
[0025]
  By performing the gradation display operation by FRC control as described above, each of the RGB pixels is equal in 16 frames, and a desired gradation display can be performed. So-called spatial modulation for performing desired gradation display within one block is achieved. In addition, each blockOn / off patternCan be different on / off patterns from adjacent blocks. Moreover, each of RGBOn / off patternCan be selected by the phase register.
  In this embodiment, the gradation data output from the VRAM 103 is directly connected to the R, G, and B data selectors 108, 113, and 116. However, the VRAM 103 and the R, G, and B data selectors are directly connected. An LUT (Look Up Table) for color conversion may be provided between 108, 113, and 116.
  In addition, the image display device of the present invention controls on / off of driving of pixels arranged in a matrix such as a graphic display device using an LCD, a CRT, or a plasma display panel or an EL display panel. Therefore, the present invention can be widely applied to and implemented in any device equipped with such an image display device. As one of the embodiments, it is conceivable to apply the image display device of the present invention to a device provided with the image display device in a user interface (for example, an input operation panel). In this case, information transmission with the user is performed with more various image representations, and the performance of the mounted device can be improved.
[0026]
【The invention's effect】
(1) Claim 1, 2Effects corresponding to the invention
  According to the present invention, since pixels included in adjacent blocks of the same gradation are driven with different on / off patterns, it is possible to eliminate display degradation such as moving that has occurred in the same conventional repeated pattern. it can. Moreover, since the pixels included in the same arrangement block are driven with different on / off patterns over the image frames in the FRC control cycle, the occurrence of local flicker can be reduced even when the frame frequency is low. it can.Also,An on / off pattern prepared as a basic pattern used when the same gradation display is performed with different on / off patternsTurnPrepared by generating by rollingOn / off patternIt requires less data and can be implemented with simple processing operations.
(2)  Effects corresponding to the invention of claim 3
  the above(1)In addition to the effect of the above, by the selector according to the block address generated by counting the timing signal of the display operation from the basic on / off pattern stored in the register, the pixel address in the block and the frame periodON / OFF pattern lightingBy selecting the data, at the same block position during the FRC control cycleOn / off patternRotation processing for performing lighting that is not the same can be performed with a simple configuration.
(3)  The effect corresponding to the invention of claim 4
  In addition to the effects (1) and (2) above, different on / off patterns used during the FRC control cycle, Number of times each pixel in each block is litBy adopting an arrangement pattern that makes the display uniform, the display image has a higher image quality.
(4) Effect corresponding to invention of Claim 5
In addition to the effects (1) to (3) described above, the on / off pattern used for the pixels of each color (R, G, B) constituting the color image is prevented from becoming the same pattern in the same frame and the same block. Since the drive (lighting) timing is controlled to be distributed for each of the colors, adjacent blocks of the same gradation have different on / off patterns depending on the block address, and each color (R, G, B) in the same block. Mutual on / off patterns can be prevented from being the same, display deterioration such as moving can be suppressed in response to color display, and the same arrangement of blocks can be achieved over the image frames in the FRC control cycle. Since the included pixels are driven with different on / off patterns, even when the frame frequency is low, local flickering occurs. It can be reduced.
(5) Effect corresponding to invention of claim 6
In addition to the effect of (4) above, the on / off pattern used for each color is rotated when the on / off pattern prepared as a basic pattern is used to prevent the on / off pattern from being the same pattern in the same frame and the same block. This is generated by setting the phase of the on / off pattern displayed within one cycle of each color to be different, so less data needs to be prepared, and the corresponding gradation display for color by simple processing operations Can be implemented.
(6) Effect corresponding to invention of Claim 7
The apparatus provided with the image display device according to any one of claims 1 to 6 improves the performance of the apparatus by realizing the effects (1) to (5).
[Brief description of the drawings]
FIG. 1 is a block diagram of a display control circuit in an embodiment of an image display device according to the present invention.
FIG. 2 shows four basic types used to generate 2/16 gradation display data.On / off patternIndicates.
FIG. 3 Basic of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 4 shows four basic types used for generating 3/16 gradation display data.On / off patternIndicates.
FIG. 5 Basic of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 6 shows four basic types used for generating 4/16 gradation display data.On / off patternIndicates.
FIG. 7 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 8 shows four basic types used for generating 5/16 gradation display data.On / off patternIndicates.
FIG. 9 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 10 shows four basic types used to generate 6/16 gradation display data.On / off patternIndicates.
FIG. 11 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 12 shows four basic types used to generate 7/16 gradation display data.On / off patternIndicates.
FIG. 13 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 14 shows four basic types used to generate 8/16 gradation display data.On / off patternIndicates.
FIG. 15 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 16 shows four basic types used to generate 9/16 gradation display data.On / off patternIndicates.
FIG. 17 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 18 shows four basic types used to generate 10/16 gradation display data.On / off patternIndicates.
FIG. 19 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 20 shows four basic types used to generate 11/16 gradation display data.On / off patternIndicates.
FIG. 21 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 22 shows four types of basics used to generate 12/16 gradation display data.On / off patternIndicates.
FIG. 23 shows the basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 24 shows four basic types used to generate 13/16 gradation display data.On / off patternIndicates.
FIG. 25: Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 26 shows four basic types used to generate 14/16 gradation display data.On / off patternIndicates.
FIG. 27 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 28 shows four basic types used to generate 15/16 gradation display data.On / off patternIndicates.
FIG. 29 Basics of FIG.On / off pattern4 × 4 pixel block and 4 × 4 block unit generated from the above.
FIG. 30 is a 4 × 4 block unit of frame 0 under FRC control.On / off patternThe repeated arrangement is shown.
FIG. 31 is a 4 × 4 block unit of frame 1 under FRC control.On / off patternThe repeated arrangement is shown.
FIG. 32: 4 × 4 block unit of frame 14 under FRC controlOn / off patternThe repeated arrangement is shown.
FIG. 33: 4 × 4 block unit of frame 15 under FRC controlOn / off patternThe repeated arrangement is shown.
FIG. 34 is a block diagram of a display control circuit in an embodiment of a color-compatible image display device according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... Timing controller, 102 ... VRAM controller, 103 ... VRAM, 104 ... Dot counter, 105 ... Line counter, 106 ... Frame counter, 107 ...On / off patternRegister 108, selector, 109 format converter, 110 display, 111 ... G phase register, 113 ... G data selector, 114 ... B phase register, 116 ... B data selector, 117 ... address converter.

Claims (7)

An image frame composed of pixels arranged in a matrix is divided into blocks of a predetermined size, and driving of each pixel included in the block is controlled on / off over a predetermined number of image frames for each block. In an image display device that enables pseudo gradation display,
A register storing a basic on / off pattern for each gradation;
Generating means for generating a plurality of different on / off patterns representing the same gradation as the on / off pattern for driving the pixels in the block from the basic on / off pattern;
With
Using the plurality of different on / off patterns, spatially adjacent blocks of the same gradation are driven with different on / off patterns, and the same arrangement of blocks over the predetermined number of image frames is also different. An image display device that is driven in an off pattern. The image display device according to claim 1,
The plurality of different on / off patterns are generated by rotating the basic on / off pattern . The image display device according to claim 2,
Lighting data of the selector on / off pattern according to the block address, the pixel address in the block, and the frame period generated by counting the display operation timing signal from the basic on / off pattern stored in the register. An image display device characterized in that it is performed by selecting. The image display device according to any one of claims 1 to 3,
An image characterized in that the different on / off patterns for displaying the same gradation are arranged so that the number of lighting times of each pixel in each block becomes uniform by a display operation over a predetermined number of image frames. Display device. In the image display device according to any one of claims 1 to 4,
An image display device, wherein the pixels are pixels of each color constituting a color image, and the on / off pattern used for each color is not the same pattern in the same frame and the same block. The image display device according to claim 5,
When rotating the basic on / off pattern, the on / off pattern used for each color is set in the same frame and by setting the phase of the on / off pattern displayed in one cycle of each color to be different. An image display device characterized by not having the same pattern in the same block.   A device comprising the image display device according to claim 1.

Images