JP4812315B2 - Gradation display device, image reading device, and image forming device - Google Patents

Description

  The present invention relates to an apparatus for gradation-displaying an image on a two-dimensional display surface and an apparatus using the same, and for example, a CRT display, a liquid crystal display, a plasma display, an EL display, an image display of a digital camera, an image display of a mobile phone, an original It can be used for a display of a scanner or a film scanner, a copying machine or a facsimile display.

Japanese Patent No. 2784005 JP 2001-215938 A Japanese Patent Laid-Open No. 9-237067 JP2003-122121A.

  In an image display device that performs on / off or lighting / non-lighting operations of display pixels arranged in a matrix at binary levels, an area gray scale method and frame rate control (FRC) are used as a method of performing pseudo gray scale display. ) There is a law.

  In the area gradation method, for each pixel included in a unit area (pixel block) of a screen in which display pixels are arranged in a matrix, on / off is controlled based on gradation data, and in that space (block area) Average brightness is determined by the number of ON pixels. That is, the gradation is expressed by the number of ON pixels. The problem with the area gray scale method is that the display resolution decreases in units of blocks.

  In the FRC method, on / off on-duty (on time or on number / predetermined time or predetermined number) is controlled based on gradation data for each pixel included in a target pixel or target region for each image frame displayed one after another. Then, the average brightness in the predetermined time (the number of frames) is determined. That is, the gradation is expressed. As a problem of the FRC method, when a large area is displayed with the same gradation in a pixel displayed in halftone (gradation), flicker called flicker occurs, and the display quality is deteriorated.

  To solve these problems, in the gradation display method described in Patent Document 1, one screen (frame) of the display device is divided into a plurality of sections, each section having N pixels, and the number N of pixels is The area gradation method is controlled so that the number of gradation displayable steps is the same. Furthermore, by sequentially giving a plurality of lighting patterns of different phases prepared corresponding to each gradation over a plurality of frames and performing the control of the FRC method, the lighting patterns in each section are made different for each frame, and the display resolution is lowered. To reduce flicker.

  Further, in the image display device described in Patent Document 2, flicker and moving phenomenon are suppressed with a simple configuration without deterioration in image quality, and four types of area gradation expression patterns (one per gradation) ( Basic patterns) groups GRAPA1 to GRAPA4, a pattern group obtained by rotating each gradation pattern by 90 °, a pattern group rotated by 180 ° and a pattern group rotated by 270 ° are used. That is, three additional rotation pattern groups are added to each basic pattern group, and a total of 16 pattern groups are used to switch the use pattern group which is used by sequentially switching 16 pattern groups in 16 frames. (0018-0021).

  Japanese Patent Laid-Open No. 2004-228688 sets a display period of N frames as one display cycle, and controls the light emission / extinction (on / off) of a pixel at a frame ratio corresponding to the gradation level to be displayed. A display device is described.

  In Patent Document 4, when a pixel block for expressing the first gradation and the second gradation is expressed, and the third gradation between the first gradation and the second gradation is expressed, the pixel block is designated as the first block. The first group of pixels is fixed to one of the first gradation and the second gradation over the reference period, and the second group of pixels is divided into the first gradation and the second floor. A halftone display that blinks in key is presented.

  However, in the above prior art, the same number of lighting patterns is required for a predetermined number of image frames, and when the number of display gradations is increased, the number of display gradations is increased under the control of the FRC method. Correspondingly, an increase in the number of lighting patterns prepared and an increase in the number of display gradations in the area gradation method control cause problems such as deterioration of the moving phenomenon accompanying an increase in the divided control area. In addition, with a simple configuration, it becomes difficult to equalize the lighting cycle over time and the lighting cycle over the area as the lighting pattern decreases, resulting in poor display quality due to the occurrence of the moving phenomenon. Problems such as deterioration occur.

  An object of the present invention is to express gradation with high display quality using relatively few lighting patterns.

(1) a two-dimensional display means (11) having a display surface that expands in the horizontal (x) and vertical (y) directions, and performing display / non-display in pixel units of on / off signal sections on the display surface;
Each of the pixel blocks (4 × 4 pixel matrix) composed of a plurality of pixels in the horizontal and vertical directions represents the distribution of on / off signals instructing light emission / non-light emission of each pixel and the display gradation of the pixel block. Basic pattern group (GPTNA) consisting of multiple light emission pattern data (GPTNA01, GPTNA02, GPTNA03, ...) expressing different gradations, and either odd or even values of the gradations Gradation memory (Prg) for storing additional pattern groups (GPTNE);
Means (48, 60) for reading light emission pattern data (Dbp) corresponding to the gradation data (B) from the gradation memory;
Means for generating a count value by counting the frame synchronizing signal emission pattern shift command signal corresponding to the (Yb) (Yb) (48,49 );
Pattern changing means (55a / 55b, 56) that shifts the light emission pattern data (Dbp) read from the gradation memory (Prg) in the horizontal direction or the vertical direction by the number of pixels specified by the shift instruction signal (Yb). );and,
Means (44, 45, 58, 57, 70) for outputting on / off signals of the light emission pattern data (Dbs) shifted by the pattern changing means (55a / 55b, 56) to the two-dimensional display means (11);
A gray scale display device (FIGS. 5, 18, 20, and 21).

  In order to facilitate understanding, the reference numerals of corresponding elements or equivalent elements or equivalent matters in the parentheses shown in the drawings and described later are added as reference for reference. The same applies to the following.

  According to this, it is possible to sequentially switch and use various pattern groups without significantly increasing the required memory capacity of the gradation memory (Prg).

(2) Each of the basic pattern group and the additional pattern group (GPTNE) is a plurality of groups having different ON / OFF signal distribution patterns;
Gray scale display device further comprises means (48) for generating a count value by counting the frame synchronizing signal (× b) Group instruction signal corresponding to the (× b); includes a
The means (48, 60) for reading out the light emission pattern data (Dbp) is provided with gradation data (GPTNE) of the basic pattern group or additional pattern group (GPTNE) designated by the group instruction signal (× b) from the gradation memory. The light emission pattern data (Dbp) corresponding to B) is read out; the gradation display device according to (1) above.

(3) one of said light-emitting patterns shift instruction signal (Yb) means for generating (48, 49) and group instruction signal (× b) means for generating (48), until the set value by counting the frame synchronizing signal The first circulation counter (48a / 48b) that initializes the count data when it counts and counts it again, and the other counts up to the set value of the first circulation counter and counts up to the set value to initialize the count data The gradation display device according to (2) above, which is a second circulation counter (49a / 49b) that counts and counts again.

(4) The first circulation counter (48a / 48b) counts the frame synchronization signal in a narrow gradation display that represents a narrow range of gradations with a small gradation value and uses only the basic pattern group for gradation expression. A narrow-tone circular counter (48a) that initializes and counts the count data when it counts up to the set value for gradation (4), and a wide range that uses the basic pattern group and the additional pattern group for gradation expression with many gradation values. A wide gradation circulation counter (48b) that counts the frame synchronization signal in the wide gradation display representing the gradations of the image and counts the data when the frame gradation signal is counted up to the wide gradation setting value (8); The 2-cycle counter also counts up to the set value (4) for the narrow tone and counts to the set value (4) of the first cycle counter for narrow tone (48a). Counts up to the setting value (8) for the wide gradation of the second circulation counter (49a) for narrow gradation and the first circulation counter (48b) for wide gradation, which initializes and counts the count data, and sets it. The gradation display device according to (3), further including a second gradation counter for wide gradation (49b) that initializes count data when counting to value (4) and counts again.

(5) The count value ( × bb ) of the wide tone circulation counter ( 48b ) is set to the odd or even value of the tone to which the additional pattern group (GPTNE) is addressed, and the narrow tone is set to other tone values. The gradation display device according to (4) above, wherein the count value (× ba) of the circulation counter (48a) is assigned.

  (6) The means (48, 60) for reading the light emission pattern data (Dbp) corresponding to the gradation data (B) from the gradation memory has a wide range (32) gradations represented by the gradation data (B). Means (62) for converting narrow range gradation data representing a narrower range (16) of gradations into gradation data representing the wide range (32) of gradations; (1) to (5) above The gradation display device according to any one of the above.

(7) Only the light emission pattern data of the basic pattern group (GPTNA) and the additional pattern group (GPTNE) not using the pattern changing means (55a / 55b, 56) are output to the pattern changing means (55a / 55b, 56). The gradation display device according to any one of the above (1) to (6), further comprising means (66) for selecting an output that uses the light emission pattern data shifted in this manner.

(8) said pattern changing means (55 / 55a / 55b, 56 ) , the emission pattern shift instruction signal (Yb) the number of pixels corresponding to the (0/1/2/3) minutes, on the horizontal (×) direction The gray scale display device according to any one of (1) to (7), wherein the horizontal shift means (55a, 56) converts the light emission pattern data (Dbs) into a shifted / off signal.

(9) the pattern changing means (55 / 55a / 55b, 56 ) , the emission pattern shift instruction signal (Yb) the number of pixels corresponding to the (0/1/2/3) minutes, on the vertical (y) direction The gray scale display device according to any one of (1) to (7), wherein the vertical shift means (55b, 56) converts the light emission pattern data (Dbs) into a shifted / off signal.

(10) A unit (48, 60) for reading the light emission pattern data (Dbp) corresponding to the gradation data is provided for each display of R, G, and B gradation data, and a total of three sets; Means (64, 65) for adding a phase shift value for making the number of pixels of the shift different from a basic pattern group or the other group from the other group; any one of the above (1) to (9) The color gradation display device described in FIG. 18 (FIG. 18).

(11) an imaging device (100) for converting an optical image into image data representing the optical image; and
An optical image reading comprising the gradation display device (10) according to any one of (1) to (10), wherein the image data generated by the imaging device is displayed on the two-dimensional display means (11). Device (Figure 1).

(12) a document scanner (100, 120) that reads an image of a document and generates image data representing the image; and
An original reading apparatus (FIG. 1) comprising: the gradation display device according to any one of (1) to (10) above, which displays image data generated by the original scanner on the two-dimensional display means (11). ).

(13) The document reading device according to (12) above;
A printer (200) for forming an image represented by the image data on paper; and
An image forming apparatus (FIG. 1) comprising image data processing means (302) for converting image data generated by the document reading apparatus into image data suitable for image forming characteristics of the printer.

  (14) The gradation display device (10) is in an operation terminal (10) that gives a user instruction to the image forming device; the image forming device according to (13) above.

  Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

  FIG. 1 shows an external appearance of a full-color digital multi-function copier MF1 including an operation board 10 equipped with a gradation display device (FIGS. 2, 4, and 5) according to a first embodiment of the present invention. The full-color copying machine MF1 is roughly constituted by units of an automatic document feeder (ADF) 120, an operation board 10, a color scanner 100, and a color printer 200. The operation board 10 and the color scanner 100 with the ADF 120 are units that can be separated from the printer 200. The color scanner 100 includes a control board having a power device driver, a sensor input, and a controller, and an engine controller. Communication is performed directly or indirectly, and the timing is controlled to read a document image.

  A LAN (Local Area Network) connected to a personal computer PC is connected to the controller board to which the scanner 100, the printer 200, and the engine including the image input / output device are connected, and a facsimile control unit (FCU) in the copier MF1 is connected. ) Is connected to an exchange PBX connected to a telephone line PN (facsimile communication line). In this embodiment, flatbed type document reading and sheet-through reading can be performed.

  As shown in FIG. 2, in addition to the liquid crystal touch panel 11, a numeric keypad 15, a clear / stop key 16, a start key 17, an initial setting are provided on the operation board 10 equipped with the gradation display device of the first embodiment of the present invention. There are a key 18, a mode switching key 19, a test print key 20, and a power key 21. Although not shown, on the left side of the liquid crystal touch panel 11 which is a two-dimensional display means, an alphabet keyboard with hiragana added for input, setting and abbreviated registration for URL, mail text, file name, folder name, etc. There is.

  The power key 21 is an operation key for instructing switching from the energy saving mode (the sleep mode or the low power mode) to the standby mode in which image printing is possible and vice versa. If the power key 21 is pressed once when the energy saving mode is set, the energy saving mode is switched to the standby mode. When the power key 21 is pressed once in the standby mode, the standby mode is switched to the sleep mode. The test print key 20 is a key for printing only one copy regardless of the set number of print copies and confirming the print result.

  By pressing the initial setting key 18, the initial state of the machine can be arbitrarily customized. It is possible to arbitrarily set the state set when the transition time to the energy saving mode is set, the paper size stored in the machine is set, or the copy function reset key is pressed. When the initial setting key 18 is operated, an "initial value setting" function for setting various initial values, an "ID setting" function, a "copyright registration / setting" function, an "usage record output" function, etc. A selection button to specify is displayed.

  On the liquid crystal touch panel 11, various function keys and messages indicating the operation states of the engine 300 and the controller board 400 are displayed. The LCD touch panel 11 is used for selecting and executing the “copy” function, “scanner” function, “print” function, “facsimile” function, “store” function, “edit” function, “register” function, and other functions. A function selection key 14 representing is displayed. An input / output screen determined for the function designated by the function selection key 14 is displayed. For example, when the “copy” function is designated, the function keys, the number of copies, and the state of the image forming apparatus are shown as shown in FIG. Messages 12 and 13 are displayed. Among the function keys 12, print color designation keys “black (BK)”, “full color”, “automatic color selection”, “blue (C)”, “red (M)” and “yellow (Y)” designation There is a key. When the operator touches a key displayed on the liquid crystal touch panel 11, the operation board 10 reads it as an operator input, and highlights the key indicating the selected function in gray indicating that it is being designated. Further, when it is necessary to specify the details of a function (for example, the type of page printing), a detailed function setting screen is popped up by touching a key. Thus, since the liquid crystal touch panel 11 uses a dot display, it is possible to graphically perform an optimal display at that time.

  3A shows an image reading input screen displayed on the liquid crystal touch panel 11 when the user touches the “read” key in the function selection key 14, and FIG. 3B shows the image reading input screen. Indicates a display on the liquid crystal touch panel 11 of an image read by the document scanner 100. When the user makes a required input on the input screen shown in FIG. 3A and double-clicks the “Get” button, the document scanner 100 reads the image, and the read image is shown in FIG. ) And the image data are stored in the memory 406 or the HDD 401 as shown in FIG. The input screen shown in FIG. 3A includes a scaled area 31 for designating an area, and a rectangular dotted line block 32 representing the designated area is displayed in the area. A small square operation location mark 33 is displayed at each of the four corners of the dotted line block 32, and by specifying this and moving it up, down, left and right, the shape of the dotted line block 32 changes while maintaining the rectangle. That is, the designated area can be adjusted. The x (horizontal direction in the figure) and y (vertical direction) coordinate values of the diagonal corner of the dotted block 32 when a document image capture instruction (double click of the “capture” button) is given are read as area designation data.

  The five buttons in the “captured image” column on the input screen shown in FIG. 3A are used to specify image processing characteristics in the scanner image processing 303 and represent the image type of the document to be read. By one-clicking the display button, image data processing that optimally represents the document image is designated. The check “Use ADF” in the column of the reading mode means specification of sheet-through reading using ADF, and if there is no check, it is reading specification of the original placement method. In the case of “use ADF”, all the originals placed on the ADF original table are automatically and sequentially read. When scanning with the flatbed method is selected, the scanning operation will be completed when a single document is scanned if “Multiple scanning” is not checked. However, if “Multiple scanning” is checked, a single document will be scanned. An instruction input screen as to whether to end the reading operation is displayed in a pop-up, and when the user instructs to end the reading operation, the reading operation is ended there. If the “take” button is clicked without instructing the end, one more original is read and an instruction input screen for popping up is displayed in a pop-up.

  FIG. 4 shows a circuit block of the operation board 10. The main body of the electric control system of the operation board 10 communicates with the CPU 402 of the controller board 400, reads the input of the operation board 10, and controls the display on the operation board 10, and stores the control program of the CPU 1. ROM 2, RAM for temporarily storing data during control, VRAM 7 for storing drawing data of the liquid crystal touch panel 11, drawing timing control of the liquid crystal touch panel 11 connected to the VRAM 7, touch input detection, etc. There are a liquid crystal display controller (LCDC) 6, a clock IC 5 for generating time data, and the like. A liquid crystal touch panel 11 having a CFL light source as a backlight 9 is connected to the LCDC 6. The CPU 1 is further connected to an inverter 8 that drives the CFL backlight 9, a key matrix of operation key groups 15 to 21, an LED matrix of display LEDs, an LED driver that drives these LEDs, and the like. Further, a nonvolatile RAM (NVRAM) 4 for storing an image processing mode is connected to the data bus to which the CPU 1 is connected.

  The CPU 1 of the operation board 10 corresponds to the user's operation on the operation board 10, reads the numeric key press, generates the input numeric data, reads the start key press, and sends a start instruction to the controller board 400. It performs normal operation reading and display output control of copiers such as transfer and reading of paper size switching input.

  In the ROM 2, in addition to the operation program of the CPU 1, the distribution of on / off signals instructing light emission / non-light emission of each pixel and the display gradation of the pixel block of a pixel block composed of a plurality of pixels in the horizontal and vertical directions are displayed. As shown in FIG. 10, four basic pattern groups GPTNA to GPTND and four additional pattern groups GPTNE to GPTNH, each of which is composed of a plurality of light emission pattern data expressing different gradations, are expressed as gradations. Stored in association with values (density 0 to 31). The contents of 4 × 4 image block data (pattern) assigned to the data index shown in FIG. 10 are shown in FIGS.

  Referring back to FIG. 4, the pixel block data (FIGS. 7 to 9) stored in the ROM 2 is allocated to the memory area of the RAM 3 by the CPU 1 during initialization when an operating voltage is applied to the operation board 10. It is written in the pattern register Prg (FIG. 5) and used for subsequent gradation display. The display data (gradation data) is written into the VRAM 7 and is synchronized with the horizontal block synchronization signal of the LCD 11 raster display (count over signal of the pixel counter 44 in FIG. 5: one pulse for every four pulses of the pixel synchronization signal). Then, it is read from the VRAM 7 by the LCDC 6 and used as a read address for the pixel block data in the pattern register Prg. The pixel block data read from the pattern register Prg is output from the LCDC 6 to the LCD 11 in accordance with a raster display pixel synchronization signal (pixel synchronization pulse) of the LCD 11.

  FIG. 5 shows an outline of the functional configuration of the LCDC 6. The display data stored in the VRAM 7 and read out by the LCDC 6 has a 16-bit (2 bytes) configuration, and monochrome display gradation data is stored in the 16-bit LSB side 5 bits. When the image data separation 60 is instructed to display 32 gradations, the 16-bit LSB side 5 bits read from the VRAM 7 are extracted as gradation data and output to the 16/32 gradation switching control 61 to display the 16 gradations. Is instructed, the 16-bit LSB side 4 bits read from the VRAM 7 are extracted as gradation data and output to the 16/32 gradation switching control 61.

  When the 16/32 gradation switching control 61 is instructed to display 32 gradations, the input 32 gradation data (5 bits) is output as it is from the data selector 63 as address designation data of the pattern register Prg. When 16-gradation display is instructed, the input 16-gradation data (4 bits) is converted into 32-gradation data by the data converter 62 and output from the data selector 63 to output the address designation data of the pattern register Prg. To do.

  FIG. 12C shows the configuration of the data conversion 62. In this data conversion 62, 4-bit gradation data is doubled by bit digit shift, and a numerical value 1 is added to convert 16-gradation data into 32 gradation values. However, in order to prevent the gradation 0 of 16 gradation expression from becoming the gradation 1 of 32 gradation expression by adding the numerical value 1, in the case of the gradation 0 of 16 gradation expression, the NAND gate 46a uses the 16th floor. Gradation expression gradation 0 is detected. In this case, the AND gate 46 is closed and the least significant bit of the 32 gradation output data is set to 0.

  Here, since the 16 gradation data is converted into 32 gradation data by a calculation of 2 + 1, when the 16 gradation data is given, it is always an odd value when converted into 32 gradation data (see FIG. Note that only the basic groups GPTNA to GPTND are assigned to the points having the density of 1, 3, 5,.

  The timing control 40 includes a pixel synchronization signal generation 41 for generating a pixel synchronization signal that divides the display on the LCD 11 in the pixel (pixel) unit in the horizontal direction (x), and the display on the LCD 11 in the pixel (line) unit in the vertical direction (y). There are a horizontal synchronization signal generation 42 for generating a horizontal synchronization signal divided by, and a vertical synchronization signal generation 43 for generating a vertical synchronization signal representing switching of the display screen (frame) of the LCD 11. The pixel synchronization signal (pulse) is counted by the horizontal pixel counter 44 to generate pixel position data Xp in the horizontal direction in the pixel block, and the vertical synchronization signal (pulse) is counted by the vertical pixel counter 45 to generate the pixel position data Xp in the pixel block. The pixel position data Yp in the vertical direction is generated. Each of the counters 44 and 45 is a cyclic counter that returns to the count value 0 when the input pulse is counted up to the count value 4, outputs a count over signal (pulse), and counts up from the count value 0. Accordingly, the count over signal of the horizontal pixel counter 44 represents a horizontal pixel block delimiter, and the count over signal of the vertical pixel counter 45 represents a vertical pixel block delimiter.

  In gradation display control, in 16 gradation display, each pixel block of 0 to 15 in a 4 × 4 block section composed of 4 × 4 pixel blocks is divided into four basic pattern groups GPTNA, GPTNB, GPTXB, GPTND, Each of the three types of change pattern groups and a total of 16 pattern groups is assigned, and in 32 gradation display, 16 pattern groups are similarly assigned to 4 × 4 block sections for odd value gradation. For the numerical gradation, four additional pattern groups GPTNE, GPTNF, GPTXG, GPTNH, three change pattern groups in each set, and a total of 32 pattern groups including 16 pattern groups in total are assigned. .

  In the embodiment shown in FIG. 5, the horizontal pattern shifter 55a is used to shift the patterns corresponding to the gradation values of the basic pattern group and the additional group. As shown in FIG. 11A, the horizontal shifter 55a shifts the basic pattern (or additional pattern) from the basic data (or additional pattern) by 1 pixel in the x direction for shifting the internal data by 1 pixel in the horizontal x direction, and 2 pixels in the horizontal x direction. A shift of 2 pixels in the x direction and a shift of 3 pixels in the x direction to shift 3 pixels in the horizontal x direction are performed. Both shifts are bits (patterns) of the 4 × 4 pixel matrix distribution shown in FIG. 6B, the basic pattern data having a 2-byte structure shown in FIG. 6B is replaced with the above-mentioned pixel-shifted data pattern (FIG. 11A) by the fixed electrical lead wiring. The count data Yb (Yba, Ybb) of the counters 49a, 49b specify the shift amount. That is, Yb = 0 is the horizontal x-direction pixel shift amount 0, Yb = 1 is the horizontal x-direction pixel shift amount 1, Yb = 2 is the horizontal x-direction pixel shift amount 2, and Yb = 3 is the horizontal x-direction pixel shift amount. The quantity 3 is specified respectively.

  The frame counter 48a is a cyclic counter that counts the vertical synchronization signal, counts over when the count value reaches 4, initializes the count value to 0, and counts the vertical synchronization signal. The count data Xba is 0-3. Represents the value of. This count data Xba is applied to gradation data having an odd gradation value, and designates a basic pattern group of the gradation register Prg. The frame block counter 49a is a cyclic counter that counts the count over signal of the counter 48a, counts over when the count value reaches 4, initializes the count value to 0, and counts the count over signal, and count data Yba Represents a value of 0-3. This count data Yba specifies the shift amount of the basic pattern. A numerical value of 0 to 15 can be expressed by a combination of Xba and Yba, and this numerical value changes every time the frame synchronization signal arrives. As shown in FIG. 11B, each of the 16 types of gradation patterns having the same expression gradation value but different on / off distributions is shown in FIG. Assigned as. Among the four groups in FIG. 11B, the upper left group is Yb = 0, the upper right group is Yb = 1, the lower left group is Yb = 2, and the lower right group is Yb = 3. , Respectively. The first (leftmost) block in each group is Xb = 0, the second block is Xb = 1, the third block is Xb = 2, and the fourth block is Xb = 3. Are respectively specified by. The internal data of the pattern is specified by the gradation data B. By the above-described counting of the frame synchronization signal by the counters 48a and 49a, the designation of the basic pattern group by the count data Xba and the designation of the shift amount by the count data Yba, the block No. shown in FIG. Are allocated in one section (4 × 4 pixel block) as shown in FIG.

  When the gradation data represents an even value, as shown in FIG. 10, the even value includes four basic pattern groups GPTNA to GPTND and four additional pattern groups GPTNE to GPTNH, and eight pattern groups in total. Therefore, the frame counter 48b and the frame block counter 49b are used for even-value gradation data. The frame counter 48b is a cyclic counter that counts the vertical synchronization signal, counts over when the count value reaches 8, initializes the count value to 0, and counts the vertical synchronization signal. The count data Xbb is 0-7. Represents the value of. The count data Xbb is applied to gradation data having an even gradation value, and designates a basic pattern group and an additional pattern group of the gradation register Prg. The frame block counter 49b is a cyclic counter that counts the count over signal of the counter 48b, counts over when the count value reaches 4, initializes the count value to 0, and counts the count over signal, and count data Ybb Represents a value of 0-3. This count data Ybb designates the shift amounts of the basic pattern and the additional pattern. A numerical value of 0 to 31 can be expressed by a combination of Xbb and Ybb, and this numerical value changes every time the frame synchronization signal arrives. Each of the 31 types of gradation patterns having the same expression gradation value but different on / off distributions is represented by the block No. Assigned as. By the above-described counting of the frame synchronization signal by the counters 48b and 49b, the basic pattern by the count data Xbb, the designation of the additional pattern group, and the shift amount by the count data Ybb, the lock Nos. 0 to 31 are represented. Are allocated within a wide area section of 8 × 4 pixel blocks.

  If the least significant bit of the gradation data is L (the gradation value is an even number), the selectors 46 and 47 output the count data Xbb and Ybb to the gradation register Prg and the selector 56, so the basic shown in FIG. A high gradation expression is displayed in a wide area section unit of 8 × 4 pixel blocks that designates a pattern group and an additional pattern group. When the least significant bit of the gradation data is H (the gradation value is an odd number), the selectors 46 and 47 output the count data Xba and Yba to the gradation register Prg and the selector 56. Therefore, the basic pattern group shown in FIG. A low gradation expression is displayed in a narrow area section unit composed of 4 × 4 pixel blocks.

  The selector 57 outputs the 2-byte pixel block data Dbs output from the selector 56 to the output control 70 one bit at a time in synchronization with the image synchronization signal. Serial output. That is, the pixel number data Xp representing the horizontal pixel position in the pixel block of the horizontal pixel counter 44 and the pixel (line) number representing the vertical pixel (line) position in the pixel block of the vertical pixel counter 45. The encoder 58 encodes the combination of data Yp (pixel position in the pixel block) into bit position data Np (0 to 15) in the 2-byte pixel block data group shown in FIG. 6B. The selector 57 outputs the bit data Dp designated by the bit position data Np in the 2-byte pixel block data group. The output control 70 serially outputs the bit data Dp to the LCD 11 in synchronization with the display raster scan of the LCD 11.

  A gradation control method using a gradation on / off pattern will be described below. FIG. 11B shows 16 blocks for 9/32 gradations (gradation 9 of 32 gradations) using the basic gradation on / off pattern. When performing gradation control, the 9/32 gradation is composed of four types of patterns, so the gradation of each pixel is controlled by the number of times of lighting in 16 frames, and flicker is not generated. A method of performing lighting control in matrix units is used. In order to complete gradation control in 16 frames, 16 types of 4 × 4 pixel patterns are required, but in the basic gradation on / off pattern, there are four types of GPTNA, GPTNB, GPTNC, and GPTND. From the four types of patterns, it is necessary to create the remaining 12 types of on / off patterns. The 16 types of 4 × 4 pixel patterns at this time are defined as block 0 to block 15, and a method for creating block 0 to block 15 will be described below.

For 9/32 gradation (odd gradation) display data, from the basic gradation on / off pattern stored in the gradation pattern register Prg,
For blocks 0, 4, 8, and 12, the GPTNA09 pattern is
Blocks 1, 5, 9, and 13 are GPTN09 patterns,
For blocks 2, 6, 10, and 14, the GPTNC09 pattern is
The GPTN09 pattern is applied to blocks 3, 7, 11, and 15, respectively.

In block 0, the GPTNA09 pattern held in the gradation pattern register Prg is applied as it is to generate a 4 × 4 pixel block.
In block 1, the GPTN09 pattern is applied as it is to generate a gradation pattern.
In block 2, the GPTNC09 pattern is applied as it is to generate a gradation pattern.
In block 3, the GPTN09 pattern is applied as it is to generate a gradation pattern.

In block 4, a vertical column on the left side of the GPTNA09 pattern is moved to the right side to generate a gradation pattern.
In block 5, the vertical column on the left side of the GPTNB09 pattern is moved to the right side to generate a gradation pattern.
In block 6, the vertical column on the left side of the GPTNC09 pattern is moved to the right side to generate a gradation pattern.
In block 7, the vertical column on the left side of the GPTND09 pattern is moved to the right side to generate a gradation pattern.

In block 8, the two vertical columns on the left side of the GPTNA09 pattern are moved to the right side to generate a gradation pattern.
In block 9, the vertical two columns on the left side of the GPTN09 pattern are moved to the right side to generate a gradation pattern.
In block 10, the two vertical columns on the left side of the GPTNC09 pattern are moved to the right side to generate a gradation pattern.
In block 11, the two vertical columns on the left side of the GPTND09 pattern are moved to the right side to generate a gradation pattern.

In block 12, the vertical three columns on the left side of the GPTNA09 pattern are moved to the right side to generate a gradation pattern.
In block 13, the three vertical columns on the left side of the GPTN09 pattern are moved to the right side to generate a gradation pattern.
In block 14, the three vertical columns on the left side of the GPTNC09 pattern are moved to the right side to generate a gradation pattern.
In block 15, the three vertical columns on the left side of the GPTND09 pattern are moved to the right side to generate a gradation pattern.

  In this way, 16 4 × 4 pixel blocks are generated based on the gradation patterns of GPTNA09, GPTNB09, GPTNC09, and GPTND09. For the other odd-numbered gradations in 32 gradations, blocks 0 to 15 are generated in the same manner as in the 9/32 gradation.

  FIG. 12 shows a wide-range display control method using a 4 × 4 pixel block. After the gradation patterns of block 0 to block 15 are created, display control is performed on the display screen. The 4 × 4 pixel block 0 to block 15 created as described above are used as a unit for a wide range of display control. First, in the first frame (first frame), block 0 is arranged in the entire display area. In the next second frame, block 1 is arranged in the entire display area. In the following, the number of blocks is sequentially increased as the number of frames increases, such as block 2 for the entire display area in the third frame and block 3 for the entire display area in the fourth frame. In the last 16th frame, the block 15 is arranged in the entire display area, and the entire display area can be used once for blocks 0 to 15 over 16 frames. A display screen is created in the display unit as described above.

  13 shows a wide range display of 9/32 gradations (gradation 9 of 32 gradations) displayed by the display control method of FIG. 12, and FIG. 14 shows 4 × 4 displayed by the display control of FIG. The number of 16-frame lighting times in a pixel is shown. When the display control method in a wide range is displayed using blocks 0 to 15 of the gradation pattern, the 16 × 16 pixel matrix is displayed as shown in FIG. Finally, the number of times each pixel is lit is 5/16 times for 9/32 gradation, and all the pixels of 4 × 4 pixels are lit 5/16 times.

  FIG. 15 shows 32 blocks for 8/32 gray levels using basic and additional gray on / off patterns. In performing gradation control, since 8/32 gradations are composed of eight patterns, the gradation of each pixel is controlled by the number of times of lighting in 32 frames, and flicker is not generated. A method of performing lighting control in matrix units is used. In order to complete gradation control in 32 frames, 32 types of 4 × 4 pixel patterns are required. However, in the basic gradation on / off pattern, GPTNA, GPTNB, GPTNC, GPTND, GPTNE, GPTNF, GPTNG Since there are 8 types of GPTNH, it is necessary to create the remaining 24 types of on / off patterns from these 8 types of patterns. The 32 types of 4 × 4 pixel patterns at this time are defined as block 0 to block 31, and a method for creating block 0 to block 31 will be described below.

When 32-gradation control is selected, from the basic and additional gradation on / off patterns held in the gradation pattern register Prg for display data of 8/32 gradations (even gradations),
Blocks 0, 8, 16, and 24 have GPTNA08 pattern,
For blocks 1, 9, 17, and 25, the GPTNB08 pattern is
Blocks 2, 10, 18, and 26 have GPTNC08 pattern,
Blocks 3, 11, 19, and 27 have GPTND08 patterns,
Blocks 4, 12, 20, and 28 contain the GPTNE08 pattern,
Blocks 5, 13, 21, and 29 have GPTNF08 pattern,
For blocks 6, 14, 22, and 30, the GPTNG08 pattern is
The GPTNH08 pattern is applied to blocks 7, 15, 23 and 31, respectively.

In block 0, the GPTNA08 pattern held in the gradation pattern register Prg is applied as it is to generate a 4 × 4 pixel block.
In block 1, the GPTNB08 pattern is applied as it is to generate a gradation pattern.
In block 2, the GPTNC08 pattern is applied as it is to generate a gradation pattern.
In block 3, the GPTND08 pattern is applied as it is to generate a gradation pattern.

In block 4, the GPTNE08 pattern is applied as it is to generate a gradation pattern.
In block 5, the GPTNF08 pattern is applied as it is to generate a gradation pattern.
In block 6, the GPTNG08 pattern is applied as it is to generate a gradation pattern.
In block 7, the GPTNH08 pattern is applied as it is to generate a gradation pattern.

In block 8, the vertical column on the left side of the GPTNA08 pattern is moved to the right side to generate a gradation pattern.
In block 9, the vertical column on the left side of the GPTNB08 pattern is moved to the right side to generate a gradation pattern.
In block 10, the vertical column on the left side of the GPTNC08 pattern is moved to the right side to generate a gradation pattern.
In block 11, the vertical column on the left side of the GPTND08 pattern is moved to the right side to generate a gradation pattern.

In block 12, the vertical column on the left side of the GPTNE08 pattern is moved to the right side to generate a gradation pattern.
In block 13, the vertical column on the left side of the GPTNF08 pattern is moved to the right side to generate a gradation pattern.
In block 14, the vertical column on the left side of the GPTNG08 pattern is moved to the right side to generate a gradation pattern.
In block 15, the vertical column on the left side of the GPTNH08 pattern is moved to the right side to generate a gradation pattern.

In block 16, the two vertical columns on the left side of the GPTNA08 pattern are moved to the right side to generate a gradation pattern.
In block 17, the two vertical columns on the left side of the GPTNB08 pattern are moved to the right side to generate a gradation pattern.
In block 18, the two vertical columns on the left side of the GPTNC08 pattern are moved to the right side to generate a gradation pattern.
In block 19, the two vertical columns on the left side of the GPTND08 pattern are moved to the right side to generate a gradation pattern.

In block 20, the two vertical columns on the left side of the GPTNE08 pattern are moved to the right side to generate a gradation pattern.
In block 21, the two vertical columns on the left side of the GPTNF08 pattern are moved to the right side to generate a gradation pattern. ,
In block 22, the two vertical columns on the left side of the GPTNG08 pattern are moved to the right side to generate a gradation pattern.
In block 23, the two vertical columns on the left side of the GPTNH08 pattern are moved to the right side to generate a gradation pattern.

In block 24, the three vertical columns on the left side of the GPTNA08 pattern are moved to the right side to generate a gradation pattern.
In block 25, the three vertical columns on the left side of the GPTNB08 pattern are moved to the right side to generate a gradation pattern.
In block 26, the vertical three columns on the left side of the GPTNC08 pattern are moved to the right side to generate a gradation pattern.
In block 27, the three vertical columns on the left side of the GPTND08 pattern are moved to the right side to generate a gradation pattern.

In block 28, the three vertical columns on the left side of the GPTNE08 pattern are moved to the right side to generate a gradation pattern.
In block 29, the three vertical columns on the left side of the GPTNF08 pattern are moved to the right side to generate a gradation pattern.
In block 30, the three vertical columns on the left side of the GPTNG08 pattern are moved to the right side to generate a gradation pattern.
In block 31, the three vertical columns on the left side of the GPTNH08 pattern are moved to the right side to generate a gradation pattern.

  In this way, 32 4 × 4 pixel blocks are generated based on the respective gradation patterns of GPTNA08, GPTNB08, GPTNC08, GPTND08, GPTNE08, GPTNF08, GPTNG08, and GPTNH08. For the other even gradations in 32 gradations, blocks 0 to 31 are generated in the same manner as in the 8/32 gradation.

  FIG. 16 shows a wide range display of 8/32 gradations, and FIG. 17 shows the number of times of 32 frame lighting with 4 × 4 pixels. When display control in a wide range is displayed using the gradation pattern blocks 0 to 31, a 16 × 16 pixel matrix is displayed as shown in FIG. 16. Eventually, the number of times each pixel is lit is 9/32 in 8/32 gradation, and all the pixels of 4 × 4 pixels are lit 9/32 times. When 16 gradation control is selected by the 16/32 gradation switching control unit 2-2, blocks 0 to 15 are generated using the same method as the odd gradation in the 32 gradation, and the display control is performed. By performing the above, 16 gradations are expressed.

  In the embodiment shown in FIG. 5, the pixel block data a to p are output from the selector 57 bit by bit in synchronization with the pixel synchronization signal, but the display data is the count data Xa (one frame) of the horizontal block counter 67. Since one is read from the VRAM 7 by being accessed by the count data ya (representing the vertical pixel block number on one frame) of the vertical block counter 68 and the VRAM 7. One display data A to be read corresponds to a 4 × 4 display pixel of the LCD 11. If one display data A is assumed to be associated with one display pixel, the display is enlarged 4 × 4 times the assumed screen size. In order to make this display 1 time, the horizontal block counter 67 is changed to a horizontal pixel counter that counts the pixel synchronization signal and is cleared by the horizontal synchronization signal, or changes the count clock to the pixel synchronization signal and Change the clear signal to a horizontal sync signal, and further change the vertical block counter 68 to a vertical pixel counter that counts the horizontal sync signal and is cleared by the vertical sync signal, or changes the count clock to a horizontal sync signal and Change the clear signal to the vertical sync signal.

  FIG. 18 shows a second embodiment applied to R, G, B color display. This is because the LCDC 6 of the first embodiment shown in FIG. 5 is provided with 16/32 gradation switching control 61 and halftone processing 50, which are roughly one set each for R, G and B, for a total of three sets. In addition, the G phase shift value register 64 and the B phase shift value register 65 are added, and in the G halftone process, the count data 0 to Xb, Yb (represented by the phase shift values of the G phase shift value register 64 are represented. The value of 15) is shifted, and the value of Xb, Yb (count data 0 to 15 represented by Xb, Yb) is shifted by the amount of the phase shift value of the B phase shift value register 65 in the B halftone process. Therefore, in this embodiment, the supply of the frame synchronization signal is delayed by the phase shift value of the G phase shift value register 64 from the start of the supply to the R halftone process, and the supply of the frame synchronization signal is started to the G halftone process. The G halftone process and B phase shift value register 64 are provided with respective delay circuits that are delayed by the phase shift value of the value register 64 and started to be supplied to the B halftone process.

  At the time of color display, display data in which R (red) is 5 bits, G (green) is 6 bits, and B (blue) is 5 bits from the MSB side of 16 bits / pixel is stored in the VRAM 7. The display data read from the VRAM 7 is divided into the image data separation 60 by dividing R (red) into 5 bits, G (green) into 6 bits, and B (blue) into 5 bits. The data is output to the pattern register 3 as 5-bit gradation data Br, Bg, Bb.

  The halftone processing addressed to each group (each color) of the halftone processing 50 performs the pattern data read out output described above with reference to FIGS. In addition, a delay corresponding to the phase shift value of the G phase shift value register 64 is set to a halftone for G so that the tone on / off patterns (pixel block pattern data) of the R, G, and B colors are not the same. In addition to the processing, a delay corresponding to the phase shift value of the B phase shift value register 65 is added to the halftone processing for B so that the block numbers designated between the colors are different.

  FIG. 19 shows a block number shift in a section linked with frame switching in color display. In the illustrated example, the phase shift value of the G phase shift value register 64 is 5 and the phase shift value of the B phase shift value register 65 is 10. The arrangement of block 0 to block 15 in the R display control is the same as in FIG. In the display control of G, when the phase shift value 5 is set in the G phase shift value register 64, the block 5 is arranged at the left end of the first row of the section, and the blocks 6 and 5 are arranged. The seventh and fourth lines are arranged sequentially. As for the arrangement of blocks 0 to 15 in the display control of B, when the phase shift value 10 is set in the B phase shift value register 65, the block 10 is arranged at the left end of the first row of the section. And up to the fourth line. By doing so, the R, G, B gradation on / off patterns at the arrangement positions of the blocks are all different patterns at the same time point. Other configurations and functions of the second embodiment are the same as those of the first embodiment shown in FIGS.

  FIG. 20 shows an outline of a functional configuration of the LCDC 6 of the third embodiment. In the third embodiment, the horizontal shifter 55a of the first embodiment is changed to the vertical shifter 55b, and the pattern corresponding to the gradation value of the basic pattern group is changed. Other configurations are the same as those of the first embodiment shown in FIGS. Below, a different part is demonstrated.

  The vertical shifter 55b shifts the basic pattern by 1 pixel in the y direction for shifting the internal data by 1 pixel in the vertical y direction, 2 pixels in the y direction for shifting 2 pixels in the vertical y direction, and 3 pixels in the vertical y direction. The y-direction three-pixel shift is performed, and both shifts are performed by shifting the data position of the basic pattern data of the 2-byte configuration by the above-described pixel by electric lead wiring, as in the rotator 55 of the first embodiment. It is to be replaced. The count data Yb of the counter 49 specifies the shift amount. That is, Yb = 0 is the vertical y-direction pixel shift amount 0, Yb = 1 is the vertical y-direction pixel shift amount 1, Yb = 2 is the vertical y-direction pixel shift amount 2, and Yb = 3 is the vertical y-direction pixel shift amount. The quantity 3 is specified respectively.

  The display data stored in the VRAM 7 and read out by the LCDC 6 has a 16-bit (2 bytes) configuration as in the first embodiment, and monochrome display gradation data is stored in the 16-bit LSB side 5 bits during monochrome display. . The image data separator 60 extracts the 16-bit LSB side 4 bits read from the VRAM 7 as gradation data and outputs it as the address designation data to the pattern register Prg.

  Even if the vertical shifter 55b of the third embodiment is used, a color gradation display device similar to that of the second embodiment can be configured.

  FIG. 21 shows an outline of a functional configuration of the LCDC 6 of the fourth embodiment. In the fourth embodiment, it is possible to select the output mode of only the light emission pattern data of the basic and additional pattern groups that does not use the horizontal shifter 55a, and the output mode of the basic, additional pattern group, and shift pattern group of the first embodiment. It is a thing. In the fourth embodiment, this selection is realized by a signal switching 66 that selectively fixes the selection signal Yb supplied to the selector 56 to data representing 0. The selection signal Yb supplied from the frame block counter 49a or 49b to the selector 56 via the selector 47 is 2-bit data indicating a numerical value of 0 to 3, and when it is data representing 0, the selector 56 The 16-bit (2-byte) data of one pixel block output by Prg is output to the subsequent selector 57 as it is.

  When the CPU 1 gives a signal L for designating the output mode of only the light emission pattern data of the basic pattern group to the signal switching 66, the signal switching 66 applies 2 bits of the selection signal Yb which is 2-bit data to each bit line. Change to L via the connected diode. Thereby, Yb given to the selector 56 is fixed to represent 0, and the selector 56 steadily outputs the 16-bit (2-byte) data of one pixel block output from the pattern register Prg to the subsequent selector 57 as it is. Output. When the CPU 1 sets the signal to be given to the signal switching 66 to H, Yb given to the selector 56 is 2-bit data that the frame block counter 49a or 49b gives to the selector 56 via the selector 47, and the row number in the section. Each time the line number in the section is switched, the value changes, and the selector 56 sequentially shifts the basic pattern data of one pixel block output from the pattern register Prg, and 1 or 2 obtained by horizontally shifting it. Data 2 shifted horizontally and data 3 shifted horizontally 3 pixels are output in this order. Note that the L / H of the signal that the CPU 1 gives to the signal switching 66 is selected and specified by the user on the input screen of the initial setting menu of the operation board in the initial setting menu that the user operates by operating the initial setting key 18.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a longitudinal sectional view showing an outline of a mechanism of a multi-function copying machine MF1 including an operation board 10 equipped with a gradation display device according to a first embodiment of the present invention. FIG. 2 is an enlarged plan view showing a part of an upper surface of an operation board 10 of the copying machine MF1 shown in FIG. (A) is an enlarged plan view showing a “read” input screen displayed on the liquid crystal display 11 of the operation board 10 when “read” is input to the operation board 10, and (b) is an image obtained by reading a document. It is an enlarged plan view which shows the image display screen which displayed. 3 is a block diagram showing an outline of a configuration of an electric system of the operation board 10. FIG. FIG. 5 is a block diagram showing an outline of a functional configuration of an LCDC (display controller) 6 shown in FIG. 4. (A) is a plan view of a bit distribution pattern in which each display bit addressed to each pixel in one pixel block is indicated by symbols a to p, and (b) is a bit a addressed to one pixel block in (a). FIG. 6C is a block diagram showing a bit arrangement in memory read / write and data transfer, and FIG. 6C is a block diagram showing a configuration of the data conversion 62 shown in FIG. FIG. 6 is a block diagram showing pixel block data of basic and additional pattern groups stored in the ROM 2 shown in FIG. 4 and written in the pattern register Prg shown in FIG. And assigned to gradation values 1-12. FIG. 6 is a block diagram showing pixel block data of basic and additional pattern groups stored in the ROM 2 shown in FIG. 4 and written in the pattern register Prg shown in FIG. And assigned to gradation values 13 to 24. FIG. 6 is a block diagram showing pixel block data of basic and additional pattern groups stored in the ROM 2 shown in FIG. 4 and written in the pattern register Prg shown in FIG. And assigned to gradation values 25-30. It is a table | surface which shows the identification symbol of the pattern data in the basic pattern group allocated to the gradation value. (A) is a plan view showing a rotated bit arrangement obtained by shifting the bit arrangement in one pixel block shown in (a) of FIG. 6 by one horizontal shift, two horizontal shifts, and three horizontal shifts. b) indicates the pixel block data No. 1 output for the gradation value 9; It is a top view which shows data. FIG. 13 is a plan view showing an arrangement of block numbers in a section represented by count data Xba and Yba of the counters 48a and 49a shown in FIG. 5, and each block number on FIG. 12 is 16 shown in FIG. Each pattern of the seed pattern group is represented. The basic pattern data of the basic pattern group read to the gradation value 5 from the pattern register Prg shown in FIG. 5 and the rotated pattern data obtained by rotating the basic pattern group include 16 types, one section (4 × 4 blocks). It is a block diagram which shows the pattern group arranged in the inside. 13 is a chart showing a gradation ratio (number of lit pixels / total number of pixels) of each pixel block expressed in a 16-frame period by switching display data distribution in conjunction with frame switching shown in FIG. It is a top view which shows the pattern addressed to each block of an 8x4 pixel block when a gradation value is an even number (8). It is a top view which shows the display data distribution addressed to the gradation value 9 in 1 section produced | generated by the 0-31 block number arrangement | sequence, "1" instruct | indicates lighting of 1 pixel, "0" instruct | indicates light extinction To do. FIG. 17 is a chart showing a gradation ratio (number of lit pixels / total number of pixels) of each pixel block expressed in a 16-frame period by switching display data distribution in conjunction with frame switching shown in FIG. 16. It is a block diagram which shows the principal part of the color gradation display apparatus of 2nd Example of this invention. It is a top view which shows the arrangement | sequence of the block number in a section in each of the R, G, B halftone process shown in FIG. It is a block diagram which shows the outline | summary of the function structure of LCDC (display controller) 6 of 3rd Example. It is a block diagram which shows the outline | summary of the function structure of LCDC (display controller) 6 of 3rd Example.

Explanation of symbols

11: LCD touch panel

Claims (14)

A two-dimensional display means having a display surface that expands in the horizontal and vertical directions, and performing display / non-display on the display surface in units of pixels of the ON / OFF signal section;
In the pixel block composed of a plurality of pixels in the horizontal and vertical directions, the distribution of the on / off signal instructing the light emission / non-light emission of each pixel and the display gradation of the pixel block are represented, each representing a different gradation. A gradation memory for storing a basic pattern group composed of a plurality of light emission pattern data and an additional pattern group addressed to either the odd value or the even value of the gradation;
Means for reading light emission pattern data corresponding to the gradation data from the gradation memory;
Means for counting a frame synchronization signal and generating a light emission pattern shift instruction signal corresponding to the count value;
Pattern changing means for shifting light emission pattern data read from the gradation memory in a horizontal direction or a vertical direction by the number of pixels specified by the shift instruction signal; and
Means for outputting an ON / OFF signal of the light emission pattern data shifted by the pattern changing means to the two-dimensional display means;
A gradation display device comprising: Each of the basic pattern group and the additional pattern group is a plurality of groups having different on-off signal distribution patterns;
The gray scale display device further comprises means for counting a frame synchronization signal and generating a group instruction signal corresponding to the count value;
The means for reading out the light emission pattern data reads out light emission pattern data corresponding to gradation data of a basic pattern group or an additional pattern group designated by the group instruction signal from the gradation memory. Tone display device. The light emitting one of the pattern shift command signal means for generating means and a group designating signal for generating a first circulation counter that counts also initializes the count data when it counts up to the set value by counting the frame synchronizing signal, 3. The gradation display device according to claim 2, wherein the other is a second circulation counter that counts up to the set value of the first circulation counter and initializes the count data when the count value is counted up. The first circulation counter counts when the frame synchronization signal is counted to the set value for narrow gradation in the narrow gradation display representing a narrow range of gradations using only the basic pattern group for gradation expression with a small gradation value. Frame synchronization in a first gradation counter for narrow gradation that initializes and counts data, and in a wide gradation display that expresses a wide range of gradations using a large number of gradation values and the basic pattern group and the additional pattern group for gradation expression A second circulation counter for wide gradation that counts the signal and initializes the count data when it counts up to the set value for wide gradation; the second circulation counter is also for the narrow gradation of the first circulation counter for narrow gradation Counting up to the set value and counting to the set value initializes the count data and counts again. The second gradation counter for wide gradation that counts up to the set value for wide gradation of the second circulation counter for narrow gradation and the first circulation counter for wide gradation and counts up to the set value and counts again. The gradation display device according to claim 3, further comprising a circulation counter.   5. The count value of the wide gradation circulation counter is assigned to the odd or even value of the gradations to which the additional pattern group is addressed, and the count value of the narrow gradation circulation counter is assigned to the other gradation values; The gradation display device described.   The means for reading the light emission pattern data corresponding to the gradation data from the gradation memory stores the narrow range gradation data representing a narrower range of gradations than the wide range gradation represented by the gradation data. 6. A gradation display device according to claim 1, further comprising means for converting into gradation data representing a key. The apparatus further comprises means for selecting an output of only the light emission pattern data of the basic pattern group and the additional pattern group not using the pattern changing means and an output using the light emission pattern data shifted by the pattern changing means. 6. The gradation display device according to any one of 6. It said pattern changing means, the number of pixels corresponding to the light emitting pattern shift instruction signal is the horizontal shifting means for converting the light emission pattern data obtained by shifting the ON / OFF signal in the horizontal direction; any of claims 1 to 7 1 The gradation display device described in one. Said pattern changing means, the number of pixels corresponding to the light emitting pattern shift instruction signal, the vertical (y) direction on / off signal is a vertical shifting means for converting the shifted emission pattern data; of claims 1 to 7 The gradation display device according to any one of the above. Means for reading out light emission pattern data corresponding to gradation data is provided for each display of R, G, and B gradation data, for a total of three sets; in addition, at least two sets are basic patterns. The color gradation display device according to claim 1, further comprising means for adding a phase shift value for making the number of pixels of the group or the shift different. An imaging device that converts a light image into image data representing it; and
An optical image reading apparatus comprising: the gradation display device according to claim 1, which displays image data generated by the imaging device on the two-dimensional display unit. A document scanner that reads an image of the document and generates image data representing the image; and
11. A document reading apparatus comprising: the gradation display device according to claim 1, wherein image data generated by the document scanner is displayed on the two-dimensional display unit. The document reading device according to claim 12;
A printer that forms an image represented by the image data on paper; and
An image forming apparatus comprising: image data processing means for converting image data generated by the document reading apparatus into image data suitable for image forming characteristics of the printer. The image forming apparatus according to claim 13 , wherein the gradation display device is in an operation terminal that gives a user instruction to the image forming apparatus.

Images