JP2006126475A - Liquid crystal display and driving method of the liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display whose heat generation is suppressed by reducing the power consumption, while suppressing deterioration in the image quality, such as flickers. <P>SOLUTION: Used is the liquid crystal display, equipped with a liquid crystal control section 5 which controls a liquid crystal panel 4. The liquid crystal control section 5 is equipped with an image deciding circuit 11 which compares the gradations of input image data by pixels with a reference gradation and a system determining section 12 which determines, as a selective inversion driving system, an inversion driving system for the polarity, when the input image data are displayed on a liquid crystal panel 4 by a plurality of pixels less than one frame containing the pixels based on the comparison results. Here, the reference gradation is set, preferably, to a border gradation between gradations with which the picture quality of the liquid crystal panel 4 is easy to deteriorate and gradations, with which the image quality is less likely to deteriorate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device and a driving method of the liquid crystal display device.

  In recent years, a large liquid crystal panel of 30 inches or more has been developed as a liquid crystal display device for TV. As a method for reducing the cost of the liquid crystal display device, it is considered to increase the number of output terminals of one data driver to reduce the number of data drivers.

  As a related technique, Japanese Unexamined Patent Application Publication No. 2003-337577 discloses a technique of a liquid crystal display device and a driving method thereof. The driving method of the liquid crystal display device includes a first stage to a third stage. In the first stage, the liquid crystal display device is driven by the first dot inversion method in which the setting polarities of adjacent pixels are opposite to each other. In the second step, it is determined whether or not a pattern in which the gradation difference between two adjacent identical color pixels in a predetermined number of consecutive pixels exceeds a predetermined range occupies a predetermined area or more in all pixels. In the third step, the first dot inversion method is changed to the second dot inversion method if the pattern occupies the predetermined area or more. The second dot inversion method is a method in which two adjacent gate lines connected to two adjacent pixels are set as one set of gate lines, and the polarity set for the gate lines is alternately inverted for each set. May be.

JP 2003-337577 A

  The amount of heat generated by the data driver increases as the power consumption increases with the increase in the size of the liquid crystal panel and the number of output terminals of the data driver increases. Therefore, it is difficult to adopt a dot inversion driving method with high power consumption but high power consumption as a driving method of the liquid crystal panel. However, reducing the number of inversions may cause image quality degradation such as occurrence of flicker. A liquid crystal display device and a driving method of the liquid crystal display device that reduce power consumption and heat generation and suppress occurrence of flicker are desired.

  Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method of the liquid crystal display device that can reduce power consumption while suppressing deterioration in image quality.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the best mode for carrying out the invention. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of the claims and the best mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

Therefore, in order to solve the above problem, the liquid crystal display device of the present invention includes a liquid crystal control unit (5 / 5a) for controlling the liquid crystal panel (4). The liquid crystal control unit (5 / 5a) includes an image determination circuit (11) that compares the gradation for each pixel in the input image data with the reference gradation, and, based on the comparison result, less than one frame including the pixel. For each of the plurality of pixels, a method determining unit (12) is provided that determines a polarity inversion driving method when the input image data is displayed on the liquid crystal panel (4) as a selective inversion driving method. Here, it is preferable that the reference gradation is set at a boundary gradation between a gradation in which the image quality is likely to deteriorate and a gradation in which the image quality is unlikely to deteriorate in the liquid crystal panel (4).
In the present invention, the polarity inversion driving method is changed based on the gradation of the input image. That is, for input image data having gradations that tend to degrade image quality, a drive method that does not affect image quality is used to suppress image quality degradation. For input image data with gradations that are unlikely to degrade image quality, a drive method that suppresses power consumption is used to reduce power consumption. By doing in this way, power consumption can be reduced as a whole while suppressing deterioration of image quality. By performing such an operation for each pixel of less than one frame, the effect can be further increased.

  According to the present invention, it is possible to reduce power consumption and suppress heat generation while suppressing deterioration of image quality such as occurrence of flicker.

  Hereinafter, embodiments of a liquid crystal display device and a driving method of the liquid crystal display device of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
First, the configuration of the first embodiment of the liquid crystal display device of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the first embodiment of the liquid crystal display device of the present invention. The liquid crystal display device 1 includes a data driver 2, a gate driver 3, a liquid crystal panel 4, an LCD controller 5, and a reference gradation voltage generator 6.

  The LCD controller 5 receives input image data 28 and a display control signal 29 from the image drawing unit 7 (example: CPU). The input image data 28 includes gradation data (RGB signals) for each pixel. The display control signal 29 includes a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and a data enable signal. Based on the input image data 28 and the display control signal 29, the image data 21 and the data side control signal 22 are output to the data driver 2 and the gate side control signal 23 is output to the gate driver 3, respectively. In addition to the normal data side control signal, the data side control signal 22 includes a control signal indicating whether the 2H dot inversion driving method or the dot inversion driving method is used for a plurality of pixels of less than one frame. The gate side control signal 23 includes a normal gate side control signal.

The LCD controller 5 includes an image determination unit 11, a method determination unit 12, and a line memory 13.
The image determination unit 11 compares the gradation of the input image data 28 with the set gradation for each pixel in the input image data 28 and determines whether the gradation of the input image data 28 is higher or lower than the set gradation. To do. The comparison result (determination result) is output to the method determination unit 12. The input image data 28 is output to the line memory 13.

  The method determining unit 12 determines an inversion driving method for displaying input image data on the liquid crystal panel 4 for each of a plurality of pixels of less than one frame based on the comparison result. “A plurality of pixels less than one frame” is exemplified by pixels for a plurality of lines such as pixels for four lines. The determination method is performed as follows, for example. For example, when the liquid crystal panel is normally white, the gradation of the predetermined number (or percentage) of the input image data 28 among “a plurality of pixels less than one frame” is lower than the set gradation (low transmittance). Alternatively, the 2H dot inversion driving method is used in the same case, and the dot inversion driving method is used in the high case. On the other hand, when the liquid crystal panel is normally black, when the gradation of the input image data 28 is higher than the set gradation (high transmittance) or the same, the 2H dot inversion driving method is used, and when it is lower, the dot inversion driving method is used. And That is, the number of inversions in the gradation region where a high voltage is applied to the liquid crystal panel is determined to be small. The predetermined number is determined by design, and is 1, for example.

  The line memory 13 temporarily stores input image data 28 corresponding to a plurality of lines determined by the method determination unit 12. For example, when the method determination unit 12 determines each pixel for four lines, the data for four lines is stored. Then, after storing the input image data 28 corresponding to a plurality of lines, the input image data 28 is output as the image data 21 to the data driver 13. The line memory 13 is provided for timing adjustment with the data-side control signal reflecting the determination result when the image data 21 is output to the data driver 13.

The reference gradation voltage generator 6 generates a gradation voltage corresponding to the gradation of the input image data and outputs it to the data driver 2.
The gate driver 3 controls a plurality of gate lines of the liquid crystal panel 4 based on the gate side control signal 23. However, it may be configured integrally with the LCD controller 5. In that case, the circuit area can be reduced.
The data driver 2 controls a plurality of data lines of the liquid crystal panel 4 based on the input image data 21, the data side control signal 22 and the reference gradation voltage 24. However, it may be configured integrally with the LCD controller 5. In that case, the circuit area can be reduced.
The liquid crystal panel 4 displays an image by controlling a plurality of gate lines and a plurality of data lines by the data driver 2 and the gate driver 3, respectively.

Here, the concept of the liquid crystal display device and the driving method of the liquid crystal display device of the present invention will be described.
The set gradation in the image determination unit 11 will be described. FIG. 2 is a graph showing the concept of the liquid crystal display device and the driving method of the liquid crystal display device of the present invention. This graph shows the voltage-transmittance characteristics of the liquid crystal in the liquid crystal panel 4. The vertical axis indicates the voltage applied to a certain pixel of the liquid crystal panel, and the horizontal axis indicates the light transmittance in the pixel. Here, an example of normally white will be described. The voltage-transmittance characteristics of the liquid crystal change abruptly around the middle gradation (about 2 to 3 V in the figure). However, in the vicinity of white (about 0 to about 2 V) and black (about 3 to 5 V), it changes gently. That is, in the vicinity of the intermediate gradation, the transmittance fluctuates even for a small voltage change, so that the flicker is easily seen. On the other hand, in the vicinity of white and black, the transmittance hardly changes with a small voltage change, and the flicker is difficult to see. Further, the gradation voltage causing power consumption and heat generation of the data driver 2 is near black, which is a high voltage and requires charging / discharging.

  From the above, in the liquid crystal display device and the driving method of the liquid crystal display device of the present invention, 2H dot inversion driving with a small number of polarity inversions in a gray-scale region near black where high voltage is required to charge and discharge and flicker is difficult to see. The method. Then, the dot inversion driving method is performed in an intermediate gradation region or less where flicker is easily visible. A gradation for switching between the dot inversion driving method and the 2H dot inversion driving method is an inversion switching gradation as shown in FIG. This inversion switching gradation is a set gradation in the image determination circuit 11. The set gradation is determined by design for each liquid crystal display device.

  Thus, according to the present invention, it is possible to reduce power consumption while suppressing deterioration in image quality such as flicker. It is preferable that the power consumption can be reduced because heat generation of each part such as the data driver 2 can be suppressed.

  It should be noted that in the gradation region near white where flicker is difficult to see, the dot inversion method with good image quality may be used, or the 2H dot inversion driving method with low power consumption may be used. That is, it is possible to provide a plurality of set gradations and use a plurality of driving methods. In that case, it is possible to carry out more detailed and accurate control for suppressing power consumption while preventing deterioration of image quality.

  Here, the 2H dot inversion driving method and the dot inversion driving method are used. However, other methods such as a 3H dot inversion driving method and a dot inversion driving method can also be used. When a 3H dot inversion driving method or a higher dot inversion driving method (example: 4H dot inversion driving method) is used, power consumption can be further reduced, which is more preferable.

  In the case of normally black, the relationship between white and black is reversed from the above case. That is, it becomes black (about 0 to about 2 V) and white (about 3 to 5 V), and it is near white that needs to be charged and discharged at a high voltage.

Next, the operation (driving method of the liquid crystal display device) of the first embodiment of the liquid crystal display device of the present invention will be described.
FIG. 3 is a flowchart showing the operation of the first embodiment of the liquid crystal display device of the present invention. Here, a case where the liquid crystal panel is normally white and the inversion driving method is determined for every four lines (four gate lines) of the horizontal pixel will be described.

(1) Step S01:
The input image data 28 transmitted from the image drawing unit 7 is determined by the image determination unit 11 for each pixel whether or not the gradation is equal to or higher than the set gradation.
(2) Step S02:
The method determination unit 12 determines whether or not the image data whose gradation is equal to or higher than the set gradation is greater than or equal to a predetermined number of pixels in the input image data 28 for four lines.
(3) Step S03:
When there are more than a predetermined number of pixels in the input image data 28 for the four lines, the method determining unit 12 determines the driving method of the input image data 28 for the four lines. The dot inversion driving method is determined.
(4) Step S04:
When the input image data 28 for four lines has no image data having a gradation equal to or higher than the set gradation, the method determining unit 12 determines the driving method of the input image data 28 for four lines. The 2H dot inversion driving method is determined.
(5) Step S05:
The input image data 28 determined by the image determination unit 11 is sequentially stored in the line memory 13. The line memory 13 has four lines corresponding to the number of horizontal pixels of the liquid crystal panel 4 which is a unit for determining the driving method.
(6) Step S06:
The input image data 28 for four lines stored in the line memory 13 is sequentially output to the data driver 2 as the image data 21 after determining the driving method. At the same time, a data-side control signal including a control signal indicating the driving method determined by the method determining unit 12 is output from the LCD controller 5 to the data driver 2. The gate side control signal is output from the LCD controller 5 to the gate driver 3.
(7) Step S07:
The liquid crystal panel 4 is driven by an output signal from the data driver 2 based on the data side control signal and an output signal from the gate driver 3 based on the gate side control signal.

  By such an operation, the liquid crystal display device can be operated.

  FIG. 4 is a conceptual diagram showing the voltage polarity applied to the liquid crystal panel 4 in the present invention. Each square in the liquid crystal panel 4 represents a pixel. “+” Or “−” in the square indicates the voltage polarity in the pixel. The left liquid crystal panel 4 shows odd frames, and the right liquid crystal panel 4 shows even frames.

  In the input image data 28 for four lines, the area where the image data whose gradation is equal to or higher than the set gradation is not more than the predetermined number of pixels (the portion where the pattern is given in the figure) is polarity inverted by the 2H dot inversion driving method. Has been done. On the other hand, polarity inversion is performed by a dot inversion driving method in a region (a portion where no pattern is applied in the drawing) having a predetermined number of pixels or more. That is, this is a driving method in which the dot inversion driving method and the 2H dot inversion driving method are switched in units of four vertical lines.

  However, it is preferable that the image determining unit 11 and the method determining unit 12 determine and switch the polarity inversion method every two frames. That is, one even frame and one odd frame shown in FIG. 4 are taken as a set, and the polarity inversion method is determined and switched for each set. This is because, if the polarity inversion method is switched between dot inversion and 2H dot inversion every frame, there is a possibility that a DC voltage is always applied to the liquid crystal panel and there is a risk of burn-in.

  Here, a case is described in which the inversion driving method is determined for every four horizontal pixel lines (four gate lines), but the number of horizontal pixel lines (the number of gate lines) is not limited to this example. That is, here, the drive method is determined and changed between the dot inversion driving method with a two-line cycle and the 2H dot inversion driving method with a four-line cycle. Therefore, it is preferable to determine and change the driving method in a 4 m line cycle (m is a natural number) that is a common multiple of the 2 line cycle and the 4 line cycle. It is more preferable to determine and change the driving method at the least common multiple of 4 lines with m = 1 as in the present embodiment, since image quality deterioration can be better suppressed.

  With such a configuration and operation of the present invention, it is possible to reduce power consumption and suppress heat generation of each unit such as the data driver 2 while suppressing deterioration in image quality such as flicker.

  Here, for all the pixels, the driving method for inverting the polarity is determined based on the gradation, but the present invention is not limited to this example. For example, the driving method of the present invention may be applied to the G signal pixel of the RGB signals, and the 2H dot inversion driving method may be used for the remaining R and B signals. Since the G signal includes much luminance information, if the present invention is applied to the G signal, it becomes difficult to see the flicker. In this case, as compared with the case where the present invention is applied to all the pixels, the control becomes easier and the power consumption and heat generation are further reduced by using the 2H dot inversion driving method for the remaining R and B signals. can do.

  As the gate driver 2 in the liquid crystal display device of the present invention, for example, a drive circuit of a matrix type liquid crystal display device disclosed in Japanese Patent No. 3056085 can be used.

FIG. 5 is a block diagram showing details of the gate driver 2 in the liquid crystal display device of the present invention. The gate driver 2 of the present invention includes a liquid crystal drive circuit A and switch circuits 204 and 208.
The liquid crystal driving circuit A outputs positive and negative voltages based on the supplied voltage of 1/2 of the supplied liquid crystal driving voltage or the voltage Vcom of the liquid crystal common electrode according to the applied image data. The circuit includes a shift register circuit 201, a data register circuit 202, a latch circuit 203, a level shift circuit 205, a decoder / grayscale voltage selection circuit 206, and an operational amplifier (op amp) 207. It consists of two systems. In the present invention, with reference to the voltage Vcom of the liquid crystal common electrode, a voltage equal to or higher than this voltage value is applied as a positive voltage, a voltage equal to or lower than this voltage value is set as a negative voltage, and is applied while maintaining a positive / negative amplitude relationship. AC drive by doing.

  In response to the output of each stage of the shift register circuit 201, the data register circuit 202 latches n (natural number) -bit image data 21 (D00 to Dxx) to be controlled in parallel. There are two systems, a data register circuit 219 and a data register circuit 220. There are m combinations of the two systems.

  The latch circuit 203 collectively latches n-bit data (image data 21: D00 to Dxx) from the data register circuit 202 in response to a latch signal (hereinafter, “STB signal”). There are two systems, a latch circuit 221 connected to the data register circuit 219 and a latch circuit 222 connected to the data register circuit 220. There are m combinations of the two systems.

  The level shift circuit 205 boosts the n-bit data from the latch circuit 203 to a liquid crystal drive voltage having a different voltage value. Two systems of a high-voltage side level shift circuit 209 and a low-voltage side level shift circuit 210 are provided. There are m combinations of the two systems. In this embodiment, the level shift circuit 209 on the high voltage side is set to boost 3.3V to 10V, for example, and the level shift circuit 210 on the low voltage side is set to boost 3.3V to 5V, for example. However, it is not limited to this step-up rate. As the level shift circuit 205, a conventionally known circuit can be used.

  Based on the control signal from the timing control circuit 215, the switch circuit 204 selects the output of the latch circuit 221 of one system as one of the high voltage side level shift circuit 209 and the low voltage side level shift circuit 210. Connect. At the same time, the output of the latch circuit 222 of the other one system is selectively connected to the other one of the high voltage side level shift circuit 209 and the low voltage side level shift circuit 210.

FIG. 6 is a block diagram illustrating a specific example of switch control of each circuit. Specifically, the switch circuit 204 performs switch control as follows. That is, as shown in FIG. 6 (a), the polarity signal (hereinafter, "POL signal") is at the high level (H) (STB signal = L), the high-pressure side level shift circuit latch circuit 221 at the junction 204 ₁ to 209, respectively connecting the latch circuit 222 at contact 204 ₂ to the level shift circuit 210 of the low-pressure side. On the other hand, as shown in FIG. 6 (b), when the POL signal is at the low level (L) (STB signal = L), in contrast to FIG. 6 (a), the low-pressure side level latch circuit 221 at the junction 204 ₄ a shift circuit 210, respectively connecting the latch circuit 222 at the junction 204 ₃ to the level shift circuit 209 of the high-pressure side. However, the POL signal and STB signal are included in the data side control signal output from the LCD controller 5 to the timing control circuit 215.

  The gradation voltage generation circuit 6 includes two systems of a high voltage side gradation voltage generation circuit 217 and a low voltage side gradation voltage generation circuit 218. The gradation voltage generation circuits 217 and 218 display gradations on the liquid crystal based on the external inputs V0, V1, V2, V3, and V4 and the external inputs V5, V6, V7, V8, and V9 (reference gradation voltage 24), respectively. The gradation voltage to be finely adjusted to 2n value. Also, each of the gradation voltage generating circuits 217 and 218 is adapted to fit the γ curve of the liquid crystal by resistance division based on the external inputs V0, V1, V2, V3, V4 and the external inputs V5, V6, V7, V8, V9. Fine-tune the gradation voltage to a proper resistance ratio.

  The decoder / grayscale voltage selection circuit 206 includes a high voltage side decoder / grayscale voltage selection circuit 211 and a low voltage side decoder / grayscale voltage selection circuit 212. 2n values of the gradation voltages output from the gradation voltage generation circuits 217 and 218 are input as reference voltages S, and these are input to the decoder unit as 2n gradation signals (for example, n = 6 bits of 64 gradation signals). 1 is decoded, is amplified by the operational amplifier OP, and is output to the operational amplifier 207 at the subsequent stage.

  The operational amplifier 207 has two systems of a high voltage side operational amplifier 213 and a low voltage side operational amplifier 214. There are m combinations of the two systems. The high-voltage-side operational amplifier 213 and the low-voltage-side operational amplifier 214 share the voltage to be amplified and output between the high-voltage side and the low-voltage side. The high-voltage side operational amplifier 213 receives an input voltage of 5V to 10V, for example, and inputs 5V to 10V. Amplify to range and output. The low-voltage operational amplifier 14 receives, for example, an input voltage of 0V to 5V, amplifies it in the range of 0V to 5V, and outputs it.

  The switch circuit 208 is shared by the two terminals of the two-system circuit of the liquid crystal drive circuit A, outputs positive and negative voltages in time series to each terminal, and maintains voltages that maintain a positive and negative amplitude relationship between the two terminals. Switch control to output. The switch circuit 208 includes a common terminal switch 208a. The common terminal switch 208a commonly connects all the output terminals Y1 to Ym of the liquid crystal drive circuit A, and connects all the output terminals Y1 to Ym to a voltage that is 1/2 of the liquid crystal drive voltage (1 / 2VLCD (example: 5V)). To. The withstand voltage of the switch circuit 208 directly connected to the liquid crystal is set to be twice or more the threshold voltage value of the liquid crystal.

Referring to FIG. 6, specifically, switch circuit 208 performs switch control as follows. That is, as shown in FIG. 6 (a), when the POL signal is high level (H) (STB signal = L), the high-pressure-side operational amplifier 213 to the output terminal Y1 at the junction 208 _1, the low-pressure-side operational amplifier in contact 208 ₂ 214 are connected to the output terminal Y2. On the other hand, as shown in FIG. 6 (b), when the POL signal is at the low level (L) (STB signal = L), in contrast to FIG. 6 (a), the output terminal of the high-pressure-side operational amplifier 213 in contact 208 ₄ to Y2, to the output terminal Y1 respectively connecting the low-pressure-side operational amplifier 214 in contact 208 _3. Further, as shown in FIG. 6C, when the STB signal is at a high level (H), the common terminal switch 208a (contacts 208 ₅ , 208 ₆ , 208 ₇ ) is turned on regardless of the state of the POL signal. All the output terminals Y1 to Ym of the liquid crystal drive circuit A are connected in common to form a 1 / 2VLCD.

  Next, the power supply voltage of each circuit is shown below. In FIG. 5, the voltages of the data register circuits 219 and 220, the latch circuits 221 and 222, and the switch circuit 204 are limited to the range of 0V to 3.3V, and the high voltage side level shift circuit 209 outputs the input voltage of 0V to 3.3V. The voltage is boosted to 5V-10V, and the low-voltage side level shift circuit 210 boosts the input voltage 0V-3.3V to the output voltage 0V-5V. The voltage of the high voltage side decoder / grayscale voltage selection circuit 211 and the operational amplifier 213 is limited to a range of 5V-10V, and the voltage of the low voltage side decoder / grayscale voltage selection circuit 212 and the operational amplifier 214 is limited to a range of 0V-5V. The voltage of the switch circuit 208 is limited to a range of 0V-10V (the voltage Vcom of the liquid crystal common electrode Vcom = 5V). The voltages applied as external inputs to the high-voltage side and low-voltage side gradation voltage generation circuits 217 and 218 are V0 = 10V, V4 = 5.5V, V5 = 4.5V, V9 = 0V, and V1, V2 , V3, V6, V7, V8 are open.

  Next, the operation of the liquid crystal display device of the present invention using the gate driver 2 of FIG. 5 according to the first embodiment (step S07 in FIG. 3) will be described with reference to FIGS. The case where the image data is 6 bits (64 gradations) will be described as an example.

However, FIG. 7 is a timing chart of each circuit shown in FIG. 7A shows the STB signal, FIG. 7B shows the POL signal, FIG. 7C shows on / off of the contacts 204 ₁ and 204 ₂ of the switch circuit 204, and FIG. 7D shows the contacts 204 ₃ and 204 ₄ of the switch circuit 204. ON / OFF, (e) ON / OFF of the contacts 208 ₁ and 208 ₂ of the switch circuit 208, (f) ON / OFF of the contacts 208 ₃ and 208 ₄ of the switch circuit 208, and (g) of the output terminal Y1. An output signal (h) indicates an output signal of the output terminal Y2.

  The switch circuit 204 and the switch circuit 208 are alternately switched as shown in FIGS. 6A and 6B by the POL signal and the STB signal input to the timing control circuit 215. As a result, positive and negative voltages are alternately applied to the liquid crystal electrodes depending on which side of the two systems of the liquid crystal drive circuit A passes 64 gradation image data.

Further, as shown in FIGS. 6C and 7, the contacts 208 ₁ , 208 ₂ , 208 ₃ are controlled by the switch control of the switch circuit 208 during the period when the STB signal input to the timing control circuit 215 is at the high level (H). , 208 ₄ is turned off, the contacts _{208 5,} 208 6, 208 ₇ is turned on, all the output terminals Y1~Ym 1/2 of the voltage of the liquid crystal drive voltage of the liquid crystal driving circuit a (example: 5V) to reset Is done.

  Further, if the period of the POL signal is set to one line period, the line of the liquid crystal panel 4 is driven by the dot inversion driving method. If the period of the POL signal is set to a two-line period, the line of the liquid crystal panel 4 is driven by the 2H dot inversion driving method.

  The operation will be described in more detail. The data register circuit 219 connected to the output terminal Y1 of the liquid crystal driving circuit A always holds low level (L) data (image data with a constant gradation) and is connected to the output terminal Y2 of the liquid crystal driving circuit A. It is assumed that the data register circuit 220 always holds high level (H) data (image data with a constant gradation).

(A) In the case of the dot inversion driving method In step S02 of FIG. 3, it is determined that the image data whose gradation is equal to or higher than the set gradation in the input image data 28 for four lines is equal to or more than a predetermined number of pixels. Is determined as the dot inversion driving method, the operation is performed at time t = t1 to t5.

(1) Time t = t1 to t3
When the POL signal (FIG. 7B) input to the timing control circuit 215 is at a high level (H) (time t = t1), the switch is switched according to the high level (H) of the STB signal (FIG. 7A). The contacts 208 ₁ , 208 ₂ (FIG. 7 (e)), 208 ₃ , 208 ₄ (FIG. 7 (f)) of the circuit 208 are turned off, and the contacts 208 ₅ , 208 ₆ , 208 ₇ (shown in FIG. (See FIG. 6C).

At this time, in one of the two systems, the contact 204 ₁ (FIG. 7C) of the switch circuit 204 is turned on and the contact 204 ₃ (FIG. 7D) is turned off. Accordingly, the low level (L) data held in the data register circuit 219 is transferred from the latch circuit 221 to the level shift circuit 209 via the switch circuit 204. The gradation voltage 10 V is selected by the decoder / gradation voltage selection circuit 211, and the current is amplified by the operational amplifier 213. When the STB signal (FIG. 7A) is switched to the low level (time t = t2), the contact 208 ₁ (FIG. 7E) of the switch circuit 208 is turned on, and the contacts 208 ₅ and 208 ₆ are turned on. Turns off. As a result, the image data is output to the output terminal Y1 (FIG. 7 (g)) of the liquid crystal drive circuit A via the switch circuit 208. Then, a gradation voltage of 10 V (polarity is plus “+”) having a predetermined voltage value is applied to the liquid crystal panel 4.

On the other hand, in the other of the two systems, the contact 204 ₂ (FIG. 7C) of the switch circuit 204 is turned on and the contact 204 ₄ (FIG. 7D) is turned off. Thus, the high level (H) data held in the data register circuit 220 is transferred from the latch circuit 222 to the level shift circuit 210 via the switch circuit 204. The gradation voltage 4.5V is selected by the decoder / gradation voltage selection circuit 212 and the current is amplified by the operational amplifier 214. When the STB signal (FIG. 7A) is switched to a low level (time t = t2), the contact 208 ₂ (FIG. 7E) of the switch circuit 208 is turned on, and the contacts 208 ₅ and 208 ₆ are turned on. Turns off. As a result, the image data is output to the output terminal Y2 (FIG. 7 (h)) of the liquid crystal drive circuit A via the switch circuit 208. Then, a gradation voltage of 4.5 V (polarity is minus “−”) having a predetermined voltage value is applied to the liquid crystal panel 4.

(2) Time t = t3 to t5
When the POL signal (FIG. 7B) input to the timing control circuit 215 is low level (L) (time t = t3), the STB signal (FIG. 7A) causes the contacts 208 ₁ , 208 ₂ (FIG. 7 (e)), 208 ₃ and 208 ₄ (FIG. 7 (f)) are turned off, and contacts 208 ₅ , 208 ₆ and 208 ₇ (not shown in FIG. 7) are turned on.

At this time, in one of the two systems, the contact 204 ₁ (FIG. 7C) of the switch circuit 204 is turned off and the contact 204 ₃ (FIG. 7D) is turned on. Accordingly, the low level (L) data held in the data register circuit 219 is transferred from the latch circuit 221 to the level shift circuit 210 via the switch circuit 204. The gradation voltage 10 V is selected by the decoder / gradation voltage selection circuit 212 and the current is amplified by the operational amplifier 214. When the STB signal (FIG. 7A) is switched to the low level (time t = t4), the contact 208 ₃ (FIG. 7F) of the switch circuit 208 is turned on, and the contacts 208 ₅ and 208 ₆ are turned on. Turns off. As a result, the image data is output to the output terminal Y1 (FIG. 7 (g)) of the liquid crystal drive circuit A via the switch circuit 208. Then, a gradation voltage of 10 V (polarity is minus “−”) having a predetermined voltage value is applied to the liquid crystal panel 4.

On the other hand, in the other of the two systems, the contact 204 ₂ (FIG. 7C) of the switch circuit 204 is turned off and the contact 204 ₄ (FIG. 7D) is turned on. Accordingly, the high level (H) data held in the data register circuit 220 is transferred from the latch circuit 222 to the level shift circuit 209 via the switch circuit 204. The gradation voltage 4.5V is selected by the decoder / gradation voltage selection circuit 211, and the current is amplified by the operational amplifier 213. When the STB signal (FIG. 7A) is switched to the low level (time t = t4), the contact 208 ₄ (FIG. 7F) of the switch circuit 208 is turned on, and the contacts 208 ₅ and 208 ₆ are turned on. Turns off. As a result, the image data is output to the output terminal Y2 (FIG. 7 (h)) of the liquid crystal drive circuit A via the switch circuit 208. Then, a gradation voltage of 4.5 V (polarity is plus “+”) having a predetermined voltage value is applied to the liquid crystal panel 4.

(B) In the case of the 2H dot inversion driving method In step S02 of FIG. 3, it is determined that the image data whose gradation is equal to or higher than the set gradation in the input image data 28 for four lines is not greater than the predetermined number of pixels. When the method is determined to be the 2H dot inversion driving method, the operation is performed at time t = t5 to t13. It is controlled by the inversion cycle of the POL signal included in the data side control signal 22.

  At time t = t5 to t9, the POL signal becomes positive “+” and constant for two cycles of the STB signal. On the other hand, from time t = t9 to t13, the POL signal becomes a constant “−”. That is, 2H dot inversion driving is performed in which the polarity is inverted every two cycles of the STB signal. The operation of each circuit is the same as that in the case of dot inversion except that the timing is different.

  The image data is exchanged for each bit. In this way, the liquid crystal panel 4 is AC driven by switch-controlling the two systems of the liquid crystal drive circuit A.

  The use of the data driver 2 as shown in FIG. 5 has two systems of circuits on the low-voltage side and the high-voltage side, so that a voltage of twice or more the threshold voltage of the liquid crystal can be dealt with with one circuit. Compared to the case, the voltage width to be dealt with by one system is small. That is, it is possible to reduce power consumption while suppressing deterioration in image quality, and to set the breakdown voltage of each circuit low.

(Second Embodiment)
First, the configuration of the second embodiment of the liquid crystal display device of the present invention will be described. FIG. 8 is a block diagram showing the configuration of the second embodiment of the liquid crystal display device of the present invention. The liquid crystal display device 30 includes a control driver 8, a gate line driving circuit 3b, and a display unit 4b. The liquid crystal display device 30 is mainly used for a mobile phone.

  The control driver 8 receives input image data 28-1, a memory control signal 29-1, and a timing control signal 29-2 from an image drawing unit 39 (example: CPU). Based on them, the common electrodes of the data line driving circuit 33 (described later), the gate line driving circuit 3b, and the display unit 4b are controlled. Thereby, an image corresponding to the input image data 28-1 is displayed on the display unit 4b. The control driver 8 includes a data driver 2b, an LCD controller 5b, and a reference gradation voltage generator 6b.

  However, the input image data 28-1 represents an input image and includes gradation data (RGB signals) of each pixel. The memory control signal 29-1 includes a V (vertical) address signal (indicating the address of the gate line). It is used for control (described later) of the display memory 31 of the data driver 2b. The timing control signal 29-2 is used to control the output timing of the data line driving circuit 33, the gate line driving circuit 3b. A vertical synchronizing signal, a horizontal synchronizing signal, a clock signal, and a data enable signal are included. The common voltage 29-10 of the common electrode is directly input from the control driver to the display unit 4b.

  The LCD controller 5b receives the input image data 28-1, the memory control signal 29-1, and the timing control signal 29-2 from the image drawing unit 39. Based on these, the display memory control signal 29-5 and the STB signal 29-6 are output to the data driver 2b (data line driving circuit 33), and the gate side control signal 23 is output to the gate line driving circuit 3b. Then, Vcom (common voltage) is output to the display unit 4b. The LCD controller 5b includes an image determination unit 11, a method determination unit 12, an inversion switching position storage memory 35, a memory control circuit 36, a timing control circuit 37, and a Vcom control circuit 38.

  The image determination unit 11 receives input image data 28-1. Its function is the same as in the first embodiment. However, the comparison result (determination result) is output to the method determination unit 12. The method determination unit 12 is the same as that in the first embodiment. However, the POL_SEL signal 28-2 (example: 1H is a 2H gate line inversion driving method and 0 is a gate line inversion driving method) indicating the determined inversion driving method is output to the inversion switching position storage memory 35.

  Based on the POL_SEL signal 28-2 and the V address signal of the memory control signal 29-1, the inversion switching position storage memory 35 stores the POL_SEL signal 28- in the memory used for the gate line corresponding to the V address signal. 2 (reverse driving method) is stored. Then, based on the read signal 29-4 of the POL_SEL signal 28-2 from the timing control circuit 37, the POL_SEL signal 28-2 stored in the memory is output as the polarity inversion control signal 28-3.

  Based on the timing control signal 29-2, the timing control circuit 37 inquires the inversion switching position storage memory 35 about the inversion driving method of each gate line by the read signal 29-4. Based on the polarity inversion control signal 28-3 and the timing control signal 29-2 as the inquiry results, the following signals are output. That is, the timing control signal 29-7 indicating the output timing of data in the display memory 31 of the data driver 2b is output to the memory control circuit 36. An STB signal 29-6 indicating the data output timing of a latch circuit 32 (described later) of the data driver 2b is output to the latch circuit 32. A polarity inversion control signal 29-8 indicating the timing of polarity inversion (example: “H gate line inversion or gate line inversion) is output to the reference gradation voltage generation circuit 6b and the Vcom control circuit 38. Then, the gate line driving circuit 3b. The gate line control signal 29-9 indicating the output timing is output to the gate line driving circuit 3b.

  Based on the memory control signal 29-1 and the timing control signal 29-7, the memory control circuit 36 generates a timing control signal 29-5 indicating the output timing of data in the display memory 31 of the data driver 2b. To 36.

  Based on the polarity inversion control signal 29-8, the Vcom control circuit 38 outputs the common voltage 29-10 of the common electrode of the display unit 4b to the common electrode. In order to reduce the power consumption, Vcom (common voltage 29-10) is AC driven between 0V and 5V, and the output voltage to the data line is inverted and driven in the range of about 5V. In the present invention, this inversion drive timing is also controlled based on the gradation of the input image data.

  Based on the polarity inversion control signal 29-8, the reference gradation voltage generator 6b sets the gradation voltages V0 to V63 corresponding to the gradation of the input image data corresponding to the polarity to positive (positive with respect to the reference voltage). ) Or negative (negative with respect to the reference voltage). Then, the data is output to the data line driving circuit 33 of the data driver 2. In the present invention, the positive or negative inversion timing of the gradation voltages V0 to V63 is also controlled based on the gradation of the input image data.

  The data driver 2b controls a plurality of data lines of the display unit 4b based on the input image data 28-1, the STB signal 29-6, the timing control signal 29-5, and the gradation voltages V0 to V63. The data driver 2 b includes a display memory 31, a latch circuit 32, and a data line driving circuit 33.

The display memory 31 stores input image data for one frame of the display unit 4b. Based on the timing control signal 29-5, the input pixel data is output to the latch circuit 32 line by line.
The latch circuit 32 stores the input image data output from the display memory 31 line by line. Based on the STB signal 29-6, the input image data 21 is output to the data line driving circuit 33 line by line.
The data line driving circuit 33 amplifies the input image data for one line output from the latch circuit to a gradation voltage for each pixel. And it outputs to the data line of the display part 4b.

  The control driver 8 transfers the image data from the image drawing unit 39 to the data driver 2b only when the display changes. In the case of a still image, the image data stored in the display memory 31 is read line by line and the image is output to the display unit 4b.

  When input image data is not newly input from the image drawing unit 39 (still image), the image data stored in the display memory 31 is not changed. In addition, the POL_SEL signal stored in the inversion switching position storage memory 35 (memory 35b) does not change. Therefore, in the case of a still image, it is displayed on the display unit 4b without changing the inversion driving method in each pixel.

The gate line driving circuit 3b controls the plurality of gate lines of the display unit 4b based on the gate side control signal 29-9.
The display unit 4b is a liquid crystal panel that displays an image by controlling a plurality of gate lines and a plurality of data lines by the data line driving circuit 33 and the gate line driving circuit 3b, respectively.

  Here, since the set gradation and image determination in the image determination unit 11 shown in FIG. 8 are the same as in the first embodiment (description of FIG. 2), description thereof is omitted.

  Also in this embodiment, it is possible to reduce power consumption while suppressing deterioration in image quality such as flicker. It is preferable that the power consumption can be reduced because heat generation of each part such as the data line driving circuit 33 can be suppressed.

  It should be noted that, in the gradation region near white where flicker is difficult to see, a gate line inversion method with good image quality may be used, or a 2H gate line inversion driving method with low power consumption may be used. That is, it is possible to provide a plurality of set gradations and use a plurality of driving methods. In that case, it is possible to carry out more detailed and accurate control for suppressing power consumption while preventing deterioration of image quality.

  Here, the 2H gate line inversion driving method and the gate line inversion driving method are used. However, other methods such as a 3H gate line inversion driving method and a gate line inversion driving method can also be used. When a 3H gate line inversion driving method or a higher gate line inversion driving method (example: 4H gate line inversion driving method) is used, power consumption can be further reduced, which is more preferable.

  In the case of normally black, the relationship between white and black is reversed from the above case. That is, it becomes black (about 0 to about 2 V) and white (about 3 to 5 V), and it is near white that needs to be charged and discharged at a high voltage.

  The reverse switching position storage memory 35 will be described in detail. FIG. 10 is a block diagram showing the configuration of the reverse position storage memory. The inversion position storage memory includes an address decoder 35a and a memory 35b (-1 to q: q is a natural number).

  Based on the address, the coder 35a decodes the V address signal of the memory control signal 29-1. Then, the write signal 35c (-1 to q) is output to the memory 35b used for the gate line corresponding to the V address signal. For example, the write signal 35c-1 is output to the memory 35b-1 used for four columns from the top of the gate line. The write signal 35c-2 is output to the memory 35b-2 used for the next four columns.

  Each of the memories 35b (-1 to q) stores a POL_SEL signal 28-2 output at the same timing as the corresponding write signal 35c (-1 to q). For example, the memory 35b-1 stores the POL_SEL signal 28-2 = 1 output at the same timing as the write signal 35c-1. As a result, as shown in the figure on the right side, the 4 columns from the top of the gate line are in the 2H gate line inversion drive system. On the other hand, the memory 35b-2 stores the POL_SEL signal 28-2 = 0 output at the same timing as the write signal 35c-2. As a result, as shown in the drawing on the right side, the four lines from the top of the gate line are in the gate line inversion driving method.

  The number of memories (q) is a quarter of the total number of gate lines (number of horizontal pixels). That is, the memory 35b is provided for every four gate lines (the number of horizontal scanning lines). This is because the inversion driving method is determined every four horizontal pixel lines (four gate lines).

  However, the number of horizontal pixel lines (number of gate lines) is not limited to this example. In other words, here, the driving method is determined and changed between the gate line inversion driving method with a two-line cycle and the 2H gate line inversion driving method with a four-line cycle. Therefore, it is preferable to determine and change the driving method in a 4 m line cycle (m is a natural number) that is a common multiple of the 2 line cycle and the 4 line cycle. It is more preferable to determine and change the driving method at the least common multiple of 4 lines with m = 1 as in the present embodiment, since image quality deterioration can be better suppressed.

  The data line driving circuit 33 and the reference gradation voltage generating circuit 6b will be described in detail. FIG. 11 is a block diagram showing the configuration of the data line driving circuit 33 and the reference gradation voltage generating circuit 6b.

  The reference gradation voltage generation circuit 6 b includes a positive polarity gradation generation unit 317, a negative polarity gradation generation unit 318, and a polarity selector 319. The positive-tone gradation generation unit 317 generates reference gradation voltages (V0 to V63) when the polarity is positive. The negative gradation generator 318 generates reference gradation voltages (V0 to V63) when the polarity is negative. The polarity selector 319 outputs a reference gradation voltage corresponding to the polarity (positive or negative) indicated by the polarity inversion control signal 29-8 to the data line driving circuit 33.

  The data line driving circuit 33 includes a gradation voltage selection circuit 306 and an operational amplifier 307. The gradation voltage selection circuit 306 includes a gradation voltage selection circuit 211 corresponding to each of the plurality of data lines. The gradation voltage selection circuit 211 selects a gradation voltage corresponding to image data from the reference gradation voltages (V0 to V63) output from the reference gradation voltage generation circuit 6b. The operational amplifier 307 has an operational amplifier 213 corresponding to each of the plurality of data lines. The gradation voltage selected by the corresponding gradation voltage selection circuit 211 is amplified.

Next, the operation (driving method of the liquid crystal display device) of the second embodiment of the liquid crystal display device of the present invention will be described.
FIG. 3 is a flowchart showing the operation of the liquid crystal display device according to the second embodiment of the present invention. Here, a case where the liquid crystal panel is normally white and the inversion driving method is determined for every four lines (four gate lines) of the horizontal pixel will be described.

(1) Step S01:
The input image data 28-1 transmitted from the image drawing unit 39 is determined by the image determination unit 11 for each pixel whether or not the gradation is equal to or higher than the set gradation.
(2) Step S02:
The method determination unit 12 determines whether or not the image data whose gradation is equal to or higher than the set gradation is greater than or equal to a predetermined number of pixels in the input image data 28 for four lines.
(3) Step S03:
When there are more than a predetermined number of pixels in the input image data 28 for the four lines, the method determining unit 12 determines the driving method of the input image data 28 for the four lines. The gate line inversion driving method is determined.
(4) Step S04:
When the input image data 28 for four lines has no image data having a gradation equal to or higher than the set gradation, the method determining unit 12 determines the driving method of the input image data 28 for four lines. The 2H gate line inversion driving method is determined.
(5) Step S05:
On the other hand, the input image data 28-1 is sequentially stored in the display memory 31.
(6) Step S06:
The input image data 28-1 stored in the display memory 31 is output to the latch circuit 32 based on the timing control signal 29-5. The input image data 28-1 stored in the latch circuit 32 is output to the data line driving circuit 33 based on the STB signal 29-6. The input image data 28-1 of the data line driving circuit 33 is output to the data line of the display unit 4b based on the reference gradation voltage generating circuit 6b. On the other hand, based on the gate line control signal 29-9, the gate line drive circuit 3b drives the gate line of the display unit 4b. Furthermore, based on the common voltage 29-10, the Vcom control circuit 38 drives the common electrode of the display unit 4b.
(7) Step S07:
Thereby, the input image data is displayed on the display unit 4b. The display unit 4b (liquid crystal panel) is driven.

  By such an operation, the liquid crystal display device can be operated.

  FIG. 9 is a conceptual diagram showing the voltage polarity applied to the liquid crystal panel 4 in the present invention. Each square in the liquid crystal panel 4 represents a pixel. “+” Or “−” in the square indicates the voltage polarity in the pixel. The left liquid crystal panel 4 shows odd frames, and the right liquid crystal panel 4 shows even frames.

  A region where the image data whose gradation is equal to or higher than the set gradation in the four lines of input image data 28-1 does not exceed the predetermined number of pixels (the portion where the pattern is given in the figure) is a 2H gate line inversion drive system. Polarity reversal is performed by. On the other hand, polarity inversion is performed by a gate line inversion driving method in a region (a portion where no pattern is applied in the drawing) having a predetermined number of pixels or more. In other words, the drive system is switched between the gate line inversion drive system and the 2H gate line inversion drive system in units of four vertical lines.

  However, it is preferable that the image determining unit 11 and the method determining unit 12 determine and switch the polarity inversion method every two frames. That is, one even frame and one odd frame shown in FIG. 9 are taken as a set, and the polarity inversion method is determined and switched for each set. This is because, if the polarity inversion method is switched between dot inversion and 2H dot inversion every frame, there is a possibility that a DC voltage is always applied to the liquid crystal panel and there is a risk of burn-in.

  Here, a case is described in which the inversion driving method is determined for every four horizontal pixel lines (four gate lines), but the number of horizontal pixel lines (the number of gate lines) is not limited to this example. In other words, here, the driving method is determined and changed between the gate line inversion driving method with a two-line cycle and the 2H gate line inversion driving method with a four-line cycle. Therefore, it is preferable to determine and change the driving method in a 4 m line cycle (m is a natural number) that is a common multiple of the 2 line cycle and the 4 line cycle. It is more preferable to determine and change the driving method at the least common multiple of 4 lines with m = 1 as in the present embodiment, since image quality deterioration can be better suppressed.

  With such a configuration and operation of the present invention, it is possible to reduce power consumption and suppress heat generation of each unit such as the data driver 2 while suppressing deterioration in image quality such as flicker.

  Here, for all the pixels, the driving method for inverting the polarity is determined based on the gradation, but the present invention is not limited to this example. For example, the driving method of the present invention may be applied to the G signal pixel of the RGB signals, and the 2H gate line inversion driving method may be applied to the remaining R and B signals. Since the G signal includes much luminance information, if the present invention is applied to the G signal, it becomes difficult to see the flicker. In this case, compared with the case where the present invention is applied to all the pixels, control becomes easier, and more power consumption and heat generation can be achieved by using the 2H gate line inversion driving method for the remaining R and B signals. Can be reduced.

  Next, with reference to FIGS. 8, 10, 11, and 12, the operation of the second embodiment (step S07 in FIG. 3) in the liquid crystal display device of the present invention will be described. The case of the key is explained as an example.

  However, FIG. 12 is a timing chart of each circuit shown in FIG. 8A shows the STB signal, FIG. 8B shows the polarity inversion control signal, FIG. 8C shows Vcom, and FIG. 8D shows the output signal of the output terminal Y, respectively.

  Based on the STB signal output from the timing control circuit 37 to the latch circuit 32 and the polarity inversion control signal 29-8, the reference gradation voltages (corresponding to the output signal Y at the output terminal) V0 to V63 and the common voltage 29- The polarity with 10 is alternately switched at a predetermined cycle.

(A) In the case of the gate line inversion drive method In step S02 of FIG. 3, it is determined that there are more than a predetermined number of pixel data in the input image data 28-1 for four lines whose gradation is equal to or higher than the set gradation. When the driving method is determined as the gate line inversion driving method, the operation is performed at time t = t5 to t7.

(1) Time t = t5 to t6
Each time the STB signal (FIG. 7 (a)) becomes high level (H), the polarity of the polarity inversion control signal (FIG. 7 (b)) switches alternately. At time t = t5 to t6, the polarity of the polarity inversion control signal (FIG. 7B) becomes positive, Vcom (FIG. 7C) becomes low level (L), and the output signal Y (FIG. 7) at the output terminal. 7 (d)) indicates a positive gradation voltage.

(2) Time t = t6 to t7
At time t = t5 to t6, the polarity of the polarity inversion control signal (FIG. 7B) becomes negative, Vcom (FIG. 7C) becomes high level (H), and the output signal Y at the output terminal (FIG. 7). 7 (d)) indicates a negative gradation voltage.

(B) In the case of 2H gate line inversion driving method In step S02 of FIG. 3, it is determined that the image data whose gradation is equal to or higher than the set gradation is not greater than the predetermined number of pixels in the input image data 28-1 for four lines. When the driving method is determined as the 2H gate line inversion driving method, the operation is performed at time t = t1 to t5.

(1) Time t = t1 to t3
Each time the STB signal (FIG. 7A) becomes high level (H), the input image data is changed. However, the polarity of the polarity inversion control signal (FIG. 7B) is alternately switched every time the TB signal (FIG. 7A) becomes high level (H) twice. At time t = t1 to t3, the polarity of the polarity inversion control signal (FIG. 7B) becomes positive, Vcom (FIG. 7C) becomes low level (L), and the output signal Y at the output terminal (FIG. 7). 7 (d)) indicates a positive gradation voltage.

(2) Time t = t3 to t5
At the time t = t3 to t5, the polarity of the polarity inversion control signal (FIG. 7B) becomes negative, Vcom (FIG. 7C) becomes high level (H), and the output signal Y (FIG. 7) at the output terminal. 7 (d)) indicates a negative gradation voltage.

  As shown in FIG. 12C, the controller driver 8 sets Vcom to AC driving. As a result, the output voltage (FIG. 12D) to the data line can be halved as compared with the case where Vcom is not AC driven. For example, in the dot inversion drive according to the first embodiment, Vcom = 5V, data line voltage negative polarity 0 to 5V, and data line voltage positive polarity 5 to 10V. On the other hand, in the gate line inversion driving of the present embodiment, the data line voltage negative polarity is 5 to 0 V (Vcom = 5 V), and the data line voltage positive polarity is 0 to 5 V (Vcom = 0 V).

  In the present invention, the control driver 8 (the data driver 2b, the LCD controller 5b, the reference gradation voltage generator 6b), the gate line driving circuit 3b, and the LCD controller 5b of the display unit 4b, which are conventionally used, are subjected to image determination. The unit 11, the method determining unit 12, and the reverse switching position storage memory 35 are used. By adding these functions, the polarity inversion driving method can be changed based on the gradation level of the input image data. Accordingly, it is possible to reduce power consumption and suppress heat generation of each unit such as the data driver 2 while suppressing deterioration in image quality such as flicker.

(Third embodiment)
First, the configuration of the third embodiment of the liquid crystal display device of the present invention will be described. FIG. 13 is a block diagram showing the configuration of the third embodiment of the liquid crystal display device of the present invention. The liquid crystal display device 1a includes a data driver 2a, a gate driver 3, a liquid crystal panel 4, an LCD controller 5a, and a reference gradation voltage generator 6.

  The LCD controller 5a receives input image data 28 and a display control signal 29 from the image drawing unit 7 (example: CPU). The input image data 28 and the display control signal 29 are the same as those in the first embodiment. Based on the input image data 28 and the display control signal 29, the image data 21, the data side control signal 22, the second polarity inversion signal (hereinafter “POL_2 signal”) 25, and the polarity inversion switching control signal (hereinafter “ POL_SEL signal ") 26 is output to the data driver 2, and the gate side control signal 23 is output to the gate driver 3. The data side control signal 22 includes a polarity inversion signal (hereinafter, “POL signal”) in addition to the normal data side control signal. The gate side control signal 23 includes a normal gate side control signal.

  The polarity inversion signal (POL signal) is always output at a timing at which a plurality of pixels (blocks) of less than one frame are driven by the dot inversion driving method. The second polarity inversion signal (POL_2 signal) is always output at the timing when the plurality of pixels (groups) of less than one frame are driven by the 2H dot inversion driving method. The polarity inversion switching control signal (POL_SEL signal) is driven by a dot inversion driving method or a 2H dot inversion driving method (either a POL signal or a POL_2 signal) for a plurality of pixels (groups) of less than one frame. Control).

The LCD controller 5 a includes an image determination unit 11, a method determination unit 12 a, and a line memory 13.
The image determination unit 11 compares the gradation of the input image data 28 with the set gradation for each pixel in the input image data 28 and determines whether the gradation of the input image data 28 is higher or lower than the set gradation. To do. The comparison result (determination result) is output to the method determination unit 12a. The input image data 28 is output to the line memory 13.

  Based on the comparison result, the method determining unit 12a determines the inversion driving method for displaying the input image data on the liquid crystal panel 4 for each of a plurality of pixels of less than one frame. “A plurality of pixels of less than one frame” is exemplified by a group of a plurality of pixels such as 4 pixels (vertical) × 2 pixels (horizontal). Since the determination method is the same as that of the first embodiment, the description thereof is omitted.

  The line memory 13 temporarily stores input image data 28 corresponding to the line of pixels in the vertical direction in the group of pixels determined by the method determination unit 12a. For example, when the method determination unit 12a determines for each pixel block of 4 pixels (vertical) × 2 pixels (horizontal), it stores four lines. Then, after storing the input image data 28 corresponding to a plurality of lines, the input image data 28 is output as the image data 21 to the data driver 13. The line memory 13 is provided for timing adjustment with the data-side control signal reflecting the determination result when the image data 21 is output to the data driver 13.

The reference gradation voltage generator 6 generates a gradation voltage corresponding to the gradation of the input image data and outputs it to the data driver 2a.
The gate driver 3 controls a plurality of gate lines of the liquid crystal panel 4 based on the gate side control signal 23. However, it may be configured integrally with the LCD controller 5. In that case, the circuit area can be reduced.
Based on the input image data 21, the data side control signal 22, the second polarity inversion signal (POL_2 signal) 25, the polarity inversion switching control signal (POL_SEL signal) 26, and the reference gradation voltage 24, the data driver 2a 4 data lines are controlled. However, it may be configured integrally with the LCD controller 5. In that case, the circuit area can be reduced.
The liquid crystal panel 4 displays an image by controlling a plurality of gate lines and a plurality of data lines by the data driver 2 and the gate driver 3, respectively.

  Here, since the set gradation and image determination in the image determination unit 11 shown in FIG. 13 are the same as in the first embodiment (description of FIG. 2), the description thereof is omitted.

  Also in this embodiment, it is possible to reduce power consumption while suppressing deterioration in image quality such as flicker. It is preferable that power consumption can be reduced because heat generation of each part such as the data driver 2a can be suppressed.

  It should be noted that in the gradation region near white where flicker is difficult to see, the dot inversion method with good image quality may be used, or the 2H dot inversion driving method with low power consumption may be used. That is, it is possible to provide a plurality of set gradations and use a plurality of driving methods. In that case, it is possible to carry out more detailed and accurate control for suppressing power consumption while preventing deterioration of image quality.

  Here, the 2H dot inversion driving method and the dot inversion driving method are used. However, other methods such as a 3H dot inversion driving method and a dot inversion driving method can also be used. When a 3H dot inversion driving method or a higher dot inversion driving method (example: 4H dot inversion driving method) is used, power consumption can be further reduced, which is more preferable.

  In the case of normally black, the relationship between white and black is reversed from the above case. That is, it becomes black (about 0 to about 2 V) and white (about 3 to 5 V), and it is near white that needs to be charged and discharged at a high voltage.

Next, the operation (driving method of the liquid crystal display device) of the third embodiment of the liquid crystal display device of the present invention will be described.
FIG. 3 is a flowchart showing the operation of the first embodiment of the liquid crystal display device of the present invention. Here, a case where the liquid crystal panel is normally white and the inversion driving method is determined for each pixel block of 4 pixels (vertical) × 2 pixels (horizontal) will be described.

(1) Step S01:
The input image data 28 transmitted from the image drawing unit 7 is determined by the image determination unit 11 for each pixel whether or not the gradation is equal to or higher than the set gradation.
(2) Step S02:
The method determining unit 12a determines whether or not the input image data 28 of the pixel block of 4 pixels (vertical) × 2 pixels (horizontal) has more than a predetermined number of image data whose gradation is equal to or higher than the set gradation. Is done.
(3) Step S03:
When the input image data 28 of the pixel block includes image data having a gradation equal to or higher than the set gradation, the driving method of the input image data 28 of the pixel block is determined by the method determination unit 12a. The inversion driving method is determined.
(4) Step S04:
When the input image data 28 of the pixel block has no image data having a gradation equal to or higher than the set gradation, the driving method of the input image data 28 for the four lines is determined by the method determination unit 12a. The 2H dot inversion driving method is determined.
(5) Step S05:
The input image data 28 determined by the image determination unit 11 is sequentially stored in the line memory 13. The line memory 13 has four lines corresponding to the number of horizontal pixels of the liquid crystal panel 4 which is a unit for determining the driving method. Four lines correspond to four pixels (vertical) of the pixel block.
(6) Step S06:
The input image data 28 for four lines stored in the line memory 13 is sequentially output to the data driver 2 as the image data 21 after determining the driving method. At the same time, the data side control signal 22 including the POL signal, the POL_2 signal 25, and the POL_SEL signal 26 indicating the driving method determined by the method determining unit 12 a are output from the LCD controller 5 to the data driver 2. The gate side control signal is output from the LCD controller 5 to the gate driver 3. The reference gradation voltage 24 is output from the reference gradation voltage generator 6 to the gate driver 3.
(7) Step S07:
The liquid crystal panel 4 is driven by an output signal from the data driver 2 based on the data side control signal and an output signal from the gate driver 3 based on the gate side control signal.

  By such an operation, the liquid crystal display device can be operated.

  FIG. 14 is a conceptual diagram showing the voltage polarity applied to the liquid crystal panel 4 in the present invention. Each square in the liquid crystal panel 4 represents a pixel. “+” Or “−” in the square indicates the voltage polarity in the pixel. The left liquid crystal panel 4 shows odd frames, and the right liquid crystal panel 4 shows even frames.

  A region in which the input image data 28 of a pixel block of 4 pixels (vertical) × 2 pixels (horizontal) does not have a predetermined number of image data whose gradation is equal to or higher than a set gradation (the portion where a pattern is applied in the figure) The polarity inversion is performed by the 2H dot inversion driving method. On the other hand, polarity inversion is performed by a dot inversion driving method in a region (a portion where no pattern is applied in the drawing) having a predetermined number of pixels or more. That is, this is a driving method in which the dot inversion driving method and the 2H dot inversion driving method are switched in units of 4 × 2 pixel block units.

  However, it is preferable that the image determining unit 11 and the method determining unit 12 determine and switch the polarity inversion method every two frames. That is, one even frame and one odd frame shown in FIG. 14 are taken as a set, and the polarity inversion method is determined and switched for each set. This is because, if the polarity inversion method is switched between dot inversion and 2H dot inversion every frame, there is a possibility that a DC voltage is always applied to the liquid crystal panel and there is a risk of burn-in.

Although the case where the inversion driving method is determined for each pixel block of 4 pixels (vertical) × 2 pixels (horizontal) has been described here, the number of pixels in the pixel block is not limited to this example.
The four pixels lined up vertically are determined as follows. That is, here, the drive method is determined and changed between the dot inversion driving method with a two-line cycle and the 2H dot inversion driving method with a four-line cycle. Therefore, it is preferable to determine and change the driving method in a 4 m line cycle (m is a natural number) that is a common multiple of the 2 line cycle and the 4 line cycle. It is more preferable to determine and change the driving method at the least common multiple of 4 lines with m = 1 as in the present embodiment, since image quality deterioration can be better suppressed.
The two pixels arranged horizontally are determined as follows. That is, the set of two pixels adjacent in the horizontal direction is always a multiple of the set of polarity of “+” and “−”. This prevents the liquid crystal from being charged up. Therefore, it is preferable to determine and change the driving method so that it becomes 2k (k is a natural number). It is more preferable to determine and change the driving method in a two-pixel cycle where k = 1 as in this embodiment because deterioration of image quality can be better suppressed.

  With the configuration and operation of the present invention, the same effects as those of the first embodiment can be obtained. In addition, since the inversion driving method is determined for each pixel block composed of a plurality of pixels, it is possible to more appropriately suppress image quality degradation such as flicker, and to further reduce power consumption, thereby reducing the data driver. It becomes possible to further suppress the heat generation of each part such as 2.

  Here, the driving method of the present invention is applied to all the pixels. However, as described above, the driving method of the present invention may be applied to the G signal pixel of the RGB signals, and the 2H dot inversion driving method may be used for the remaining R and B signals. Also in this case, compared to the case where the present invention is applied to all the pixels, the control becomes easier and the power consumption and heat generation are reduced by using the 2H dot inversion driving method for the remaining R and B signals. It can be reduced more.

  As the gate driver 2a in the liquid crystal display device of the present invention, for example, a drive circuit obtained by modifying the gate driver 2 described in FIG. 5 can be used.

  FIG. 15 is a block diagram showing details of the gate driver 2a in the liquid crystal display device of the present invention. The gate driver 2a of the present invention includes a liquid crystal drive circuit Aa and switch circuits 104 and 108.

  The liquid crystal drive circuit Aa outputs positive and negative voltages based on the supplied liquid crystal drive voltage or the voltage Vcom of the liquid crystal common electrode according to the applied image data. A shift register circuit 101, a data register circuit 102, a latch circuit 103, a level shift circuit 105, a decoder / grayscale voltage selection circuit 106, and an operational amplifier (op-amp) 107 are included. These circuit configurations consist of two systems. In the present invention, with reference to the voltage Vcom of the liquid crystal common electrode, a voltage equal to or higher than this voltage value is applied as a positive voltage, a voltage equal to or lower than this voltage value is set as a negative voltage, and is applied while maintaining a positive / negative amplitude relationship. AC drive by doing.

  In response to the output of each stage of the shift register circuit 101, the data register circuit 102 latches n (natural number) -bit image data 21 (D00 to Dxx) to be controlled in parallel. Two systems of data register circuit 119 and data register circuit 120 are provided. There are m combinations of the two systems. The data register circuit 102 further includes a register circuit 123 for storing the POL_SEL signal for each set of two systems.

  The latch circuit 103 collectively latches n-bit data (image data 21: D00 to Dxx) from the data register circuit 102 in response to a latch signal (hereinafter, “STB signal”). There are two systems, a latch circuit 121 connected to the data register circuit 119 and a latch circuit 122 connected to the data register circuit 120. There are m combinations of the two systems. The latch circuit 103 is further provided with a register circuit 124 for storing the POL_SEL signal for each set of two systems.

  The level shift circuit 105 boosts the n-bit data from the latch circuit 103 to a liquid crystal drive voltage having a different voltage value. Two systems of a high-voltage side level shift circuit 109 and a low-voltage side level shift circuit 110 are provided. There are m combinations of the two systems. In the present embodiment, the high-voltage side level shift circuit 109 is set to boost 3.3V to 10V, for example, and the low-voltage side level shift circuit 110 is set to boost 3.3V to 5V, for example. However, it is not limited to this step-up rate. As the level shift circuit 105, a conventionally known circuit can be used.

  Based on a control signal (POL signal or POL_2 signal) from the timing control circuit 115, the switch circuit 104 outputs the output of one system of the latch circuit 121 to the high-voltage side level shift circuit 109 and the low-voltage side level shift circuit 110. Selectively connect to one of them. At the same time, the output of the latch circuit 122 of another system is selectively connected to the other one of the high-voltage side level shift circuit 109 and the low-voltage side level shift circuit 110. The switch circuit 104 further includes a switch for selecting one of the POL signal and the POL_2 signal as a control signal in accordance with the POS_SEL signal stored in the register circuit (123, 124) for each pixel block.

16 to 21 are block diagrams illustrating specific examples of switch control of each circuit. However, in these figures, in a set of two systems of the left, indicating when the (dot inversion driving method) of the POL signal is selected as the control signal at the junction 104 ₅ by POL_SEL signal = 0. In the right set of two systems, indicating when the (2H dot inversion driving method) of POL_2 signal as a control signal at the junction 104 ₆ by POL_SEL signal = 1 is selected.

Specifically, the switch circuit 104 performs switch control as follows.
In one set of two systems of the left side of FIG. 16, the POL signal = high level (H) (STB signal = L), the latch circuit 121 at the junction 104 ₁ to the high-pressure side level shift circuit 109, a latch circuit with contacts 104 ₂ 122 are connected to the low-voltage side level shift circuit 110, respectively.
In the right set of two systems, low pressure by POL_2 signal = high level (H) (STB signal = L), the latch circuit 121 at the junction 104 ₁ to the high-pressure side level shift circuit 109, a latch circuit 122 at contact 104 ₂ Each is connected to the side level shift circuit 110.

In one set of two systems of the left side of FIG. 17, the POL signal = low level (L) (STB signal = L), the latch circuit 121 at the junction 104 ₄ to the low pressure side level shift circuit 110, a latch circuit at the junction 104 ₃ 122 are connected to the high voltage side level shift circuit 109, respectively.
In the right set of two systems, low pressure by POL_2 signal = high level (H) (STB signal = L), the latch circuit 121 at the junction 104 ₁ to the high-pressure side level shift circuit 109, a latch circuit 122 at contact 104 ₂ Each is connected to the side level shift circuit 110.

In one set of two systems of the left side of FIG. 18, the POL signal = high level (H) (STB signal = L), the latch circuit 121 at the junction 104 ₁ to the high-pressure side level shift circuit 109, a latch circuit with contacts 104 ₂ 122 are connected to the low-voltage side level shift circuit 110, respectively.
In the right set of two systems, a high pressure by POL_2 signal = low level (L) (STB signal = L), the latch circuit 121 at the junction 104 ₄ to the low pressure side level shift circuit 110, a latch circuit 122 at contact 104 ₃ Each is connected to the side level shift circuit 109.

In one set of two systems of the left side of FIG. 19, the POL signal = low level (L) (STB signal = L), the latch circuit 121 at the junction 104 ₄ to the low pressure side level shift circuit 110, a latch circuit at the junction 104 ₃ 122 are connected to the high voltage side level shift circuit 109, respectively.
In the right set of two systems, a high pressure by POL_2 signal = low level (L) (STB signal = L), the latch circuit 121 at the junction 104 ₄ to the low pressure side level shift circuit 110, a latch circuit 122 at contact 104 ₃ Each is connected to the side level shift circuit 109.

  The gradation voltage generation circuit 6, the decoder / gradation voltage selection circuit 106, and the operational amplifier 107 are the same as the gradation voltage generation circuit 6, the decoder / gradation voltage selection circuit 206, and the operational amplifier 207 of the first embodiment. The description is omitted. However, the high-voltage gradation voltage generation circuit 117 and the low-voltage gradation voltage generation circuit 118 correspond to the high-voltage gradation voltage generation circuit 217 and the low-voltage gradation voltage generation circuit 218, respectively. The high voltage side decoder / grayscale voltage selection circuit 111 and the low voltage side decoder / grayscale voltage selection circuit 112 correspond to the high voltage side decoder / grayscale voltage selection circuit 211 and the low voltage side decoder / grayscale voltage selection circuit 212, respectively. The high-voltage side operational amplifier 113 and the low-voltage side operational amplifier 114 correspond to the high-voltage side operational amplifier 213 and the low-voltage side operational amplifier 214, respectively.

  The switch circuit 108 is shared by the two terminals of the two-system circuit of the liquid crystal drive circuit Aa, outputs positive and negative voltages in time series to each terminal, and maintains voltages that maintain a positive and negative amplitude relationship between the two terminals. Switch control to output. The switch circuit 108 includes a common terminal switch 108b. The common terminal switch 108b connects all the output terminals Y1 to Ym of the liquid crystal drive circuit Aa in common, and connects all the output terminals Y1 to Ym to 1/2 the liquid crystal drive voltage (1/2 VLCD (example: 5V)). To. The breakdown voltage of the switch circuit 108 directly connected to the liquid crystal is set to be twice or more the threshold voltage value of the liquid crystal. The common terminal switch 108b shorts the data lines every two horizontal directions in order to reduce power consumption. It can be controlled independently every two lines.

Referring to FIGS. 16 to 19, specifically, switch circuit 108 performs switch control as follows. However, in these figures, in a set of two systems of the left, indicating when the (dot inversion driving method) of the POL signal is selected as the control signal at the junction 108 ₅ by POL_SEL signal = 0. In the right set of two systems, indicating when the (2H dot inversion driving method) of POL_2 signal as a control signal at the junction 108 ₆ by POL_SEL signal = 1 is selected.

In one set of two systems of the left side of FIG. 16, POL signal = high level (H) (STB signal = L), the high-pressure-side operational amplifier 113 to the output terminal Y1 at the junction 108 _1, the low-pressure-side operational amplifier 114 with contacts 108 ₂ Are respectively connected to the output terminal Y2.
In the right set of two systems, the POL_2 signal = high level (H) (STB signal = L), the output terminal Y3 high pressure-side operational amplifier 113 with contacts 108 _1, output terminal a low pressure-side operational amplifier 114 with contacts 108 ₂ Connect to Y4 respectively.

In one set of two systems of the left side of FIG. 17, POL signal = low level (L) (STB signal = L), the high-pressure-side operational amplifier 113 to the output terminal Y2 at the junction 108 _4, the low-pressure-side operational amplifier 114 with contacts 108 ₃ Are respectively connected to the output terminal Y1.
In the right set of two systems, the POL_2 signal = high level (H) (STB signal = L), the output terminal Y3 high pressure-side operational amplifier 113 with contacts 108 _1, output terminal a low pressure-side operational amplifier 114 with contacts 108 ₂ Connect to Y4 respectively.

In one set of two systems of the left side of FIG. 18, POL signal = high level (H) (STB signal = L), the high-pressure-side operational amplifier 113 to the output terminal Y1 at the junction 108 _1, the low-pressure-side operational amplifier 114 with contacts 108 ₂ Are respectively connected to the output terminal Y2.
In the right set of two systems, the POL_2 signal = low level (L) (STB signal = L), the high-pressure-side operational amplifier 113 to the output terminal Y4 at contacts 108 _4, the output terminal a low pressure-side operational amplifier 114 with contacts 108 ₃ Connect to Y3 respectively.

In one set of two systems of the left side of FIG. 19, POL signal = low level (L) (STB signal = L), the high-pressure-side operational amplifier 113 to the output terminal Y2 at the junction 108 _4, the low-pressure-side operational amplifier 114 with contacts 108 ₃ Are respectively connected to the output terminal Y1.
In the right set of two systems, the POL_2 signal = low level (L) (STB signal = L), the high-pressure-side operational amplifier 113 to the output terminal Y4 at contacts 108 _4, the output terminal a low pressure-side operational amplifier 114 with contacts 108 ₃ Connect to Y3 respectively.

  20 to 21 are block diagrams illustrating specific examples of switch control of the common terminal switch 108b. However, these drawings show a case where the POL signal is selected as the control signal by the POL_SEL signal = 0 in the pair of two systems on the left side (dot inversion driving method). A pair of two systems on the right side shows a case where the POL_2 signal is selected as a control signal by the POL_SEL signal = 1 (2H dot inversion driving method).

Referring to FIG. 20, when the STB signal is at the high level (H), the common terminal switch 108b (related to the output terminals (Y1, Y2 in the figure) controlled by the POL signal is used in the period in which only the POL signal is inverted. The contacts 108b ₁ and 108b ₂ ) are turned on. As a result, the output terminals (Y1, Y2 in the figure) controlled by the POL signal in the liquid crystal drive circuit Aa are connected in common and set to 1/2 VLCD. However, the common terminal switches 108b (contacts 108b ₁ and 108b ₂ ) related to the output terminals (Y3 and Y4 in the figure) controlled by the POL_2 signal remain off.

Referring to FIG. 21, when the STB signal is at a high level (H), all the common terminal switches 108b (contacts 108b ₁ and 108b ₂ ) are turned on in a cycle in which the POL signal and the POL_2 signal are inverted. As a result, all the output terminals (Y1 to Y4 in the figure) of the liquid crystal drive circuit Aa are connected in common to make a 1 / 2VLCD.

  Next, regarding the power supply voltage of each circuit, data register circuits 119 and 120, latch circuits 121 and 122, switch circuits 104 and 108, level shift circuits 109 and 110, decoder / gradation voltage selection circuits 111 and 112, and an operational amplifier 113 are used. , 114 are the same as the data register circuits 219, 220, latch circuits 221, 222, switch circuits 204, 208, level shift circuits 209, 210, decoder / grayscale voltage selection circuits 211, 212, and operational amplifiers 213, 214, respectively. . The voltage applied as an external input to the gradation voltage generation circuits 117 and 118 is the same as that of the gradation voltage generation circuits 217 and 218.

  Next, the operation of the liquid crystal display device of the present invention using the gate driver 2a of FIG. 15 (step S07 in FIG. 3) will be described with reference to FIGS. The case where is 6 bits (64 gradations) will be described as an example.

However, FIG. 22 is a timing chart of each circuit shown in FIG. 22A shows the STB signal, FIG. 22B shows the POL signal, and FIG. 22C shows the POL_2 signal.
(D) is ON / OFF of the contacts 104 ₁ and 104 ₂ of the switch circuit 104, (e) is ON / OFF of the contacts 104 ₃ and 104 ₄ of the switch circuit 104, (f) is a contact 108 _{1 of} the switch circuit 108, 108 ₂ on / off, (g) denotes a contact ₁₀₈ 3, 108 ₄ on / off of the switching circuit 108. However, (d) to (g) are for the case where the line is POL_SEL signal = 0 (dot inversion driving method).
(H) ON / OFF of the contacts 104 ₁ and 104 ₂ of the switch circuit 104, (i) ON / OFF of the contacts 104 ₃ and 104 ₄ of the switch circuit 104, and (j) a contact 108 _{1 of} the switch circuit 108, 108 ₂ on / off, (k) denotes a contact ₁₀₈ 3, 108 ₄ on / off of the switching circuit 108. However, (h) to (k) correspond to the case of the line of POL_SEL signal = 1 (2H dot inversion driving method).
(L) is an output signal of the output terminal Y1, (m) is an output signal of the output terminal Y2, (n) is an output signal of the output terminal Y3, and (o) is an output signal of the output terminal Y4.

  The switch circuit 104 and the switch circuit 108 alternately for each line as shown in FIGS. 16 to 19 by the POL signal, POL_2 signal and STB signal input to the timing control circuit 115 and the POL_SEL signal input to the data register circuit 102. (Y1, Y2), or alternately (Y3, Y4) every two lines. As a result, positive and negative voltages are alternately applied to the liquid crystal electrodes in a predetermined cycle depending on which side of the two systems of the liquid crystal drive circuit Aa passes the 64-gradation image data.

As shown in FIGS. 21 to 22, the contacts 108 ₁ , 108 ₂ , 108 ₃ , and 108 ₄ are controlled by the switch control of the switch circuit 108 during the period when the STB signal input to the timing control circuit 115 is at a high level (H). Is turned off, the contacts 108b ₁ and 108b ₂ are turned on, and all the output terminals Y1 to Ym of the liquid crystal drive circuit Aa are reset to a voltage (for example, 5V) that is ½ of the liquid crystal drive voltage.

  In addition, by selecting one of the POL signal and the POL_2 signal for each pixel block according to the POL_SEL signal, the liquid crystal panel 4 can be selected according to one of the dot inversion driving method and the 2H dot inversion driving method. The pixel block is driven.

  The operation will be described in more detail. The data register circuit 119 connected to the output terminal Y1 of the liquid crystal drive circuit Aa always holds low level (L) data (image data with a constant gradation) and is connected to the output terminal Y2 of the liquid crystal drive circuit A. It is assumed that the data register circuit 120 always holds high level (H) data (image data with a constant gradation).

(A) In the case of the dot inversion driving method In step S02 of FIG. 3, if the input image data 28 of the pixel block of 4 pixels × 2 pixels has image data whose gradation is equal to or higher than the set gradation more than a predetermined number of pixels. If it is determined, the driving method is determined as the dot inversion driving method. In this case, the POL_SEL signal = 0, and the output terminals Y1 and Y2 side in FIGS. 16 to 21 and (a), (b), (d) to (g), (l), and (m) in FIG. The operation shown in

Based on the LCD control 5a polarity inversion switching control signal output from the 26 (POL_SEL signal = 0), the switch circuit 104 selects the POL signal by the contact 104 _5, the switch circuit 108 selects the POL signal by the contact 108 ₅ To do.

(1) Time t = t1 to t3 (corresponding to the left side in FIGS. 16 and 18)
When the POL signal (FIG. 22B) input to the timing control circuit 115 is at a high level (H) (time t = t1), the STB signal (FIG. 22A) is set to a high level, so that the switch circuit 108 The contacts 108 ₁ and 108 ₂ (FIG. 22 (f)), 108 ₃ and 108 ₄ (FIG. 22 (g)) are turned off. On the other hand, the contacts 108b ₁ and 108b ₂ ((not shown in FIG. 22, see left side of FIGS. 17 and 18) are turned on.

At this time, in one of the two systems, the contact 104 ₁ (FIG. 22 (d)) of the switch circuit 204 is turned on and the contact 104 ₃ (FIG. 22 (e)) is turned off. As a result, the low level (L) data held in the data register circuit 119 is transferred from the latch circuit 121 to the level shift circuit 109 via the switch circuit 104. The gradation voltage 10 V is selected by the decoder / gradation voltage selection circuit 111 and the current is amplified by the operational amplifier 113. When the STB signal (FIG. 22A) is switched to the low level (time t = t2), the contact 108 ₁ (FIG. 22F) of the switch circuit 108 is turned on, and the contacts 108b ₁ and 108b ₂ are turned on. Turns off. As a result, the image data is output to the output terminal Y1 (FIG. 22 (l)) of the liquid crystal drive circuit Aa via the switch circuit. Then, a gradation voltage of 10 V (polarity is plus “+”) having a predetermined voltage value is applied to the liquid crystal panel 4.

On the other hand, in the other of the two systems, the contact 104 ₂ (FIG. 22D) of the switch circuit 104 is turned on and the contact 104 ₄ (FIG. 22E) is turned off. Thus, the high level (H) data held in the data register circuit 120 is transferred from the latch circuit 122 to the level shift circuit 110 via the switch circuit 104. The gradation voltage 4.5V is selected by the decoder / gradation voltage selection circuit 112, and the current is amplified by the operational amplifier 114. When the STB signal (FIG. 22 (a)) is switched to a low level (time t = t2), the contact 108 ₂ (FIG. 22 (f)) of the switch circuit 108 is turned on, and the contacts 108b ₁ and 108b ₂ are turned on. Turns off. As a result, the image data is output to the output terminal Y2 (FIG. 22 (m)) of the liquid crystal drive circuit Aa via the switch circuit. Then, a gradation voltage of 4.5 V (polarity is minus “−”) having a predetermined voltage value is applied to the liquid crystal panel 4.

(2) Time t = t3 to t5 (corresponding to the left side in FIGS. 17 and 19)
When the POL signal (FIG. 22B) input to the timing control circuit 115 is low level (L) (time t = t3), the contact of the switch circuit 108 is determined by the high level of the STB signal (FIG. 22A). 108 ₁ and 108 ₂ (FIG. 22 (f)), 108 ₃ and 108 ₄ (FIG. 22 (g)) are turned off. On the other hand, the contacts 108b ₁ and 108b ₂ ((not shown in FIG. 22 but refer to the left side of FIGS. 20 and 21) are turned on.

At this time, in one of the two systems, the contact 104 ₁ (FIG. 22d) of the switch circuit 104 is turned off and the contact 104 ₃ (FIG. 22 (e)) is turned on. Thereby, the low level (L) data held in the data register circuit 119 is transferred from the latch circuit 121 to the level shift circuit 110 via the switch circuit 104. The decoder / gradation voltage selection circuit 112 selects the gradation voltage 10V, and the operational amplifier 114 amplifies the current. When the STB signal (FIG. 22A) is switched to a low level (time t = t4), the contact 108 ₃ (FIG. 22G) of the switch circuit 108 is turned on, and the contacts 108b ₁ and 108b ₂ are turned on. As a result, the image data is output to the output terminal Y2 (FIG. 22 (m)) of the liquid crystal drive circuit Aa via the switch circuit 108. Then, the gradation voltage having a predetermined voltage value is supplied to the liquid crystal panel 4. 10V (the polarity is minus “−”) is applied.

On the other hand, in the other of the two systems, the contact 104 ₂ (FIG. 22D) of the switch circuit 104 is turned off and the contact 104 ₄ (FIG. 22E) is turned on. Thereby, the high level (H) data held in the data register circuit 120 is transferred from the latch circuit 122 to the level shift circuit 109 via the switch circuit 104. The gradation voltage 4.5V is selected by the decoder / gradation voltage selection circuit 111, and the current is amplified by the operational amplifier 113. When the STB signal (FIG. 22A) is switched to a low level (time t = t4), the contact 108 ₄ (FIG. 22G) of the switch circuit 108 is turned on, and the contacts 108b ₁ and 108b ₂ are turned on. Turns off. As a result, the image data is output to the output terminal Y2 (FIG. 22 (m)) of the liquid crystal drive circuit Aa via the switch circuit. Then, a gradation voltage of 4.5 V (polarity is plus “+”) having a predetermined voltage value is applied to the liquid crystal panel 4.

(B) In the case of the 2H dot inversion driving method In step S02 of FIG. 3, the input image data 28 of the pixel block of 4 pixels × 2 pixels does not have image data whose gradation is equal to or higher than the set gradation more than the predetermined number of pixels. Is determined, the driving method is determined to be the 2H dot inversion driving method. In that case, the POL_SEL signal = 1, and the output terminals Y3 and Y4 side in FIGS. 16 to 21 and (a), (c), (h) to (k), (n), and (o) in FIG. The operation shown in

Based on the LCD control 5a polarity inversion switching control signal output from the 26 (POL_SEL signal = 1), the switch circuit 104 selects the POL_2 signal by contacts 104 _6, the switch circuit 108 selects the POL_2 signal by contacts 108 ₆ To do.

  At time t = t1 to t5, the POL_2 signal becomes a plus “+” and constant for two cycles of the STB signal (corresponding to the right side in FIGS. 16 and 17). On the other hand, at time t = t5 to t9, the POL_2 signal becomes negative “−” and is constant (corresponding to the right side in FIGS. 18 and 19). That is, 2H dot inversion driving is performed in which the polarity is inverted every two cycles of the STB signal.

  The operation of each circuit is different in timing (timing chart of each contact of the switch circuits 104, 108: (h) to (k), timing chart of the output terminals Y3, Y4: (n), (o)) Since this is the same as in the case of dot inversion, its description is omitted.

  The use of the data driver 2a as shown in FIG. 15 has two low-voltage and high-voltage circuits, so that a single circuit can handle a voltage more than twice the liquid crystal threshold voltage. Compared to the case, the voltage width to be dealt with by one system is small. That is, it is possible to reduce power consumption while suppressing deterioration in image quality, and to set the breakdown voltage of each circuit low.

  In the first embodiment, the polarity inversion driving method is changed for each of the plurality of gate lines. However, the polarity inversion driving method may be changed for each of the plurality of data lines. For example, it can be implemented by using the data driver 2a of the third embodiment and the line memory 13 for one frame.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the liquid crystal display device of the present invention. FIG. 2 is a graph showing the concept of the liquid crystal display device and the driving method of the liquid crystal display device of the present invention. FIG. 3 is a flowchart showing the operation of the first and third embodiments of the liquid crystal display device of the present invention. FIG. 4 is a conceptual diagram showing the voltage polarity applied to the liquid crystal panel in the present invention. FIG. 5 is a block diagram showing details of the gate driver in the liquid crystal display device of the present invention. 6A to 6C are block diagrams illustrating specific examples of switch control of each circuit. 7A to 7H are timing charts of the circuits shown in FIG. FIG. 8 is a block diagram showing the configuration of the second embodiment of the liquid crystal display device of the present invention. FIG. 9 is a conceptual diagram showing the voltage polarity applied to the liquid crystal panel in the present invention. FIG. 10 is a block diagram showing the configuration of the reverse recording position storage memory. FIG. 11 is a block diagram showing a configuration of the data line driving circuit. 12A to 12D are timing charts of the circuits shown in FIG. FIG. 13 is a block diagram showing the configuration of the third embodiment of the liquid crystal display device of the present invention. FIG. 14 is a conceptual diagram showing the voltage polarity applied to the liquid crystal panel in the present invention. FIG. 15 is a block diagram showing details of the gate driver in the liquid crystal display device of the present invention. FIG. 16 is a block diagram illustrating a specific example of switch control of each circuit. FIG. 17 is a block diagram illustrating a specific example of switch control of each circuit. FIG. 18 is a block diagram illustrating a specific example of switch control of each circuit. FIG. 19 is a block diagram illustrating a specific example of switch control of each circuit. FIG. 20 is a block diagram illustrating a specific example of switch control of each circuit. FIG. 21 is a block diagram illustrating a specific example of switch control of each circuit. 22A to 22O are timing charts of the circuits shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a, 30 Liquid crystal display device 2, 2a, 2b Data driver 3 Gate driver 3b Gate line drive circuit 4 Liquid crystal panel 4b Display part 5, 5a, 5b LCD controller 6 Reference gradation voltage generation part 7 Image drawing part 8 Control driver DESCRIPTION OF SYMBOLS 11 Image determination part 12 Method determination part 13 Line memory 21 Image data 22 Data side control signal 23 Gate side control signal 24 Reference gradation voltage 25 2nd polarity inversion signal (POL_2)
26 Polarity inversion switching control signal (POL_SEL)
28, 28-1 Input image data 29 Display control signal 29-1 Memory control signal 29-2, POL_SEL signal 28-3, 29-8 Polarity inversion control signal 29-4 Read signal 29-5 Display memory control signal 29- 6 STB signal 29-7 Timing control signal 29-9 Gate line control signal 29-10 Common voltage 35b Memory 35c Write signal 31 Display memory 32
33 Data line driving circuit 34
35 Inversion switching position storage memory 36 Memory control circuit 37 Timing control circuit 38 Vcom control circuit 39 Image drawing unit 101, 201 Shift register circuit 102, 202 Data register circuit 103, 203 Latch circuit 104, 108, 204, 208 Switch circuit 105, 205 level shift circuit 106, 206 decoder / gradation voltage selection circuit 107, 207 operational amplifier (op amp)
108b, 208a Common terminal switch 109, 209 (High voltage side) Level shift circuit 110, 210 (Low voltage side) Level shift circuit 111, 211 High voltage side decoder / gradation voltage selection circuit 112, 212 Low voltage side decoder / gradation voltage selection circuit 113, 213 High-voltage side operational amplifier 114, 214 Low-voltage side operational amplifier 117, 217 High-voltage side gradation voltage generation circuit 118, 218 Low-voltage side gradation voltage generation circuit 119, 120, 219, 220 Data register circuit 121, 122, 221, 222 Latch circuit

Claims (17)

A liquid crystal control unit for controlling the liquid crystal panel;
The liquid crystal control unit
An image determination unit that compares a gradation for each pixel in the input image data with a reference gradation;
A method determining unit that determines, based on the comparison result, a polarity inversion driving method when the input image data is displayed on a liquid crystal panel as a selective inversion driving method for each of a plurality of pixels of less than one frame including the pixel; A liquid crystal display device. The liquid crystal display device according to claim 1.
The liquid crystal display device, wherein the reference gradation is set to a gradation at a boundary between a gradation in which image quality in the liquid crystal panel is likely to deteriorate and a gradation in which deterioration is difficult. The liquid crystal display device according to claim 2,
The deterioration of the image quality is generation of flicker. The liquid crystal display device according to any one of claims 1 to 3,
The plurality of pixels includes a first number of horizontal lines corresponding to a first inversion period in an inversion driving method less than a reference gradation voltage, and a second inversion in an inversion driving method at or above a reference gradation gradation voltage. A liquid crystal display device, which is a pixel for a horizontal line that is a common multiple of the number of second horizontal lines for a period. The liquid crystal display device according to any one of claims 1 to 3,
When the number of pixels less than the gradation voltage of the reference gradation is n (n is a natural number) or more in the plurality of pixels, the method determination unit performs dot inversion on the inversion driving method in the plurality of pixels of the input image data. Drive system,
The n is a natural number, which is smaller than the number of the plurality of pixels. The liquid crystal display device according to claim 5.
When the number of pixels less than the reference gradation voltage is less than n in the plurality of pixels, the method determination unit changes the inversion driving method in the plurality of pixels of the input image data to 2H or more dot inversion. A liquid crystal display device with a drive system. The liquid crystal display device according to any one of claims 1 to 6,
A data line driving unit for controlling output to a data line of the liquid crystal panel so as to display the input image data by the selective inversion driving method;
The liquid crystal control unit outputs a selection signal indicating the selective inversion driving method to the data line driving unit;
The liquid crystal display device, wherein the data line driving unit includes an inversion switch unit that inverts the polarity of the output to the data line at the timing of polarity inversion in the selective inversion driving method based on the selection signal. The liquid crystal display device according to claim 7.
The data line driving unit includes:
A first switch unit that selects one of a first system circuit and a second system circuit as a selection system circuit as a path of the input image data;
A first level shift unit that shifts the input image data to a first voltage level as one polarity in the circuit of the first system;
A second level shift unit that shifts the input image data to a second voltage level lower than the first voltage level as the other polarity in the second system circuit;
A second switch that switches the output from the selection system circuit to output to the output terminal corresponding to the input image data, and based on the selection signal, the polarity inversion in the selective inversion drive method A liquid crystal display device that controls switching of the first switch unit and the second switch unit at timing. The liquid crystal display device according to any one of claims 1 to 8,
The method determining unit determines the polarity inversion driving method for each 2 × m (m is a natural number) frame. (A) comparing the gradation for each pixel in the input image data with a reference gradation;
(B) determining, based on the comparison result, an inversion driving method for displaying the input image data on a liquid crystal panel as a selective inversion driving method for each of a plurality of pixels less than one frame including the pixel;
(C) displaying the input image data by the selective inversion driving method; and a method for driving a liquid crystal display device. The method for driving a liquid crystal display device according to claim 10.
The step (b)
(B1) comprising a step of outputting a selection signal indicating the selective inversion driving method;
The step (c) includes:
(C1) A method for driving a liquid crystal display device, comprising: inverting the polarity when outputting the input image data at the timing of polarity inversion in the selective inversion driving method based on the selection signal. The method for driving a liquid crystal display device according to claim 11,
The step (c1) includes:
(C11) Based on the selection signal, the input image data is shifted to one of a first voltage level as one polarity and a second voltage level lower than the first voltage level as the other polarity. Steps,
(C12) A method of driving a liquid crystal display device, comprising: outputting the shifted input image data to a corresponding output terminal. The method for driving a liquid crystal display device according to any one of claims 10 to 12,
The liquid crystal display device driving method, wherein the reference gray level is set to a gray level at a boundary between a gray level at which flicker is easily visible and a gray level at which the liquid crystal panel is difficult to see. The method for driving a liquid crystal display device according to any one of claims 10 to 12,
The plurality of pixels includes a first number of horizontal lines corresponding to a first inversion period in an inversion driving method less than a reference gradation voltage, and a second inversion in an inversion driving method at or above a reference gradation gradation voltage. A method of driving a liquid crystal display device, which is a pixel for a horizontal line of a common multiple of a second horizontal line number for a period. The method for driving a liquid crystal display device according to any one of claims 10 to 12,
When the number of pixels less than the gradation voltage of the reference gradation is n (n is a natural number) or more in the plurality of pixels, the method determination unit performs dot inversion on the inversion driving method in the plurality of pixels of the input image data. Drive system,
The n is a natural number and is smaller than the number of the plurality of pixels. The method for driving a liquid crystal display device according to claim 15,
When the number of pixels less than the gradation voltage of the reference gradation is less than n (n is a natural number) in the plurality of pixels, the method determination unit sets the inversion driving method in the plurality of pixels of the input image data to 2H or A method for driving a liquid crystal display device in which a dot inversion driving system is used. The method for driving a liquid crystal display device according to any one of claims 10 to 16,
The step (b)
(B1) comprising a step of determining the selective inversion driving method for each 2 × m (m is a natural number) frame based on the comparison result;
The step (c) includes:
(C1) A method of driving a liquid crystal display device, comprising the step of displaying the input image data by the selective inversion driving method every 2 × m frames.

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