JP2008015038A - Display controller and its drive control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display controller capable of achieving low power consumption by efficiently collecting electric charges. <P>SOLUTION: The display controller includes latch circuits 101, 102 for holding the color data of a preceding line and a present line, a latch circuit 103 for holding a polarity signal of the preceding line, and a collection control circuit 109 for controlling a collection switch on the basis of the color data of the preceding line and the present line, the polarity signal, and the collection clock. In either case of a driving method for performing common inversion in each frame and a driving method for performing common inversion in each line, efficient charge collection can be performed and low power consumption can be achieved. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display control circuit and a drive control method thereof.

  Mobile display device driving ICs such as mobile phone terminals are required to have ultra-low power consumption. In mobile display devices, standby time (standby mode) occupies most during actual use, and the demand for low power consumption during standby time is severe.

  In mobile display devices, in the standby time, a display method using eight colors (display using 1-bit data for each RGB) is used, not full color (RGB: all gradation display). In the case of display in eight colors, the source driver that drives the source line is not an analog buffer, but a buffer that uses an inverter that drives the source line based on 1-bit data for each color data of RGB (in the case of a normal rotation buffer, the inverter 2 Stage configuration) is used.

  Note that as a configuration for reducing power consumption of a display device, Patent Document 1 discloses that a voltage higher than that of a common electrode is connected between a source driver (source driver) and a liquid crystal panel when the source line is connected. A drive system that recovers the charge of the source line that it had and has a recovery capacitor (external capacitor) that supplies the charge to the source line that had a lower voltage than the common electrode, and reuses the existing charge Discloses a TFT-LCD using multi-stage charge recycle with further improved power consumption reduction efficiency and a driving method thereof.

  FIG. 10 is a diagram showing a configuration of the invention described in Patent Document 1. In FIG. In addition, in this application, in order to make an explanation intelligible, the drawing of patent document 1 is rewritten. Referring to FIG. 10, in the display in eight colors used during standby (RGB: binary by 1-bit data, for example), the source buffer (source driver) 108 for driving the source line is not an analog buffer, but RGB color data. A tristate buffer that drives the source line based on 1-bit data is used. More specifically, the source buffer 108 is configured as a tri-state buffer including a first-stage inverter and an inverter whose output enable / disable is controlled by the recovery clock 105, and the recovery clock 105 is turned on (for example, HIGH level). ), The output of the source buffer 108 is HI-Z (high impedance state), the recovery switch 110 is turned on, and the charge of the source line is accumulated in the recovery capacitor 112. Next, the recovery clock 105 is turned off (for example, LOW level), the recovery switch 110 is turned off, the output of the source buffer 108 is enabled, and the source line is charged from the source buffer 108. In FIG. 10, the upper side from the pad 113 corresponds to a display control device (also referred to as “display control driver” or “controller IC”), and the lower side from the pad 113 corresponds to a display panel (LCD panel). The capacitance connected to each source line of the panel represents the pixel capacitance with an equivalent circuit. The source driver (source buffer) and the source line are also called a data driver and a data line, respectively.

  Further, for example, as shown in FIG. 11 (refer to FIG. 11, the drawing of Patent Document 2 has been rewritten in order to make the explanation easy to understand) in Patent Document 2, the COM buffer 118 is provided, and the recovery switch 119 is turned on. By doing so, the output (common electrode) of the COM buffer 118 and the recovery capacity can be recovered. In the configuration of FIG. 11, the source lines S1, S2, S3 and the common electrode (COMMON electrode) are collected simultaneously. In the example shown in FIG. 11, the capacitance of the common electrode to which the pad 120 is connected is used as the capacitance for storing the collected charges.

  Further, in Patent Document 3, for example, as shown in FIG. 12, a current line data latch circuit that holds current line color data, a previous line data latch circuit that holds previous line color data, and a previous line color. A switching control unit for controlling the recovery switch from the data, the current line color data, and the recovery clock is provided. As for the source line S1, the switching control unit 541 switches the high voltage switch (transfer) according to the output from the previous line data latch circuit 451 only when the outputs of the current line and the previous line data latch circuits 551 and 451 are different. Gate) 411 and one of the low-voltage switch (transfer gate) 421 are turned on, then the other is turned on in accordance with the output of the previous data latch by the transfer from the current line data latch circuit 551, and the source line S1 is set to the high voltage capacity. It is connected to the element (recovery capacity for high voltage) 431 or the low voltage capacity element (recovery capacity for low voltage) 432. In the source line where the applied voltage changes before and after the phase, the charge is effectively accumulated and supplied, reducing the power consumption, and in the source line where the applied voltage does not change, the holding voltage does not change. When voltage is applied, there is no power consumption.

  FIG. 13 is a timing chart for explaining the operation of the configuration shown in FIG. When the Nth line is displayed, the pixel switch control signal is activated, the source line of the display control device and the source line on the display panel become conductive, the output of the previous line data latch 451 is “0”, and the current line data The source line S 1 whose output of the latch 551 is “1” is connected to the low-pressure recovery capacitor 432 by the recovery clock HIGH, and then connected to the high-pressure recovery capacitor 431, and the voltage C is written by the D / A converter 311. Is done. When the output of the previous line data latch 452 is “1” and the output of the current line data latch 552 is “0”, the source line S2 is connected to the recovery capacitor 431 for high voltage by the recovery clock HIGH, and then for the low voltage. The voltage C is written by the D / A converter 312 by being connected to the recovery capacitor 432. In the N + 1 line, the source line S1 is changed from a high voltage to a low voltage, the source line S2 is changed from a low voltage to a high voltage, and the N line is mutually connected. The reverse driving operation is performed. In this way, the collection operation is controlled by determining whether or not to collect from the color data of the previous line and the current line.

JP 2001-22329 A JP 2002-244622 A JP 2003-271105 A

  In the conventional technique described above, when common inversion driving is not performed or when common inversion driving is performed for each frame, it is possible to obtain a desired recovery efficiency with respect to charge recovery. However, in the above-described conventional technique, when performing common inversion driving for each line, the method of judging based only on data may increase the current depending on the data. That is, there is a problem that the collection effect cannot be expected depending on the driving method.

  In order to solve the above-described problems, the invention disclosed in the present application is generally configured as follows.

  An apparatus according to one aspect of the present invention includes a recovery switch that controls connection / disconnection of an output node of a buffer (driver) that outputs data to a pixel of a display panel, and a charge recovery capacitor; Means for turning on and off the recovery switch based on data and polarity signals relating to the previous line and the current line.

  In the apparatus according to the present invention, the on / off control is performed by the control signal, and when on, the recovery switch that connects the source line to the recovery capacity, the data of the previous line, the data of the current line, and the polarity signal of the previous line For controlling ON / OFF of the recovery switch based on a combination of data of the previous line, current line data, previous line polarity signal, current line polarity signal, and recovery clock value A recovery control circuit that generates and outputs a control signal.

  In the present invention, the recovery control circuit determines the change of the previous data and the current data using the upper bits of the data.

  In the present invention, the previous data and the current data are 1-bit data for each color of RGB.

  In the present invention, the recovery control circuit determines the change of the previous data and the current data using 1-bit data.

  The present invention further includes another recovery switch for controlling on / off of the connection between the output of the buffer for driving the common electrode of the display panel and the recovery capacitor based on another input recovery clock. It is good also as a structure.

  In the present invention, the source buffer for driving the source line is based on a control signal from the recovery control circuit, when the recovery switch is on, the output is in a high impedance state, and when the recovery switch is off, Includes a tri-state buffer that is enabled for output.

  In the present invention, the collection control circuit inputs the data of the previous line and the data of the current line, and outputs the first and second values when the data of the previous line and the current line match or do not match. The first and second values are output when the previous line polarity signal and the current line polarity signal match and do not match. When the output of the first logic circuit and the output of the second logic circuit are the same, the output of the first logic circuit and the output of the second logic circuit match or do not match, The third logic circuit that outputs a second value, the number clock, and the output of the third logic circuit, and when the output of the third logic circuit is a second value, the number clock Is output as the control signal.

  The drive control method according to another aspect of the present invention performs on / off control of the connection between the output node of the driver and the charge recovery capacitor based on the data and the polarity signal regarding the previous line and the current line.

The method according to the present invention includes a recovery switch that controls connection between a source line connected to a pixel of a display panel and a recovery capacitor, and performs a recovery operation of the data line by performing on / off control of the recovery switch. A control method,
Holds the previous line data and current line data, holds the previous line polarity signal, and sets the recovered clock based on the combination of the previous line and current line data and the previous line and current line polarity signal values. In response, the collection switch is turned on and off.

  According to the present invention, efficient charge recovery can be performed and low power consumption can be realized. According to the present invention, efficient charge recovery can be performed regardless of the driving method.

  By applying the present invention to a display device of a portable terminal, it contributes to low power consumption during standby.

  In order to describe the present invention described above in more detail, it will be described below with reference to the accompanying drawings. The present invention includes a latch circuit (101, 102) for holding color data of the previous line and the current line, a latch circuit (103) for holding a polarity signal of the previous line, color data of the previous line and the current line, and a polarity signal. And a recovery control circuit (109) for controlling the recovery switch (110) based on the recovery clock and a charge recovery operation based on a change in data for each line and a polarity signal, so that a common for each frame. In either case of inversion driving or common inversion driving for each line, efficient charge recovery can be performed and low power consumption can be realized. Hereinafter, description will be made with reference to examples.

  FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. Referring to FIG. 1, in this embodiment, a previous line data latch 101 that latches data of the previous line, a current line data latch 102 that latches data of the current line, and a previous line polarity that latches the polarity signal of the previous line. A signal latch 103; a selector switch 106 for switching and outputting the R latch, G latch and B latch of the current line data latch 102; a decoder 107 for decoding the output of the selector switch 106; and an output (1 bit) of the decoder 107 Data) source buffer (source driver) 108, color data of the previous line and current line, polarity signal 104 of the previous line and current line, and control signal for controlling on / off of the recovery switch 110 from the recovery clock 105 A recovery control circuit 109 for outputting 111 and a recovery capacity 112; 0 has one end connected to the recovery capacitor 112, the other end is commonly connected to each source line (output of the source buffer 108).

  In FIG. 1, the upper side from the pad 113 represents a display control device (controller IC) including a source driver, and the lower side from the pad 113 corresponds to the display panel. The signal R selector Sig, the G selector Sig, and the B selector Sig are supplied from the display control device side, turn on the switches 114, 115, and 116, respectively, and connect the source line on the display control device side to the R, G, Connect to B source line. A pixel switch (TFT) of a line selected by a gate driver (not shown) is turned on, and data signals of R, G, and B source lines are applied to the pixel electrode.

  In the display in 8 colors used during standby (RGB: binary by 1-bit data, for example), the source buffer (source driver) 108 for driving the source line drives the source line based on 1-bit data for each color data of RGB. A tristate buffer is used. That is, source buffer 108 has the same configuration as that shown in FIG. 10, and has a two-stage configuration of an inverter that receives a binary signal from decoder circuit 107 and a tristate inverter. However, in this embodiment, the tri-state inverter is not directly controlled for output enable and output disable (output is in the HI-Z state) by the recovery clock as shown in FIG. Output enable and output disable are controlled by a signal obtained by inverting the control signal 111 from 109 by an inverter. When the recovery switch 110 is turned on by the control signal 111 from the recovery control circuit 109 that controls on / off of the recovery switch 110, the tri-state buffer is turned off (the output is in the HI-Z state). When 10 is off, the tri-state inverter is turned on (output enable state).

  2 and 3 are timing charts for explaining the operation of the present embodiment shown in FIG.

Front polarity signal = LOW, panel output Sig = LOW, white display (data = 1),
Current polarity signal = LOW, panel output Sig = HIGH, black display (data = 0),
Front polarity signal = HIGH, panel output Sig = LOW, black display (data = 0),
Current polarity signal = HIGH, panel output Sig = HIGH, white display (data = 1),
Consider the case. The panel output Sig is a signal output from the source buffer 108 (a signal from the pad 113).

  FIG. 2 shows a case where common inversion driving is performed for each frame.

<When changing from white to black>
As shown in FIG. 2, when the panel output Sig1 (R) shifts from the Nth line to the N + 1th line, the color shifts from white to black. At that time, the charging operation of the R data line is required. Therefore, in the N + 1 line, when the R selector Sig is on (when the switch 114 is on), the collection switch 1 (110) is once turned on, and the source line S1 is connected to the collection capacitor 112, and the panel load Is charged from the recovery capacity (see “Perform recovery” in the panel output Sig1 in FIG. 2). When the R selector Sig is on, the collection switch 1 (110) is turned off by the control signal 111 from the collection control circuit 109, and charging is performed from the source buffer 108. During the period when the recovery switch 1 (110) is on, the output of the source buffer 108 of the source line S1 is in the Hi-Z state.

<When there is no change from white to white and from black to black>
For example, when the panel output Sig2 (R) shifts from the N-th line to the (N + 1) -th line, it changes from black to black and there is no change in the output voltage, so no charging / discharging operation is required. For this reason, in this embodiment, the collecting operation is not performed.

<When changing from black to white>
For example, when the panel output Sig2 (G) shifts from the Nth line to the (N + 1) th line, the color shifts from black to white. At that time, a discharge operation is required. For this reason, the recovery switch 2 (110) is once turned on, the output of the source buffer 108 is connected to the recovery capacitor 112, and the recovery capacitor 112 is charged from the source line S2 (panel load). Next, the collection switch 2 (110) is turned off by the control signal 111 from the collection control circuit 109, the source buffer 108 is turned on, and the source buffer 108 is discharged. During the period when the recovery switch 2 (110) is on, the output of the source buffer 108 of the source line S2 is in the Hi-Z state.

  As described above, in this embodiment, even if the line changes, the polarity does not change (the value of the polarity signal does not change), and in a driving method in which common inversion driving is performed for each frame, white (data = The recovery operation can be efficiently performed by turning on the recovery switch only when the color changes from 1) to black (data = 0) or from black (data = 0) to white (data = 1).

  Next, a case where common inversion driving is performed for each line will be described with reference to FIG.

<When there is no change from white to white>
For example, when the panel output Sig1 (R) shifts from the Nth line to the N + 1th line, the color shifts from white to white. Since the polarities of the Nth and N + 1th lines are inverted, the source line S1 needs to be charged. Therefore, the recovery switch 1 (110) is turned on once, the source line S1 is connected to the recovery capacitor 112, and the source line S1 (display panel load) is charged from the recovery capacitor 112. Next, the collection switch 1 (110) is turned off by the control signal 111 from the collection control circuit 109, and the source line S1 is charged from the source buffer. During the period when the recovery switch 1 (110) is on, the output of the source buffer 108 of the source line S1 is in the Hi-Z state.

<When there is a change from white to black and from black to white>
For example, when the panel output Sig2 (R) shifts from the Nth line to the (N + 1) th line, the panel output Sig2 (R) changes from black to white and there is no change in the output voltage, so that the charging / discharging operation of the source line S2 is not required. Therefore, the collection operation is not performed.

<When there is no change from black to black>
For example, when the panel output Sig2 (G) shifts from the Nth line to the N + 1th line, the color shifts from black to black. At that time, the discharge operation of the source line S2 is required. Therefore, once the recovery switch 2 (110) is turned on and connected to the recovery capacity, the recovery capacity 112 is charged from the source line S2 (panel load). Next, the recovery switch 2 (110) is turned off by the control signal 111 from the recovery control circuit 109, and the source line S2 is discharged from the source buffer. During the period when the recovery switch is on, the output of the source buffer 108 of the source line S2 is in the Hi-Z state.

From the above, in a driving method that performs common inversion driving for each line,
From white (data = 1) to white (data = 1),
Black (data = 0) to black (data = 0)
As described above, the recovery operation can be efficiently performed by turning on the recovery switch 110 only when there is no change in the color data.

  FIG. 9 is a diagram showing an example of the configuration of the collection control circuit 109 of FIG. EXOR1 that takes exclusive OR of previous line polarity signal and current line polarity signal, EXOR2 that takes exclusive OR of previous line data and current line data, and exclusive output of EXOR1 and EXOR2 output An EXOR3 that takes a logical sum, and an AND circuit that outputs a logical product of the recovery clock and the output of the exclusive OR circuit EXOR3 as a recovery switch control signal (111 in FIG. 1). If the previous line polarity signal and the current line polarity signal do not match, if the previous line data and the current line data match, the recovery switch control signal is set to HIGH level by the recovery clock, and the previous line polarity signal and the current line polarity signal match. In this case, when the previous line data and the current line data do not match, the recovery switch control signal is set to HIGH level by the recovery clock.

  4 (A) and 4 (B) are diagrams for comparing and explaining the operational effects of the present invention and the prior art (Patent Documents 1 and 2). 4A and 4B, the left half is a border display, the upper right half is a white solid display, and the lower right half is a black solid display. It depends on the driving method for common inversion driving for each frame.

  FIG. 4A corresponds to the LCD screen of the present invention, and can perform a collecting operation in accordance with data changes. The presence / absence of the recovery operation is determined from the change in the polarity signal and the data (color data), and the charge recovery operation optimal for the color change can be performed.

  In the case of the conventional technique of FIG. 4B, collection is always performed for each line. For this reason, when the left half is a border display, the optimum collecting operation is performed. However, in the right half, even pixels that should not be collected originally (no color change) are collected. Since recovery is performed even when the source voltage does not need to change, an extra current is consumed. For this reason, the recovery efficiency also decreases.

  Although FIG. 4 shows the case of frame inversion, the same can be said for line inversion.

  FIGS. 5A and 5B are diagrams for comparing the effects of the present invention and the prior art (Patent Document 3), and are based on a driving method in which common inversion is performed for each frame. In both FIG. 5A showing an example of the present invention and FIG. 5B showing an example of the prior art, a collecting operation corresponding to a change in data is performed. However, the present invention promotes efficiency more than the conventional technique (Patent Document 3) in the following points.

  According to the present invention, the number of times of connection (collection) with an external capacitor is smaller than that of the prior art (the present invention, once, and twice in Patent Document 3). Therefore, according to the present invention, it is advantageous when writing is performed a plurality of times. For example, in the case of writing three times, 1 × 3 = 3 times in the present invention, and 2 × 3 = 6 times in Patent Document 3.

  Other than the frame inversion, Patent Document 3 cannot achieve its effect. On the other hand, the present invention achieves efficient collection during line inversion. This will be described below.

  6A and 6B are diagrams for comparing the effects of the present invention with the prior art (Patent Document 3), and are based on a driving method in which common inversion is performed for each line. In FIG. 6A exemplarily illustrated in the present invention, a collecting operation corresponding to a polarity signal and a data change can be performed. In FIG. 6B exemplifying the prior art (Patent Document 3), the collection operation is performed according to the data change. However, since the polarity signal is not taken into consideration, the collection is performed for each line when the left half is a border display. This is not the optimal recovery operation, and causes an increase in current.

  The left half is a border display, the upper right half is a white solid display, and the lower right half is a black solid display. When the common inversion driving is performed for each line, it is necessary to perform the collecting operation only when the color does not change within one screen. The reason is that even if there is a color change for each line, the polarity of the line also changes, so that it is not necessary to change the voltage of the data line. According to the present invention, since the presence / absence of the collecting operation is determined from the polarity signal and the color data, the collecting operation optimum for the color change can be performed.

  In the case of Patent Document 3 in FIG. 6B, the operation is completely opposite to that of the present invention in FIG. This is because a polarity signal that is inverted for each line is not taken into consideration. For this reason, the current reduction effect by charge recovery cannot be realized, and an excess current flows, resulting in an increase in current consumption. In the case of Patent Document 3, it can be applied to a driving method in which common inversion is performed for each frame or a method in which common inversion driving is not performed, but is not suitable for a driving method in which common inversion is performed for each line.

  On the other hand, the present invention can realize the optimum recovery operation for all the driving methods regardless of the driving method.

  Next, another embodiment of the present invention will be described. FIG. 7 is a diagram showing a configuration of another embodiment of the present invention, and shows a circuit configuration including a COM buffer.

  In many cases, the display control driver includes a COM buffer 118 in addition to the source output. According to this embodiment, the recovery switch 4 (119) is turned on by the COM recovery clock 105B so that the charge of the COM output can also be recovered by the recovery capacitor 112. FIG. 8 is a timing chart for explaining the operation of another embodiment of the present invention shown in FIG. At the beginning of the frame, the recovery clock (for COM) 105B is activated, the recovery switch 4 (119) is turned on, and the charge of the COMMON electrode (COM output Sig) is recovered. When the recovery switch 4 (119) is on, the output of the COM buffer 118 is HI-Z. When the recovery switch 4 (119) is turned off, the COM output Sig is driven by the COM buffer 118.

  According to each of the embodiments described above, the recovery operation is performed more efficiently by determining the recovery / non-recovery according to the change and polarity of data, thereby realizing low power consumption. The electrification recovery according to the present embodiment is preferably performed in the 8-color mode in the standby mode or the like.

  The recovery control circuit 109 makes a determination based on predetermined high-order bits of the RGB data when detecting a change between the previous line data and the current line data. The upper bits may be a plurality of bits from the MSB (Most Significant Bit) side, or may be the MSB 1 bit.

  In the above-described embodiment, the charge recovered from the source line to the recovery capacitor 112 has been described along with an example of reuse in the source line. However, the present invention is not limited to such a configuration, and the recovery capacitor Of course, the accumulated charge 112 may be reused in other circuits.

  In the above embodiment, the RGB 8-color display mode has been described, but the present invention can of course be applied to a display device that does not perform color display.

  Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the configurations of the above-described embodiments, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, including modifications.

It is a figure which shows the structure of one Example of this invention. It is a timing waveform diagram for demonstrating operation | movement of one Example of this invention. It is a timing waveform diagram for demonstrating operation | movement of one Example of this invention. (A), (B) is a figure for comparing and explaining this invention and a prior art (patent document 1, 2). (A), (B) is a figure for comparing and explaining this invention and a prior art (patent document 3). (A), (B) is a figure for comparing and explaining this invention and a prior art (patent document 3). It is a figure which shows the structure of the other Example of this invention. It is a timing waveform diagram for demonstrating operation | movement of the other Example of this invention. It is a figure which shows the structure of the collection | recovery control circuit in one Example of this invention. It is a figure which shows an example of a structure of a prior art (patent document 1). It is a figure which shows an example of a structure of a prior art (patent document 2). It is a figure which shows an example of a structure of a prior art (patent document 3). It is a timing waveform diagram for demonstrating operation | movement of a prior art (patent document 3).

Explanation of symbols

101 previous line data latch 102 current line data latch 103 previous line polarity signal latch 104 polarity signal 105 recovery clock 105B recovery clock for COM 106 switch 107 decoder 108 source buffer 109 recovery control circuit 110 recovery switch 111 control signal 112 recovery capacity 113, 120 Pad 114, 115, 116 Switch 118 COM buffer 119 Recovery switch 311, 312 D / A converter 411, 412 High pressure switch 421, 422 Low pressure switch 431 High pressure recovery capacity 432 Low pressure recovery capacity 451, 452 Previous line data latch 551, 552 Current line data latch 541, 542 switching control unit

Claims (14)

A recovery switch that controls connection / disconnection of an output node of a buffer that drives and outputs data to pixels of the display panel, and a capacitor for charge recovery;
Means for on / off control of the recovery switch based on data and polarity signals for the previous line and the current line;
A display control device comprising: A recovery switch that is on / off controlled by a control signal and connects the source line to the recovery capacity when on,
A circuit that holds the data of the previous line, the data of the current line, and the polarity signal of the previous line;
Based on the combination of the previous line data and current line data, the previous line polarity signal and current line polarity signal, and the value of the recovery clock, the control signal for controlling on / off of the recovery switch is generated and output. A recovery control circuit;
A display control apparatus comprising:   The display control apparatus according to claim 2, wherein the collection control circuit determines a change between the previous data and the current data using an upper bit of the data.   The display control apparatus according to claim 2, wherein the previous data and the current data are 1-bit data of each color of RGB.   5. The display control apparatus according to claim 4, wherein the collection control circuit determines the change between the previous data and the current data using 1-bit data.   It further comprises another recovery switch for controlling on / off of the connection between the output of the buffer for driving the common electrode of the display panel and the recovery capacitor based on another input recovery clock. The display control device according to claim 2.   Based on a control signal from the recovery control circuit, the source buffer that drives the source line is in an output high impedance state when the recovery switch is on, and in an output enable state when the recovery switch is off. The display control apparatus according to claim 2, further comprising a tristate buffer. The collection control circuit inputs the data of the previous line and the data of the current line, and outputs the first and second values respectively according to the coincidence and mismatch of the data of the previous line and the data of the current line And the logic circuit of
A second logic circuit for inputting the polarity signal of the previous line and the polarity signal of the current line, and outputting the first and second values in accordance with the coincidence and mismatch of the polarity signal of the previous line and the polarity signal of the current line, respectively. When,
The output of the first logic circuit and the output of the second logic circuit are input, and the first and second logic circuits are output in accordance with the coincidence and mismatch of the output of the first logic circuit and the output of the second logic circuit. A third logic circuit that outputs a value of 2, respectively;
The frequency clock and the output of the third logic circuit are received, and when the output of the third logic circuit is a second value, the frequency clock is output as the control signal. Item 6. The display control device according to Item 2 or 5.   A display device comprising the display control device according to claim 1 or 2 and a display panel.   A portable terminal comprising the display device according to claim 9.   A display device characterized in that on / off control of a connection between an output node of a buffer for driving and outputting data to a display panel and a capacitor for charge collection is performed on the basis of data and polarity signals relating to the previous line and the current line. Drive control method. A drive control method for a display device having a recovery switch for connecting a source line to a recovery capacity,
While holding the previous line data and current line data, holding the previous line polarity signal,
A drive control method for controlling on / off of the recovery switch in response to a recovery clock based on a combination of data of the previous line and the current line and a value of a polarity signal of the previous line and the current line .   The drive control method according to claim 11, wherein the change of the previous data and the current data is determined using upper bits of data.   12. The drive control method according to claim 11, wherein the previous data and the current data are RGB 1-bit data for each color.

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