KR102491946B1 - Driver ic and display using the same - Google Patents

Abstract

According to the present embodiment, a controller for transmitting and receiving a digital data signal in which a copy image signal obtained by copying at least one bit among a plurality of bits of a digital image signal is disposed between a clock signal and a digital image signal, a data driver IC, and a display device using the same is to provide
According to the present embodiments, it is possible to prevent distortion of data from occurring even when a state change occurs when a clock signal and an image signal are converted into transmitted clock signals and thus, it is possible to suppress generation of noise on a screen of a display device. .

Description

Controller, driver IC and display device using the same {DRIVER IC AND DISPLAY USING THE SAME}

The present embodiments relate to a controller, a driver IC, and a display device using the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and liquid crystal display devices (LCD: Liquid Crystal Display Device), plasma display devices, organic light emitting display devices ( Various types of display devices such as organic light emitting display devices (OLEDs) are being utilized.

Such a display device may display an image by transmitting a data signal from a data driver to the display device based on a timing signal provided from a timing controller. In order to transmit a plurality of timing control signals and digital image signals to the data driver, the timing control unit requires data transmission lines for transmitting digital image signals of R data, G data, and B data between the timing control unit and the data driver, and the data driver. Many wires, such as control wires for controlling operation timing such as output and polarity conversion operation, and transmission wires for transmitting clock signals, must be formed.

In order to solve the above problem, the number of wires can be reduced by transmitting clock signals and digital image signals together through a protocol between a timing controller and a data driver. However, when a clock signal and a digital video signal are transmitted through the same wiring, a digital video signal may be transmitted after the clock signal, and the state of the signal may be changed when the transmitted signal is converted from the clock signal to the digital video signal. . In addition, when the state of the signal is changed in the process of transmitting the signal, distortion may occur in the digital image signal following the clock signal, resulting in noise and the like in the image displayed on the display device.

An object of the present embodiments is to provide a controller, a data driver IC, and a display device using the controller and data driver IC that prevent deterioration of image quality by minimizing generation of noise.

Another object of the present embodiments is to provide a data transmission method that does not require redesign of a controller or driver IC by preventing a change in data packets to be transmitted.

In one aspect, the present embodiments receive a digital data signal including a clock signal and a digital video signal according to a predetermined protocol, but transmit at least one bit among a plurality of bits of the digital video signal between the clock signal and the digital video signal. Includes a data signal receiving unit for receiving a digital data signal in which the copied video signal is placed, and a data signal supplying unit for receiving the digital data signal received from the data signal receiving unit and converting a plurality of digital video signals into analog data signals and outputting the converted data signal. It is to provide a data driver IC that

In another aspect, the present embodiments receive a digital video signal, generate a duplicated video signal in which at least one bit of a plurality of bits of the digital video signal is copied, and convert a clock signal and a digital video signal according to a predetermined protocol. It is to provide a controller for generating a digital data signal including a clock signal and a digital image signal, generating a digital data signal including a duplicate image signal between a clock signal and a digital image signal, and transmitting the generated digital data signal through one wire.

In another aspect, the present embodiments transmit a digital data signal including a clock signal and a plurality of digital image signals according to a display panel including a plurality of pixels formed in an area where a gate line and a data line intersect, and a predetermined protocol. However, a control unit for transmitting a digital data signal in which a copy video signal obtained by copying at least one bit of the video signal of the digital video signal is disposed between the clock signal and the digital video signal, a gate driver for transmitting a gate signal to a gate line, and a control unit To provide a display device including a data driver that receives digital data signals from the digital data signals, extracts a plurality of digital video signals from the digital data signals, converts them into analog data signals, and outputs them to data lines.

In another aspect, the present embodiments are a data transmission method for transmitting data for transmitting a clock signal and a digital image signal by dividing a period in which a data signal is transmitted into a first period, a second period, and a third period. Receiving a digital video signal and a control signal from a host device, receiving a digital video signal and a control signal and copying at least one bit of the digital video signal to generate a duplicate video signal, and clocking in a first period In the second period, the duplicate video signal and the digital video signal are transferred so that the duplicate video signal is adjacent to the clock signal, and in the third period, the dummy signal is transferred so that the third period is shorter than the first period. It is to provide a data transmission method comprising transmitting a signal.

According to the present embodiments, it is possible to prevent data distortion from occurring even when a state change occurs when the clock signal and the image signal are converted, thereby suppressing noise on the screen of the display device 100. It is possible to provide a controller, data driver IC, and a display device using the same.

In addition, according to the present embodiments, since the data packet can be set identically to the protocol used previously, it is possible to provide a data transmission method capable of transmitting data without requiring changes such as redesigning the driver IC. there is.

1 is a structural diagram showing an example of a display device according to the present embodiment.
FIG. 2 is a structural diagram showing a first embodiment of the data driver shown in FIG. 1;
FIG. 3 is a structural diagram showing a second embodiment of the data driver shown in FIG. 1;
FIG. 4A is a timing diagram illustrating a first embodiment of a data packet transmitted according to a signal transmission protocol between a controller and a data driver shown in FIG. 1 .
FIG. 4B is a timing diagram illustrating a second embodiment of a data packet transmitted by a signal transmission protocol between a control unit and a data driver shown in FIG. 1 .
FIG. 5 is a graph showing state changes of a clock signal and a digital data signal in a data packet transmitted to the data driver shown in FIG. 1 .
6A is a graph showing the degree of distortion of a digital image signal not adjacent to a clock signal when the signal is transmitted.
6B is a graph showing the degree of distortion of a digital image signal adjacent to a clock signal when the signal is transmitted.
7 is a flowchart illustrating an embodiment of a data transmission method according to this embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention are described in detail below with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present invention. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

1 is a structural diagram showing an example of a display device according to the present embodiment.

Referring to FIG. 1 , a display device 100 may include a display panel 110 , a controller 120 , a gate driver 130 , and a data driver 140 .

The display panel 110 includes a plurality of gate lines (G1, G2, ..., Gn-1, Gn) and a plurality of data lines (D1, D2, ..., Dm-1, Dm) formed in the intersection area. A pixel 101 may be included. Also, the display panel 110 may be a liquid crystal display panel or an organic light emitting display panel using an organic light emitting diode. However, it is not limited thereto. In addition, the display panel 110 may further include a plurality of power supply lines and, in the case of an organic light emitting display panel, may further include a plurality of emission signal lines and initialization signal lines. However, the wiring of the display panel 110 is not limited thereto.

The control unit 120 may receive digital image signals (RGB) from an external host device (not shown) and transmit them to the data driver 140 . In addition, the control unit 120 controls the gate driver 130 and the data driver 140 by receiving control signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a clock signal (ck) from the host device. control signals (GCS, DCS) to be transmitted. The control signals GSC and DSC that control the gate driver 130 and the data driver 140 generated by the controller 120 include a clock signal ck, a gate enable, a gate start pulse, a data enable, and a data start pulse. , may be a polarity signal (POL). However, it is not limited thereto. Also, the controller 120 may be a timing controller. However, it is not limited thereto.

The control unit 120 may receive control signals (GCS and DCS) and digital image signals (RGB) from the host device through a preset interface protocol. In addition, the control unit 120 can communicate with the data driver 140 through a preset interface protocol to transmit digital data signals including a clock signal ck and a plurality of digital image signals RGB. . In addition, the controller 120 may transmit a digital data signal in which a copy image signal obtained by copying at least one bit of an image signal among a plurality of bits of the digital image signal is disposed between the clock signal and the digital image signal. The controller 120 can transmit the clock signal ck and the digital image signal RGB to the data driver 140 through the same wire according to a preset protocol. Accordingly, the number of wires disposed between the controller 120 and the data driver 140 can be reduced. However, allowing the clock signal ck and the digital image signal RGB to flow through the same wire is not limited to reducing the number of wires. Here, the transmission of the clock signal ck and the digital image signal RGB together to the data driver 140 means that the digital image signal RGB is transmitted through the same wiring after the clock signal ck is transmitted. can

In addition, one or more communication interfaces may exist between the control unit 120 and the data driver 140, and a corresponding protocol is defined for each communication interface. The interface between the control unit 120 and the data driver 140 may include one or more of EPI (Embedded Clock Point to Point Interface) and LVDS (Low-Voltage Differential Signaling). However, the interface is not limited thereto.

The gate driver 130 is connected to the plurality of gate lines (G1, G2, ..., Gn-1, Gn) and each pixel 101 through the plurality of gate lines (G1, G2, ..., Gn-1, Gn) A gate signal can be transmitted to In addition, the gate driver 130 may transmit a light emitting signal by being connected to the light emitting signal line if the light emitting signal line is wired in the display panel 110 . However, it is not limited thereto. The gate driver 130 may receive the gate driver control signal GCS from the controller 120 . Here, the gate driver 130 is illustrated as a component separate from the display panel 110, but is not limited thereto and may be configured on the side of the display panel 110 in a gate-in-panel (GIP) method.

The data driver 140 is connected to a plurality of data lines (D1, D2, ..., Dm-1, Dm), and each pixel 101 through a plurality of data lines (D1, D2, ..., Dm-1, Dm) data signals can be transmitted. The data driver 140 may receive a digital video signal RGB and a data driver control signal DCS from the control unit 120 . Here, the data driver 140 is shown as one component, but is not limited thereto and may be implemented in plural according to the resolution of the display panel 110 . In addition, the data driver 140 can receive the clock signal ck among the digital image signal RGB and the data driver control signal DCS through the same wire, and thus the control unit 120 and the data driver 140 The number of wires between them can be reduced.

In addition, the data driver 140 serves as a receiving unit for receiving the digital image signal (RGB) and the data driver control signal (DCS) transmitted from the controller 120, and the controller 120 transmits the digital image signal (RGB) and data It can perform the role of a transmitting unit that generates a driver control signal (DCS) and transfers it to the data driver 140 . Accordingly, the controller 120 and the data driver 140 may be driven as a pair.

FIG. 2 is a structural diagram showing a first embodiment of the data driver shown in FIG. 1;

Referring to FIG. 2 , the data driver 240 may include a data signal receiver 241 and a data signal supply unit 242 .

The data signal receiving unit 241 receives a digital data signal including a digital image signal RGB and a data driver control signal DCS including a clock signal ck according to a preset protocol, and receives the clock signal ck It is possible to receive a digital data signal in which a copy image signal obtained by copying at least one bit of the image signal among the plurality of digital image signals is disposed between the digital image signal and the plurality of digital image signals. The data signal receiving unit 241 may serially receive digital image signals and transmit them to the data signal supplying unit 242 in parallel. Since the data signal receiving unit 241 can receive the digital image signal RGB and the clock signal ck through the same wire, the number of wires connected to the control unit 120 can be reduced.

The data signal supplier 242 may receive the digital data signal received from the data signal receiver 241 and convert a plurality of digital image signals into analog data signals to output. The data signal supply unit 242 may output analog data signals in parallel and transmit them to a plurality of data lines D1, D2, ..., Dm-1, Dm.

FIG. 3 is a structural diagram showing a second embodiment of the data driver shown in FIG. 1;

Referring to FIG. 3 , the data driver 340 may include a shift register 341a, a latch 341b, a digital to analog converter (DAC) 342a, and an output buffer 342b. The shift register 341a receives the data driver control signal (DCS) and stores the serially transmitted digital image signal (RGB) in the latch 341b, and the latch 341b stores the serially transmitted digital image signal (RGB). can be output in parallel. Also, the DAC 342a operates by receiving the polarity signal POL, converts the digital image signal RGB into an analog data signal, and transfers the converted data signal to the output buffer 342b. Also, the output buffer 342b may transfer analog data signals output from the DAC 342a to a plurality of data lines in parallel. Here, the shift register 341a and the latch 341b may be the data signal receiver 241 of FIG. 2 , and the DAC 342a and the output buffer 342b may be the data signal supply unit 242 of FIG. 2 .

4A is a timing diagram illustrating a first embodiment of a data packet transmitted according to a signal transmission protocol between a control unit and a data driver shown in FIG. 1, and FIG. 4B is a signal transmission between a control unit and a data driver shown in FIG. 1 It is a timing diagram showing the second embodiment of the data packet transmitted by the protocol.

A data packet of a data signal transmitted from the controller 120 to the data driver 140 may include a video signal, a clock signal, and a dummy signal composed of a plurality of bits. The transmission time of 1 bit may take 1 Unit Interval (UI), but may vary depending on the resolution of the display panel 110 or the bit rate of data. In addition, the data packet is transmitted by dividing the digital data signal into three transmission sections (1phase, 2phase, 3phase) by a preset protocol, and the clock signal (ck) is transmitted in the first section (1phase), and the second section The digital image signal (RGB) may be transmitted in phase 2, and the dummy signal (DMY) may be transmitted in phase 3. Also, the digital image signals R0, R1, R2, ..., G0, G1, G2, ..., B5, B6, B7 may be differential signals. In addition, the digital image signal RGB may consist of a total of 24 bits in which data for red (R), green (G), and blue (B) are expressed in 8 bits, respectively. However, it is not limited to this, and if the R, G, and B data each contain 10 bits of data, the digital video signal can contain a total of 30 bits, and if the R, G, B data each contain 6 bits of data, A digital video signal may include a total of 18 bits.

Referring to FIG. 4A, it will be described that the digital image signal can consist of a total of 24 bits, in which data for red (R), green (G), and blue (B) are each represented by 8 bits. The data packet includes a clock signal, a digital image signal, and a dummy signal, and 2 bits may be allocated to the clock signal and 1 bit may be allocated to the dummy signal. Also, the dummy signal and the clock signal may have a logic value of 0 1 1 (L H H) according to a preset protocol. In addition, the data packet may include a 1-bit copy video bit (R0'). Accordingly, the data packet may include a total of 28 bits, including 2 bits of clock signal (CK), 1 bit of duplicate image signal (R0`), 24 bits of digital image signal (RGB), and 1 bit of dummy signal (DMY). Transmission time may take 28 UI. The first period (1 phase) takes 2 UI time because the clock signal (ck) is 2 bits, and the third period (3 phase) takes 1 UI time because the dummy signal (DMY) is 1 bit. ) may take shorter than the first period (1 phase).

Referring to FIG. 4B, a data packet of a data signal may include a dummy signal, a clock signal, and a digital image signal. The data packet includes a clock signal, a digital video signal, and a dummy signal, and 2 bits can be allocated to each of the clock signal and the dummy signal. Also, the dummy signal and the clock signal of the data packet may have a logic value of 0 0 1 1 (L L H H) according to a preset protocol. Accordingly, a data packet may be composed of a clock signal of 2 bits, a digital video signal of 24 bits, and a dummy signal of 2 bits, so that a total of 28 UIs may be required to transmit the data packet. At this time, the first period (1 phase) takes 2 UI time because the clock signal (ck) is 2 bits, and the third period (3 phase) takes 2 UI time because the dummy signal (DMY) is 2 bits. The period (phase 1) and the third period (phase 3) may take the same amount of time. Here, the same does not mean completely the same in terms of time, but may include a slight time difference.

Therefore, the same time may be taken to transmit data packets in both FIGS. 4A and 4B, so data packets may be transmitted using the same interface protocol.

And, as shown in FIG. 5, the clock signal ck can be transmitted in the intervals T1 and T2, and the digital image signal RGB can be transmitted in the interval T3. At this time, since the clock signal (ck) is fixed as a high state (H) signal and the digital image signal is a differential signal, the high state (H) signal is transmitted and the first digital image signal (R0) is transmitted in the sections T1 and T2. It can be seen that a signal having both a high state (H) and a low state (L) is being transmitted in the T3 section. Accordingly, it can be seen that the state of the transmitted signal is changed at the point at which the clock signal ck is converted to the digital image signal R0 (the point at which the period T3 begins). However, although not shown, since the digital video signal is transmitted as a differential signal, no state change appears between each bit of the digital video signal.

Due to this, when the transmitted signal is converted from the clock signal ck to the digital image signal RGB, distortion may occur in the digital image signal RGB. More specifically, distortion may occur in the first digital image signal R0 adjacent to the clock signal ck. Therefore, as shown in FIG. 4B, the digital image signals R0, R1, R2, ..., G0, G1, G2, ..., B5, B6, B7 adjacent to the clock signal ck are all displayed on the display panel 110. If data is actually used for the image displayed in , noise may appear on the display panel 110 due to distortion generated in the first digital image signal R0. In addition, as shown in FIG. 4A, between the clock signal ck and the first digital image signal R0, the digital image signals R0, R1, R2, ..., G0, G1, G2, ..., B5, B6, B7 ), distortion may occur in the copied image data R0' when one of the plurality of bits of ) is arranged. However, when the data packet is configured as shown in FIG. 4A, distortion occurs only in the copied image data (R0′) that is not actually used for displaying the image, and distortion does not occur in the digital image signal actually used for the image. Therefore, noise may not appear on the display panel 110 .

Here, the copied image data is illustrated as replicating the first bit R0 of the digital image signal, but is not limited thereto, and it is also possible to copy any one bit among a total of 24 bits of the digital image signal. In addition, it is also possible to pre-store one bit of a digital video signal and insert the stored bit between a digital video signal and a clock signal to be generated later.

6A is a graph showing the degree of distortion of a digital video signal that is not adjacent to a clock signal when a signal is transmitted, and FIG. 6B is a graph showing the degree of distortion of a digital video signal that is adjacent to a clock signal when a signal is transmitted. it's a graph

Referring to FIGS. 6A and 6B , an x-axis is a time axis and a y-axis is an axis for voltage magnitude. In addition, since the digital video signal is a differential signal, a high state and a low state appear simultaneously within 1 UI, and a diamond-shaped empty space may be displayed in the center. Here, the lozenge shape is not an exact lozenge shape, and a lozenge is displayed by connecting a virtual line to an empty space. In addition, the presence or absence of distortion of the signal can be determined using the size of the lozenge.

In order to determine the size of the lozenge, the lengths to the upper vertex and the lower vertex based on the imaginary horizontal line at the center of the lozenge are referred to as d11 and d12 in FIG. 6a, and d21 and d22 in FIG. 6b, respectively. In 6a, the length to the left vertex and the length to the right vertex based on the imaginary vertical line at the center of the lozenge are referred to as c11 and c21, respectively, and in FIG. 6b, the length to the left vertex and the right vertex The lengths up to may be referred to as c21 and c22, respectively. In the case of a normal range in which no distortion occurs, it can be set that each of d11, d21, d12, and d22 must take 0.25 UI or more, and each of c11, c21, c12, and c22 must have a difference of 90 mV or more.

Comparing Figures 6a and 6b, it can be seen that the size of the lozenge shown in Figure 6a is larger than the size of the diamond shown in Figure 6b, and the size of the diamond shown in Figure 6a is 0.25 UI for d11 and d12. It is larger and c11 and c12 are sizes that can be determined to be in the normal range than 90 mV, but in the case of FIG.

Therefore, if the cloned video signal is placed adjacent to the clock signal, only the cloned video signal can be distorted, and the actual used video signal is not distorted, so no noise is generated in the image displayed on the display panel 110. can

7 is a flowchart illustrating an embodiment of a data transmission method according to this embodiment.

Referring to FIG. 7, a data signal transmission period is divided into a first period (1 phase), a second period (2 phase), and a third period (3 phase), and a clock signal (ck) and a digital video signal (RGB) are transmitted. As a data transmission method for transmitting data to be transmitted, a digital video signal and a control signal are received from a host device (S700), a digital video signal (RGB) and a data driver control signal (DSC) are received and at least one of the digital video signals Generating a copy video signal by copying the bits of (S710), causing the clock signal (ck) to be transmitted in the first period (1 phase), and the copy video signal and digital video signal (RGB) in the second period (2 phase) is transmitted and the dummy signal (DMY) is transmitted in a third period (3phase), and data may be transmitted such that the third period (3phase) is shorter than the first period (1phase) (S720). Since the clock signal (ck) and the digital video signal (RGB) are serially transmitted together, distortion may occur in the video signal caused by the state change of the digital video signal (RGB) in the clock signal (ck), but the copy video signal By disposing between the clock signal and the digital image signal actually used in the image displayed on the display panel, it is possible to prevent noise from occurring by causing distortion to the duplicated image signal. In addition, although the time required for the second phase (2 phase) may be increased by 1US due to the duplicate video signal, the third phase (3 phase) in which the dummy signal is transmitted is shortened so that the total transmission time of one data packet is reduced. It takes 28 UI, and there is an advantage that there is no need to change the design or protocol of the control unit 120 or the data driver 140.

In one embodiment, the bit of the video signal to be copied by the copy video signal may be at least one bit adjacent to the clock signal among a plurality of bits of the digital video signal.

The above description and accompanying drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art can combine the configuration within the scope not departing from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device (100)
110: display panel
101: pixel
120: control unit
130: gate driver
140: data driver

Claims (12)

A digital data signal including a clock signal and a digital video signal is received according to a predetermined protocol, and a copy video signal obtained by copying at least one bit among a plurality of bits of the digital video signal is provided between the clock signal and the digital video signal. a data signal receiver for receiving the digital data signal; and
A data signal supply unit receiving the digital data signals received by the data signal receiver and converting the plurality of digital image signals into analog data signals and outputting them;
The copy video signal is arranged between the clock signal and a first digital video signal transmitted adjacent to the clock signal, so that the digital data signal is arranged in the order of the clock signal, the duplicate video signal, and the digital video signal. Driver IC. According to claim 1
According to the preset protocol, the digital data signal is divided into three transmission sections and received, the clock signal is transmitted in the first section, and the duplicate video signal and the digital video signal are transmitted in the second section. A data driver IC in which a dummy signal is transmitted in section 3 and the section 3 is shorter than section 1. According to claim 1,
The copy image signal is a signal obtained by copying at least one bit transmitted most adjacent to the clock signal among a plurality of bits of a digital image signal. Receiving a digital video signal and generating a duplicate video signal in which at least one bit of a plurality of bits of the digital video signal is copied;
A digital data signal including a clock signal and a digital video signal is generated according to a predetermined protocol, the digital data signal in which the duplicate video signal is disposed between the clock signal and the digital video signal is generated, and the generated digital data signal is generated. The data signal is transmitted through one wire,
The duplicated video signal is disposed between the clock signal and a first digital video signal transmitted adjacent to the clock signal, so that the digital data signal is disposed in the order of the clock signal, the duplicated video signal, and the digital video signal. . According to claim 4
According to the preset protocol, the digital data signal is divided into three transmission sections and transmitted, the clock signal is transmitted in the first section, and the duplicate video signal and the digital video signal are transmitted in the second section. A controller in which a dummy signal is transmitted in section 3, and the section 3 is shorter than section 1. According to claim 4,
The copy video signal is a signal obtained by copying at least one bit transmitted most adjacent to the clock signal among a plurality of bits of a digital video signal. a display panel including a plurality of pixels formed in an area where a gate line and a data line intersect;
A digital data signal including a clock signal and a digital video signal is transmitted according to a predetermined protocol, wherein at least one bit of the video signal among a plurality of bits of the digital video signal is copied between the clock signal and the digital video signal. a control unit for transmitting the digital data signal in which the image signal is arranged;
a gate driver transmitting a gate signal to the gate line; and
A data driver receiving the digital data signal from the control unit, extracting a plurality of digital video signals from the digital data signal, converting the digital video signal into an analog data signal, and outputting the digital video signal to the data line;
The duplicated video signal is disposed between the clock signal and a first digital video signal transmitted adjacent to the clock signal, so that the digital data signal is disposed in the order of the clock signal, the duplicated video signal, and the digital video signal. Device. According to claim 7,
The data driver includes a data signal receiving unit for receiving the digital data signal transmitted from the control unit through one wire; and
and a data signal supply unit extracting a plurality of digital image signals from the digital data signals received by the data signal receiver and converting them into analog data signals for output. According to claim 7
According to the preset protocol, the digital data signal is divided into three transmission sections and transmitted, the clock signal is transmitted in the first section, and the duplicate video signal and the digital video signal are transmitted in the second section. A display device in which a dummy signal is transmitted in three sections, and the third section is shorter than the first section. According to claim 7,
The copy image signal is a signal obtained by copying at least one bit transmitted most adjacent to the clock signal among a plurality of bits of the digital image signal. A data transmission method in which a clock signal and a digital image signal are transmitted by dividing a period in which a data signal is transmitted into a first period, a second period, and a third period,
Receiving a signal including a digital video signal from a host device;
generating a copy image signal by copying at least one bit of the digital image signal; and
The clock signal is transferred in the first period, the duplicate video signal and the digital video signal are transferred so that the duplicate video signal is adjacent to the clock signal in the second period, and a dummy signal is transferred in the third period. However, the step of transmitting the data signal so that the third interval is shorter than the first interval,
The copy video signal is arranged between the clock signal and a first digital video signal transmitted adjacent to the clock signal, so that the data signal is arranged in the order of the clock signal, the duplicate video signal, and the digital video signal. Way. According to claim 11,
The bit of the video signal to be copied by the copy video signal is at least one bit adjacent to the clock signal among a plurality of bits of the digital video signal.

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