KR20180003735A - Display device and method of driving the same - Google Patents

Abstract

The present invention relates to a display device and a method of driving the same. The number of boots of at least one color data among color data transferred between devices is set different from the number of bits of other color data. It is possible to increase data transfer efficiency and reduce a hardware resource.

Description

DISPLAY DEVICE AND METHOD OF DRIVING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for transmitting data with different color depths for each color and a driving method thereof.

Due to the development of process technology and driving circuit technology of display devices, the resolution of display devices has increased and products with UHD resolution are on the market. UHD (Ultra High Definition) has 3840 * 2160 = 8.3 million pixels. The number of pixels in the UHD is about four times larger than the number of pixels in the FHD (1920 * 1080) Therefore, the UHD can reproduce the input image more precisely than the FHD, thereby realizing a clear and smooth image quality. A pixel means a minimum unit dot constituting a computer display or a computer image. The number of pixels means PPI (Pixels Per Inch).

The resolution of HD is expressed as "K", such as 2K and 4K. Here, K stands for 'Kilo', or 1,000, as a digital cinema standard standard. For example, based on the number of horizontal pixels, 2K means 2,000 pixels, and 4K means 4,000 pixels. 2K of 2048 * 1080 resolution is almost similar to 1920 * 1080 of FHD resolution, but 2K is mainly used in broadcasting and movie field. 4K, which has a resolution of 4096 * 2160, is sometimes referred to as Ultra Definition (UDD) or Ultra High Definition (UHD) because it is four times the size of an FHD and is a very different quality than Quad Full High Definition (QFHD) or FHD.

In a pixel array of a display device having a UHD (3840 * 2160) resolution, the number of data lines is 3840 * 3 = 11,520, and the number of gate lines is 2160. 3840 * 3 to 3 is the case where one pixel contains 3 RGB subpixels. The source driver IC (Integrated Circuit) for driving the data lines requires approximately 16 ICs when the IC is selected as the IC having 720 channels. In the source drive IC, one channel is connected to one data line, which is connected to one subpixel for every row line of the pixel array.

In order to realize high picture quality, display devices are increasing in data transmission due to high resolution, color depth expansion, high speed driving, and the like. As the amount of data transfer increases, the clock frequency, data rate, and bandwidth increase between devices.

An exemplary interface scheme for data transmission between devices on a display device is a low-voltage differential signaling (LVDS) interface. However, the LVDS interface can not adequately cope with the increase in the amount of data transmission. In a 120Hz panel with a 10-bit color depth with FHD resolution, 48 pairs of 24 pairs are required when employing the LVDS interface. The LVDS interface also transmits the clock signal along with the input video data. Therefore, in the LVDS interface, as the amount of data increases, the clock frequency becomes higher, and EMI (electromagnetic interference) control is required.

According to the LVDS interface standard, a signal should be transmitted around a voltage of 1.2 V at the ground (GND). Due to the implementation of the LSI (Large Scale Integration) refinement process, the specification of the signal voltage required in the LVDS interface has led to a large limitation in LSI design. In this situation, interfaces such as DVI (Digital Video Interface), HDMI (High Definition Multimedia Interface) and DisplayPort have been proposed and put into practical use.

Because DVI and HDMI have skew adjustment function and HDMI has high-bandwidth digital content protection (HDCP) as contents protection function, there are many advantages in video signal transmission between devices. However, The internal video signal transmission has a disadvantage in that the function is excessive and the power consumption is large.

DisplayPort has been standardized by the Video Electronics Standards Association (VESA) to replace LVDS. DisplayPort is equipped with HDCP in consideration of transmission between devices as well as HDMI, so there is a problem that power consumption is increased, transmission power is fixed, loss occurs when signal is transmitted at low frequency, and the receiver needs to reproduce clock have.

The V-by-One interface was developed by THine Electronics. The V-by-one interface improves signal transmission quality compared to existing LVDS interfaces due to the introduction of the equalizer function and realizes high-speed data transmission of 3.75Gbps per 1Pair. The V-by-one interface solves the skew adjustment problem resulting from the clock transmission of the LVDS interface due to the application of Clock Data Recovery (CDR). And the V-by-one interface can reduce EMI noise due to clock transmission because there is no clock transmission that was necessary in LVDS. This V-by-one interface is becoming a promising alternative to the LVDS interface because it can increase the amount of data transfer and effectively cope with high-speed driving.

The prior art sets the bit number of the red, green, and blue data the same, and transmits data to the same bit in each color among the devices even if the inteface is used. As a result, in the related art, the amount of data transfer is increased in a display device requiring high resolution and high-speed driving, resulting in low data transmission efficiency and high hardware resources.

An object of the present invention is to provide a display device and a driving method thereof that can increase data transmission efficiency and reduce hardware resources by setting the number of bits of data for each color differently in consideration of human perceived luminance.

A display apparatus of the present invention includes a timing controller for receiving input image data including pixel data from a host system, and a data driver for converting the pixel data received from the timing controller into a data voltage. The pixel data transmitted between the timing control unit and the pixel data includes at least first color data, second color data and third color data. The boot number of at least one of the first through third color data is set different from the number of bits of the other color data.

The color data having the lowest perceived luminance has the highest number of gradations and the lowest luminance contribution at a low gradation of 10 nit or less as compared with other color data.

When the first color data is red data, the second color data is green data, and the third color data is blue data, the color data having the lowest perceived brightness is the third color data.

The number of bits of the second color data is larger than that of the other colors.

The number of bits of the first color data is the same as the second color data or the third color data.

The pixel data further includes white data. The number of bits of the white color data is equal to or more than the color data having the largest number of bits among the first to third color data.

A dummy bit is added to the LSB of the color data in which the number of bits is relatively small among the color data.

The timing controller and the data driver are integrated into one IC chip.

The host system transmits the pixel data to the transmission timing controller through any one of an LVDS and a V-by-One interface. The timing controller transmits the pixel data to the data driver through any one of EPI and mini-LVDS.

The driving method of the display device sets the number of bits of the color data having the lowest known brightness in the pixel data transmitted between the devices to be lower than other color data.

The present invention can improve the number of wirings, transmission rate, bandwidth, and number of wirings for image processing in a device by transmitting different image data between devices by changing the color depth of each color.

FIG. 1 is a graph showing luminance per color for obtaining a white light luminance of 500 nit.
2 is a diagram illustrating an example in which the number of bits per color is set differently on the signal transmission path between the devices of the present invention.
3 is a block diagram schematically showing a display device according to an embodiment of the present invention.
4 is a block diagram schematically illustrating an image processor.
FIG. 5 is a view showing a color image reproduced when the color depth of blue is reduced in consideration of the same color depth and human perceived luminance.
FIG. 6 is a diagram showing a data transmission format when 10 bits of RGB are transmitted in the EPI interface.
FIG. 7 shows an example in which a dummy bit is added to match the data transmission format when the number of bits per color is changed.
8 is a diagram showing an example of a circuit configuration of the source drive IC and data having a different number of bits per color.
9 is a diagram showing a method of pixel data in which the number of bits per color is different in the DAC of the source drive IC to which the single gamma compensation circuit is applied.
FIGS. 10A and 10B are diagrams showing a method of pixel data in which the number of bits per color is different in the DAC of the source drive IC to which the double gamma compensation circuit is applied.
11A to 11C are diagrams showing a method of pixel data in which the number of bits per color is different in the DAC of the source drive IC to which the independent gamma compensation circuit for each color is applied.
12 is a diagram illustrating a data transmission rate calculated based on an EPI interface in order to show the effect of the present invention.
13 is a diagram illustrating a wiring connection for an EPI interface between a timing control unit and a source drive IC in a display device according to an embodiment of the present invention.
14 and 15 are diagrams showing signal formats of the EPI interface protocol.
FIG. 16 is a diagram showing an improvement effect in data transmission when the color depth for each color is different in the present invention, compared with the conventional technology in which color depths are the same in each color.
17 is a diagram schematically showing a configuration of a V-by-one interface circuit.
18 is a diagram showing the number of lanes according to the video driving format in the V-by-one interface.
FIG. 19 is a diagram showing a data rate and a data coding method in a V-by-one interface when the number of bits of each color is differentiated in various examples.
20 shows the effect of reducing the number of lanes required for data transmission to 14 lanes in the case of UHD 120 Hz when transmitting pixel data with W / R / G / B = 10/8/9/8 bits on a V-by- Fig.
FIG. 21 is a diagram showing an example of using 5 bytes 16lane for W = 10 bits, G = 9 bits, R = 8 bits, and B = 8 bits in V-by-One interface communication.

The display device of the present invention is based on the Weber-Fechner Fraction theory that the JND (Just Noticeable Difference) that distinguishes the brightness difference according to the intensity of the stimulus (brightness) among the characteristics recognized by the human eye is different, ). Color depth refers to color depth, color depth, or bit depth. Color Depth is defined as the number of bits of data written to a pixel. The unit of color depth is bits per pixel (bpp). The higher the color depth, the richer the color within a pixel. In general, when n (n is a positive integer) bits are used, 2 ⁿ colors can be represented.

The present invention reduces the number of bits of color that a human can not distinguish brightness difference to reduce the number of colors, the number of wirings for signal transmission between devices without degrading the perceived quality of a user, the data transmission rate, the data transmission bandwidth, And the like can be significantly reduced.

The line, pair, and lane described in the following description of data communication are defined as follows. A line is a physical transmission path in which signals such as data and clock are transmitted in series. A pair includes two lines in which the same signal is transmitted in opposite polarity. A lane is a channel through which a signal is transmitted through a pair of lines. Pairs and lanes can be used in the same sense.

The display device of the present invention can be implemented as a flat panel display device such as a liquid crystal display (LCD), an organic light emitting display (OLED) display device, and the like. In the following embodiments, an OLED display device is described as an example of a flat panel display device, but the present invention is not limited thereto.

A compensation method for compensating a change in driving characteristics of the pixels may be applied to improve the image quality and lifetime of the OLED display device. The compensation method is divided into an internal compensation method and an external compensation method. The internal compensation method automatically compensates the threshold voltage deviation between the driving TFTs within the pixel circuit. In order to perform internal compensation, the current flowing in the OLED must be determined regardless of the threshold voltage of the driving TFT, so that the configuration of the pixel circuit becomes complicated. The internal compensation method is difficult to compensate for the mobility deviation between the driving TFTs. The external compensation method senses the electrical characteristics (threshold voltage, mobility, etc.) of the driving TFTs and modulates the pixel data of the input image in the compensation circuit outside the display panel based on the sensing result, Thereby compensating for the characteristic change.

The external compensation method senses the voltage or current of the pixel through the sensing signal line connected to the pixels in the display panel and outputs the sensing result to an analog-to-digital converter (ADC) And transmits the data to the timing control unit (TCON). The timing controller TCON modulates the pixel data of the input image based on the sensing result of the pixel using a preset external compensation algorithm to compensate the change of the driving characteristic of the pixel.

The method of sensing and compensating the driving characteristics of a pixel for external compensation is disclosed in Korean Patent Application 10-2013-0134256 (Nov. 11, 2013), Korean Patent Application 10-2013-0141334 (Nov. 20, 2013) 10-2013-0149395 (Dec. 03, 2013), Korean Patent Application 10-2013-0166678 (December 30, 2013), Korean Patent Application 10-2014-0115972 (April 29, 2014), Korea Patent It is proposed in the application 10-2015-0101228 (May 20, 2015), Korean patent application 10-2015-0093654 (June 30, 2015), and Korean patent application 10-2015-0149284 (October 27, 2015) And a method of sensing the voltage of a driver TFT that is driven by a driving TFT, 0168424 (May 201,2010), and the like, and a method of sensing a current of a driving TFT, 05.), Korean Patent Application 10-2014-0175191 (Dec. 08, 2014). ), Korean patent application 10-2015-0115423 (Aug. 17, 2015), Korean patent application 10-2015-0188928 (December 29, 2015), Korean patent application 10-2015-0117226 ), Which is incorporated herein by reference.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

As can be seen from Fig. 1, the luminance of each color for obtaining the white light luminance of 500 nit in the display device is different. 2.2 The luminance contributions of red (R), green (G), and blue (B) in the gamma curve are R: G: B = 0.25: 0.65: 0.10.

On the other hand, in the case of RGB 10-bit color depth, the luminance discrimination depth is high in the order of Blue> Red> Green at a low luminance of less than 10 nit in a 500 nit white luminance condition. In other words, the lower the luminance of 10 nit or less, the larger the number of gradations of blue luminance than the other colors (R, G) and the smallest luminance difference (1 Gray DELTA L) between the gradations. In the case of blue, the number of gradations of 1 nit or less is about 170 or more, and the luminance difference (1 Gray ΔL) between gradations is 0.0058 nit. This low luminance difference (1 Gray DELTA L) is so low that it is difficult for the human eye to resolve the luminance difference according to the gradation, so it is difficult for the user to distinguish the gradation. Therefore, the blue color is unnecessarily large in view of whether the color depth at the low luminance is human luminance.

Hereinafter, the term " color with low luminance perception " means data having the largest number of gradations and the lowest luminance contribution at a low gradation of 10 nit or less as compared with other color data constituting one pixel data.

In the present invention, the color depth of a color having a low perceived luminance is discriminated and a bit number of data per color is set differently in consideration of a cognitive characteristic that a human eye recognizes a luminance difference. For example, when the pixel data includes RGB data, the color depth of the pixel data transmitted between the devices 21 and 22 is calculated as Blue < Red ≤ Green. In the example of FIG. 2, N + a, N + b, N + c are the number of bits per color. N is a positive integer of 2 or more. a, b, and c are constant values previously set to different values in order to give a difference in the number of bits per color in consideration of human perceived luminance. The first device 21 may be a signal transmitter Tx and the second device 22 may be a signal receiver Rx. In the case of a display device, the first device 21 may be a timing controller (TCON) and the second device 22 may be a source drive IC (SIC). Or the first device 21 may be a host system (SYSTEM), and the second device 22 may be a timing control unit (TCON).

In the example of FIG. 2, the number of bits per color can be differentiated by various methods as follows.

(One) a = b? c

(2) a ≠ b = c

(3) a ≠ b ≠ c

(One) Is an example in which the number of bits of red and green is the same, and the number of bits of blue is smaller than the number of bits.

(2) Is an example where the number of bits of green and blue is the same, and the number of bits is smaller than the number of bits of red.

(3) Is an example where the number of bits of each of RGB is green> red> blue.

This differentiation of color depth by color reduces the number of bits of transmitted data, thereby reducing the signal transmission load between the devices, thereby reducing hardware resources and improving the performance of the display device. By reducing the number of data bits at the time of signal transmission, it is possible to reduce the number of wirings, the data transfer rate, and the bandwidth on the signal transmission path between the devices 21 and 22 and reduce the number of wirings in each of the devices 21 and 22 have.

3 is a block diagram schematically showing a display device according to an embodiment of the present invention.

3, the display device of the present invention includes a display panel 10, a timing controller 11, a data driver 12, and a gate driver 13. The data driver 12 may include one or more source drive ICs (SIC). The timing controller 11 and the data driver 12 may be integrated in one IC chip in a mobile device.

The timing control unit 11 receives data of an input image from the host system 20. [ The host system 20 and the timing controller 11 can transmit signals including input image data through an interface such as LVDS and V-by-One. The timing controller 11 and the data driver 12 may transmit signals through an interface such as an EPI (Embedded Panel Interface) interface or mini-LVDS proposed by the present applicant.

At least one of the host system 20 and the timing controller 11 can further transmit white W data together with RGB data. The number of bits of the W data may be set to be equal to or more than the data having the largest number of bits among RGB data.

The applicant of the present application has proposed an EPI interface protocol for minimizing the number of wires between the timing controller 11 and the data driver 12 and stabilizing signal transmission in Korean patent application 10-2008-0127458 (2008-12-15), US application 12 Korean Patent Application No. 10-2008-0127456 (2008-12-15), US Application No. 12 / 461,652 (2009-08-19), Korean Patent Application No. 10-2008-0132466 (2008- 12-23), and US Application No. 12 / 537,341 (2009-08-07).

The EPI interface protocol satisfies the following (1) to (3) interface specifications.

(1) A signal is transmitted through a serial communication by connecting the transmitting end of the timing control unit and the receiving end of the source driving ICs of the data driving unit via a data wire pair in a point-to-point manner.

(2) No separate clock wiring pair is connected between the timing control section and the source drive ICs. The timing control unit transmits the control data and the pixel data of the input image to the source drive ICs together with the clock signal through the data wiring pair.

(3) A clock recovery circuit for clock and data recovery (CDR) is built in each of the source drive ICs. The timing controller transmits a clock training pattern or preamble signal to the source drive ICs so that the output phase and frequency of the clock recovery circuit can be locked. The clock recovery circuit built in the source drive ICs generates an internal clock when a clock training pattern signal and a clock signal input through the data wiring pair are input.

In the EPI interface protocol, the timing controller transmits a preamble signal in the phase-I to the source drive ICs before transmitting the control data and the pixel data of the input image, as shown in FIG. The clock recovery circuit of the source drive IC performs a clock training (CT) operation according to the preamble signal to recover the received clock and stably fix the phase and frequency of the recovered internal clock. After the phase and frequency of the internal clock are stably fixed, a data link is established between the source driver IC and the timing controller for transmitting the data of the input image. The timing control section transfers the control data to the source drive ICs in phase-II after receiving the lock signal LOCK received from the last source drive IC, and then transfers the pixel data of the input image to the source drive ICs in phase- It begins to transmit.

When any one of the source drive ICs unlocks the output phase and frequency of the built-in clock recovery circuit, the source drive IC outputs a lock signal, which is transmitted to the timing control unit, at a low logic level, . The final source drive IC transfers the lock signal inverted to the low logic level to the timing controller. The timing control unit retransmits the preamble signal to the source drive ICs so that the clock training of the source drive ICs is resumed when the lock signal is inverted to the low logic level.

In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 are crossed, and the pixels P are arranged in a matrix form for each of the intersection areas. The pixels may comprise red (R), green (G), and blue (B) subpixels for color implementation. The pixels may further include white (W, W) subpixels in addition to RGB subpixels. The pixels may further include one or more of blue, cyan, magenta, yellow, and yellow subpixels. To implement the external compensation method, the display panel 10 may further include a sensing circuit and a sensing circuit connected between the pixels and the ADC.

A touch screen using an in-cell touch sensor may be implemented on the display panel 10. The in-cell touch sensor is embedded in the pixel array of the display panel 10. The insole touch sensor can be realized as a capacitive type touch sensor that senses a touch based on a change in capacitance before and after touch. The touch sensors may be disposed on the display panel 10 in an on-cell type or an add-on type.

Each of the subpixels receives a high potential power supply (EVDD) and a low potential power supply (EVSS) from a power supply not shown. The pixel P may include an OLED, a driving TFT (Thin Film Transistor), a plurality of switch TFTs, and a storage capacitor (Cst). The TFTs constituting the pixel P may be implemented as a p-type or an n-type MOSFET. The semiconductor layer of the TFTs may comprise amorphous silicon, polysilicon, or an oxide.

The gate driver 13 may be implemented as an IC, or may be formed directly on the display panel 10 by a gate-driver In Panel (GIP) process. The gate driver 13 sequentially supplies gate pulses synchronized with the data voltage of the input image to the gate lines 15 during the image display period under the control of the timing controller 11, And supplies the gate pulse synchronized with the gate pulse.

The data driver 12 converts the pixel data of the input image received from the timing controller 11 during the image display period into data voltages and outputs the data voltages to the data lines 14. [ Is applied to the pixel electrode of each of the subpixels through the switch TFT which is turned on in accordance with the gate pulse supplied to the data lines 14. [ The data driver 12 receives the sensing voltage obtained from each of the sub pixels by the sensing circuit through the sensing lines. The data driver 12 converts the sensing voltage into digital data using the ADC connected to the sensing line and transmits the digital data to the timing controller 11. [

The timing controller 11 controls the operation of the source drive IC 12, the gate driver 13, the external compensation sensing circuit, and the touch sensor driver based on the timing information received from the host system 20 based on the signals received from the host system 20. [ The timing controller 11 receives the pixel data of the input image in order to compensate for a change in driving characteristics of the pixel based on the sensing data for external compensation received from the data driver 12. [ And is modulated by a preset external compensation algorithm. The sensing data is digital data output through the ADC and is data that is separate from the pixel data of the input image, as a driving characteristic sensing result of the pixel.

The host system 20 may be any one of a television system, a set-top box, a navigation system, a computer, a DVD player, a Blu-ray player, a home theater system, and a phone system. The host system includes a system on chip (SoC) with a built-in scaler to convert the data of the input image into a format suitable for display on the display panel 10. [ The host system transmits the timing signals synchronized with the data of the input image to the timing controller 11. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a dot clock, and the like. The host system 20 executes the application program associated with the coordinate information of the touch input received from the touch sensor driver.

The host system 20 or the timing controller 11 can process serial or parallel data when processing data using an image processing algorithm. In this case, the present invention can improve the number of wirings and the data transmission efficiency in the host system 20 or the timing controller 11 by applying the difference in the number of bits per color in consideration of human perceived brightness.

The example of FIG. 4 schematically shows an image processor that processes image processing algorithms. The image processor may be disposed in the host system 20 or the timing controller 11. [

4, the image processor includes a degamma correction unit 31, an algorithm execution unit 32, a gamma correction unit 33, and the like.

The degamma correction unit 31 performs a de-gamma process on the pixel data of the input image so that the change amount of the digital value and the change amount of the brightness are equal to each other. The pixel data input to the degamma correction unit 31 is composed of red data (hereinafter referred to as "R data"), green data (hereinafter referred to as "G data") and blue data ). Pixel data having 10 bits each of RGB can be input to the degamma correction unit 31. [ The degamma correction unit 31 may extend the bit number by color in consideration of the perceived brightness at the time of the degamma processing. For example, the degamma correction unit 31 can reduce the number of bits of the B data in comparison with the R data and the G data. 4, 12-bit R data, 14-bit G data, and 11-bit B data are output to the degamma correction unit 31.

The algorithm executing unit 32 executes an operation required for various algorithms for image quality improvement such as an external compensation algorithm and a color temperature compensation algorithm. The number of bits of B data in the RGB data output from the algorithm executing section 32 is the smallest. The gamma correction unit 33 modulates the RGB data values received from the algorithm executing unit 32 along a 2.2 gamma correction curve. Each of the RGB data output from the gamma correction unit 33 can be output in 10 bits. The bit number of the B data can be reduced in comparison with the other colors in consideration of the perceived brightness in the output data of the gamma correction unit 33. [ Data of a color having a relatively small number of bits can be transmitted to another device with the same bit number as data of another color by adding a dummy bit.

Previously, the same number of bits of RGB were transmitted within the image processor. In this case, 14 * 3 signal transmission wirings are required for 14-bit RGB, and the number of required wirings increases in proportion to the number of pixel data to be simultaneously processed.

The present invention can reduce the number of signal transmission lines in the image processor by using the differentiated bit number for each color based on the characteristic of recognizing the luminance stimulus as shown in FIG. As a result, the present invention can reduce the hardware resources required for high-resolution, high-speed driving. For example, assuming 16-pair processing for 4K (UHD) 120Hz Display (V-by-one Interface), 42 * 16 = 672 wires between the circuit blocks in the image processor and as many registers need. In this case, as shown in FIG. 4, by applying a system in which the number of bits per color is different, 80 wires and the number of registers can be reduced.

For an 8K 120Hz display (V-by-one interface), assuming 64-pair processing, 42 * 64 = 2688 wires and registers between circuit blocks in the image processor are required. In this case, as shown in FIG. 4, by applying a system in which the number of bits per color is different, 320 lines and registers can be reduced.

FIG. 5 is a view showing a color image reproduced when the color depth of blue is reduced in consideration of the same color depth and human perceived luminance.

Referring to FIG. 5, the left color image shows the color depth when each of RGB is 8 bits. The right color image shows the color depth when R data and G data are 8 bits and B data is 7 bits. In the case of B data, since the perceived luminance is low, one bit number is reduced, but the user does not recognize the blue color depth difference. Accordingly, the present invention can reduce the number of bits of color with low luminance contribution and low luminance difference between gradations, thereby enhancing the signal transmission efficiency without degrading the perceived image quality.

FIG. 6 is a diagram showing a data transmission format when 10 bits of RGB are transmitted in the EPI interface. FIG. 7 shows an example in which a dummy bit is added to match the data transmission format when the number of bits per color is changed.

In the EPI interface, the pixel data of the input image is transmitted in a data packet as shown in FIG. The data packet contains RGB data arranged between clock bits (CLKs). If the RGB data are each equal to 10 bits, the RGB data is allocated to Bit 2 - 31 as shown in FIG. 6, and is transmitted from the LSB (Least Significant Bit) in each of the RGB data.

The present invention can reduce the number of bits in each of the R data and the B data in consideration of the perceived brightness. In the example of FIG. 7, the number of bits of R data is 9 bits, and the number of bits of B data is 8 bits. The number of bits of G data is 10 bits. In order to transmit different data by color depth by applying the present EPI interface circuit as it is, the present invention adds a dummy bit to a reduced number of colors, and transmits the data by expanding the bit number to a bit number not reduced. In this case, the dummy bit is assigned to the LSB.

A color having a low luminance can not be decomposed by a person in a gradation at a low gradation. Accordingly, the dummy bit can be set to 0 or 1 or randomly because the user can not know the gradation change of the luminance according to the dummy bit value added as the LSB to the data of the color having the low perceived luminance.

If the dummy bit added to the data of the color having low luminance is generated with the same value as the LSB of the data of the color, the signal transmission bandwidth (frequency) can be reduced by reducing the number of transitions in signal transmission as shown in FIG. . In the example of FIG. 7, the R data is 9 bits from R0 to R8, and dummy bit 1 bit is added to R0, which is the LSB, to the same value as R0. B data is 8 bits from B0 to B7 and dummy bit2 bit is added to B0 before LSB.

8 is a diagram showing an example of a circuit configuration of the source drive IC and data having a different number of bits per color.

8, the source driver IC SIC of the present invention includes an input register, a data latch, a level shifter, a digital-to-analog converter (DAC) , An output buffer (Out Buffer), and the like. The CDR circuit in the source drive IC (SIC) is omitted.

The source drive IC can receive pixel data, including the data with different bits per color (Color 1, Color 2, Color 3) via the EPI interface or the mini LVDS interface. In Color 1, the valid data bits with image information are b1 ~ b9, and the dummy bit without image information is b0. In Color 2, the valid data bits with video information are b0 to b9, and there are no dummy bits. In Color 3, valid data bits with image information are b2 ~ b9, and dummy bits without image information are b0, b1. The dummy bit is the LSB bit.

Color 1 may be R data, Color 2 may be G data, and Color 3 may be B data.

The input register temporarily stores the data received serially. The data latch sequentially latches the bits of the data received from the input register and simultaneously outputs the data to the level shifter in response to a source output enable signal SOE (not shown). The level shifter converts the voltage of the data into a voltage level that can be processed by the DAC. The DAC converts the digital data into an analog data voltage by selecting the gamma compensation voltage according to the digital value of the input data. This data voltage is output to the data lines 14 of the display panel 10 through the output buffer.

The DAC is implemented based on the highest number of bits in each color. The DAC may be implemented by a single gamma compensation circuit as shown in FIG. 9 or a double gamma compensation circuit as shown in FIGS. 10A and 10B. And the DAC can be implemented with a three-color independent gamma compensation circuit as shown in Figs. 11A to 11C.

9 is a diagram showing a method of pixel data in which the number of bits per color is different in the DAC of the source drive IC (SIC) to which the single gamma compensation circuit is applied.

Referring to FIG. 9, data of each color (Color 1, Color 2, Color 3) are processed in common in one DAC. In each color, the digital data is converted to the gamma compensation voltage by the DAC without discriminating the gamma compensation voltage.

The DAC generates a gamma compensation voltage between Vdd and Vss by using a voltage divider circuit (RS) using a resistor string. The DAC selects the data voltage corresponding to the digital data value by selecting the gamma compensation voltage using the switch elements S0 to S9 switched according to the bits (b0 to b9, / b0 to / b9) of the data. / b0 ~ / b9 is the inverted bit. The dummy bit has a value of 0 or 1, and the voltage may vary slightly depending on the value of the dummy bit. Since the data to which the dummy bit is added is the data of the color having the low luminance of recognition, the voltage difference according to the dummy bit value may occur, but the user can not distinguish the luminance difference between the lines caused by the difference of the voltage.

FIGS. 10A and 10B are diagrams showing a method of pixel data in which the number of bits per color is different in the DAC of the source drive IC to which the double gamma compensation circuit is applied.

Referring to FIGS. 10A and 10B, the DAC of the source drive IC includes a first DAC (DAC1) for processing data of high color depth (Color 1, Color 2) and a first DAC And a second DAC (DAC2) for processing the data of the second DAC.

The first DAC (DAC1) generates a gamma compensation voltage between Vdd and Vss using a voltage divider circuit (RS). The first DAC (DAC1) is implemented based on the number of bits of the color having the largest color depth. A gamma compensation voltage is selected using switch elements S0 to S9 switched according to 10 bits (b0 to b9, / b0 to / b9) of Color 1 or Color 2 data to select a data voltage corresponding to the digital data value do.

The second DAC (DAC2) is implemented based on the color depth of Color 3. The second DAC (DAC2) generates a gamma compensation voltage between Vdd and Vss using a voltage divider circuit (RS). The second DAC 2 selects the gamma compensation voltage using the switch elements S0 to S8 switched according to the 8 bits (b0 to b7, / b0 to / b7) of the Color 3 data, Select the data voltage.

The value of the dummy bit added to the data of Color 1 and Color 3 is 0 or 1. The data voltage of Color 1 can be finely varied according to the value of the dummy bit. However, as described above, when the user perceives the luminance difference between dots due to the dummy bit at a low gradation of the color with low recognition luminance, I can not.

11A to 11C are diagrams showing a method of pixel data in which the number of bits per color is different in the DAC of the source drive IC to which the independent gamma compensation circuit for each color is applied.

11A to 11C, the DAC of the source drive IC includes a first DAC (DAC1) for processing data of a first color (Color 1), a second DAC (DAC1) for processing data of a second color And a second DAC (DAC2) for processing data of a third color (Color 3).

The first DAC (DAC1) is implemented on the color depth basis of Color 1. The first DAC (DAC1) generates a gamma compensation voltage between Vdd and Vss using a voltage divider circuit (RS). The first DAC DAC1 selects the gamma compensation voltage using the switch elements S0 through S8 switched according to 9 bits (b0 through b8, / b0 through / b8) of the Color 1 data, Select the data voltage.

The second DAC (DAC2) is implemented based on the color depth of the Color 2 having the largest color depth. The second DAC (DAC2) generates a gamma compensation voltage between Vdd and Vss using a voltage divider circuit (RS). The second DAC (DAC2) selects the gamma compensation voltage using the switch elements (S0 to S9) switched according to 10 bits (b0 to b9, / b0 to / b9) of the Color 2 data, Select the data voltage.

The third DAC (DAC3) is implemented based on the color depth of the Color 3 having the smallest color depth. The third DAC (DAC3) generates a gamma compensation voltage between Vdd and Vss using a voltage divider circuit (RS). The third DAC (DAC3) selects the gamma compensation voltage using the switch elements (S0 to S7) switched according to the 8 bits (b0 to b7, / b0 to / b7) of the Color 3 data, Select the data voltage.

In the present invention, the color depth for each color is set differently so that the color depth of the color having higher brightness is higher than that of the related art in which the color depth is the same for all colors as shown in FIG. 12 during data transmission between devices or devices, The data rate can be significantly improved without increasing the clock frequency. Figure 12 is a data rate calculated on an EPI interface basis. The data transmission rate can be calculated as follows.

13 is a diagram showing a wiring connection for an EPI interface between the timing controller and the source drive ICs (SIC1 to SIC12) in the display device according to the embodiment of the present invention. 13 is an example in which the number of source drive ICs is 12, but the present invention is not limited thereto. For example, the number of source drive ICs may be one or more. 14 and 15 are diagrams showing signal formats of the EPI interface protocol.

13, the source drive ICs 12 receive data from the timing controller 11 via the EPI interface and transmit the ADC data to the timing controller 11 via a separate pair of ADC data lines SL do.

The source drive ICs SIC1-SIC12 may include a portion of the sensing circuit, e.g., an ADC, an integrator, and the like. The source drive ICs 12 may update the sensing timing signal in response to the command code of the control data packet received from the timing controller 11. [

The timing control section 11 and the source drive ICs 12 are connected through an EPI data wire pair DL and also connected via an ADC data wire pair SL for external compensation. The ADC data is digital data obtained as a result of driving characteristic sensing of the pixel. The EPI data line pair DL is connected in a point-to-point manner by connecting the timing control unit 11 and the source drive ICs 12 in a 1: 1 manner.

The timing control unit 11 transmits a clock training pattern or preamble CT through an EPI data wire pair DL according to an EPI interface protocol through an EPI data wire pair DL, (CTR), and a video data packet (DATA) to the source drive ICs 12 in series.

13, PCB1 and PCB2 are source PCBs (Printed Circuit Boards) on which the source driver ICs SIC1 to SIC12 are mounted.

In Fig. 14, " VB " is a vertical blank period and " HB " is a horizontal blank period. The vertical blank period VB is a blank period until the (N + 1) th frame data is input between the Nth (N is a positive integer) frame period and the (N + 1) The horizontal blank period HB is a blank period between the Nth (N is positive integer) line data of the display panel 10 and the (N + 1) th line data. The N-th line data is data to be written to the pixels arranged in the N-th horizontal line of the display panel 10. The (N + 1) -th line data is data to be written to the pixels arranged in the (N + 1) -th horizontal line of the display panel 10. [

The data received via the EPI data wire pair DL is transmitted to the source drive ICs 12 along with the clock bits. The length of one data packet may be 34 UI including a clock bit (CLK) and a packet dummy bit (DUM) when 10 bits of RGB are respectively as shown in FIG. 15, but the present invention is not limited thereto. 1 UI is 1 bit transmission time. 34 The UI contains 4 bits of CLK and DUM bits and 30 bits of RGB data.

The control data packet transmitted through the EPI data line pair (DL) includes source control data for controlling the operation timing of the source drive IC, an option signal, and a sensing timing signal for controlling the operation of the sensing circuit. The option signal includes a gate start pulse (GSP) for controlling the shift register start timing of the gate driver, a skew option signal of the source drive IC, various optional signals of the gate driver and the source driver IC, A command code that defines an update period, and the like. The gate timing signal for controlling the driving timing of the gate driving unit may be transmitted to the gate driving unit through another wiring.

The ADC data wiring pair SL can connect the timing control section 11 to the plurality of source drive ICs 12 in parallel. For example, the source drive ICs 12 connected to the first PCB PCB1 are connected to the timing controller 11 via a first pair of ADC data lines SL. The source drive ICs 12 connected to the second PCB PCB2 are connected to the timing controller 11 via a second pair of ADC data lines SL. The source drive ICs 12 transfer the ADC output data to the timing controller 11 via the ADC data wiring pair SL. The ADC output data is the result of sensing the driving characteristics of the pixels.

The timing controller 11 transmits the data of the input image of the host system 20 to the source drive ICs 12 so as to satisfy the EPI interface protocol. The timing control unit 11 encodes the sensing timing signal in the control data packet. The sensing timing signal may include a plurality of signals for individually controlling the plurality of elements. The timing controller 11 may encode the update time information of the sensing timing signal in some bits of the control data packet. The update time information reduces the update time of each of the sensing timing signals within a time period equal to or less than one horizontal period (1 HT) and defines the updater time. The update time of each of the sensing timing signals may be varied by the update time information.

FIG. 16 is a diagram showing an improvement effect in data transmission when the color depth for each color is different in the present invention, compared with the conventional technology in which color depths are the same in each color.

Referring to FIG. 16, when the number of bits of a color having a low perceived luminance is reduced, the number of bits of a color having a high perceived luminance is increased at the same data rate, thereby improving the perceived image quality. The data transfer rate of the present invention is higher than in the prior art when the number of bits of a color having a high luminance perception is the same and the number of bits of a color having a relatively low luminance is relatively different in the prior art and the present invention.

If the data packet length is determined by the number of bits for different colors without the dummy bit addition, the frequency of the data packet can be obtained by 3 clocks since the data packet length is reduced by the number of bits reduced.

17 is a diagram schematically showing a configuration of a V-by-one interface circuit. 18 is a diagram showing the number of lanes according to the video driving format in the V-by-one interface. The V-by-one interface can dramatically reduce the number of communication lines required for data transmission over the LVDS interface through high-speed parallel-to-serial conversion. Due to these advantages, it is used as a device interface standard for realizing resolution higher than UHD in a display device.

17 and 18, the V-by-one interface includes a transmitting terminal Tx and a receiving terminal Rx. This interface device exemplifies a V-by-one interface, but is not limited thereto.

In order to perform data communication via the V-by-one interface, an auxiliary signal transmission link in which auxiliary signals LOCKN and HTPDN are transmitted in addition to a main link in which data is transmitted between a transmitting terminal Tx and a receiving terminal Rx .

The receiving end Rx lowers the HTPDN signal to a low level and the transmitting end Tx responds to a low level HTPDN signal to generate a CDR training pattern signal To the receiving end Rx. The receiving end Rx has a built-in CDR circuit for restoring the clock. The CDR circuit of the receiving end Rx receives the CDR training pattern signal, locks the phase and frequency of the output, and lowers the LOCKN signal to a low level. When the LOCKN signal is lowered to a low level, the transmitting terminal Tx starts to transmit pixel data of the input image after transmitting an Align (ALN) training pattern signal to the receiving end Rx for a predetermined time.

The present invention differs color depths in the order of W> G> R> B as shown in FIG. 19 in order to increase the expression power of a color having a high luminance of a display device while maintaining an existing data rate (Bit Rate) in V- do. As a result, the present invention can increase the number of colors recognizable by the user and increase the brightness, thereby improving the image quality. The bit of the white (W) data is not necessarily limited to more than the bits of the other colors. For example, the number of bits of the W data can be set equal to that of the G data.

In the V-by-One interface communication, when the color depth is graded in the order of W> G> R> B, the number of data transmission lanes can be reduced without degrading the perceived quality of the user.

In the V-by-One interface communication, when transmitting 5 bytes (40 bits) data per lane at a speed of 3.7 Gbps per lane, the conventional technique transmits 40 bits per 10 bits per pixel. In this case, 16 lanes are required for UHD 120 Hz.

In contrast, the present invention transmits a total of 35 bits per pixel at W / R / G / B = 10/8/9/8 bits under the V-by-One interface communication condition. As a result, the present invention requires 14 lanes for the UHD 120 Hz, so that 2 lanes can be reduced compared to the conventional technology.

FIG. 21 is a diagram showing an example in which 5 bytes 16lane is used when W = 10 bits, G = 9 bits, and R = 8 bits B = 8 bits in V-by-One interface communication. Color-by-color-depth-method of WRGB data can be applied between devices or within devices.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing control part (TCON)
12: Data driving circuit (SIC) 20: Host system

Claims (10)

A display device comprising: a timing controller for receiving input image data including pixel data from a host system; and a data driver for converting pixel data received from the timing controller into a data voltage,
Wherein the pixel data transmitted between the timing control unit and the pixel data includes at least first color data, second color data, and third color data,
Wherein the number of bits of at least one of the first through third color data is different from the number of bits of the other color data. The method according to claim 1,
The number of bits of the color data having the lowest known brightness among the first to third color data is set to be lower than that of the other color data,
Wherein the color data having the lowest perceived luminance has the largest number of gradations and the lowest luminance contribution at a low gradation of less than 10 nit as compared with other color data. The method according to claim 1,
When the first color data is red data, the second color data is green data, and the third color data is blue data,
And the color data having the lowest perceived brightness is the third color data. The method of claim 3,
And the number of bits of the second color data is larger than that of the other colors. The method of claim 3,
And the number of bits of the first color data is the second color data or the third color data. The method according to claim 1,
Wherein the pixel data further comprises white data,
Wherein the number of bits of the white color data is equal to or larger than the color data having the largest number of bits among the first to third color data. 7. The method according to any one of claims 1 to 6,
And a dummy bit is added to LSB of color data having a relatively small number of bits among the color data. 7. The method according to any one of claims 1 to 6,
Wherein the timing controller and the data driver are integrated in one IC chip. 8. The method according to any one of claims 1 to 7,
The host system transmits the pixel data to the transmission timing controller through one of an LVDS and a V-by-One interface,
Wherein the timing controller transmits the pixel data to the data driver through any one of an EPI and a mini-LVDS. A timing controller for receiving pixel data including at least first color data, second color data, and third color data from the host system, and a timing controller for converting the pixel data received from the timing controller into a gamma compensation voltage, And a data driver for outputting the data to the data driver,
Wherein the number of bits of the color data having the lowest perceived brightness is set to be lower than that of the other color data among the first to third color data.

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