KR20230103559A - Timing Controller, Data Driver and Display Device including the same - Google Patents

Abstract

The present invention includes a data driving unit; a timing control unit including a transmission terminal control unit for controlling the data driver and sensing whether or not there is a change in voltage on a transmission line connected to the data driver; and a display panel displaying an image based on the data voltage output from the data driver, wherein the timing controller determines whether the data driver is in a normal operating state based on a voltage change on a transmission line connected to the data driver. A display device for judging may be provided.

Description

Timing controller, data driver and display device including the same {Timing Controller, Data Driver and Display Device including the same}

The present invention relates to a timing controller, a data driver, and a display device including the same.

As information technology develops, the market for display devices, which are communication media between users and information, is growing. Accordingly, the use of display devices such as a light emitting display device (LED), a quantum dot display device (QDD), and a liquid crystal display device (LCD) is increasing.

The display devices described above include a display panel including sub-pixels, a driving unit outputting a driving signal for driving the display panel, and a power supply unit generating power to be supplied to the display panel or the driving unit.

In the above display devices, when a driving signal, for example, a scan signal and a data signal, is supplied to subpixels formed on a display panel, the selected subpixel transmits light or emits light directly, thereby displaying an image.

The present invention simplifies the configuration (circuit parts) of the device by eliminating the lock feedback line for exchanging lock signals between the timing control unit and the data driver, and switches directly when determining whether the data driver is normally locked. It is to reduce line load through control or indirect control method using protocol.

The present invention includes a data driving unit; a timing control unit including a transmission terminal control unit for controlling the data driver and sensing whether or not there is a change in voltage on a transmission line connected to the data driver; and a display panel displaying an image based on the data voltage output from the data driver, wherein the timing controller determines whether the data driver is in a normal operating state based on a voltage change on a transmission line connected to the data driver. A display device for judging may be provided.

The timing controller may determine that the data driver is normally operable when the voltage on the transmission line increases compared to the previous one.

The data driver may include a receiving end controller having at least one resistor and a switch to change the voltage on the transmission line.

The receiving end controller includes a first resistor having one end connected to a first transmission line connected to the timing control unit, and a second resistor having one end connected to the other end of the first resistor and the other end connected to a second transmission line connected to the timing control unit. A switch may include a resistor, a first electrode connected to a connection point between the first resistor and the second resistor, and a second electrode connected to the other end of the second resistor and the second transmission line.

The switch is controlled by the data driver or a signal transmitted from the timing controller, and the voltage on the transmission line may change according to the turn-on or turn-off of the switch.

The transmitting end controller may be electrically connected to a transmission line connected to the data driver only when sensing whether or not the voltage has changed.

The transmitting end controller includes a second switch having a first electrode connected to a first transmission line connected to the data driver, a third switch having a first electrode connected to a second transmission line connected to the data driver, and the second switch. A first terminal is connected to the second electrode of the buffer and a second terminal is connected to the second electrode of the third switch.

The timing controller may determine whether the plurality of data drivers are in a normal operating state based on voltage changes on transmission lines connected to the plurality of data drivers.

In another aspect, the present invention provides a reception buffer unit for receiving a data packet applied through a transmission line; and a receiving end controller having at least one resistor and a switch to change the voltage on the transmission line, wherein the switch is turned on or off in response to a signal applied from the outside or inside to change the voltage on the transmission line. A data driving unit may be provided.

The receiving end control unit includes a first resistor having one end connected to a first transmission line, a second resistor having one end connected to the other end of the first resistor and the other end connected to a second transmission line coupled to the timing control unit, and A switch may include a first electrode connected to a connection point between a resistor and the second resistor and a second electrode connected to the other end of the second resistor and the second transmission line.

In another aspect, the present invention provides a transmit buffer unit for transmitting data packets through a transmission line; and a transmission terminal control unit configured to sense a voltage change on the transmission line, and when the voltage change on the transmission line is sensed, the reception terminal determines that the normal operation is possible and controls the transmission buffer unit so that the data signal is included in the data packet and transmitted. can do.

The transmitting end controller includes a second switch having a first electrode connected to a first transmission line connected to the receiving end, a third switch having a first electrode connected to a second transmission line connected to the receiving end, and a second switch of the second switch. A buffer having a first terminal connected to an electrode and a second terminal connected to the second electrode of the third switch may be included.

The present invention has an effect of simplifying the configuration (circuit parts) of the device by eliminating a lock feedback line for exchanging a lock signal between the timing controller and the data driver. In addition, the present invention has an effect of reducing line load through direct control of a switch or indirect control using a protocol when determining whether a data driver is normally locked based on detection of a voltage change on a transmission line instead of a feedback line.

FIG. 1 is a schematic block diagram of a light emitting display device, and FIG. 2 is a schematic configuration diagram of a subpixel shown in FIG. 1 .
3 and 4 are diagrams for explaining the configuration of a gate-in-panel scan driver, and FIG. 5 is a diagram illustrating an arrangement example of a gate-in-panel scan driver.
6 is a diagram showing a light emitting display device according to the first embodiment of the present invention, and FIG. 7 is a diagram showing some configurations of a timing control unit and a data driver according to the first embodiment of the present invention.
8 is a waveform diagram for explaining a part related to a communication method established between a timing controller and a data driver according to a first embodiment of the present invention, and FIGS. 9 and 10 are waveforms related to the device shown in FIG. 11 is a diagram illustrating a change in voltage of a control unit of the receiving end according to the operating state of FIGS. 9 and 10 .
12 is a diagram showing some configurations of a timing controller and a data driver according to a second embodiment of the present invention, and FIG. 13 is related to a communication method established between a timing controller and a data driver according to a second embodiment of the present invention. 14 and 15 are diagrams for explaining the operating state of the device related to the waveform shown in FIG. 13, and FIG. 16 is a receiving end control unit according to the operating state of FIGS. 14 and 15. It is a diagram showing voltage change.
17 is a waveform diagram for explaining a part related to a communication method established between a timing controller and a data driver according to a third embodiment of the present invention, and FIG. 18 is a waveform diagram for explaining a part of a section of FIG. 17 in more detail. 19 is a flowchart for explaining a driving method according to a third embodiment of the present invention.
20 is a waveform diagram for explaining a control method of switches included in a timing controller and a data driver according to a fourth embodiment of the present invention.

The display device according to the present invention may be implemented as a television, video player, personal computer (PC), home theater, automobile electric device, smart phone, etc., but is not limited thereto. The display device according to the present invention may be implemented as a light emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), and the like. However, hereinafter, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode is taken as an example.

FIG. 1 is a schematic block diagram of a light emitting display device, and FIG. 2 is a schematic configuration diagram of a subpixel shown in FIG. 1 .

1 and 2, the light emitting display device includes an image supply unit 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, and a power supply unit 180. etc. may be included.

The image supply unit (set or host system) 110 may output various driving signals together with an image data signal supplied from the outside or an image data signal stored in an internal memory. The image supplier 110 may supply data signals and various driving signals to the timing controller 120 .

The timing controller 120 includes a gate timing control signal (GDC) for controlling the operation timing of the scan driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronization signals ( A vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and the like can be output. The timing controller 120 may supply the data signal DATA supplied from the image supply unit 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

The scan driver 130 may output a scan signal (or scan voltage) in response to a gate timing control signal (GDC) supplied from the timing controller 120 . The scan driver 130 may supply scan signals to subpixels included in the display panel 150 through the gate lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or directly formed on the display panel 150 in a gate-in-panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 and converts the digital data signal into analog data based on the gamma reference voltage. It can be converted to voltage and output. The data driver 140 may supply data voltages to subpixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

The power supply unit 180 generates a high-potential first power source and a low-potential second power source based on an external input voltage supplied from the outside, and passes through the first power line EVDD and the second power line EVSS. can be printed out. The power supply 180 provides not only the first power supply and the second power supply, but also a voltage required to drive the scan driver 130 (eg, a gate voltage including a gate high voltage and a gate low voltage) or a voltage required to drive the data driver 140. Required voltage (drain voltage including drain voltage and half drain voltage) and the like can be generated and output.

The display panel 150 may display an image in response to a driving signal including a scan signal and a data voltage, a first power source and a second power source, and the like. Sub-pixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. Also, sub-pixels emitting light may include pixels including red, green, and blue or pixels including red, green, blue, and white.

For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and may include a switching transistor, driving It may include a pixel circuit made of a transistor, a capacitor, an organic light emitting diode, and the like. Since the subpixel SP used in the light emitting display device directly emits light, the circuit configuration is complicated. In addition, there are various compensation circuits for compensating for deterioration of organic light emitting diodes that emit light as well as driving transistors that supply driving current necessary for driving the organic light emitting diodes. Accordingly, it is referred to that the sub-pixel SP is simply illustrated in the form of a block.

Meanwhile, in the above description, the timing control unit 120, the scan driving unit 130, the data driving unit 140, etc. have been described as if they were individual components. However, one or more of the timing controller 120, the scan driver 130, and the data driver 140 may be integrated into one IC, depending on how the light emitting display device is implemented.

3 and 4 are diagrams for explaining the configuration of a gate-in-panel scan driver, and FIG. 5 is a diagram illustrating an arrangement example of a gate-in-panel scan driver.

As shown in FIG. 3 , the gate-in-panel scan driver 130 may include a shift register 131 and a level shifter 135 . The level shifter 135 may generate scan clock signals Clks and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180 . The scan clock signals Clks may be generated in the form of J phases having different phases such as 2 phase, 4 phase, 8 phase, etc. (J is an integer equal to or greater than 2).

The shift register 131 operates based on signals (Clks, Vst) output from the level shifter 135, and scan signals (Scan[1] to Scan [m]) can be output. The shift register 131 may be formed in a thin film form on a display panel by a gate-in-panel method.

As shown in FIGS. 3 and 4 , the level shifter 135 may be formed independently in the form of an IC unlike the shift register 131 or may be included inside the power supply unit 180 . However, this is only one example and is not limited thereto.

As shown in FIGS. 5A and 5B , the shift registers 131a and 131b outputting scan signals from the gate-in-panel scan driver may be disposed in the non-display area NA of the display panel 150 . The shift registers 131a and 131b may be disposed in the left and right non-display areas NA of the display panel 150 as shown in FIG. 5A, or in the upper and lower non-display areas NA of the display panel 150 as shown in FIG. 5B. can Meanwhile, in FIGS. 5A and 5B , the arrangement of the shift registers 131a and 131b in the non-display area NA is illustrated and described as an example, but is not limited thereto.

6 is a diagram showing a light emitting display device according to the first embodiment of the present invention, and FIG. 7 is a diagram showing some configurations of a timing control unit and a data driver according to the first embodiment of the present invention.

As shown in FIG. 6 , the light emitting display device according to the first embodiment of the present invention may include a display panel 150 , a plurality of data drivers 140a to 140d and a timing controller 120 . The plurality of data drivers 140a to 140d are each mounted on a plurality of flexible boards 145, one side of the plurality of flexible boards 145 is connected to the display panel 150, and the other side opposite to the plurality of flexible boards 145 is a printed circuit board. (148).

The plurality of data drivers 140a to 140d and the timing controller 120 may exchange signals based on a communication interface. In this case, the communication interface may be an Embedded Clock Point-Point Interface (EPI) based on an embedded clock method. The EPI interface can transmit data signals, control signals, clock signals, etc. in the form of differential signals through a wire pair.

As shown in FIG. 7 , the timing control unit 120 according to the first embodiment of the present invention includes a first data processing unit 123, a clock adjustment unit 124, a signal synthesis unit 125, and a transmission buffer unit 126. and a transmitting end controller 127 and the like.

The first data processing unit 123 may serve to process the RGB data signals RGB and various control signals CON to be output from the timing controller 120 in a form capable of serial transmission. To this end, the first data processor 123 may include a serializer.

The clock adjusting unit 124 controls the clock signal CLK so that the RGB data signal RGB and various control signals CON to be output from the timing controlling unit 120 are transmitted based on the appropriate clock signal CLK. can do. To this end, the clock control unit 124 may include a phase-locked loop (PLL).

The signal synthesis unit 125 outputs the RGB data signal RGB output from the first data processing unit 123, various control signals CON, and the clock signal CLK output from the clock adjustment unit 124 in the form of data packets. It can play a role in synthesizing so that it can be done. To this end, the signal synthesis unit 125 has a first input terminal connected to the output terminal of the first data processing unit 123, a second input terminal connected to the output terminal of the clock adjusting unit 124, and an output terminal connected to the input terminal of the transmission buffer unit 126. this can be connected.

The transmission buffer unit 126 may serve to transmit data packets output from the signal synthesis unit 125 through an EPI interface (EPI) connected to the data driver 140 . To this end, the transmit buffer unit 126 may have a first terminal connected to the first transmission line of the EPI interface (EPI) and a second terminal connected to the second transmission line. That is, the transmission buffer unit 126 may be connected to a pair of transmission lines.

The transmitting end controller 127 may serve to receive (sens) a signal or voltage fed back from the data driver 140 through an EPI interface (EPI). To this end, the transmitting end controller 127 may have a first terminal connected to the first transmission line and a second terminal connected to the second transmission line. Meanwhile, like the reception buffer unit 146 of the data driver 140 described below, the transmission terminal control unit 127 has a first terminal connected to the first transmission line of the EPI interface (EPI) and a second terminal to the second transmission line. terminal is connected. Accordingly, the data packet transmitted from the transmission buffer unit 126 can be received in the same way as the data packet received by the data driver 140, and a voltage change on the transmission line can be sensed.

The data driver 140 according to the first embodiment of the present invention may include a receive buffer 146, a second data processor 143, a clock restorer 144, and a receiver control unit 147. In addition, the data driver 140 includes a data conversion unit for converting the digital RGB data signal (RGB) output from the reception buffer unit 146 into an analog RGB data voltage and a signal output for outputting the RGB data voltage. may include, etc.

The reception buffer unit 146 may serve to receive data packets transmitted through an EPI interface (EPI) associated with the timing controller 120 . To this end, the reception buffer unit 146 may have a first terminal connected to a first transmission line of the EPI interface (EPI) and a second terminal connected to a second transmission line.

The second data processing unit 143 may play a role of non-serialization in order to extract RGB data signals (RGB) and various control signals (CON) from serial data packets transmitted through the reception buffer unit 146 . To this end, the second data processing unit 143 may include a de-serializer.

The clock recovery unit 144 may play a role of extracting or restoring the clock signal CLK from the serial data packet transmitted through the reception buffer unit 146 .

The receiving terminal controller 147 may play a role of causing a voltage change according to whether the clock signal CLK is normally restored by the clock recovery unit 144 . The receiving end control unit 147 connects the first transmission line constituting the EPI interface (EPI) so that the voltage change according to whether the clock signal CLK is normally restored is fed back to the transmitting end control unit 127 included in the timing control unit 120. 2 It may include a circuit connected to the transmission line. To this end, the receiving terminal controller 147 may include a first resistor R1, a second resistor R2, and a switch SW.

The first resistor R1 may have one end connected to the first transmission line and the other end connected to one end of the second resistor R2 and the first electrode of the switch SW. The second resistor R2 may have one end connected to the other end of the first resistor R1 and the other end connected to the second electrode of the switch SW and the second transmission line. The switch SW has a first electrode connected to the connection point of the first resistor R1 and the second resistor R2 and a second electrode connected to the other end of the second resistor R2 and the second transmission line, and a data driver. A control electrode may be connected to the control unit included in the interior of 140. At least one of the first resistor R1 , the second resistor R2 , and the switch SW may be located outside the data driver 140 . Meanwhile, the switch SW may be controlled by a signal applied from the outside of the data driver 140 .

In the light emitting display device according to the first embodiment of the present invention, the data driver 140 operates normally based on the transmission controller 127 included in the timing controller 120 and the receiver controller 147 included in the data driver 140. It is possible to determine whether the operation is possible.

In addition to the description, the data driver 140 may be in a normal operating state when the normal restoration of the clock signal CLK is completed. In this case, since the data driver 140 is in a normal operating state by restoring the clock signal CLK, a switch control signal can be output from the controller.

When a switch control signal is output from the control unit, the switch SW included in the receiving end control unit 147 may be turned on or off. Also, a voltage change may occur in the first transmission line and the second transmission line constituting the EPI interface EPI in response to turning on or off of the switch SW. A voltage change of the first transmission line and the second transmission line constituting the EPI interface (EPI) may be received and sensed by the transmission terminal controller 127 included in the timing controller 120 .

Since such an operation is possible, the light emitting display device according to the first embodiment of the present invention can delete a lock feedback line for exchanging a lock signal between the timing controller 120 and the data driver 140. do. The lock signal is a signal indicating whether the phase of the internal clock of the data driver 140 is locked. The timing controller 120 may determine whether the data driver 140 is in a normal operating state based on the lock signal and perform the next operation (eg, RGB data signal transmission, etc.).

Hereinafter, the description of the first embodiment will be concreted based on the communication method related to the present invention and the operating state of the device according to the communication method.

8 is a waveform diagram for explaining a part related to a communication method established between a timing controller and a data driver according to a first embodiment of the present invention, and FIGS. 9 and 10 are waveforms related to the device shown in FIG. 11 is a diagram illustrating a change in voltage of a control unit of the receiving end according to the operating state of FIGS. 9 and 10 .

As shown in FIGS. 8 to 10 , when power (VCC) for driving the timing controller 120 is applied, the timing controller 120 controls the timing controller 120 through the EPI interface (EPI) coupled with the data driver 140. A data packet having a system of phase 1 (Phase-I), phase 2 (Phase-II), and phase 3 (Phase-III) can be transmitted.

The first phase (Phase-I) may be a period in which a clock training pattern is transmitted so that the clock recovery unit 144 included in the data driver 140 can extract or restore a normal and stable clock signal CLK. The second phase (Phase-II) may be a period in which a control signal (CON) for controlling a device included in the data driver 140 is transmitted. The third phase (Phase-III) may be a section in which the RGB data signal (RGB) is transmitted to the data driver 140 . Therefore, the first phase (Phase-I) and the second phase (Phase-II) can be transmitted during the blank period in which no image is displayed on the display panel, and the third phase (Phase-III) displays the image on the display panel. It can be transmitted during the active period to indicate.

The data driver 140 converts the logic low internal lock signal ILOCK to the logic high internal lock signal ( ILOCK). In FIG. 8, "tLock" means a reference time required for changing the internal lock signal ILOCK.

The switch (SW) included in the control unit 147 of the receiving end of the data driver 140 is turned on or off by the switch control signal (RX LOCK FB) output from the control unit during the first phase (Phase-I) period. (Off). Hereinafter, when the switch (SW) of the receiving terminal control unit 147 is turned off, the voltage change of the first transmission line and the second transmission line constituting the EPI interface (EPI) will be described as an example, but this is the opposite. may be

When the data driver 140 enters a normal operating state through clock training, the internal lock signal ILOCK may be changed from logic low to logic high.

When the internal lock signal ILOCK is in a logic low state, the switch SW of the control unit 147 of the receiving end may have a turn-on state as shown in FIG. 9 . Also, when the internal lock signal ILOCK is in a logic high state, the switch SW of the control unit 147 of the receiving end may be switched to an off state as shown in FIG. 10 .

As shown in FIG. 10, when the switch (SW) is turned off, the voltage (Vterm) on the transmission line is affected by the first resistor (R1) and the second resistor (R2) [Vterm = i * (R1 + R2)], a change (voltage increase) may occur as can be seen in the “tFB” section of FIG. 11 . However, as shown in FIG. 9, when the switch SW is turned on, the voltage Vterm on the transmission line is affected by the first resistor R1 [Vterm = i * (R1)]. As can be seen outside the "tFB" section of , no change may occur.

The presence or absence of a change in the voltage Vterm on the transmission line may be received and sensed by the transmitter controller 127 included in the timing controller 120 . Also, when an increase in the voltage Vterm on the transmission line is detected as in the “tFB” section of FIG. can judge

Since such an operation is possible, the light emitting display device according to the first embodiment of the present invention can delete a lock feedback line for exchanging a lock signal between the timing controller 120 and the data driver 140. do. On the other hand, when the clock recovery unit 144 of the data driver 140 is not normally operable, that is, in a lock fail state, the timing controller 120 controls the clock through the first phase (Phase-I). Training can be continued. In addition, in the description of the present invention, the case where the voltage (Vterm) on the transmission line increases compared to the previous one is taken as an example, but on the contrary, it may be based on the case where the voltage Vterm decreases compared to the previous one.

12 is a diagram showing some configurations of a timing controller and a data driver according to a second embodiment of the present invention, and FIG. 13 is related to a communication method established between a timing controller and a data driver according to a second embodiment of the present invention. 14 and 15 are diagrams for explaining the operating state of the device related to the waveform shown in FIG. 13, and FIG. 16 is a receiving end control unit according to the operating state of FIGS. 14 and 15. It is a diagram showing voltage change.

As shown in FIG. 12, the timing control unit 120 according to the second embodiment of the present invention includes a first data processing unit 123, a clock adjustment unit 124, a signal synthesis unit 125, and a transmission buffer unit 126. and a transmitting end controller 127 and the like. Also, the data driver 140 according to the second embodiment of the present invention may include a receive buffer 146, a second data processor 143, a clock restorer 144, and a receiver controller 147.

The second embodiment of the present invention differs from the first embodiment in the configuration of the transmission terminal control unit 127 included in the timing control unit 120 and the transmission protocol of the EPI interface, which will be mainly described. Therefore, the remaining parts not explained in the second embodiment refer to the first embodiment.

The transmitting end controller 127 included in the timing controller 120 may include a buffer BUF, a second switch SW2 and a third switch SW3. The second switch SW2 has a first electrode connected to the first transmission line constituting the EPI interface EPI, a second electrode connected to the first terminal of the buffer BUF, and a control unit included in the timing controller. A control electrode may be connected. The third switch (SW3) has a first electrode connected to the second transmission line constituting the EPI interface (EPI), a second electrode connected to the second terminal of the buffer (BUF), and a control unit included in the timing control unit. A control electrode may be connected. Meanwhile, the second switch SW2 and the third switch SW3 may be controlled by a signal applied through a transmission line connected to the data driver 140 .

As shown in FIGS. 13 to 15 , when power (VCC) for driving the timing controller 120 is applied, the timing controller 120 controls the timing controller 120 through the EPI interface (EPI) coupled with the data driver 140. A data packet having a system of phase 1 (Phase-I), phase 2 (Phase-II), and phase 3 (Phase-III) can be transmitted.

The first phase (Phase-I) may be a period in which a clock training pattern is transmitted so that the clock recovery unit 144 included in the data driver 140 can extract or restore a normal and stable clock signal CLK. In the second phase (Phase-II), the first switch control signals FB and RX LOCK FB for controlling the first switch SW1 included in the control unit 147 of the receiving end of the data driver 140 and the data driver 140 ) It may be a section for transmitting a control signal (CON) for controlling the device included in. The third phase (Phase-III) may be a section in which the RGB data signal (RGB) is transmitted to the data driver 140 . Therefore, the first phase (Phase-I) and the second phase (Phase-II) can be transmitted during the blank period in which no image is displayed on the display panel, and the third phase (Phase-III) displays the image on the display panel. It can be transmitted during the active period to indicate.

The data driver 140 converts the logic low internal lock signal ILOCK to the logic high internal lock signal ( ILOCK). In FIG. 13, "tLock" means a reference time required for changing the internal lock signal ILOCK.

The first switch (SW) included in the receiving terminal control unit 147 of the data driver 140 is the first switch control signal (FB, RX LOCK FB) output from the timing control unit 120 during the second phase (Phase-II) period ) can be turned on or turned off (Off). And, the second switch (SW2) and the third switch (SW3) included in the transmitter control unit 127 of the timing control unit 120 transmit the second and third switches output from the timing control unit 120 during the second phase (Phase-II) period. It can be turned on or off at the same time by the third switch control signal (TX SW).

When the data driver 140 enters a normal operating state through clock training, the internal lock signal ILOCK may be changed from logic low to logic high.

When the internal lock signal (ILOCK) is in a logic low state, as shown in FIG. ) and the third switch SW3 may have a turn-off state. Also, when the internal lock signal ILOCK is in a logic high state, the first switch 1SW of the receiving end controller 147 is turned off and the second switch included in the transmitting end controller 127 is turned off as shown in FIG. 15 . (SW2) and the third switch (SW3) can be turned on (On) state.

As shown in FIG. 15, when the first switch (SW) is turned off, the voltage (Vterm) on the transmission line is affected by the first resistor (R1) and the second resistor (R2) [Vterm = i * ( R1 + R2)], a change (voltage increase) may occur as can be seen in the “tFB” section of FIG. 16 .

However, as shown in FIG. 14, when the first switch SW is turned on, the voltage Vterm on the transmission line is affected by the first resistor R1 [Vterm = i * (R1)]. As can be seen outside the “tFB” section of FIG. 16, no change may occur.

The presence or absence of a change in the voltage Vterm on the transmission line may be received and sensed by the transmitter controller 127 included in the timing controller 120 . When an increase in the voltage Vterm on the transmission line is detected as in the “tFB” section of FIG. 16, the timing control unit 120 sets the data driver 140 to a normal operating state, that is, to a reception lock (Rx Lock) state. can judge In addition, if the second switch (SW2) and the third switch (SW3) included in the transmission terminal control unit 127 are turned on only when the voltage (Vterm) on the transmission line changes, the use of the transmission terminal control unit 127 line load can be reduced. That is, since the transmission line and the transmitting end controller 127 are electrically connected only when the voltage change on the transmission line is sensed, the problem of increasing the line load can be prevented.

17 is a waveform diagram for explaining a part related to a communication method established between a timing controller and a data driver according to a third embodiment of the present invention, and FIG. 18 is a waveform diagram for explaining a part of a section of FIG. 17 in more detail. 19 is a flowchart for explaining a driving method according to a third embodiment of the present invention.

Hereinafter, since the third embodiment of the present invention is based on the same implemented device as the second embodiment, FIG. 12 is also referred to. However, the third embodiment differs from the second embodiment in the integrated switch control signal (FB) included in the second phase (Phase-II) and the resulting change in the voltage (Vterm) on the transmission line. This will be mainly explained. . Therefore, the remaining parts not explained in the third embodiment refer to the second embodiment.

As shown in FIGS. 12 and 17 to 19 , when power (VCC) for driving the timing controller 120 is applied or a vertical blank period (VB) is reached, the timing controller 120 is a data driver ( 140), the first phase (Phase-I) may be transmitted (Tx Phase-I transmission) through the EPI interface (EPI) entered into (S10). The first phase (Phase-I) may include a clock training pattern.

Subsequently, it may be determined whether or not the reference time tLock required for changing the internal lock signal ILOCK of the data driver 140 has passed (S20). If the reference time (tLock) has not passed (N), you can wait until the corresponding time has passed, and if the reference time (tLock) has passed (Y), since the internal lock signal (ILOCK) is changed to logic high, timing The control unit 120 may transmit (Tx Phase-II transmission) the second phase (Phase-II) through the EPI interface (EPI) connected with the data driver 140 (S30). The second phase (Phase-II) may include a first switch control signal (FB, RX LOCK FB) for controlling the first switch (SW1) included in the control unit 147 of the receiving end of the data driver 140.

The timing controller 120 turns on the second switch (SW2) and the third switch (SW3) included in the transmitter controller 127 (S40), and turns on the first switch included in the receiver controller 147 of the data driver 140. A first switch control signal (FB, RX LOCK FB) for turning off the switch (SW1) (Rx SW1 Off) may be transmitted (S50). The first switch control signal (FB, RX LOCK FB) for turning off the first switch (SW1) (Rx SW1 Off) is in the form of a data packet (eg, FB Packet(1) => FB_Start(111000), SW1(Off)(111~)) can be taken, but is not limited thereto.

Thereafter, the timing controller 120 may determine a state in which the data driver 140 can normally operate, that is, whether reception is locked (Rx CDR = Lock ?) (S60). When the data driver 140 can operate normally (Y), the first switch SW1 can maintain a turned-off (Tx SW1 Off) state (S70).

Thereafter, the timing controller 120 may sense the output of the transmitter controller 127 (Tx S2 Sensing) to detect whether or not the voltage (Vterm) on the transmission line has changed (S80). The first switch control signal (FB) for turning on (Rx SW1 On) the first switch (SW1) when there is a voltage change (voltage increase) by determining whether the voltage (Vterm) on the transmission line is changed (S80). , RX LOCK FB) may be transmitted (S100).

The first switch control signal (FB, RX LOCK FB) for turning on the first switch (SW1) (Rx SW1 On) may take the same form as FB Packets (N-1) and (N) of FIG. 18, but Not limited. Meanwhile, referring to FIG. 18, the period during which the first switch SW1 is actually turned on may be after FB Packet (N).

Since the timing controller 120 recognizes that the data driver 140 is normally operable due to detection of an increase in the voltage Vterm on the transmission line as shown in the “tFB” section of FIG. 18, thereafter, the voltage Vterm on the transmission line ) can be reversed.

To this end, the timing control unit 120 transmits (S110) the first switch control signal (FB, RX LOCK FB) for turning on the first switch (SW1) (Rx SW1 On), and then switches the second switch (SW2) and The second and third switch control signals TX SW for turning off the third switch SW3 (Tx SW2/3 Off) may be output (S120).

Thereafter, the timing controller 120 may transmit the control signal CON located next to the first switch control signal FB in the second phase (Phase-II) (S130). The control signal (CON) of the second phase (Phase-II), like the first switch control signal (FB), also uses the form of a data packet (eg, CON Packet => CTR_Start (101010), CTR Data) like "CON Packet". can be taken, but is not limited thereto.

Thereafter, the timing controller 120 may transmit the third phase (Phase-III) (Tx Phase-III transmission) to transmit the RGB data signal (RGB) to the data driver 140 (S140).

In this way, when the data packet transmitted through the EPI interface (EPI) is transmitted with a signal for controlling the first switch (SW1), the advantage of specifying the control subject as the timing control unit 120 (synchronized control between devices & circuitry possible) simplification of) can be provided. In addition, the operation initial values of the second switch SW2 and the third switch SW3 are turned off, and the power supply VCC for driving the timing controller 120 is applied or the vertical blank period (VB) If the first switch control signal (FB, RX LOCK FB) is transmitted only at , the line load can be reduced.

20 is a waveform diagram for explaining a control method of switches included in a timing controller and a data driver according to a fourth embodiment of the present invention.

Hereinafter, since the fourth embodiment of the present invention is based on the device implemented identically to the second and third embodiments, FIG. 12 is also referred to. However, since the fourth embodiment has a difference in the control method of the switches included in the timing controller and the data driver compared to the second and third embodiments, this will be mainly described. Therefore, the remaining parts not described in the fourth embodiment refer to the second and third embodiments.

12 and 20, the second switch SW2 and the third switch SW3 included in the transmitter controller 127 of the timing controller 120 are turned off in response to the first set time tTx. (Off), turn-on (On), and turn-off (Off) flow. The second and third switch control signals TX SW for turning the second and third switches SW2 and SW3 off or on are determined inside the timing control unit 120. It may occur during the first phase (Phase-I) period corresponding to 1 set time (tTx), but is not limited thereto.

The first switch (SW1) included in the control unit 147 of the receiving terminal of the data driver 140 operates in a flow of turn on, turn off, and turn on in response to the second set time tRx. can do. The first switch control signal (RX LOCK FB) for turning on or off the first switch (SW1) corresponds to the second set time (tRx) determined inside the data driver 140 It may occur during the first phase (Phase-I) period, but is not limited thereto.

According to the same method as in the fourth embodiment, a feedback line (Lock Feedback Line) for transmitting and receiving a lock signal between the timing controller 120 and the data driver 140 without separately changing the data packet transmitted through the EPI interface (EPI). line) can be deleted. In addition, circuit simplification and line load can be reduced without separately changing data packets transmitted through the EPI interface (EPI).

As described above, the present invention has an effect of simplifying the configuration (circuit parts) of the device by deleting a lock feedback line for exchanging a lock signal between the timing controller and the data driver. In addition, the present invention has an effect of reducing line load through direct control of a switch or indirect control using a protocol when determining whether a data driver is normally locked based on detection of a voltage change on a transmission line instead of a feedback line.

120: timing control unit 123: first data processing unit
124: clock adjustment unit 125: signal synthesis unit
126: transmission buffer unit 127: transmission end control unit
140: data driving unit 146: receiving buffer unit
143: second data processing unit 144: clock recovery unit
147: receiving end control SW, SW1: switch (or first switch)
SW2: 2nd switch SW3: 3rd switch

Claims (12)

data driver;
a timing control unit including a transmission terminal control unit for controlling the data driver and sensing whether or not there is a change in voltage on a transmission line connected to the data driver; and
A display panel displaying an image based on the data voltage output from the data driver;
The timing controller determines whether the data driver is in a normal operating state based on a voltage change on a transmission line connected to the data driver. According to claim 1,
The timing controller
The display device determining that the data driver is in a normal operating state when the voltage on the transmission line increases compared to the previous one. According to claim 1,
the data driver
and a receiving end controller having at least one resistor and a switch to change the voltage on the transmission line. According to claim 3,
The receiving end control unit
A first resistor having one end connected to a first transmission line connected to the timing controller;
a second resistor having one end connected to the other end of the first resistor and the other end connected to a second transmission line connected to the timing controller;
and a switch comprising a first electrode connected to a connection point between the first resistor and the second resistor and a second electrode connected to the other end of the second resistor and the second transmission line. According to claim 4,
the switch
A display device controlled by the data driver or a signal transmitted from the timing controller, wherein the voltage on the transmission line changes according to turning on or off of the switch. According to claim 1,
The transmitting end control unit
A display device electrically connected to a transmission line connected to the data driver only when sensing the presence or absence of the voltage change. According to claim 6,
The transmitting end control unit
a second switch having a first electrode connected to a first transmission line connected to the data driver;
a third switch having a first electrode connected to a second transmission line connected to the data driver;
and a buffer having a first terminal connected to the second electrode of the second switch and a second terminal connected to the second electrode of the third switch. According to claim 1,
The timing controller
A display device for determining whether or not the plurality of data drivers are normally operable based on changes in voltage on a transmission line connected to the plurality of data drivers. a reception buffer unit for receiving a data packet applied through a transmission line; and
a receiving end control having at least one resistor and a switch for varying the voltage on the transmission line;
The switch is turned on or off in response to a signal applied from the outside or inside to change the voltage on the transmission line. According to claim 9,
The receiving end control unit
A first resistor having one end connected to the first transmission line;
a second resistor having one end connected to the other end of the first resistor and the other end connected to a second transmission line connected to the timing controller;
and a switch comprising a first electrode connected to a connection point between the first resistor and the second resistor and a second electrode connected to the other end of the second resistor and the second transmission line. a transmission buffer unit for transmitting data packets through a transmission line; and
A transmitting end control unit for sensing a change in voltage on the transmission line,
A timing control unit for controlling the transmit buffer unit to determine that the receiving terminal is in a normal operating state when a change in voltage on the transmission line is detected, and to transmit a data signal included in a data packet. According to claim 11,
The transmitting end control unit
A second switch having a first electrode connected to a first transmission line connected to the receiving end;
A third switch having a first electrode connected to a second transmission line connected to the receiving end;
and a buffer having a first terminal connected to a second electrode of the second switch and a second terminal connected to a second electrode of the third switch.

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