KR20130120319A - Driving circuit for image display device and method for driving the same - Google Patents

Abstract

Te present invention relates to a driving device of an image display apparatus capable of reducing power consumption at a data transmission process by improving an interface mode of the image display apparatus and a method for driving the same and the feature of the present invention is to comprise; an image display panel having multiple pixel areas; a data driver including multiple data direct circuits which drive data lines of the image display panel; a timing controller which arranges and analyzes image data from outside to a horizontal line unit to be fitted to the data lines which are driven by each data direct circuit and compresses and maintains the arranged data with a compression ratio corresponding with an analyzed result and supplies it to the each data direct circuit, thereby controlling so that the each data direct circuit changes current amounts according to a black term which is changed or maintained by the compression ratio. [Reference numerals] (4) Data driver;(6) Gate driver;(8) Timing controller

Description

TECHNICAL FIELD [0001] The present invention relates to a driving apparatus for a video display device and a driving method thereof. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a video display apparatus, and more particularly, to a driving apparatus and a driving method of a video display apparatus that can reduce power consumption during a data transmission process by improving a data interface method of a video display apparatus.

Recently, a video display device has been developed to realize a screen with high frequency and high resolution in order to realize a more satisfactory screen.

In recent years, image data and control signals are transmitted using a low voltage differential signaling (LVDS) interface technology. The LVDS interface technology is a technology for converting the image data and control signals into LVDS signals. Specifically, the LVDS interface method converts a TTL (Transistor-Transistor Logic) signal into an LVDS signal, and then converts the LVDS signal into a TTL signal to form a timing format. The formatted data and control signals are separately controlled And may be supplied to an integrated circuit or a drive integrated circuit.

The image data supplied to the image display panel to display an image may be data of 8 bits for three colors, i.e., red (R), green (G) and blue (B). In this case, the 3-bit color image data of 8 bits are divided into a control signal such as a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, a data enable signal DE and a clock signal CLK, Signal transmission lines and respective buffers and the like.

In recent years, efforts have been made to reduce power consumption while allowing various convenience items to be applied to a video display device in accordance with various demands of users. Accordingly, various techniques for reducing power consumption are required in the driving devices of the image display panel and the image display panel, and methods for reducing power consumption are also required in the data interface method of the image display device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to improve a data interface method of an image display apparatus so that a data transfer period can be shortened and a power consumption can be reduced in a blank period To a driving apparatus for a video display apparatus and a driving method thereof.

According to an aspect of the present invention, there is provided an apparatus for driving an image display apparatus including: an image display panel formed with a plurality of pixel regions; A data driver including a plurality of data integration circuits for driving data lines of the image display panel; And arranging and analyzing image data from the outside in units of horizontal lines in accordance with data lines driven by the respective data accumulation circuits and compressing or holding the sorted data at a compression rate corresponding to the analyzed result, And a timing controller for controlling the amount of current for each blank period during which the respective data integrated circuits are varied or maintained by the compression ratio.

Wherein the timing controller comprises: a data alignment unit for aligning the image data in units of at least one horizontal line in accordance with the number of data lines driven by the respective data integration circuits; And a data analyzing section for mapping compressed data to a look-up table to generate compressed data at a compression ratio corresponding to the number of gradations or the number of gradation levels used for the aligned data, and supplying the compressed data to each of the data integration circuits .

Data aligned in horizontal line units to correspond to each data integration circuit are mapped to a look-up table so as to correspond to the number of gradation levels or gradation levels used, and compressed data, which is a header bit, And when the number of gradations or the number of gradation levels of the data arranged in the horizontal line unit is equal to or greater than the preset number, the aligned data is maintained in a state of zero compression rate and supplied to each of the data integration circuits .

Wherein a resistance capacity during a blank period of each horizontal period is greater than a resistance capacity of a data transmission period in data interface lines of each data integrated circuit in which compressed data or sorted data corresponding to the set compression ratio is received And a current capacity control unit for varying the resistance of the data interface line during the blank period to reduce the amount of current.

Wherein the current amount control unit includes a plurality of resistance elements arranged in a parallel structure with different resistance capacities in respective data interface lines formed in the respective data integration circuits, A first switching element for connecting a resistance element having a smaller resistance capacity among the plurality of resistance elements to the respective interface lines in parallel during a data transfer period of the horizontal periods, And a second switching element for connecting a resistance element having a larger resistance capacity among the resistance elements in parallel to each of the interface lines in a blank period of the resistance element.

According to another aspect of the present invention, there is provided a method of driving a video display device including a video display panel having a plurality of pixel regions and a plurality of data accumulation units driving data lines of the video display panel, A method of driving a video display device having a data driver including a circuit, comprising the steps of: arranging and analyzing video data from the outside in units of horizontal lines in accordance with data lines driven by the respective data integrated circuits; Compressing or maintaining the sorted data at a corresponding compression rate and supplying the data to the respective data integration circuits; And varying a current amount of the interface line for each blank period which is varied or held by the compression ratio.

Wherein the step of compressing or maintaining the sorted data and supplying the sorted data to each data integration circuit includes arranging the image data in at least one horizontal line unit in accordance with the number of data lines driven by the respective data integration circuits using a data arrangement unit And a data analyzing unit for mapping the data arranged in horizontal line units to correspond to each of the data integration circuits to a look-up table and outputting the compressed data at a compression rate corresponding to the number of gradations or the number of gradation levels used for the aligned data And supplying the compressed data to each of the data integration circuits.

Data aligned in horizontal line units to correspond to each data integration circuit are mapped to a look-up table so as to correspond to the number of gradation levels or gradation levels used, and compressed data, which is a header bit, And when the number of gradations or the number of gradation levels of the data arranged in the horizontal line unit is equal to or greater than the preset number, the aligned data is maintained in a state of zero compression rate and supplied to each of the data integration circuits .

Wherein the step of varying a current amount of an interface line of each data integration circuit in which compressed data or sorted data corresponding to the set compression ratio is received comprises the step of changing a resistance capacity during a blank period of each horizontal period to a resistance capacity The resistance of the data interface line is increased during the blank period to reduce the amount of current.

Wherein the step of varying the amount of current of the interface line includes a step of changing a resistance of the plurality of resistance elements arranged in a parallel structure with different resistance capacities in the respective data interface lines formed in the respective data integration circuits in the data transfer period of each horizontal period, A step of connecting a resistance element having a smaller capacitance to each of the interface lines in parallel, and a step of connecting a resistance element having a larger resistance capacity among the respective resistance elements in parallel during the blanking period of each horizontal period The method comprising the steps of:

According to an embodiment of the present invention, there is provided a driving apparatus for a video display device and a driving method thereof, which improves the data interface scheme so as to shorten a data transfer period in at least one horizontal period, During the blank period, power consumption can be reduced.

1 is a circuit diagram showing a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a block diagram specifically showing the liquid crystal display device shown in FIG. 1. FIG.
FIG. 3 is a block diagram showing driving areas of data integrated circuits according to the data integrated circuits of FIG. 2; FIG.
4 is a diagram specifically showing the timing controller of FIG. 1 and FIG. 2;
FIG. 5 is a diagram showing a data compression rate change and a corresponding blank period variation rate in at least one horizontal period unit. FIG.
6 is a diagram showing data format information corresponding to a compression rate change;
7A and 7B are diagrams showing a data interface unit constituted respectively in a timing controller and a data integration circuit;

Hereinafter, a driving apparatus and a driving method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The image display device may be a flat display device generally used, for example, a liquid crystal display, a field emission display, a plasma display panel, and an organic light emitting diode display device (Organic Light Emitting Diode Display) or the like. However, a liquid crystal display device will be described below as an example for convenience of explanation.

1 is a circuit diagram showing a liquid crystal display device according to an embodiment of the present invention. 2 is a block diagram specifically showing the liquid crystal display device shown in FIG.

The liquid crystal display device shown in FIGS. 1 and 2 includes a liquid crystal panel 2 formed with a plurality of pixel regions; A gate driver 3 for driving the plurality of gate lines GL1 to GLn provided in the liquid crystal panel 2; A data driver 4 including a plurality of data integrated circuits 4a for driving a plurality of data lines DL1 to DLm provided in the liquid crystal panel 2; And arranges and analyzes the image data RGB from the outside in units of horizontal lines in accordance with the data lines DL1 to DLm driven by the respective data integration circuits 4a and compresses the sorted data at a compression ratio corresponding to the analysis result And supplies the data to the data integration circuit 4a so that each data integration circuit 4a can reduce the amount of current for each blank period during which the data is varied by the compression ratio.

The timing controller 8 aligns and analyzes the image data RGB corresponding to the driving data lines DL1 to DLm for each data integration circuit 4a by using the built-in memory or the look-up table, The compressed data can be compressed and transmitted. However, if necessary, a separate memory or a look-up table 12 may be further provided and used to generate a header file of the image data (RGB) upon compression transmission of the timing controller 8.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, and a liquid crystal capacitor (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating film interposed therebetween. Alternatively, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween.

2, the data driver 4 is provided between one side of the liquid crystal panel 2 and at least one source printed circuit board 5 and is connected to the data lines DL1 to DLm of the corresponding region, And a plurality of data accumulation circuits 4a for driving the plurality of data accumulation circuits 4a. Here, each of the plurality of data integrated circuits 4a is mounted on the data circuit film, and is connected between the liquid crystal panel 2 and the source printed circuit board 5.

Each data integration circuit 4a includes a data control signal DCS from the timing controller 8, for example, a source start signal SSP, a source shift clock SSC, A source output enable (SOE) signal, and the like. In addition, each data integration circuit 4a receives the compressed data, that is, the header file and the aligned data Data, from the timing controller 8, and supplies the analog data, that is, the video signal, to the data lines.

Each of the data integration circuits 4a restores the aligned data Data using the data control signal DCS and the header bit (compressed data) when compressed data that is a header bit is supplied from the timing controller 8 , And converts the restored data (Data) into an analog voltage, that is, a video signal. In this manner, when header bits are supplied with compressed data, the blank period is varied except for the period during which the header bits are supplied during each horizontal period according to the compression rate of the data. At this time, each data integration circuit 4a uses at least one of the data control signals DCS to increase the resistance capacity of the data interface line for each blank period of each horizontal period depending on the data compression rate, .

On the other hand, when the data (Data) arranged without compression is supplied as it is, each data integration circuit 4a converts the data (Data) as it is, into an analog voltage, that is, a video signal. In this case, although the blank period is shorter than the horizontal period in which the compressed data is supplied, the resistance capacity of the data interface line can be increased in the blank period to reduce the consumption current amount.

Each of the data integrated circuits 4a outputs the alignment data (Data) input from the timing controller 8 according to the SSC when the data Data arranged in a state where the compression rate is 0 is supplied as it is or when the aligned data Data is restored Data). In response to the SOE signal, a video signal for one horizontal line is supplied to each of the data lines DL1 to DLm for every one horizontal period in which scan pulses are supplied to the gate lines GL1 to GLn. At this time, the data driver 4 selects a positive or negative gamma voltage having a predetermined level according to the gradation value of the aligned data Data, and outputs the selected gamma voltage to each of the data lines DL1 to DLm Supply.

The gate driver 6 may be formed integrally with the liquid crystal panel 2 in the image non-display area of the liquid crystal panel 2 or may be provided in an integrated circuit form and provided separately on either side of the liquid crystal panel 2. The gate driver 6 outputs the gate control signal GCS from the timing controller 8, for example, a gate start pulse (GSP), a gate shift clock (GSC) A scan pulse is sequentially supplied to each gate line GL1 to GLn using a gate output enable (GOE) signal or the like. During a period in which no scan pulse is supplied to each of the gate lines GL1 to GLn, a gate low voltage is supplied.

The timing controller 8 may be provided on a separate control printed circuit board 10 as shown in FIG. 2 or may be provided on a source printed circuit board 5 to receive image data RGB and synchronization signals DCLK, Hsync, Vsync, DE), and controls the gate driver 6 and each of the plurality of data integrated circuits 4a.

Specifically, the timing controller 8 supplies image data (RGB) input from the outside such as the graphic system 9 and the like to the data line driver of each data integration circuit 4a in accordance with driving of the liquid crystal panel 2 Align at least one horizontal line unit. Then, the gradation level of the data (Data) aligned in at least one horizontal line unit is analyzed to set the compression ratio to correspond to the number of analyzed gradations, that is, the number of gradations (gradation levels) used in at least one horizontal line. Then, the compressed data is supplied to the data integration circuit 4a at the corresponding extrusion rate so that the respective data integration circuits 4a increase the resistance capacity of the data interface lines during the remaining blank periods except for the period during which the compressed data is transmitted The amount of current consumption can be reduced.

In addition, the timing controller 8 uses at least one of externally input synchronizing signals, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync, And controls the gate driver 3 and each data integration circuit 4a by generating control signals GCS and DCS and supplying them to the gate driver 3 and the respective data integration circuits 4a, respectively.

FIG. 3 is a configuration diagram showing driving areas of data integrated circuits according to the data integrated circuits of FIG. 2; FIG.

Referring to FIG. 3, data lines DL1 to DLm are respectively connected to the output channels of the plurality of data integrated circuits 4a to correspond to the output channels. Accordingly, the liquid crystal panel 2 may be divided into a plurality of regions 1DM to 6DM according to the formation region of the data lines connected to the respective data integrated circuits 4a. In other words, each of the data integrated circuits 4a corresponds to each of the regions 1DM to 6DM and supplies the video signals to corresponding data lines DL1 to DLm connected thereto.

The timing controller 8 controls the timing controller 8 so that the inputted image data RGB is supplied to at least one horizontal line unit in accordance with the data line driving number of each data integration circuit 4a in order to drive the respective regions of the liquid crystal panel 2, . The gradation level of the data (Data) arranged in at least one horizontal line unit is analyzed to set the compression ratio so as to correspond to the number of analyzed gradations, that is, the number of gradations (gradation levels) used in at least one horizontal line.

4 is a diagram specifically showing the timing controller of FIG. 1 and FIG. 2. FIG.

The timing controller 8 shown in Fig. 4 includes a data arrangement section 22 for arranging image data RGB in units of at least one horizontal line in accordance with the data lines DL1 to DLm driven by the respective data integration circuits 4a, Up table by mapping the data (HLdata) arranged in the horizontal line unit to correspond to the data integrated circuit 4a to the lookup table so as to output the compressed data (HLdata) to the lookup table at a compression rate corresponding to the number of gradations And a data analysis unit 24 for supplying the compressed data to the respective data integration circuits 4a.

The data HLdata aligned on a horizontal line basis so as to correspond to each data integration circuit 4a are mapped to a look-up table so as to correspond to the number of gradations (gradation levels) used so that compressed data, And supplied to each data integration circuit 4a through the analysis unit 24. [ At this time, the number of gradations (gradation levels) is preset and applied to a look-up table for generating a header file. For example, when the number of gradations (gradation levels) is set to 16 levels, the gradation levels (gradation levels) are mapped to the number of gradation levels within 16 gradation levels in the look-up table so that the compression rate can be applied up to 8 times. However, if the number of gradations (gradation levels) of the data HLdata arranged in units of horizontal lines is equal to or greater than the preset number, for example, 16 gradations, the aligned data Data is maintained in the state of 0 compression rate And supplied to each data integration circuit 4a.

5 is a diagram showing a change in data compression rate and a change rate of a blank period in at least one horizontal period unit. 6 is a diagram showing data format information corresponding to a compression rate change.

Referring to FIGS. 5 and 6, each horizontal period is set to a data transmission period and a blank period in which packet data, sorting data (HLData), and compressed data are transmitted. Therefore, if the data transfer period during which the alignment data (HLData) or compressed data is transferred is shortened, the blank period is increased. Since each data integration circuit 4a increases the resistance capacity of the data interface line in the blank period during each horizontal period to reduce the amount of current consumption, the higher the compression ratio of the alignment data HLData, the longer the blank period and the more the current consumption decreases .

The aligned data HLdata of the data sorting unit 22 are mapped to the look-up table so as to correspond to the number of gradations (gradation levels) used so that compressed data that is a header bit is generated, ) Is preset and applied to a look-up table that generates a header file. Referring to FIG. 6, when the number of gradations (gradation levels) is set to 16 levels, the gradation (gradation levels) are mapped to a number within 16 gradation levels in the look-up table, have. However, when the number of gradations (gradation levels) is equal to or greater than a predetermined number, for example, 16 gradations, the aligned data Data is supplied to each data accumulation circuit 4a as it is with a compression rate of zero.

When the number of the same level gradations of data HLData aligned in at least one horizontal line unit is 5 to 16, the compressed data is transmitted in 4 bits which can transmit 5 to 16 tone values, so that the compression rate can be doubled . Thus, since the number of bits of the compressed data transmitted to the data integrated circuit 4a is reduced to 1/2, the blank period is increased by the reduced data transfer period.

If the number of the same level gradations of data HLData aligned in at least one horizontal line unit is three and four, the compression rate can be quadrupled because the compressed data is transmitted in two bits capable of transmitting three or four tone values. Thus, since the number of bits of the compressed data transmitted to the data integration circuit 4a is reduced to 1/4, the blank period is increased by the reduced data transfer period.

When the number of gradations of the same level of the data (HLData) arranged in at least one horizontal line unit is two, the compressed data is transmitted at one bit capable of transmitting two gradation values, for example, black or white data, . Thus, since the number of bits of the compressed data transmitted to the data integration circuit 4a is reduced to 1/8, the blank period is increased by the reduced data transfer period.

If the data arranged in at least one horizontal line unit are arranged at one gradation level, there is no need to transmit compressed data, so that one horizontal period can be set as a blank period without a data transfer period.

7A and 7B are diagrams showing a data interface unit constituted respectively by the timing controller and the data integration circuit.

As shown in FIG. 7A, the timing controller 8 is provided with an LVDS transmission section, in which image data (HLdata) having an aligned compression rate of 0, compressed data compressed at a predetermined compression rate, and a plurality of control signals (Vsync, Hsync, DE , DCLK) into an LVDS signal and transmits it to the LVDS receiver of each data integration circuit 4a.

The process of converting the TTL signal into the LVDS signal is as follows. The image data HLdata having the compression rate of 0 supplied to the LVDS receiving unit of each data integration circuit 4a is divided into three colors: red (R), green (G) (8) bits of data for the data (B). In this case, the 3-color image data of 8 bits are applied to the TTL-TO-LVDS converter 110 constituting the LVDS transmission unit through a 24-line TTL (Transistor-Transistor Logic) signal transmission line. On the other hand, the compressed data compressed at a predetermined compression rate becomes data of any one of 1 bit to 4 bits. At this time, the 3-color video data is transmitted through a TTL (Transistor-Transistor Logic) signal transmission line of 1 to 12 lines, To-TTL-to-LVDS converter 110 constituting a transmission unit. The control signal is applied to the TTL-TO-LVDS converter 110 through a corresponding TTL signal transmission line having 6 or more lines, and a dot clock DCLK thereof is applied to a first phase-locked loop 120 .

The TTL-TO-LVDS converter 110 outputs the LVDS signals IN0, IN1 and IN2 to be transmitted for each transmission line through the first to third buffers 130a, 130b and 130c. The first PLL 120 also converts the dot clock DCLK into an LVDS signal and transmits the clock signal CKIN through the fourth buffer 130d.

7B, an LVDS receiving unit is formed in each data integration circuit 4a. The LVDS receiving unit converts the LVDS signal into a 1-port LVDS data of each pixel, which is converted into an LVDS signal, (HLdata), compressed data, and a plurality of control signals (Vsync, Hsync, DE) into a TTL signal.

The LVDS signal including the aligned data (HLdata) and the compressed data transmitted through IN0, IN1, and IN2 is transmitted to the fifth to seventh buffers 210a, 210b, and 210c TO-TTL converter 220 and the LVDS-converted clock signal CKIN is also input to the second PLL 230 through the eighth buffer 210d. The second PLL 230 provides a reference signal to the LVDS-TO-TTL converter 220 with a TTL signal. The LVDS-TO-TTL converter 220 converts the input LVDS signal into a TTL signal, .

The receiving end of each data integration circuit 4a, that is, the data interface lines in which the compressed data or the aligned data is received corresponding to the compression rate set in the data analysis process through the look-up table, And a current amount control unit (OSW) for varying the resistance capacity of the data interface line so as to be larger than the resistance capacity of the data transfer period, thereby increasing the resistance capacity of the data interface line during the blank period and reducing the amount of current consumption.

Concretely, each of the IN0, IN1 and IN2 receiving ends of the data interface lines formed in the respective data integrated circuits 4a, that is, the fifth to seventh buffers 210a, 210b and 210c, A resistance element R2 having a small resistance capacity among the plurality of resistance elements R1 and R2 in the data transfer period of each horizontal period according to at least one of the arranged plurality of resistance elements R1 and R2 and data control signals, A first switching element SW2 for connecting the first switch SW1 and the second switch SW2 in parallel to each interface receiver, and a resistance capacity of each of the resistors R1 and R2 in the blank period of each horizontal period according to at least one of the data control signals And a second switching element SW2 for connecting a larger resistance element R1 in parallel to each interface receiving end.

The first switching device SW2 connects the resistance element R2 having a small resistance capacity among the plurality of resistance elements R1 and R2 to the respective interface receiving ends in parallel during the data transfer period of each horizontal period, Can be increased. Therefore, during the data transfer period, it is possible to interface the compressed data and the control signals with a high current amount by the low resistance capacity.

On the other hand, the second switching device SW2 connects the resistance element R1 having a larger resistance capacity among the plurality of resistance elements R1 and R2 to the respective interface receiving ends in parallel during the blanking period of each horizontal period, It is possible to reduce the amount of current with respect to the period. Therefore, in the blank period, a low current amount can be maintained by the high resistance capacity, and the power consumption can be reduced.

As described above, the driving apparatus and the driving method of the image display apparatus according to the embodiment of the present invention improve the data interface method in units of the data transfer period and the blank period to shorten the data transfer period, The power consumption can be reduced in the blank period in which the voltage is extended or maintained in the predetermined period.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Claims (10)

An image display panel formed with a plurality of pixel regions;
A data driver including a plurality of data integration circuits for driving data lines of the image display panel; And
The image data from outside is sorted and analyzed in units of horizontal lines in accordance with the data lines driven by the data accumulation circuits and the sorted data is compressed or maintained at a compression rate corresponding to the analyzed result, So that each of the data integrated circuits can vary the amount of current for each blank period during which the data is varied or maintained by the compression ratio. The method according to claim 1,
The timing controller
A data arrangement section for arranging the image data in at least one horizontal line unit in accordance with the number of data lines driven by the respective data integration circuits,
Mapping data arranged in units of horizontal lines corresponding to each data integration circuit to a look-up table to generate compressed data at a compression rate corresponding to the number of gradations or the number of gradation levels used for the aligned data, And a data analyzing unit for supplying the data to the respective data integrated circuits. 3. The method of claim 2,
The data arranged in units of horizontal lines corresponding to the respective data integrated circuits
The compressed data, which is a header bit mapped to the look-up table so as to correspond to the number of gradation levels or the number of gradation levels used, is supplied to each data integration circuit through the data analysis section,
Wherein when the number of gradations or the number of gradation levels of the data arranged in the horizontal line unit is equal to or greater than the preset number, the aligned data is maintained in a state of zero compression rate and supplied to each of the data accumulation circuits. Device for driving a device. The method of claim 3,
The data interface lines of the respective data integrated circuits in which compressed data or aligned data corresponding to the set compression rates are received
And a current capacity control unit for varying the resistance capacity during the blank period of each horizontal period so as to be larger than the resistance capacity of the data transfer period so as to increase the resistance capacity of the data interface line during the blank period And a driving circuit for driving the video display device. 5. The method of claim 4,
The current-
A plurality of resistive elements arranged in parallel on the data interface lines formed in the respective data integration circuits,
A first switching element for connecting a resistance element having a smaller resistance capacity among the plurality of resistance elements in parallel to each of the interface lines in a data transfer period of each of the horizontal periods according to at least one of the data control signals,
And a second switching element for connecting a resistance element having a larger resistance capacity among the resistance elements in parallel to each of the interface lines in a blank period of each horizontal period according to at least one of the data control signals And a driving circuit for driving the video display device. A method of driving a video display device including a data driver including a video display panel formed with a plurality of pixel regions and a plurality of data integrated circuits driving data lines of the video display panel,
The image data from outside is sorted and analyzed in units of horizontal lines in accordance with the data lines driven by the data accumulation circuits and the sorted data is compressed or maintained at a compression rate corresponding to the analyzed result, ; And
And varying the amount of current of the interface line for each blank period which is varied or maintained by the compression ratio. The method according to claim 6,
The step of compressing or maintaining the sorted data and supplying it to each of the data integration circuits
Arranging the image data by at least one horizontal line unit in accordance with the number of data lines driven by the respective data integration circuits by using a data arrangement unit,
Mapping data arranged in horizontal line units to a look-up table so as to correspond to each of the data integration circuits by using a data analysis unit, and generating compressed data at a compression rate corresponding to the number of gradations or the number of gradation levels used for the aligned data And supplying the compressed data to each of the data integration circuits. 8. The method of claim 7,
The data arranged in units of horizontal lines corresponding to the respective data integrated circuits
The compressed data, which is a header bit mapped to the look-up table so as to correspond to the number of gradation levels or the number of gradation levels used, is supplied to each data integration circuit through the data analysis section,
Wherein when the number of gradations or the number of gradation levels of the data arranged in the horizontal line unit is equal to or greater than the preset number, the aligned data is maintained in a state of zero compression rate and supplied to each of the data accumulation circuits. A method of driving a device. 9. The method of claim 8,
Wherein the step of varying the amount of current of the interface line of each data integration circuit in which compressed data or aligned data corresponding to the set compression ratio is received
The resistance capacity of the data interface line is increased during the blank period by using a current amount control unit that varies the resistance capacity during the blank period of each horizontal period to be larger than the resistance capacity of the data transfer period And a driving method of the video display device. 10. The method of claim 9,
The step of varying the amount of current of the interface line
And a resistance element having a smaller resistance capacity among a plurality of resistance elements arranged in a parallel structure with different resistance capacities in respective data interface lines formed in the respective data integration circuits in the data transfer period of each horizontal period, Connecting in parallel to the line, and
And connecting a resistance element having a larger resistance capacity among the resistance elements to the respective interface lines in parallel during the blanking period of each horizontal period.

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