KR20230102599A - Gamma Voltage Generating Circuit and Display Device including the same - Google Patents

Abstract

The present invention includes a display panel for displaying an image; a data driver supplying a data voltage to the display panel; and a main gamma voltage generator supplying voltages divided into multiple levels from outside the data driver, and generating a gamma reference voltage for red inside the data driver based on the voltages supplied from the main gamma voltage generator. a gamma voltage generation circuit including a sub-gamma voltage generator including a red gamma circuit for generating a gamma reference voltage for green, a green gamma circuit for generating a gamma reference voltage for green, and a blue gamma circuit for generating a gamma reference voltage for blue; divides voltages supplied from the main gamma voltage generator to generate the gamma reference voltage for red, and the red gamma circuit and the blue gamma circuit are generated from voltages supplied from the main gamma voltage generator and an internal circuit. It is possible to provide a light emitting display device that generates the gamma reference voltage for red and the gamma reference voltage for blue, respectively, by adding or subtracting a voltage difference between the applied voltages.

Description

Gamma Voltage Generating Circuit and Display Device including the same}

The present invention relates to a gamma voltage generating circuit and a light emitting display device including the same.

As information technology develops, the market for display devices, which are communication media between users and information, is growing. Accordingly, the use of display devices such as a light emitting display device (LED), a quantum dot display device (QDD), and a liquid crystal display device (LCD) is increasing.

The display devices described above include a display panel including sub-pixels, a driving unit outputting a driving signal for driving the display panel, and a power supply unit generating power to be supplied to the display panel or the driving unit.

In the above display devices, when a driving signal, for example, a scan signal and a data signal, is supplied to subpixels formed on a display panel, the selected subpixel transmits light or emits light directly, thereby displaying an image.

The present invention integrates (internalizes) some of the circuits included in the gamma voltage generator circuit into the data driver to simplify the configuration of the circuit (eg, simplify the output channel of the gamma voltage generator circuit).

The present invention includes a display panel for displaying an image; a data driver supplying a data voltage to the display panel; and a main gamma voltage generator supplying voltages divided into multiple levels from outside the data driver, and generating a gamma reference voltage for red inside the data driver based on the voltages supplied from the main gamma voltage generator. a gamma voltage generation circuit including a sub-gamma voltage generator including a red gamma circuit for generating a gamma reference voltage for green, a green gamma circuit for generating a gamma reference voltage for green, and a blue gamma circuit for generating a gamma reference voltage for blue; divides voltages supplied from the main gamma voltage generator to generate the gamma reference voltage for red, and the red gamma circuit and the blue gamma circuit are generated from voltages supplied from the main gamma voltage generator and an internal circuit. It is possible to provide a light emitting display device that generates the gamma reference voltage for red and the gamma reference voltage for blue, respectively, by adding or subtracting a voltage difference between the applied voltages.

The green gamma circuit, the red gamma circuit, and the blue gamma circuit may include the same number of resistors.

The main gamma voltage generator and the sub gamma voltage generator select at least one of the voltages divided into a plurality of levels based on a plurality of switches that are divided and connected to voltage dividing nodes of a plurality of resistors, and a main switch circuit and a sub switch. Each circuit may contain

The red gamma circuit and the blue gamma circuit add or subtract a voltage difference between voltages supplied from the main gamma voltage generator and voltages generated from the sub switch circuit to obtain the gamma reference voltage for red and the gamma reference for blue. Each voltage can be generated.

The red gamma circuit includes a first differential amplifier including a plurality of differential amplifiers for adding or subtracting a voltage difference between voltages supplied from the main gamma voltage generator and positive voltages output from the sub switch circuit; , The blue gamma circuit includes a second differential amplifier including a plurality of differential amplifiers for adding or subtracting a voltage difference between voltages supplied from the main gamma voltage generator and negative voltages output from the sub switch circuit. can do.

The main gamma voltage generator and the sub gamma voltage generator may include a communication interface for exchanging data.

The main gamma voltage generator includes a main register storing a register value and a data transmission unit converting voltages output through the main switch circuit based on the register value into data and transmitting the data, wherein the sub gamma voltage generator includes the main gamma voltage A data receiving unit receiving voltages supplied from the generating unit, and a sub register outputting a register value for controlling the sub switch circuit based on the voltages supplied from the data receiving unit and the data supplied from the data transmitting unit. can

In another aspect, the present invention provides a main gamma voltage generator including a main switch circuit for selecting at least one of voltages divided into a plurality of levels based on a plurality of switches that are divided and connected to voltage dividing nodes of a plurality of resistors; and a sub-gamma voltage generator including a sub-switch circuit for selecting at least one of voltages divided into a plurality of levels based on a plurality of switches that are divided and connected to voltage dividing nodes of a plurality of resistors, wherein the sub-gamma voltage The generator generates a red gamma reference voltage based on the voltages supplied from the main gamma voltage generator, a red gamma circuit that generates a gamma reference voltage for red, a green gamma circuit that generates a gamma reference voltage for green, and a blue gamma circuit that generates a gamma reference voltage for blue. wherein the green gamma circuit divides the voltages supplied from the main gamma voltage generator to generate the red gamma reference voltage, and the red gamma circuit and the blue gamma circuit are supplied from the main gamma voltage generator. A gamma voltage generation circuit may be provided that generates the gamma reference voltage for red and the gamma reference voltage for blue by adding or subtracting a voltage difference between the generated voltages and the voltages generated from the sub switch circuit.

The red gamma circuit includes a first differential amplifier including a plurality of differential amplifiers for adding or subtracting a voltage difference between voltages supplied from the main gamma voltage generator and positive voltages output from the sub switch circuit; , The blue gamma circuit includes a second differential amplifier including a plurality of differential amplifiers for adding or subtracting a voltage difference between voltages supplied from the main gamma voltage generator and negative voltages output from the sub switch circuit. can do.

The main gamma voltage generator includes a main register storing a register value and a data transmission unit converting voltages output through the main switch circuit based on the register value into data and transmitting the data, wherein the sub gamma voltage generator includes the main gamma voltage A data receiving unit receiving voltages supplied from the generating unit, and a sub register outputting a register value for controlling the sub switch circuit based on the voltages supplied from the data receiving unit and the data supplied from the data transmitting unit. can

The present invention has an effect of simplifying the configuration of the circuit (eg, simplifying the output channel of the gamma voltage generating circuit) by integrating (internalizing) some circuits included in the gamma voltage generating circuit into the data driver. In addition, the present invention has an effect of simplifying wiring layout and processes required therefor by simplifying the configuration of a gamma voltage generating circuit when implementing a display device expressing an image based on an RGB independent gamma reference voltage. In addition, the present invention has an effect of providing a programmable gamma voltage generation circuit capable of simplifying a control system and signal lines and relatively freely changing gamma to suit the characteristics of a display device.

FIG. 1 is a schematic block diagram of a light emitting display device, and FIG. 2 is a schematic configuration diagram of a subpixel shown in FIG. 1 .
3 and 4 are diagrams for explaining the configuration of a gate-in-panel scan driver, and FIG. 5 is a diagram illustrating an arrangement example of a gate-in-panel scan driver.
6 is a diagram showing a data driver having a gamma voltage generation circuit according to the first embodiment of the present invention, FIG. 7 is a diagram showing a main gamma voltage generator and a sub gamma voltage generator, and FIG. It is a diagram for explaining a part related to the shown RGB resistance array, and FIG. 9 is a diagram for explaining the advantages according to the first embodiment of the present invention.
10 is a diagram showing a main gamma voltage generator and a sub gamma voltage generator according to a second embodiment of the present invention, FIG. 11 is a diagram for explaining parts related to the differential amplifier shown in FIG. 10, and FIG. 12 is It is a drawing for explaining the advantages according to the second embodiment of the present invention.
13 is a diagram showing a main gamma voltage generator and a sub gamma voltage generator according to a third embodiment of the present invention, and FIG. 14 is a diagram for explaining a part related to data output through the serial interface shown in FIG. 13 .

The display device according to the present invention may be implemented as a television, video player, personal computer (PC), home theater, automobile electric device, smart phone, etc., but is not limited thereto. The display device according to the present invention may be implemented as a light emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), and the like. However, hereinafter, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode is taken as an example.

FIG. 1 is a schematic block diagram of a light emitting display device, and FIG. 2 is a schematic configuration diagram of a subpixel shown in FIG. 1 .

1 and 2, the light emitting display device includes an image supply unit 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, and a power supply unit 180. etc. may be included.

The image supply unit (set or host system) 110 may output various driving signals together with an image data signal supplied from the outside or an image data signal stored in an internal memory. The image supplier 110 may supply data signals and various driving signals to the timing controller 120 .

The timing controller 120 includes a gate timing control signal (GDC) for controlling the operation timing of the scan driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronization signals ( VSYNC, which is a vertical synchronization signal, and HSYNC, which is a horizontal synchronization signal) can be output. The timing controller 120 may supply the data signal DATA supplied from the image supply unit 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

The scan driver 130 may output a scan signal (or scan voltage) in response to a gate timing control signal (GDC) supplied from the timing controller 120 . The scan driver 130 may supply scan signals to subpixels included in the display panel 150 through the gate lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or directly formed on the display panel 150 in a gate-in-panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 and converts the digital data signal into analog data based on the gamma reference voltage. It can be converted to voltage and output. The data driver 140 may supply data voltages to subpixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

The power supply unit 180 may generate a high potential voltage and a low potential voltage based on an external input voltage supplied from the outside, and output them through the first power line EVDD and the second power line EVSS. The power supply 180 is used not only for the high potential voltage and the low potential voltage, but also for driving the scan driver 130 (for example, a gate voltage including a gate high voltage and a gate low voltage) or for driving the data driver 140. Required voltage (drain voltage including drain voltage and half drain voltage) and the like can be generated and output.

The display panel 150 may display an image in response to a driving signal including a scan signal and a data voltage and a driving voltage including a high potential voltage and a low potential voltage. Sub-pixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. Also, sub-pixels emitting light may include pixels including red, green, and blue or pixels including red, green, blue, and white.

For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and may include a switching transistor, driving It may include a pixel circuit made of a transistor, a capacitor, an organic light emitting diode, and the like. Since the subpixel SP used in the light emitting display device directly emits light, the circuit configuration is complicated. In addition, there are various compensation circuits for compensating for deterioration of organic light emitting diodes that emit light as well as driving transistors that supply driving current necessary for driving the organic light emitting diodes. Accordingly, it is referred to that the sub-pixel SP is simply illustrated in the form of a block.

Meanwhile, in the above description, the timing control unit 120, the scan driving unit 130, the data driving unit 140, etc. have been described as if they were individual components. However, one or more of the timing controller 120, the scan driver 130, and the data driver 140 may be integrated into one IC, depending on how the light emitting display device is implemented.

3 and 4 are diagrams for explaining the configuration of a gate-in-panel scan driver, and FIG. 5 is a diagram illustrating an arrangement example of a gate-in-panel scan driver.

As shown in FIG. 3 , the gate-in-panel scan driver 130 may include a shift register 131 and a level shifter 135 . The level shifter 135 may generate driving clock signals Clks and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180 . The driving clock signals Clks may be generated in the form of J phases (J is an integer equal to or greater than 2) having different phases, such as two phases, four phases, and eight phases.

The shift register 131 operates based on signals (Clks, Vst) output from the level shifter 135, and scan signals (Scan[1] to Scan [m]) can be output. The shift register 131 may be formed in a thin film form on a display panel by a gate-in-panel method.

As shown in FIGS. 3 and 4 , the level shifter 135 may be formed independently in the form of an IC unlike the shift register 131 or may be included inside the power supply unit 180 . However, this is only one example and is not limited thereto.

As shown in FIG. 5 , the shift registers 131a and 131b outputting scan signals from the gate-in-panel scan driver may be disposed in the non-display area NA of the display panel 150 . The shift registers 131a and 131b are arranged in the left and right non-display areas NA of the display panel 150 as an example, but are not limited thereto.

6 is a diagram showing a data driver having a gamma voltage generation circuit according to the first embodiment of the present invention, FIG. 7 is a diagram showing a main gamma voltage generator and a sub gamma voltage generator, and FIG. It is a diagram for explaining a part related to the shown RGB resistance array, and FIG. 9 is a diagram for explaining the advantages according to the first embodiment of the present invention.

As shown in FIG. 6, the data driver 140 includes a data receiver 141 (RX), a shift register 142 (Shift Register), a first latch 143 (1st Line Latch), and a second latch 144 (2nd Line Latch). Latch), a sub gamma voltage generator 145, a DA converter 146 (DA Converter), an output unit 147 (Multi-Channel Output), and the like.

The data receiver 141 receives digital data signals, control signals, clock signals, etc. output from the timing control unit 120 (TCON), and controls the device included in the data driver 140 based on this. It can play a role in generating signals. The shift register 142 may play a role of controlling the digital data signal transmitted from the timing controller 120 to be applied line by line.

The first latch 143 may perform a role of sampling and outputting a digital data signal under the control of the shift register 142 . The first latch 143 serves to sample the data signal and may be referred to as a sampling latch. The second latch 144 may serve to hold and output the digital data signal output from the first latch 143 . The second latch 144 serves to hold (maintain) the data signal and may be referred to as a holding latch.

The sub gamma voltage generator 145 may serve to generate a gamma reference voltage to be provided to the DA converter 146 in conjunction with the main gamma voltage generator 160 located outside the data driver 140. . At least one of the main gamma voltage generator 160 and the sub gamma voltage generator 145 may change the gamma voltage value (or gamma tap) in a programmable manner. The main gamma voltage generator 160 and the sub gamma voltage generator 145 may be collectively referred to as gamma voltage generator circuits 160 and 145 .

The DA conversion unit 146 may perform a role of converting the digital data signal output from the second latch 144 into an analog data voltage and outputting the converted data voltage. The DA converter 146 may convert a digital data signal into an analog data voltage based on the gamma reference voltage output from the gamma voltage generating circuits 160 and 145 . The output unit 147 may serve to output analog data voltages converted by the DA converter 146 through each output channel. Data voltages output from the output unit 147 may be applied to subpixels through data lines.

As shown in FIG. 7 , the main gamma voltage generator 160 includes a main resistance sequence (MRS) including a plurality of resistors, a main switch circuit (MSWP) including a plurality of switches and resistors, and a plurality of buffers. It may include a main buffer (MBUF), etc.

The main resistor series (MRS) serves to divide the voltage that can be obtained between the high voltage (V_high) and the low voltage (V_low) into multiple levels based on a plurality of resistors connected in series between the high voltage (V_high) and the low voltage (V_low). can do.

The main switch circuit MSWP includes at least one of voltages divided into a plurality of levels based on a plurality of switches (or further including resistors) connected to voltage division nodes of a plurality of resistors included in the main resistance array MRS. can play a role in selecting as the output voltage. The main switch circuit MSWP may vary a plurality of output voltages in response to register values of A bits (A is a natural number) supplied from the outside. The main switch circuit MSWP can be selected as an A-bit decoder.

The main buffer MBUF may play a role of buffering and outputting an output voltage output from the main switch circuit MSWP based on a plurality of buffers that are divided and connected to the output terminal of the main switch circuit MSWP. A plurality of output voltages output from the main buffer MBUF may be supplied to the sub gamma voltage generator 145 .

The sub gamma voltage generator 145 includes a red gamma circuit (RRS) including a plurality of resistors, a green gamma circuit (GRS) including a plurality of resistors, a blue gamma circuit (BRS) including a plurality of resistors, a first A sub switch circuit SSWP1 and a second sub switch circuit SSWP2 may be included.

The red gamma circuit RRS may serve to generate a gamma reference voltage for red based on a plurality of resistors connected in series between the high voltage V_high and the low voltage V_low. Voltage dividing nodes of the plurality of resistors included in the red gamma circuit RRS may be separately connected to a plurality of buffers included in the main buffer MBUF of the main gamma voltage generator 160 . The red gamma circuit RRS may include at least twice as many resistors Rx2N as resistors RxN included in the green gamma circuit GRS or the blue gamma circuit BRS.

The first sub-switch circuit SSWP1 is divided among the voltages divided into a plurality of levels based on a plurality of switches (or further including resistors) connected to the voltage division nodes of the plurality of resistors included in the red gamma circuit RRS. It can play a role in selecting at least one as an output voltage. The first sub switch circuit SSWP1 can vary a plurality of output voltages in response to register values of B bits (B being a natural number and a number smaller than A defining the number of bits of the main switch circuit) supplied from the outside. The first sub switch circuit SSWP1 may be selected as a B bit decoder.

The first sub-buffer SBUF1 serves to buffer and output the output voltage output from the first sub-switch circuit SSWP1 based on a plurality of buffers that are divided and connected to the output terminal of the first sub-switch circuit SSWP1. can A plurality of output voltages output from the first sub-buffer SBUF1 may be supplied to the green gamma circuit GRS.

The green gamma circuit (GRS) may serve to generate a gamma reference voltage for green based on a plurality of resistors. Voltage divider nodes of a plurality of resistors included in the green gamma circuit GRS may be separately connected to a plurality of buffers included in the first sub buffer SBUF1. The green gamma circuit GRS may include resistors R×N that are at least two times smaller than the resistors R×2N included in the red gamma circuit RRS.

The second sub-switch circuit SSWP2 is divided among the voltages divided into a plurality of levels based on a plurality of switches (or further including resistors) connected to the voltage division nodes of the plurality of resistors included in the red gamma circuit RRS. It can play a role in selecting at least one as an output voltage. The second sub switch circuit SSWP2 can vary a plurality of output voltages in response to register values of B bits (B being a natural number and a number smaller than A defining the number of bits of the main switch circuit) supplied from the outside. The second sub switch circuit SSWP2 may be selected as a B-bit decoder.

The second sub-buffer SBUF2 serves to buffer and output the output voltage output from the second sub-switch circuit SSWP2 based on a plurality of buffers that are divided and connected to the output terminal of the second sub-switch circuit SSWP2. can A plurality of output voltages output from the second sub buffer SBUF2 may be supplied to the blue gamma circuit BRS.

The blue gamma circuit (BRS) may serve to generate a gamma reference voltage for blue based on a plurality of resistors. Voltage dividing nodes of the plurality of resistors included in the blue gamma circuit BRS may be separately connected to a plurality of buffers included in the second sub-buffer SBUF2. The blue gamma circuit BRS may include the same number of resistors R×N as the resistors R×N included in the green gamma circuit GRS. Accordingly, the blue gamma circuit BRS and the green gamma circuit GRS are equally arranged from the first stage resistor array 1st to the Mth stage resistor array Mth and can generate the same output voltage. However, the blue gamma circuit BRS may include fewer resistors than the green gamma circuit GRS.

As shown in FIGS. 7 and 8 , the green gamma circuit GRS and the blue gamma circuit BRS may have a subordinate connection relationship to the red gamma circuit RRS. The red gamma circuit (RRS) may be implemented to have a higher number of bits than the green gamma circuit (GRS) and the blue gamma circuit (BRS). On the other hand, the green gamma circuit (GRS) and the blue gamma circuit (BRS) may have the same number of bits. However, the number of bits of the green gamma circuit (GRS) may be implemented higher than that of the blue gamma circuit (BRS).

In the first embodiment, the green gamma circuit (GRS) and the blue gamma circuit (BRS) have a connection relationship subordinate to the red gamma circuit (RRS), so that the green gamma circuit (GRS) and the blue gamma circuit (BRS) are connected to the red gamma circuit (RRS). In the case of not having a finer voltage step than the circuit RRS, it may be selected for circuit simplification.

As shown in FIG. 9 , according to the first embodiment of the present invention, the gamma voltage generator circuits 160 and 145 are divided into a main gamma voltage generator 160 and a sub gamma voltage generator 145, among which A part of the sub-gamma voltage generator 145 may be implemented inside the data drivers 140A to 140C.

As a result, the first embodiment of the present invention simplifies the configuration of the gamma voltage generation circuit when implementing a display device requiring RGB independent gamma, such as the red, green, and blue gamma voltage generation circuits 160_R, 160_G, and 160_B (eg : Simplify the output channel of the gamma voltage generating circuit). In addition, as the configuration of the gamma voltage generating circuit is simplified, the wiring layout and processes required for this may be simplified by reducing the complexity of wirings disposed outside the data drivers 140A to 140C.

Hereinafter, other embodiments of the present invention will be described, focusing on new or changed configurations to avoid duplication of description. That is, the part related to the overlapping configuration refers to the first embodiment.

10 is a diagram showing a main gamma voltage generator and a sub gamma voltage generator according to a second embodiment of the present invention, FIG. 11 is a diagram for explaining parts related to the differential amplifier shown in FIG. 10, and FIG. 12 is It is a drawing for explaining the advantages according to the second embodiment of the present invention.

As shown in FIG. 10 , the sub gamma voltage generator 145 may serve to generate a gamma reference voltage in conjunction with the main gamma voltage generator 160 . Since the main gamma voltage generator 160 may have the same configuration as the first embodiment, refer to the first embodiment.

The sub gamma voltage generator 145 includes a red gamma circuit (RRS) including a plurality of resistors, a green gamma circuit (GRS) including a plurality of resistors, a blue gamma circuit (BRS) including a plurality of resistors, and a sub resistor. A column SRS, a sub switch circuit SSWP, a first differential amplifier DAMP1 and a second differential amplifier DAMP2, and the like may be included.

The green gamma circuit (GRS) may serve to generate a gamma reference voltage for green based on a plurality of resistors. Dividing nodes of a plurality of resistors included in the green gamma circuit GRS may be separately connected to a plurality of buffers included in the main buffer MBUF. The green gamma circuit (GRS) may have the same number of resistors (R×N) included in the red gamma circuit (RRS) or the blue gamma circuit (BRS).

The sub-switch circuit SSWP is at least one of voltages divided into a plurality of levels based on a plurality of switches (or further including resistors) connected to voltage division nodes of a plurality of resistors included in the red gamma circuit RRS. can play a role in selecting as the output voltage. The sub switch circuit SSWP can vary a plurality of output voltages in response to register values of B bits (B is a natural number and is smaller than A defining the number of bits of the main switch circuit) supplied from the outside.

The sub-resistor sequence SRS is a voltage that can be obtained between the second high voltage V_high2 and the second low voltage V_low2 based on a plurality of resistors connected in series between the second high voltage V_high2 and the second low voltage V_low2. can play a role in distributing to multiple levels. The second high voltage V_high2 may be selected as a positive voltage, and the second low voltage V_low2 may be selected as a negative voltage. The level of the second high voltage V_high2 may be equal to or lower than the level of the high voltage V_high applied to the main resistance array MRS. Also, the level of the second low voltage V_low2 may be lower than the level of the low voltage V_low applied to the main resistor array MRS.

The sub-switch circuit SSWP has at least one of voltages divided into a plurality of levels based on a plurality of switches (or further including resistors) connected to voltage division nodes of a plurality of resistors included in the sub-resistor array SRS. can play a role in selecting as the output voltage. The sub switch circuit SSWP can vary a plurality of output voltages in response to register values of B bits (B is a natural number and is smaller than A defining the number of bits of the main switch circuit) supplied from the outside.

The sub switch circuit SSWP has a first positive voltage output terminal P1 to an Mth positive voltage output terminal Pm capable of outputting a first positive voltage to an Mth positive voltage and a first negative voltage It may include a first negative voltage output terminal (N1) to an M-th negative voltage output terminal (Nm) capable of outputting the Mth negative voltage. As such, the sub switch circuit SSWP may output a plurality of positive voltages and a plurality of negative voltages based on the ground voltage transmitted through the ground line GND.

The first differential amplifier DAMP1 may include a plurality of differential amplifiers. The first differential amplifier DAMP1 increases or decreases the voltage based on the difference (voltage difference) between the voltage output from the sub switch circuit SSWP and the voltage output from the main buffer MBUF to generate and vary multiple output voltages. can do. The plurality of differential amplifiers included in the first differential amplifier DAMP1 have first input terminals respectively connected to a plurality of positive voltage output terminals included in the sub switch circuit SSWP, and are included in the main buffer MBUF. Second input terminals may be respectively connected to a plurality of buffers. For example, in the 1-1 differential amplifier located in the first stage (1st), the first input terminal is connected to the first positive voltage output terminal (P1) of the sub switch circuit (SSWP), and the main buffer (MBUF) A second input terminal may be connected to the first buffer included in . And the 1st-2nd differential amplifier located in the 2nd terminal (2nd) has a first input terminal connected to the second positive voltage output terminal (P2) of the sub switch circuit (SSWP) and is included in the main buffer (MBUF). A second input terminal may be connected to the second buffer.

The red gamma circuit (RRS) may serve to generate a gamma reference voltage for red based on a plurality of resistors. Dividing nodes of the plurality of resistors included in the red gamma circuit RRS may be separately connected to output terminals of the plurality of differential amplifiers included in the first differential amplifier DAMP1. The red gamma circuit RRS may have the same number of resistors R×N as the number of resistors included in the green gamma circuit GRS or the blue gamma circuit BRS.

The second differential amplifier DAMP2 may include a plurality of differential amplifiers. The second differential amplification unit DAMP2 increases or decreases the voltage based on the difference (voltage difference) between the voltage output from the sub switch circuit SSWP and the voltage output from the main buffer MBUF to generate and change multiple output voltages. can do. The first input terminals of the plurality of differential amplifiers included in the second differential amplifier DAMP2 are respectively connected to the negative voltage output terminal included in the sub switch circuit SSWP, and the plurality of differential amplifiers included in the main buffer MBUF Second input terminals may be respectively connected to the buffers. For example, the 2-1 differential amplifier located in the first stage (1st) has a first input terminal connected to the first negative voltage output terminal (N1) of the sub switch circuit (SSWP), and the main buffer (MBUF) A second input terminal may be connected to the first buffer included in . Also, the 2-2 differential amplifier positioned at the second stage (2nd) has a first input terminal connected to the second negative voltage output terminal (N2) of the sub switch circuit (SSWP) and is included in the main buffer (MBUF). A second input terminal may be connected to the second buffer.

The blue gamma circuit (BRS) may serve to generate a gamma reference voltage for blue based on a plurality of resistors. Dividing nodes of the plurality of resistors included in the blue gamma circuit BRS may be separately connected to output terminals of the plurality of differential amplifiers included in the second differential amplifier DAMP2. The blue gamma circuit (BRS) may have the same number of resistors (R×N) included in the red gamma circuit (RRS) or the green gamma circuit (GRS).

As shown in FIGS. 10 and 11, the differential amplifiers DAMP included in the first differential amplifier DAMP1 and the second differential amplifier DAMP2 are V0 = V2 - V1 and V0 under the condition that all resistances are the same. The same formula can be satisfied.

The differential amplifier (DAMP) outputs the output terminal (V0) according to the voltage difference between the first voltage (V1) input through the first input terminal (-) and the second voltage (V2) input through the second input terminal (+). ), the voltage to be output can be increased or decreased. The differential amplifier DAMP adds a voltage when the difference between the first voltage V1 and the second voltage V2 corresponds to a negative value, but may subtract a voltage when the difference between the first voltage V1 and the second voltage V2 corresponds to a positive value.

In the second embodiment, the voltage difference between the red gamma circuit (RRS), the green gamma circuit (GRS), and the blue gamma circuit (BRS) is measured to generate the gamma reference voltage of the green gamma circuit (GRS) and the blue gamma circuit (BRS). It uses the input/output characteristics of a differential amplifier (DAMP) that can be added or subtracted.

As shown in FIG. 12, the second embodiment of the present invention is a method capable of implementing a red gamma reference voltage value (Red) and a blue gamma reference voltage value (Blue) based on the green gamma reference voltage value (Green). can be chosen On the other hand, when using the differential method as in the second embodiment, the step of 1 LSB can be "V_high / 2 ^A > (V_hgih2 - Vlow2) / 2 ^B , and A = B that determines the resolution DA conversion when satisfied There is an advantage that the required resolution of the negative can be lowered (the size of the IC can be reduced because the step of 1 LSB can be implemented small).

13 is a diagram showing a main gamma voltage generator and a sub gamma voltage generator according to a third embodiment of the present invention, and FIG. 14 is a diagram for explaining a part related to data output through the serial interface shown in FIG. 13 .

As shown in FIG. 13 , the sub gamma voltage generator 145 may serve to generate a gamma reference voltage in conjunction with the main gamma voltage generator 160 . Since the configuration of the main gamma voltage generator 160 and the configuration of the sub gamma voltage generator 145 can be implemented identically to those of the second embodiment except for the newly added serial interface, this is see

The main gamma voltage generator 160 includes a main resistor array (MRS) including a plurality of resistors, a main switch circuit (MSWP) including a plurality of switches and resistors, a main buffer (MBUF) including a plurality of buffers, a plurality of It may include a first switch circuit (SWA) including a switch, a second switch circuit (SWB) including a plurality of switches, a main register (MREG) and a data transmission unit (GTX).

The first switch circuit SWA includes a plurality of switches that are divided and connected between the plurality of buffers included in the main buffer MBUF and the plurality of output channels 1Ch to MCh included in the main gamma voltage generator 160. can do. The first switch circuit SWA may play a role of controlling the voltage output from the main buffer MBUF to be output or not to be output through the plurality of output channels 1Ch to MCh.

The second switch circuit (SWB) distinguishes between a plurality of output channels (1Ch to MCh) included in the main gamma voltage generator 160 and a plurality of data terminals (D1 to Dm) included in the data transmission unit (GTX). It may include a plurality of switches connected to each other. The second switch circuit (SWB) may perform a role of controlling the voltage output through the plurality of output channels (1Ch to MCh) to be transferred to or not transmitted to the data transmission unit (GTX).

In the data transmitter GTX, a plurality of data terminals D1 to Dm are connected to a plurality of switches included in the second switch circuit SWB, and a sub register SREG included in the sub gamma voltage generator 145 may have a communication interface (CLK) capable of data transmission. When the first switch circuit (SWA) and the second switch circuit (SWB) are turned on, the data transmission unit (GTX) receives voltages output through a plurality of output channels (1Ch to MCh) and divides them into at least one channel. and transfer it to the sub register (SREG). The data transmission unit GTX may convert voltages output through a plurality of output channels 1Ch to MCh into data based on register values stored in the main register MREG and transmit the data.

The sub gamma voltage generator 145 includes a red gamma circuit (RRS) including a plurality of resistors, a green gamma circuit (GRS) including a plurality of resistors, a blue gamma circuit (BRS) including a plurality of resistors, and a sub resistor. column (SRS), sub switch circuit (SSWP), first differential amplifier (DAMP1), second differential amplifier (DAMP2), sub register (SREG), protection circuit (DD), and data receiver (GRX) can include

The data receiver GRX may have a plurality of data terminals D1 to Dm connected to a plurality of output channels 1Ch to MCh. The data receiving unit GRX may serve to transmit voltages transmitted through the plurality of output channels 1Ch to MCh to the sub register SREG.

The sub register SREG may be connected to the data transmission unit GTX based on the communication interface CLK, input terminals connected to the data reception unit GRX, and output terminals connected to the sub switch circuit SSWP. The sub register SREG may serve to output a register value capable of controlling the sub switch circuit SSWP based on the voltage received from the data receiver GRX and the data supplied from the data transmitter GTX. there is.

As shown in FIGS. 13 and 14 , in the third embodiment, a serial interface capable of exchanging data in a communication method may be implemented between the main gamma voltage generator 160 and the sub gamma voltage generator 145. there is. According to the third embodiment, in the step of applying the logic voltage (3.3V) prior to the high voltage (V_high) required for the main resistor array (MRS), the voltage output from the main gamma voltage generation unit 160 is converted into data to form a sub-gamma voltage. It can be transmitted to the generator 145.

The data transmission unit GTX has a register value for applying the green gamma reference voltage (1Ch Green) output through the first channel to the red gamma reference voltage (1Ch Red) of the first channel based on the main register (MREG) and After being converted into data in the form of a register value to be applied to the green gamma reference voltage (1Ch Blue) of the first channel, it can be transmitted to the sub gamma voltage generator 145 through the communication interface CLK. The data transmitter GTX may sequentially prepare data from the first channel to the Mth channel in this way and transmit the data to the sub gamma voltage generator 145 . Also, the sub gamma voltage generator 145 receiving the data of the Mth channel from the first channel can control the sub switch circuit SSWP based on this.

As described above in the first embodiment, the gamma voltage generating circuits 160 and 145 according to the present invention can change the gamma voltage value (or gamma tap) in a programmable manner. In the second embodiment, the main switch circuit MSWP of the main gamma voltage generator 160 and the sub switch circuit SSWP of the sub gamma voltage generator 145 are separated from each other. As a result, the second embodiment can independently control their gamma voltage values (or gamma taps), but separate control systems and signal lines for separately controlling the main switch circuit (MSWP) and the sub switch circuit (SSWP). etc are needed.

However, in the third embodiment, although the main switch circuit (MSWP) of the main gamma voltage generator 160 and the sub switch circuit (SSWP) of the sub gamma voltage generator 145 are separated from each other, data is transmitted through a communication method. can receive As a result, the third embodiment can simplify a separate control system and signal line for controlling the sub switch circuit SSWP while having the same advantages as the second embodiment. In addition, the gamma can be relatively freely changed according to the characteristics of the display device through the control of the main switch circuit MSWP of the main gamma voltage generator 160 and the sub switch circuit SSWP of the sub gamma voltage generator 145. .

As described above, the present invention has an effect of simplifying the configuration of the circuit (eg, simplifying the output channel of the gamma voltage generating circuit) by integrating (internalizing) some of the circuits included in the gamma voltage generating circuit into the data driver. In addition, the present invention has an effect of simplifying wiring layout and processes required therefor by simplifying the configuration of a gamma voltage generating circuit when implementing a display device expressing an image based on an RGB independent gamma reference voltage. In addition, the present invention has an effect of providing a programmable gamma voltage generation circuit capable of simplifying a control system and signal lines and relatively freely changing gamma to suit the characteristics of a display device.

160: main gamma voltage generator MRS: main resistance series
MSWP: main switch circuit MBUF: main buffer
RRS: red gamma circuit GRS: green gamma circuit
BRS: blue gamma circuit SSWP1: first sub switch circuit
SSWP2: 2nd sub switch circuit DAMP1: 1st differential amplifier
DAMP2: 2nd differential amplifier

Claims (10)

a display panel displaying an image;
a data driver supplying a data voltage to the display panel; and
a main gamma voltage generator supplying voltages divided into multiple levels from outside the data driver; and generating a gamma reference voltage for red inside the data driver based on the voltages supplied from the main gamma voltage generator. a gamma voltage generation circuit including a sub-gamma voltage generator including a red gamma circuit, a green gamma circuit generating a gamma reference voltage for green, and a blue gamma circuit generating a gamma reference voltage for blue;
The green gamma circuit divides the voltages supplied from the main gamma voltage generator to generate the gamma reference voltage for red;
The red gamma circuit and the blue gamma circuit add or subtract a voltage difference between voltages supplied from the main gamma voltage generator and voltages generated from an internal circuit to obtain the gamma reference voltage for red and the gamma reference voltage for blue. Each light emitting display device generated. According to claim 1,
The green gamma circuit, the red gamma circuit, and the blue gamma circuit
A light emitting display device including the same number of resistors. According to claim 2,
The main gamma voltage generator and the sub gamma voltage generator
A light emitting display device including a main switch circuit and a sub switch circuit for selecting at least one of voltages divided into a plurality of levels based on a plurality of switches that are divided and connected to voltage dividing nodes of a plurality of resistors. According to claim 3,
The red gamma circuit and the blue gamma circuit
and generating the red gamma reference voltage and the blue gamma reference voltage, respectively, by adding or subtracting a voltage difference between voltages supplied from the main gamma voltage generator and voltages generated from the sub switch circuit. According to claim 4,
The red gamma circuit
a first differential amplifier including a plurality of differential amplifiers for adding or subtracting a voltage difference between voltages supplied from the main gamma voltage generator and positive voltages output from the sub switch circuit;
The blue gamma circuit
and a second differential amplifier including a plurality of differential amplifiers for adding or subtracting a voltage difference between voltages supplied from the main gamma voltage generator and negative voltages output from the sub switch circuit. According to claim 5,
The main gamma voltage generator and the sub gamma voltage generator
A light emitting display device including a communication interface for exchanging data. According to claim 6,
The main gamma voltage generator
A main register in which register values are stored;
A data transmission unit configured to convert voltages output through the main switch circuit into data based on the register value and transmit the data;
The sub gamma voltage generator
a data receiving unit receiving voltages supplied from the main gamma voltage generating unit;
and a sub-resistor outputting a register value for controlling the sub-switch circuit based on the voltages supplied from the data receiver and the data supplied from the data transmitter. a main gamma voltage generator including a main switch circuit for selecting at least one of the voltages divided into a plurality of levels based on a plurality of switches connected to voltage dividing nodes of a plurality of resistors; and
a sub-gamma voltage generator including a sub-switch circuit for selecting at least one of voltages divided into a plurality of levels based on a plurality of switches that are divided and connected to voltage dividing nodes of a plurality of resistors;
The sub gamma voltage generator
A red gamma circuit for generating a gamma reference voltage for red based on the voltages supplied from the main gamma voltage generator, a green gamma circuit for generating a gamma reference voltage for green, and a blue gamma circuit for generating a gamma reference voltage for blue do,
The green gamma circuit divides the voltages supplied from the main gamma voltage generator to generate the gamma reference voltage for red;
The red gamma circuit and the blue gamma circuit add or subtract a voltage difference between voltages supplied from the main gamma voltage generator and voltages generated from the sub switch circuit to obtain the gamma reference voltage for red and the gamma reference for blue. A gamma voltage generation circuit for generating voltages respectively. According to claim 8,
The red gamma circuit
a first differential amplifier including a plurality of differential amplifiers for adding or subtracting a voltage difference between voltages supplied from the main gamma voltage generator and positive voltages output from the sub switch circuit;
The blue gamma circuit
and a second differential amplifier including a plurality of differential amplifiers for adding or subtracting a voltage difference between voltages supplied from the main gamma voltage generator and negative voltages output from the sub switch circuit. According to claim 9,
The main gamma voltage generator
A main register in which register values are stored;
A data transmission unit configured to convert voltages output through the main switch circuit into data based on the register value and transmit the data;
The sub gamma voltage generator
a data receiving unit receiving voltages supplied from the main gamma voltage generating unit;
and a sub-resistor outputting a register value for controlling the sub-switch circuit based on the voltages supplied from the data receiver and the data supplied from the data transmitter.

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