KR20160033827A - Apparatus and method of data interface of display device - Google Patents

Abstract

The present invention relates to a data interface apparatus of a display device and a method thereof. The data interface apparatus includes a transmission part which inserts a clock signal and control data into input digital video data and transmits it; and a receiving part which generates an internal clock based on the clock signal received by data line pairs connected to the transmission part, and then restores the digital video data. The transmission part can transfer digital video data of a specific color which has a transmission value, ′0′ among the digital video data having a first color to a forth color.

Description

TECHNICAL FIELD [0001] The present invention relates to a data interface device and a method of a display device,

The present invention relates to a display device, and more particularly, to a data interface device and method of a display device.

2. Description of the Related Art Flat panel displays for displaying images using digital data include a liquid crystal display (LCD) using liquid crystal, a plasma display panel (PDP) using an inert gas discharge, an organic light emitting diode An organic light emitting diode (OLED) display device, and the like.

In general, flat panel displays use various data interface methods to reduce signal transmission lines during data transmission / reception and to reduce EMI and power consumption during data transmission at high speed. For example, the applicant of the present application has developed a clocked embedded (" clock ") circuit that can minimize the number of wires between the timing controller and the source drive ICs and stabilize signal transmission by connecting the timing controller and source drive ICs in a point- Clock Embedded "interface, a so-called" EPI (Embedded point to point interface) "is disclosed in Korean Patent Publication No. 10-2010-0068938 (2010-06-24), Korean Patent Publication No. 10-2010-0068936 24, Korean Patent Publication No. 10-2010-0073718 (2010-07-01).

On the other hand, in recent flat panel display devices, the drive frequency is increasing with increasing resolution and size, and a faster data transfer rate is required. However, there is a limit frequency at which the EPI can be driven at a high speed. When data exceeding the limit frequency is transmitted, there is a fear of data loss and may cause unstable driving of the flat panel display.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a data interface apparatus and method of a display apparatus capable of lowering a transmission frequency of data and reducing power consumption by transition of data do.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

According to an aspect of the present invention, there is provided a data interface device for a display device, including: a transmitter for transmitting clock signals and control data to input digital video data; And a reception unit for generating an internal clock based on the clock signal received through the pair of data lines connected to the transmission unit and then restoring the digital video data; The transmitter may encode digital video data of a specific color having a transmission value of '0' among the digital video data having the first color to the fourth color into 2-bit indication data (Indicate data) and transmit the encoded data.

According to another aspect of the present invention, there is provided a data interface method for a display device, including: searching for a specific color having a transmission value of '0' among image data of four colors inputted by a transmission unit; The transmitting unit generating 2-bit instruction data corresponding to the specific color; Converting the image data of the three colors excluding the specific color and the instruction data into a differential signal pair and transmitting the differential signal pair; Receiving the difference signal pair from the transmission unit and generating image data of the specific color having a data value of '0' according to the instruction data; And sampling the image data of the specific color generated by the receiving unit and the image data of the remaining three colors.

According to the solution of the above-mentioned problems, the present invention has the following effects.

In the present invention, the timing controller searches for a specific color having a transmission value of '0' among data of four colors, encodes data corresponding to the specific color into 2-bit indicative data, and transmits the data. The source driver IC decodes the instruction data provided from the timing controller to generate and recover data of the specific color having a data value of '0'. Accordingly, the present invention can reduce the transmission amount of digital video data having four colors, and can reduce the transmission frequency of data by reducing the length of data transmission packets. In addition, since the transmission frequency of data is lowered in the present invention, power consumption due to transition of data can be reduced.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below, or may be apparent to those skilled in the art from the description and the description.

1 is a configuration diagram of an OLED display device according to an embodiment of the present invention.
2 is a block diagram showing a transmitter of the timing controller (TCON) and a receiver of the source drive IC (SIC).
3 is a difference signal pair showing a case of transmitting image data of four colors according to the conventional EPI protocol.
4 is a difference signal pair showing a case of transmitting four-color image data according to the present invention.
5 is a configuration diagram of the data generating unit 21 shown in FIG.
6 is a configuration diagram of the sampling circuit 27 shown in FIG.
FIG. 7 is a flowchart showing a step-by-step description of the data interface method of the display device according to the embodiment.

The meaning of the terms described herein should be understood as follows. The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms. It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one. The term "on" means not only when a configuration is formed directly on top of another configuration, but also when a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of a data interface apparatus and method of a display apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

The display device of the present invention may be applied to a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting display (OLED), an electrophoresis display (EPD), and the like. Note that in the following embodiments, an OLED display device is mainly described as an example of a flat panel display device, but it should be noted that the display device of the present invention is not limited to an OLED display device.

Further, the timing controller and the source drive IC of the present invention can be applied to a semiconductor integrated circuit device, (Clock Embedded) interface proposed in Patent Document 10-2010-0073718 (2010-07-01) or the like. Hereinafter, the clock-embedded interface proposed in the above documents is defined as an embedded point-to-point interface (EPI) protocol.

1 is a configuration diagram of an OLED display device according to an embodiment of the present invention.

1, an OLED display according to an exemplary embodiment of the present invention includes a display panel PNL, a timing controller TCON, one or more source drive ICs SIC # 1 to SIC # 4, (GIC).

The display panel PNL includes a plurality of gate lines GL and a plurality of data lines DL intersecting with each other. This display panel PNL is defined by a plurality of pixels arranged in a matrix form by the intersection structure of the data lines DL and the gate lines GL. In order to improve luminance and reduce power consumption, a large number of pixels are required to display red (R), green (G), and blue (B) as the first to third colors, (W).

Each pixel includes an OLED and a pixel driving circuit for driving the OLED.

The pixel driving circuit includes a switching TFT, a driving TFT, and a capacitor. The switching TFT charges the capacitor with the data voltage supplied from the data line DL in response to the scan pulse supplied from the gate line GL. The driving TFT controls the amount of current supplied to the OLED according to the data voltage charged in the capacitor to control the amount of light emitted from the OLED.

The pixel driving circuit may further include a compensation circuit for compensating a threshold voltage and a mobility of the driving TFT or a deviation of a threshold voltage and a mobility of the OLED. The compensation circuit includes a plurality of TFTs and a compensation capacitor to compensate for the threshold voltage and mobility of the driving TFT or the deviation of the threshold voltage and mobility of the OLED. The compensation circuit may be an internal compensation circuit that operates within a period in which the display panel displays an image, or an external compensation circuit that operates during a blank period in which the display panel does not display an image. That is, the compensation circuit may be any of an internal compensation circuit or an external compensation circuit designed by the present applicant.

On the other hand, in Fig. 1, a solid line is a pair of data wires through which signals such as a clock training pattern signal, control data, and video data of an input video are transmitted. Also, in Fig. 1, the dotted line is a lock feedback signal wiring connected between the last source drive IC (SIC # 4) and the timing controller (TCON).

The timing controller TCON receives vertical and horizontal synchronizing signals Vsync and Hsync from an external host system not shown via an interface such as a Low Voltage Differential Signaling (LVDS) interface and a TMDS (Transition Minimized Differential Signaling) A data enable signal DE, and a main clock signal CLK. The timing controller TCON is connected in series to each of the source drive ICs (SIC # 1 to SIC # 4) through a pair of data wirings.

The timing controller TCON operates as a transmitter of the data interface device so as to satisfy the EPI protocol described above. In particular, the timing controller (TCON) of the present invention is a timing controller (TCON) of the present invention, in which the digital video data RGB (RGBW) having a transmission value of '0' among the digital video data RGBW having the first to fourth colors or G or B or W) is encoded with 2-bit Indicate data (ID) and then transmitted to lower the transmission frequency of the data and reduce the power consumption by the transition of data have. Specifically, in the embodiment of the present invention, since the display panel PNL has pixels displaying white W as the color of the fourth color, the timing controller TCON supplies the source drive ICs SIC # The digital video data RGBW transmitted to the SIC # 4 has the first to fourth colors RGBW. In this case, since the amount of data increases due to the addition of the fourth color W, a higher data transfer rate may be required. However, according to the present invention, digital video data (R or (RGBW)) of a specific color having a transmission value of '0' among the digital video data RGBW having the first to fourth colors G or B or W) is encoded with 2-bit instruction data (ID) and then transmitted, thereby lowering the transmission frequency of the data. This will be described later in detail with reference to Figs. 2 to 5.

The timing controller TCON controls the operation timings of the source drive ICs SIC # 1 to SIC # 4 and the gate drive IC (GIC). The timing controller TCON supplies a clock training pattern signal, control data, digital video data RGBW of the input image to the source drive ICs SIC # 1 to SIC # 4 according to a new signal transmission standard defined by the EPI protocol. Etc. to a differential signal pair, and serially transmits the data to the source drive ICs (SIC # 1 to SIC # 4) via the data wire pair.

The timing controller TCON transmits a clock training pattern signal to the source drive ICs SIC # 1 to SIC # 4 when the lock signal LOCK inputted through the lock feedback signal wiring is at a low logic level, LOCK) is reversed to a high logic level, the control data and the digital video data (RGBW) of the input video are resumed. The lock signal LOCK fed back to the timing controller TCON is inverted to the low logic level only when the clock recovery circuit output of all the source drive ICs SIC # 1 to SIC # 4 is unlocked.

The source drive ICs (SIC # 1 to SIC # 4) operate as a receiver of the data interface device to satisfy the EPI protocol described above. In particular, the source drive ICs (SIC # 1 to SIC # 4) of the present invention decode 2-bit instruction data (ID) among the difference signal pairs provided from the timing controller (TCON) And restores the digital video data RGBW having the fourth color. This will be described in detail later with reference to FIG. 2 and FIG.

The source drive ICs SIC # 1 to SIC # 4 generate an output of the clock recovery circuit through clock training when a lock signal LOCK of a high logic level and a clock training pattern signal are inputted from the previous stage source drive IC . When the phase and frequency of the output of the source drive ICs SIC # 1 to SIC # 4 are locked and the clock and data recovery (CDR) function is stabilized, The drive IC sends a high logic level lock signal. On the other hand, when the CDR function of all the source drive ICs SIC # 1 to SIC # 4 is stabilized, the last source drive IC SIC # 6 supplies the lock signal LOCK of the high logic level through the lock- (TCON). A DC power supply voltage (VCC) of a high logic level is input to a lock signal input terminal of the first source drive ICs (SIC # 1).

The timing controller TCON receives control data and video data in which the EPI clock CLK is embedded after the high logic level lock signal LOCK from the last source drive IC SIC # SIC # 1 to SIC # 4). The control data includes source control data for controlling the output timing of the data voltage output from the source drive ICs (SIC # 1 to SIC # 4), the polarity of the data voltage, and the like. The control data may include gate control data for controlling the operation timing of the gate drive IC (GIC).

Each of the source drive ICs SIC # 1 to SIC # 4 may be connected to the data lines of the display panel PNL by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. The source drive ICs SIC # 1 to SIC # 4 receive a clock training pattern signal, control data, video data, and the like, each of which includes an EPI clock CLK through a pair of data lines. The CDR circuit of the source drive ICs (SIC # 1 to SIC # 4) inputs the EPI clock (CLK) to the clock recovery circuit to generate internal clocks. The clock recovery circuit generates internal clocks and a lock signal (LOCK) using a phase locked loop or a delay locked loop. The source drive ICs SIC # 1 to SIC # 4 sample the video data bits of the input image in accordance with the internal clock timing, and then convert the sampled RGBW bits into parallel data.

The source drive ICs (SIC # 1 to SIC # 4) decode the control data input through the pair of data lines by a code mapping method to recover the source control data and the gate control data. The source drive ICs SIC # 1 to SIC # 4 convert the video data of the input video into the positive / negative analog video data voltages in response to the restored source control data, . The source drive ICs SIC # 1 to SIC # 4 may transmit gate control data to one or more of the gate drive ICs (GICs).

The gate drive IC (GIC) may be connected to the gate lines GL of the display panel PNL through a TAP process or may be embedded on the TFT array substrate of the display panel PNL by a GIP (Gate In Panel) process . The gate drive IC (GIC) receives a gate pulse directly from the timing controller (TCON) or in response to gate control data received via the source drive ICs (SIC # 1 to SIC # 4) ).

2 is a block diagram showing a transmitter of the timing controller (TCON) and a receiver of the source drive IC (SIC).

2, the transmission unit of the timing controller TCON includes a data generation unit 21, a clock generation unit 22, a data conversion unit 23, and an output buffer unit 24. The receiver of the source drive IC (SIC) includes a receive buffer unit 25, a clock recovery unit 26, and a sampling unit 27.

The data generating unit 21 generates the control data based on the input sync signal SYNC, and outputs the sorted digital video data RGBW. Specifically, the data generating unit 21 arranges and outputs the digital video data RGBW of the input image according to the resolution of the display panel PNL from the host system through the LVDS interface or the TMDS interface. The data generation unit 21 generates control data including source control data and gate control data based on a synchronization signal SYNC input from the host system.

The data generating unit 21 transmits n (n is a natural number greater than 2) bits of the digital video data RGBW having the first to fourth colors, and when the transmission value is '0' The digital video data (R or G or B or W) of a specific color is encoded with 2-bit instruction data (ID) and output.

For reference, according to the EPI protocol, when the digital video data RGBW transmitted from the timing controller TCON to the source drive ICs SIC # 1 to SIC # 4 has the first color to the fourth color RGBW , And each digital video data (RGBW) can be transmitted by 10 bits (bits). In this case, as shown in Fig. 3, each of the difference signal pairs transmitted from the timing controller TCON transmits 20 bits of digital video data of two colors, and the difference signal pair is a total of 40 bits of digital video data . However, the digital video data RGBW having the first to fourth colors always have digital video data of a specific color (R or G or B or W) regardless of the pattern or gradation of the image to be displayed, '. Therefore, in the data interface device according to the conventional EPI protocol, the digital video data (R or G or B or W) of a specific color is transmitted even when the transmission value is '0', and the digital video data is transmitted / , Waste of data transmission efficiency.

4, the digital video data (R or G or B or W) of a specific color having a transmission value of '0' is encoded into 2-bit indication data And then transmits. In FIG. 4, the instruction data (ID) is outputted in the last order in the packet for transmitting the digital video data, but the order in which the instruction data (ID) is output is not limited to the present invention. In this case, one of the pair of difference signals transmitted from the timing controller TCON according to the present invention includes 10-bit data Data1 of the first color, 5-bit data Data3 of the third color, (ID) of the third color, and the remaining one-bit data (Data2) of the second color, the remaining five-bit data (Data3) of the third color, and the remaining one of the instruction data Can be transmitted. Therefore, each of the difference signal pairs of the present invention transmits 16 bits of digital video data and transmits a total of 32 bits of digital video data. As described above, according to the present invention, the transmission amount of the digital video data RGBW having the first to fourth colors can be reduced to 32 bits per 40 bits, thereby reducing the length of the data transmission packet. Therefore, the present invention can lower the transmission frequency of data and reduce the power consumption due to the transition of data.

5, the data generation unit 21 includes a search unit 32, an encoding unit 34, and a first memory 36. [

The retrieval unit 32 retrieves the digital video data (R or G or B or W) of a specific color whose transmission value is '0' among the inputted digital video data RGBW of the first to fourth colors And outputs the encoded signal ES according to the search result. To this end, the search unit 32 may refer to the first memory 36. As shown in Table 1, the first memory 36 corresponds to each of the first to fourth colors RGBW The above instruction data (ID) can be mapped.

The encoding unit 34 converts the digital video data (R or G or B or W) of the specific color into 2-bit indication data (ID) according to the encoding signal ES provided from the search unit 32 And outputs the digital video data (Data1, Data2, Data3) of the remaining colors excluding the instruction data (ID) and the digital data of the specific color.

The clock generator 22 frequency-divides a sync signal SYNC input from the outside, for example, a dot clock, and outputs the EPI clock CLK.

The data converter 23 embeds control data and EPI clocks CLK between the digital video data Data supplied from the data generator 21 and outputs the embeded data.

The output buffer 24 converts the data output from the data converter 23 into a differential signal pair and transmits the differential signal pair to the source drive IC (SIC).

The receive buffer 25 receives the difference signal pair transmitted from the timing controller TCON through the data wire pair.

The clock recovery circuit 26 restores the internal clock from the received EPI clock CLK.

The sampling circuit 27 samples each of the control data and the digital video data according to an internal clock. In particular, the sampling unit 27 generates digital video data of the specific color whose data value is '0' according to the instruction data, and restores the digital video data RGBW having the first color to the fourth color do.

To this end, the sampling circuit 27 includes a determination unit 42, a decoding unit 44, and a second memory 46 as shown in FIG.

The determination unit 42 determines the digital video data of a specific color having a data value of 0 by analyzing the instruction data ID and determines whether the data input through the reception buffer unit 25 is digital Video data, and outputs a decoded signal DS according to the determined result. For this, the determination unit 42 may refer to the second memory 46. As shown in Table 2, the second memory 46 stores, for each of the values of the instruction data (ID) The color of each of the data input through the reception buffer unit can be mapped. For example, when the instruction data ID is '10', the determination unit 42 determines that the first through third data Data1, Data2, and Data3 input through the reception buffer unit 25 are white (W), red (R), and green (G), and the video data of blue (B) is determined to be '0'.

The decoding unit 44 reconstructs the digital video data having the first to fourth colors according to the decoding signal DS provided from the determination unit, and then samples the reconstructed data. For example, when the instruction data ID is '10', the decoding unit 44 decodes the decoded signal DS according to the decoded signal DS to determine that it is white (W), red (R), green (G) And samples each of the first to third data (Data1, Data2, Data3). The decoding unit 44 generates blue (B) video data having a data value of '0', and then samples the video data.

FIG. 7 is a flowchart showing a step-by-step description of the data interface method of the display device according to the embodiment.

Hereinafter, the data interface method of the display apparatus will be described with reference to Figs. 2 and 5 to 7, in the embodiment of the present invention.

In step S10, the timing controller TCON searches for a specific color whose transmission value is '0' among the data of four colors. Specifically, the searching unit 32 of the timing controller TCON selects the digital video data R (RGBW) of a specific color whose transmission value is '0' among the input digital video data RGBW of the first to fourth colors or G or B or W), and outputs the encoded signal ES according to the search result.

In step S20, the timing controller TCON generates 2-bit instruction data (ID) corresponding to the specific color. Specifically, the encoding unit 34 of the timing controller TCON outputs digital video data (R or G or B or W) of the specific color according to the encoding signal ES provided from the search unit 32 And is encoded into 2-bit instruction data (ID).

In step S30, the timing controller TCON transmits data of three colors excluding the specific color and the instruction data (ID). More specifically, the data converter 23 of the timing controller TCON supplies control data and EPI clocks between the three-color data and the instruction data (ID) except for the specific color provided from the data generator 21, (CLKs) are embedded. The output buffer 24 converts the data output from the data converter 23 into a differential signal pair and transmits the differential signal pair to the source drive IC (SIC).

In step S40, the source drive IC (SIC) receives the difference signal pair through the data wire pair. The source driver IC SIC generates data of the specific color having a data value of '0' according to the instruction data (ID), and restores and samples the generated data of the specific color and the remaining three colors of data . To this end, the source drive IC (SIC) may use the determination unit 42, the decoding unit 44, and the second memory 46.

As described above, in the present invention, the timing controller searches a specific color having a transmission value of '0' among data of four colors, encodes data corresponding to the specific color into 2-bit indicating data, and transmits the data. The source driver IC decodes the instruction data provided from the timing controller to generate and recover data of the specific color having a data value of '0'. Accordingly, the present invention can reduce the transmission amount of digital video data having four colors, and can reduce the transmission frequency of data by reducing the length of data transmission packets. In addition, since the transmission frequency of data is lowered in the present invention, power consumption due to transition of data can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of. Therefore, the scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present invention.

21: Data generator 22: Clock generator
23: data conversion unit 24: output buffer unit
25: receiving buffer unit 26: clock recovery unit
27: Sampling part ID: indicating data

Claims (8)

A transmitter for inserting and transmitting clock signals and control data to the input digital video data; And
And a receiver for generating an internal clock based on the clock signal received through the pair of data lines connected to the transmitter and for restoring the digital video data;
The transmitting unit encodes digital video data of a specific color having a transmission value of '0' among the digital video data having the first to fourth colors by encoding the data of the display device into two-bit indication data (Indicate data) Interface device. The method according to claim 1,
The transmitting unit
A data generating unit for generating the control data based on the input synchronization signal, and sorting and outputting the input digital video data;
A clock generator for generating the clock signal based on the synchronization signal;
A data converter for inserting the control data and the clock signal into digital video data provided from the data generator and outputting the data; And
And an output buffer unit for converting the data output from the data conversion unit into a differential signal pair and transmitting the data signal pair;
Wherein the data generating unit encodes each of the digital video data having the first to fourth colors by n bits (n is a natural number greater than 2), encodes the digital video data of a specific color into 2-bit instruction data, The data interface device of the display device. 3. The method of claim 2,
The data generation unit
A search unit for searching digital video data of a specific color having a transmission value of '0' among the input digital video data of the first to fourth colors and outputting an encoded signal according to the search result;
And encoding the digital video data of the specific color into 2-bit indication data in accordance with the encoding signal provided from the retrieving unit to sort the digital video data of the remaining colors excluding the instruction data and the digital data of the specific color, ; And
And a first memory to which the instruction data corresponding to each of the first to fourth colors are mapped. The method of claim 3,
The receiving unit
A reception buffer unit receiving the difference signal pair provided from the transmission unit through the data line pair;
A clock recovery unit for recovering the clock signal received through the normal reception buffer unit into an internal clock; And
And a sampling unit for sampling the control data and the digital video data according to an animation internal clock;
Wherein the sampling unit generates the digital video data of the specific color whose data value is '0' according to the instruction data, and restores the digital video data of the first color to the fourth color. 5. The method of claim 4,
The sampling unit
Determines the digital video data of a specific color whose data value is '0' by analyzing the instruction data, determines which color digital video data the data input through the reception buffer unit is, and then outputs the decoded signal And outputting
A decoding unit for reconstructing the digital video data having the first to fourth colors according to the decoding signal provided from the determination unit and then sampling the reconstructed data; And
And a second memory in which colors of respective data input through the reception buffer unit are mapped in correspondence with the values of the instruction data. 6. The method according to any one of claims 1 to 5,
Wherein the transmitting unit is incorporated in a timing controller, and the receiving unit is embedded in a source drive IC. 6. The method according to any one of claims 1 to 5,
Wherein the receiving unit generates a data voltage according to the restored digital video data and then supplies the generated data voltage to a liquid crystal display panel or an organic light emitting diode display panel. Searching for a specific color whose transmission value is '0' among the image data of four colors inputted by the transmission unit;
The transmitting unit generating 2-bit indicative data corresponding to the specific color;
Converting the image data of the three colors excluding the specific color and the instruction data into a differential signal pair and transmitting the differential signal pair;
Receiving the difference signal pair from the transmission unit and generating image data of the specific color having a data value of '0' according to the instruction data; And
And sampling the image data of the specific color generated by the receiving unit and the image data of the remaining three colors.

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