KR20150063796A - Apparatus and method of data interface of flat panel display device - Google Patents

Abstract

The present invention relates to a data interface apparatus of a flat panel display device and a method thereof. It includes a transmission part which includes a timing controller, inserts a delimiter of a clock element between data to generate EPI data, and transmits the generated EPI data to a packet unit; and a reception part which is formed in source drive ICs connected to the timing controller, recovers the data and the delimiter from the EPI data provided from the transmission part, and generates internal clocks based on the delimiter. The transmission part changes the raising and poling timing of the delimiter with at least one packet unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a data interface device and method for a flat panel display,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly, to a data interface apparatus and method of a flat panel display capable of reducing the number of transmission lines by inserting and transmitting clocks into digital data.

2. Description of the Related Art Flat panel displays for displaying images using digital data include a liquid crystal display (LCD) using liquid crystal, a plasma display panel (PDP) using an inert gas discharge, an organic light emitting diode An organic light emitting diode (OLED) display device, and the like.

Such a flat panel display device has been increasing in resolution and size, and the amount of data to be transmitted is increasing. As a result, the transmission frequency of data increases and the number of transmission lines of data increases, thereby generating a large amount of electromagnetic interference (hereinafter referred to as EMI). Particularly, the EMI problem is mainly generated at the digital interface between the timing controller of the flat panel display and the plurality of source drive ICs (Integrated Circuit), resulting in unstable driving of the flat panel display.

Conventional flat panel displays employ various data interface methods in order to reduce signal transmission lines during data transmission / reception and to reduce EMI and power consumption during high-speed data transmission. For example, the applicant of the present application has developed a clocked embedded (" clock ") circuit that can minimize the number of wires between the timing controller and the source drive ICs and stabilize signal transmission by connecting the timing controller and source drive ICs in a point- Clock Embedded "interface, a so-called" EPI interface "is disclosed in Korean Patent Publication No. 10-2010-0068938 (2010-06-24), Korean Patent Publication No. 10-2010-0068936 (2010-06-24) Publication No. 10-2010-0073718 (2010-07-01).

Referring to FIG. 1, in the conventional EPI interface, the timing controller includes clock information defined as "Delimiter " in the data and supplies the data packet including the delimiter to the source drive IC. Then, the source drive IC generates internal clocks using the delimiter of the data packet provided from the timing controller, and samples the data.

However, in the conventional EPI interface, the data values of the delimiter inserted before and after the data packet are always fixed values. Accordingly, the frequency of the data packet is fixed and the noise of a specific frequency component is repeatedly generated when the data packet is transmitted, which is problematic in EMI.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a data interface apparatus and method for a flat panel display capable of reducing electromagnetic interference while reducing signal transmission lines during data transmission / reception using a clock embedded interface The purpose is to provide.

According to an aspect of the present invention, there is provided a data interface device for a flat panel display (PDP) device, the data interface device being embedded in a timing controller and generating a data packet by inserting a delimiter including clock information between data A transmitter for transmitting the generated data packets; And a receiving unit built in each of the plurality of source drive ICs connected to the timing controller to recover the delimiter and the data from the data packet provided from the transmitting unit and generate a plurality of internal clocks based on the delimiter and; And the transmitter changes the data value of the delimiter by at least one packet unit.

Wherein the transmitter comprises: a clock generator for generating the delimiter by frequency-dividing a frequency of a synchronizing signal input from the outside, the data generator varying data values of the delimiter according to a predetermined order; And a data packet generator for generating the data packet to be supplied to each of the source drive ICs by inserting the delimiter between the data.

Wherein the clock generator comprises: a signal generator for generating a data value of a plurality of delimeters to be inserted into the data packet; And a delimiter selector for selecting any one of the data values of the plurality of delimeters provided from the signal generator and varying the rising and falling timings of the delimiter based on the selected data.

The data values of the plurality of delimeters include 0001, 0011, 0111, 1000, 1100, and 1110. [

The receiver comprising: a decompressor for decompressing the delimiter and the data from the data packet provided from the transmitter; A reference clock generator for generating a reference clock based on the data value of the delimiter; An internal clock generator for generating the plurality of internal clocks using the reference clock; And a phase correcting unit for comparing the reference clock with the plurality of internal clocks to correct the phases of the plurality of internal clocks.

A clock selector for selecting one of the plurality of internal clocks in synchronization with a sequence of varying the data value of the delimiter in the clock generator; And a delay correcting unit for comparing the selected internal clock with the reference clock to correct a delay of the selected internal clock.

According to another aspect of the present invention, there is provided a data interface method for a flat panel display (LCD) device including a timing controller, a transmitter including a clock generator for generating clocks, Generating packets and transmitting the generated data packets; Restoring the delimiter and the data from the data packet provided from the transmitter in a receiver built in each of a plurality of source drive ICs connected to the timing controller and generating a plurality of internal clocks based on the delimiter Include; And the transmitter changes the data value of the delimiter by at least one packet unit.

The generating of the data packets by the transmitter may include generating the delimiter by frequency-dividing a synchronization signal input from the outside, the data values of the delimiter varying in accordance with a prescribed order; And inserting the delimiter between the data to generate the data packet to be supplied to each of the source drive ICs.

Wherein generating the delimiter comprises generating a data value of a plurality of delimeters to be inserted into the data packet; Selecting one of the data values of the plurality of delimeters, and varying the rising and falling timings of the delimiter based on the selected data.

The data values of the plurality of delimeters include 0001, 0011, 0111, 1000, 1100, and 1110. [

The receiving of the data packet by the receiving unit may include restoring the delimiter and the data from the data packet provided from the transmitting unit; Generating a reference clock based on a data value of the delimiter; Generating the plurality of internal clocks using the reference clock; And comparing the reference clock with the plurality of internal clocks to correct the phases of the plurality of internal clocks.

The step of correcting the phases of the plurality of internal clocks may include selecting one of the plurality of internal clocks in synchronization with a sequence of varying the data value of the delimiter, And comparing the selected internal clock with the reference clock to correct the delay of the selected internal clock.

In the present invention, a delimiter including clock information is inserted before and after a data packet using a clock embedded method, and the data value of the delimiter is changed at least every one packet unit. Accordingly, the present invention can vary the length of a data packet by at least one packet unit, and can reduce EMI by distributing noise repeatedly generated at a specific frequency when transmitting a data packet.

1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention.
2 is a diagram showing a transmitting section 50 incorporated in the timing controller TCON and a receiving section 60 circuit incorporated in each of the source drive ICs SIC.
3 is a configuration diagram of the clock generator 22 shown in FIG.
4 is a diagram illustrating a data packet.
5 is a diagram illustrating the length of data packets according to the present invention.
Fig. 6 is a configuration diagram of the phase corrector 34 shown in Fig.

Hereinafter, a data interface device and method of a flat panel display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The flat panel display of the present invention can be applied to a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode (OLED) Display, OLED), or the like. In the following embodiments, the liquid crystal display device will be mainly described, but the present invention is not limited to the liquid crystal display device.

1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention.

1 includes a liquid crystal display panel PNL, a timing controller TCON, one or more source drive ICs SIC # 1 to SIC # 4, and gate drive ICs GIC.

The liquid crystal display panel PNL includes liquid crystal cells arranged in a matrix form by an intersection structure of the data lines DL and the gate lines GL.

A pixel array including data lines DL, gate lines GL, TFTs, and storage capacitors is formed on the TFT array substrate of the liquid crystal display panel PNL. The liquid crystal cells are driven by an electric field between a pixel electrode to which a data voltage is supplied through a TFT and a common electrode to which a common voltage is supplied. The gate electrode of the TFT is connected to the gate line GL, the source electrode of the TFT is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell. The TFT is turned on according to the gate pulse supplied through the gate line GL to supply the data voltage from the data line DL to the pixel electrode of the liquid crystal cell.

A black matrix, a color filter, and a common electrode are formed on the color filter substrate of the liquid crystal display panel PNL.

In each of the TFT array substrate and the color filter array substrate of the liquid crystal display panel (PNL), a polarizing plate is attached and an alignment film for setting a pre-tilt angle of liquid crystal is formed. A spacer for maintaining a cell gap of the liquid crystal cell Clc may be formed between the TFT array substrate of the liquid crystal display panel PNL and the color filter array substrate.

The liquid crystal display panel PNL is a vertical field driving type such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode or a horizontal electric field driving method such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Can be implemented. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. The transmissive liquid crystal display device and the transflective liquid crystal display device each include a backlight unit. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller TCON receives vertical and horizontal synchronizing signals Vsync and Hsync from an external host system not shown through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a TMDS (Transition Minimized Differential Signaling) (Data Enable, DE), and an external timing signal such as a main clock (CLK). The timing controller TCON is connected in series to each of the source drive ICs (SIC # 1 to SIC # 4) through a pair of data wirings.

The timing controller TCON of the present invention transmits the digital video data of the input image to the source drive ICs SIC # 1 to SIC # 4 using the clock embedded system interface, and the source drive ICs SIC # SIC # 4) and the gate drive IC (GIC). For example, the clock-embedded interface of the present invention is disclosed in Korean Patent Publication No. 10-2010-0068938 (2010-06-24), Korean Patent Publication No. 10-2010-0068936 (2010-06-24) , Korean Patent Publication No. 10-2010-0073718 (2010-07-01), and the like can be used. A more detailed description of the EPI protocol that can be applied to the present invention replaces the above references.

1, a solid line is a pair of data lines for transmitting signals such as clock training signals, control data, and video data of the input video provided from the timing controller TCON to the source drive IC (SIC # 4). In Figure 1, the dashed line is the lock feedback signal wiring connected between the last source drive IC (SIC # 4) and the timing controller (TCON).

The timing controller TCON converts the clock training signal, the control data, the digital video data of the input image, and the like into the difference signal pairs to the source drive ICs SIC # 1 to SIC # 4 according to the signal transmission standard defined by the EPI protocol And serially transferred to the source drive ICs (SIC # 1 to SIC # 4) through the data wire pair.

The timing controller TCON transmits a clock training signal to the source drive ICs SIC # 1 to SIC # 4 when the lock signal LOCK input through the lock feedback signal wiring is at a low logic level and outputs a lock signal LOCK when the lock signal LOCK is low logic level. Is reversed to the high logic level, the control data and the digital video data transmission of the input video are resumed.

The timing controller TCON receives the control signal and the video data from the source drive ICs SIC # 1 to SIC # 4 after receiving the lock signal LOCK of the high logic level from the last source drive IC SIC # . The control data includes source control data for controlling the output timing of the data voltage output from the source drive ICs (SIC # 1 to SIC # 4), the polarity of the data voltage, and the like. The control data may include gate control data for controlling the operation timing of the gate drive IC (GIC).

The clock training signal transmitted from the timing controller (TCON) to the source drive ICs (SIC # 1 to SIC # 4) includes a delimiter including clock information. The present invention varies the delimiter data at least every one packet unit. Therefore, the present invention is applicable to a case where the length of a data packet transmitted from the timing controller (TCON) to the source drive ICs (SIC # 1 to SIC # 4) changes at least every one packet unit, It is possible to reduce the EMI by dispersing the noise.

The source drive ICs SIC # 1 to SIC # 4 generate an output of the clock recovery circuit through clock training when a lock signal LOCK of a high logic level is input from the previous stage source drive IC, Is locked and the CDR (Clok and Data Recovery) function is stabilized, the high logic level lock signal is transmitted to the next stage source drive IC. When the CDR function of all the source drive ICs SIC # 1 to SIC # 4 is stabilized, the last source drive IC SIC # 4 outputs the lock signal LOCK of the high logic level to the timing controller TCON ).

Each of the source drive ICs SIC # 1 to SIC # 4 may be connected to the data lines of the liquid crystal display panel PNL by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. The source drive ICs (SIC # 1 to SIC # 4) receive the clock training signal, control data, video data, and the like through the data wire pair.

The CDR circuit of the source drive ICs (SIC # 1 to SIC # 4) inputs the delimiter to the clock recovery circuit to generate the number of RGB bits of video data x two internal clocks. The clock recovery circuit outputs internal clocks using a phase locked loop (PLL) or a delay locked loop (DLL) and generates a lock signal (LOCK) do. The source drive ICs (SIC # 1 to SIC # 4) sample the video data bits of the input image in accordance with the internal clock timing, and then convert the sampled RGB bits into parallel data. The CDR circuit and the clock recovery circuit in the present invention will be described later in detail with reference to FIG. 2 to FIG.

The source drive ICs (SIC # 1 to SIC # 4) decode the control data input through the data wiring pair by a code mapping method to recover the source control data and the gate control data. The source drive ICs SIC # 1 to SIC # 4 convert the video data of the input video into the positive / negative analog video data voltages in response to the restored source control data, (DL). The source drive ICs SIC # 1 to SIC # 4 may transmit gate control data to one or more of the gate drive ICs (GICs).

The gate drive IC (GIC) may be connected to the gate lines of the TFT array substrate of the liquid crystal display panel through the TAP process or directly formed on the TFT array substrate of the liquid crystal display panel (PNL) by a GIP (Gate In Panel) process . The gate drive IC (GIC) is connected to the positive / negative analog video data voltage in response to the gate control data received directly from the timing controller (TCON) or received through the source drive ICs (SIC # 1 to SIC # And sequentially supplies the gate pulses to be synchronized to the gate lines GL.

2 is a diagram showing a transmitting section 50 incorporated in the timing controller TCON and a receiving section 60 circuit incorporated in each of the source drive ICs SIC.

The transmitter 50 is embedded in a timing controller (TCON), inserts a delimiter as a clock component between data to generate data packets, and transmits the generated data packets. The transmission unit 50 includes a data arrangement unit 20, a clock generation unit 22, a data packet generation unit 24, and a transmission buffer 18.

The data sorting unit 20 arranges and outputs the digital video data RGB inputted from the host system according to the resolution of the liquid crystal display panel PNL.

The clock generator 22 generates a delimiter as a clock component by frequency-dividing a dot clock, for example, a synchronization signal SYNC input from the outside. The clock generating unit 22 generates control data including the source control data and the gate control data based on the synchronization signal SYNC.

The clock generating unit 22 of the present invention varies the rising and falling timings of the delimiter at least every one packet unit. The clock generating unit 22 varies the rising and falling timings of the delimiter in accordance with a prescribed order.

The data packet generator 24 generates a data packet by inserting a delimiter as a clock component between the data arranged in the data arranger 20.

The receiving unit 60 is built in each of the plurality of source drive ICs SIC connected to the timing controller TCON and restores the delimiter and data from the data packet provided from the transmitting unit 50, An internal clock is generated to sample the data. The receiving unit 60 includes a receiving buffer 26, a restoring unit 28, a reference clock generating unit 30, an internal clock generating unit 32, a phase correcting unit 34, (36).

The restoration unit 28 restores the delimiter and data from the data packet provided from the transmission unit 50 through the reception buffer 26. [

The reference clock generating unit 30 generates a reference clock CLK_Ref based on the delimiter recovered from the restoring unit 28. [

The internal clock generator 32 generates a plurality of internal clocks CLKs using the reference clock CLK_Ref. To this end, the internal clock generator 32 uses a PLL or a DLL. A plurality of internal clocks (CLKs) can be used as a latch signal for sampling data.

The phase corrector 34 compares the plurality of internal clocks CLKs generated from the internal clock generator 32 with the reference clock CLK_Ref to correct the phases of the plurality of internal clocks CLKs. The phase corrector 34 outputs the lock signal LOCK when phase correction of the plurality of internal clocks CLKs is completed.

The sampling circuit 36 samples the data reconstructed from the reconstruction unit 28 using a plurality of internal clocks (CLKs) and outputs the sampled data.

3 is a configuration diagram of the clock generator 22 shown in FIG. 4 is a diagram illustrating a data packet. 5 is a diagram illustrating the length of data packets according to the present invention.

3, the clock generator 22 includes a signal generator 38 for generating data values of a plurality of delimeters, and a data generator 32 for generating either one of data values of a plurality of delimeters provided from the signal generator 38 And a delimiter selection unit 40 for varying the rising and falling timings of the delimiter based on the selected data.

The signal generator 38 generates data of a plurality of delimeters to be inserted into the data packet using the synchronization signal SYNC. The data value of the delimiter has a certain bit. For example, the data values of a number of delimeters may each be set to four bits. For reference, the delimiter data value should be transitioned once per data packet. Accordingly, the data of a plurality of delimeters may include 0001, 0011, 0111, 1000, 1100, 1110. That is, the data of a plurality of delimeters includes 0001, 0011, 0111, 1000, 1100 and 1110 which are changed once from '1' to '0' or changed from '0' to '1'.

The delimiter selection unit 40 receives data of a plurality of delimiters from the signal generation unit 38 and selects one of the data of the plurality of delimiters. The rising and falling timings of the delimiter are varied and output based on the selected data.

For reference, one packet in the EPI protocol is inserted with a delimiter as a clock component before and after a data packet, as shown in Fig. In the conventional EPI protocol, the data of the delimeter is fixed to '0011'. However, the present invention can vary the frequency of the data packet by at least one packet unit by varying the data value of the delimiter. Referring to FIG. 5, it can be seen that the length and frequency per one data packet are variable and variable as the data of the delimeter varies with 0001, 0111, 0001, 0011, 0001, and so on. Therefore, the present invention can reduce EMI by distributing noise repeatedly generated in a specific frequency band when transmitting a data packet. Although not shown, according to the present applicant's experiments, in the present invention using a 4-bit variable delay meter, the peak noise compared to the prior art using the fixed delay meter is reduced to 1/5 level, the noise is reduced to 3 to 5 dB I can confirm that it is shrinking.

Fig. 6 is a configuration diagram of the phase corrector 34 shown in Fig.

6, the phase corrector 34 includes a clock selector 42 for selecting and outputting any one of a plurality of internal clocks CLKs generated from the internal clock generator 32, And a delay corrector 44 for comparing the internal clock selected from the reference clock CLK_Ref with the reference clock CLK_Ref to correct the delay of the selected internal clock.

The clock selection unit 42 selects the internal clock corresponding to the sequence in synchronization with the order of varying the rising and falling timings of the delimiter in the clock generation unit 22 provided in the transmission unit 50 when the internal clock is selected do. For reference, when the delay meter is varied according to the present invention, the plurality of internal clocks generated based on the delay meter have different phases. Therefore, in order to accurately correct the phases of the internal clocks, which are different from each other, the present invention selects the corresponding internal clock in synchronism with the order in which the delay meters vary in phase correction of a plurality of internal clocks. The phase of the plurality of internal clocks is corrected by comparing the selected internal clock with the reference clock (CLK_Ref). Therefore, even if the delimiter is variable, the present invention can accurately correct the phase of the internal clock generated based on the delimiter.

The delay corrector 44 compares the internal clocks selected from the clock selector 42 with the reference clock CLK_Ref, and adjusts the delay of the selected internal clock. For this purpose, the delay correction unit 44 may be configured as a DLL.

As described above, according to the present invention, a delimiter including clock information is inserted before and after a data packet using a clock embedded system, and the data value of the delimiter is changed at least every one packet unit. Accordingly, the present invention can vary the length of a data packet by at least one packet unit, and can reduce EMI by distributing noise repeatedly generated at a specific frequency when transmitting a data packet.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

50: transmission unit 60:
20: data arranging unit 22: clock generating unit
24: EPI data generation unit 34: phase correction unit

Claims (12)

A transmitter included in the timing controller, generating a data packet by inserting a delimiter including clock information between the data, and transmitting the generated data packets;
And a receiving unit built in each of the plurality of source drive ICs connected to the timing controller to recover the delimiter and the data from the data packet provided from the transmitting unit and generate a plurality of internal clocks based on the delimiter and;
Wherein the transmitter changes the data value of the delimiter by at least one packet unit. The method according to claim 1,
The transmitting unit
A clock generator for generating the delimiter by dividing a frequency of a synchronizing signal input from the outside, and varying the data value of the delimiter in accordance with a prescribed order;
And a data packet generator for generating the data packet to be supplied to each of the source drive ICs by inserting the delimiter between the data. The method of claim 2,
The clock generator
A signal generator for generating a data value of a plurality of delimeters to be inserted into the data packet;
And a delimiter selection unit for selecting any one of data values of a plurality of delimeters provided from the signal generation unit and varying the rising and falling timings of the delimiter based on the selected data, The data interface device of the device. The method of claim 3,
The data values of the plurality of delimeters
0001, 0011, 0111, 1000, 1100, 1110. The flat panel display of claim 1, The method of claim 2,
The receiving unit
A restoring unit for restoring the delimiter and the data from the data packet provided from the transmission unit;
A reference clock generator for generating a reference clock based on the data value of the delimiter;
An internal clock generator for generating the plurality of internal clocks using the reference clock;
And a phase correcting unit for comparing the reference clock with the plurality of internal clocks to correct phases of the plurality of internal clocks. The method of claim 5,
The phase correction unit
A clock selector for selecting one of the plurality of internal clocks in synchronization with a sequence of varying the data value of the delimiter in the clock generator;
And a delay corrector for comparing the selected internal clock with the reference clock to correct a delay of the selected internal clock. Generating a data packet by inserting a delimiter including clock information between the data in the transmitter incorporated in the timing controller, and transmitting the generated data packets;
Restoring the delimiter and the data from the data packet provided from the transmitter in a receiver built in each of a plurality of source drive ICs connected to the timing controller and generating a plurality of internal clocks based on the delimiter Include;
Wherein the transmitter changes the data value of the delimiter by at least one packet unit. The method of claim 7,
Wherein the generating of the data packets by the transmitter comprises:
Generating a delimiter by frequency-dividing a synchronizing signal input from the outside, the data values of the delimiter varying in accordance with a prescribed order;
And inserting the delimiter between the data to generate the data packet to be supplied to each of the source drive ICs. The method of claim 8,
The step of generating the delimiter
Generating a data value of a plurality of delimeters to be inserted into the data packet;
Selecting one of the data values of the plurality of delimeters, and varying the rising and falling timings of the delimiter based on the selected data. The method of claim 9,
The data values of the plurality of delimeters
0001, 0011, 0111, 1000, 1100, 1110. The flat panel display of claim 1, The method of claim 8,
The receiving of the data packet by the receiving unit
Recovering the delimiter and the data from the data packet provided from the transmitter;
Generating a reference clock based on a data value of the delimiter;
Generating the plurality of internal clocks using the reference clock;
And comparing the reference clock with the plurality of internal clocks to correct the phases of the plurality of internal clocks. The method of claim 11,
The step of correcting the phase of the plurality of internal clocks
Selecting one of the plurality of internal clocks in synchronization with a sequence in which the data value of the delimiter is varied;
And comparing the selected internal clock with the reference clock to correct a delay of the selected internal clock.

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