KR20130020338A - Clock embedded interface device and image display device using the samr - Google Patents

Abstract

PURPOSE: A clock embedded interface device and an image display device using the same are provided to form a phase difference between the recovered clock signal and the transmitted image data by forming a phase difference between a delimiter transmission period and an image data transmission period when an image data packet is transmitted. CONSTITUTION: A transmitting unit(20) serially arranges and transmits data. A receiving unit(30) outputs the serially arranged data in parallel. A clock signal generating unit(22) generates a first clock signal. A data arranging unit(24) transmits the data by generating a phase difference of 0.5 UI between an image data transmission period and a delimiter transmission period of image data packets. A clock signal recovering unit(32) generates and outputs a second clock signal by recovering a first clock signal. A data recovering unit(34) outputs the serially arranged data in parallel. [Reference numerals] (22) Clock signal generating unit; (24) Data arranging unit; (32) Clock signal recovering unit; (34) Data recovering unit

Description

CLOCK EMBEDDED INTERFACE DEVICE AND IMAGE DISPLAY DEVICE USING THE SAMR}

The present invention provides a clock embedded interface device capable of reducing electromagnetic interference (EMI) while reducing signal transmission lines during display data transmission / reception using a clock embedded interface method and image display using the same. Relates to a device.

2. Description of the Related Art Recently, various types of image display devices have emerged as means for variously touching digital contents. The most commonly used image display devices are flat panel display devices such as liquid crystal display devices, organic light emitting display devices, and field emission display devices. ) And a plasma display panel are mainly used.

These video display devices employ an intra-panel interface method so that data can be transmitted and received between a driver for driving an image display panel and a controller for controlling the driver.

Conventionally, the intra-panel interface method includes a Reduced Swing Differential Signaling (RSDS) interface employing a multi-drop scheme, a mini-LVDS (low voltage differential signaling), and a point-to-point Point-to-point differential signaling (PPDS) interface.

However, the above-described intra panel interface schemes require many signal lines for transmitting control signals or data, and have many problems due to electromagnetic interference (EMI). Recently, an intra panel interface protocol using a clock embedding technology for transmitting a clock signal together with display data in a data transmission line has been applied. However, the clock embedded interface method also cannot eliminate the problems caused by electromagnetic interference, and needs to be improved to further reduce the number of signal transmission lines.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and includes a clock embedded interface device and a video display device using the same to reduce electromagnetic interference while reducing signal transmission lines during transmission and reception of display data using a clock embedded interface method. The purpose is to provide.

In order to achieve the above object, a clock embedded interface device according to an embodiment of the present invention aligns and transmits data in series so that a first clock signal is included, and a phase difference between a dilometer transmission period and an image data transmission period of the data. A transmitter for sorting and transmitting the data such that the data is generated; And a receiver configured to recover a first clock signal included in the data from the transmitter, to generate and output a second clock signal, and to output the serially aligned data in parallel according to the second clock signal. It features.

The transmitter may include a clock signal generator that generates the first clock signal using a phase locked loop or a delay locked loop according to a reference clock signal from an external source, and the first clock signal to be included in the data. And a data alignment unit for serially arranging and transmitting the data so as to have a phase difference of at least 0.5 UI (Unit Interval) between the delimiter transmission period of the image data packets and the image data transmission period during the transmission of the aligned data. It is characterized by.

The receiver recovers the first clock signal from the image data packet of the serially supplied data to generate and output a second clock signal having a phase difference of at least 0.5 UI from the image data of the image data packet. And a data recovery unit for outputting the serially aligned data in parallel according to the second clock signal.

The second clock signal generated by restoring the first clock signal from the image data packet is a low or high pulse phase locked loop generated to have a phase difference difference of at least 50% from each image data of the image data packet. It is characterized in that the signal.

The second clock signal may be generated to have a phase difference of at least 0.5 UI or a phase difference of at least 0.5 UI with the image data aligned and output in parallel, and the restored image data may be latched to a storage means including a register or a memory. To be used as a latch signal.

The data alignment unit outputs a clock training signal such that the data recovery unit is locked or disabled in an initialization period of every horizontal line, and controls a corresponding driver or integrated circuit in an enable period of each horizontal line. And outputting control data, and generating and outputting an image data packet serially included in each of the horizontal line unit data supply periods, wherein the delimiter and the image data have a phase difference of at least 0.5 UI period.

The data aligning unit generates and outputs a reduced period of at least 0.5 UI periods for each consecutive signal of the same bit ("00" and "11") among the bit signals of the delimiter, so that the delimiter and each image data is at least 1 UI period. And generating and outputting the image data packet so as to have a phase difference therebetween.

In addition, an image display device using a clock embedded interface device according to an embodiment of the present invention for achieving the above object includes a display panel for displaying an image having a plurality of pixel areas; A data driver for driving data lines of the display panel; And a timing controller for aligning and supplying image data from the outside to the data driver in series to suit the driving of the display panel, and generating a data control signal to control the data driver. A transmitter having various technical features described above is provided, and the data driver is provided with a receiver having various technical features described above to align and transmit and receive image data from the outside through the transmitter and the receiver. do.

The data driver uses the above-described second clock signal as a latch signal to latch image data from the transmitter to its latch unit.

The clock embedded interface device of the present invention having the technical features as described above and the image display device using the same have a phase difference between a delimiter transmission period and an image data transmission period during image data packet transmission, thereby restoring the generated clock signal. It may also have a phase difference from the transmitted image data.

Accordingly, the restored generated clock signal may be used as a latch signal, thereby reducing data transmission lines or simplifying the configuration of the clock signal generator.

In addition, when reducing the data transmission line or simplifying the configuration of the clock signal generator, electromagnetic interference due to data transmission may be reduced.

1 is a block diagram showing a clock embedded interface device according to an embodiment of the present invention.
2 is a diagram illustrating a transmission protocol of data transmitted from a transmitter of FIG. 1.
FIG. 3 is a waveform diagram illustrating the clock training signal of FIG. 2. FIG.
4 is a protocol for asserting control data of FIG.
FIG. 5 is a diagram for describing an image data packet of FIG. 2 and a restored second clock signal. FIG.
6 is a block diagram illustrating in detail a liquid crystal display according to an exemplary embodiment of the present invention.

Hereinafter, a clock embedded interface device and an image display device using the same according to an embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a clock embedded interface device according to an exemplary embodiment of the present invention.

The clock embedded interface device illustrated in FIG. 1 arranges and transmits data LData in series so that a first clock signal CLK1 is included, and a delimiter transmission period of the data LData and image data Data. A transmitter 20 for aligning and transmitting the data LData such that a phase difference occurs in a transmission period; And generating and outputting the second clock signal CKL2 by restoring the first clock signal CLK1 included in the data LData from the transmitter 20, and serially aligned according to the second clock signal CKL2. The receiver 30 outputs the data LData in parallel.

The transmitter 20 transmits a delimiter and a data transmission period of the image data packets during a transmission period of serially aligned data LData, in particular, a transmission period of each image data packet. The data (LData) are arranged and transmitted so that a phase difference of at least 0.5 UI (Unit Interval) occurs.

To this end, the transmitter 20 uses a phase locked loop (PLL) or a delay locked loop (DLL) in accordance with a reference clock signal RCLK from the outside to transmit the first clock signal CLK1. The clock signal generation unit 22 generating the first and second clock signals CLK1 are included in the data LData to align and transmit the data LData in series, and the transmission period of the aligned data LData. The data aligning unit 24 for transmitting the data (LData) so as to have a phase difference of at least 0.5 UI (Unit Interval) between the delimiter transmission period of the image data (Data) packets and the image data (Data) transmission period. Equipped.

In detail, the data aligner 24 aligns and transmits the data LData in series so that the first clock signal CLK1 is included using the first clock signal CLK1 generated from the clock signal generator 22. do. The data aligning unit 24 performs at least a phase difference of at least 0.5 UI (Unit Interval) between the delimiter transmission period of the image data packets and the image data transmission period of the serially aligned data LData. It arranges and transmits data (LData) to have. At this time, the data aligning unit 24 aligns and transmits the first clock signal CLK1 to be included in the data LData.

If the transmission period of the image data packets has a phase difference of at least 0.5 UI between the delimiter transmission period and the image data data transmission period, the transmission period of the image data packet having the phase difference is greater than the transmission period of the image data packet having no phase difference. It may be shorter. For example, one packet image data of 6 bits (6Bit) may be transmitted in a 21 UI period shorter than a conventional 22 UI period without phase difference. A method of arranging and transmitting image data (Data) transport packets by the data alignment unit 24 will be described in detail later with reference to the accompanying drawings.

Meanwhile, the receiver 30 generates and outputs a second clock signal CKL2 by restoring the first clock signal CLK1 included in the data LData from the transmitter 20, wherein the second clock signal is generated. The serially aligned data LData is output in parallel according to CKL2.

The receiver 30 restores the first clock signal CLK1 from the image data packet of the data LData, which is supplied in series, to at least 0.5 from the image data of the image data packet. A clock recovery unit 22 that generates and outputs a second clock signal CKL2 having a phase difference of the UI, and a data recovery unit that outputs data LData arranged in series according to the second clock signal CKL2 in parallel 34 is provided.

The clock signal recovery unit 22 may receive serially received data (LData), that is, image data packets having a phase difference of at least 0.5 UI (Unit Interval) between the delimiter transmission period and the image data transmission period. The second clock signal CLK2 is generated by restoring the first clock signal CLK1 from the first. To this end, the clock signal recovery unit 22 may use a phase locked loop (PLL) or a delay locked loop (DLL). When the first clock signal CLK1 is restored from the respective image data data packets, the restored first clock signal CLK1, that is, the second clock signal CLK2 has 0.5UI in each image data packet. Since the unit has a phase difference of unit interval, the image data of the image data packet has a phase difference of 0.5 UI or more. Accordingly, the second clock signal CLK2 generated by restoring the first clock signal CLK1 from the image data packet is at least 50% different from each of the image data Data of the image data packet. They are generated with low or high pulses, respectively, to have a differential phase difference. The second clock signal CLK2 generated as described above shows image data Data that is generated and reconstructed so as to have a phase difference of at least 50% or a period of at least 0.5 UI and image data that are aligned and output in parallel. It can be used as a latch signal so that it can be latched to an unregistered register or memory means.

FIG. 2 is a diagram illustrating a transmission protocol of data transmitted from the transmitter of FIG. 1.

Referring to FIG. 2, the data aligning unit 24 of the transmitting unit 20 performs a clock training signal so that the data restoring unit 34 is locked or disabled in the initialization period ST1 of every horizontal line. Outputs control data for controlling a corresponding driver, an integrated circuit, or the like in the enable period ST2 for every horizontal line, and outputs the control data for the data supply period ST3 for every horizontal line. The delimiter and the image data Data generate and output serially the image data packet included with at least 0.5 UI period phase difference.

During each horizontal period, the data alignment unit 24 transmits a clock training signal to the data recovery unit 34 so that the data recovery unit 34 of the receiver 30 is locked or disabled. . For example, the transmitter 20 generates a clock training signal as shown in FIG. 3 when the power is turned on or when a soft fail occurs in a driver or an integrated circuit to which image data packets are output. And, it can be transmitted to the data recovery unit 34.

In the enable period ST2 during every horizontal period, control data for controlling a corresponding driver, an integrated circuit, or the like is supplied. As shown in FIG. 4, a control signal transmission line for transmitting control signals to each driver or integrated circuit is not required by transmitting control data in every horizontal line unit of a corresponding driver or integrated circuit. You may not. Such control data may include a synchronization signal or a data enable signal that is activated when an image data packet is supplied. The control data includes a delimiter set to the bit signal "0011" and the like. The delimiter of the control data indicates the start of transmission of control data for each horizontal line. .

In the data supply period ST3 during the horizontal period, the image data data packet including the delimiter and the image data Data having at least 0.5 UI period phase difference is supplied. The delimiter of the image data packet indicates the start of image data transmission for each horizontal line. This delimiter may be set to the bit signal "0011" or the like, as shown in FIG. For example, when the delimiter is set to the bit signal " 0011 ", if one bit is 1 UI period, " 00 " is generated as 2 UI, " 11 " However, in order for the delimiter and each image data (Data) to have a phase difference of at least 0.5 UI, the delimiter bit signal generation period should be generated to be reduced by at least 0.5 UI period. Therefore, when the delimiter is set to the bit signal is set to "0011", "00" is generated in 1.5UI period, "11" is also generated in the period of 1.5UI so that each same bit generation period is reduced by 0.5UI period. The delimiter and the respective image data Data have at least 1 UI period phase difference.

As described above, the data aligning unit 24 generates and outputs the delimiter and the respective image data by reducing and generating at least 0.5 UI periods for each signal of the same bit ("00" and "11") among the bit signals of the delimiter. The image data packet may be generated and output such that the data has a phase difference by at least 1 UI period.

On the other hand, the clock signal recovery unit 32 restores the first clock signal CLK1 from the image data packet having a phase difference of at least 1 UI during the delimiter transmission period and the image data Data transmission period, thereby recovering the second clock signal. The signal CLK2 (DLL Clock of Fig. 5) is generated. In this case, the restored second clock signal CLK2 (the DLL clock of FIG. 5) has a delimiter transmission period and an image data data transmission period of each image data packet of at least 0.5 UI (1UI in FIG. 5). Since the phase difference has a phase difference of at least 0.5 UI (for example, 50%) than the image data Data of the image data packet. Each of the second clock signals CLK2 (ie, the DLL clock of FIG. 5) generated in this manner may include image data packets of the reconstruction data SData, in particular, each image data Data and 0.5 UI (for example, 50%) phase difference. Accordingly, the second clock signal CLK2 may be used as a latch signal so that the reconstructed image data Data may be latched to a memory means (not shown).

On the other hand, when the image data packet is transmitted in the same period (for example, a 2-bit 2.0 UI DLL) so that a phase difference does not occur between the delimiter transmission period and the image data transmission period, the 2.0UI DLL signal of FIG. As shown by (a plurality of DLLs shown by dotted lines), the respective image data Data and the second clock signal are synchronized. In this case, a separate latch signal needs to be generated so that the reconstructed image data Data can be latched to a memory means (not shown).

As described above, the clock embedded interface device of the present invention has a phase difference between the delimiter transmission period and the image data transmission period when the image data packet is transmitted, such that the reconstructed generated clock signal also has a phase difference with the transmitted image data. can do. Accordingly, the restored generated clock signal may be used as a latch signal, thereby reducing data transmission lines or simplifying the configuration of the clock signal generator. In addition, when reducing the data transmission line or simplifying the configuration of the clock signal generator, electromagnetic interference due to data transmission may be reduced.

The clock embedded interface device according to the present invention may be used for a flat panel type image display device which is generally used, for example, a liquid crystal display device, an organic light emitting diode display device, a field emission display device, and a plasma display device. For example, an example in which the clock embedded interface device of the present invention is applied to a liquid crystal display is as follows.

6 is a configuration diagram illustrating in detail a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 6 includes a liquid crystal panel 2 formed with a plurality of pixel regions; A gate driver 3 driving a plurality of gate lines GL1 to GLn provided in the liquid crystal panel 2; A data driver 4 for driving the plurality of data lines DL1 to DLm included in the liquid crystal panel 2; And supplying the image data RGB from the outside to the data driver 4 in series according to the driving of the liquid crystal panel 2 and generating a gate and data control signals GCS and DCS. And a timing controller 8 for controlling the data drivers 6 and 4. Here, the timing controller 8 is provided with a transmitter 20 shown in FIG. 1, and the data driver 4 is provided with a receiver 30, respectively, so that the external device via the transmitter 20 and the receiver 30 is externally provided. Image data (RGB) from the image is sorted and transmitted and received.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel area defined by the plurality of gate lines GL1 through GLn and the plurality of data lines DL1 through DLm, and a liquid crystal capacitor connected to the TFT. (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies the image signals from the respective data lines DL1 to DLm to the pixel electrodes in response to the scan pulses from the respective gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the image signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating layer interposed therebetween. In contrast, the storage capacitor Cst is formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween.

The data driver 4 includes a plurality of data integrated circuits respectively provided between one side of the liquid crystal panel 2 and at least one source printed circuit board 5 to drive the data lines DL1 to DLm. do. Here, at least one integrated circuit of the plurality of data integrated circuits 4a includes the receiver 30 described with reference to FIGS. 1 to 5. The data integrated circuit converts and outputs the image data Data supplied from the transmitter 20 of the timing controller 8 into an analog voltage, that is, an image signal, using the data control signal DCS from the timing controller 8. .

In detail, the data integrated circuit latches the image data Data received by the receiver 30 according to the second clock signal CLK2 to its own latch unit. In addition, in response to the source output enable signal of the data control signal DCS, one horizontal line corresponds to an image signal corresponding to one horizontal line every scan period in which scan pulses are supplied to the gate lines GL1 to GLn. To feed. At this time, the data driver 4 selects a positive or negative gamma voltage having a predetermined level according to the gray value of the image data Data, and supplies the selected gamma voltage to each data line DL1 to DLm as an image signal. do.

The gate driver 3 may be integrally formed with the liquid crystal panel 2 in the image non-display area of the liquid crystal panel 2 or may be provided in the form of an integrated circuit and separately provided on either side of the liquid crystal panel 2. The gate driver 3 sequentially supplies scan pulses to the gate lines GL1 to GLn using the gate control signal GCS from the timing controller 8 or the like. The gate low voltage is supplied to the gate lines GL1 through GLn during the period when the scan pulse is not supplied.

The timing controller 8 uses the data alignment unit 24 of the transmitter 20 to drive digital image data RGB, which is input from the outside, to drive the liquid crystal panel 2, in particular, to drive data lines of each data integrated circuit. Aligned to the number, and supplied to the receiver 30 of the data integrated circuit. The gate and data control signals GCS and DCS are generated using at least one of an input synchronization signal, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronization signals Hsync and Vsync. The gate driver and each data integrated circuit are controlled by supplying them to the gate driver 3 and the data integrated circuit, respectively.

As described above, the transmitter 20 and the receiver 30, which are clock embedded interface devices, may be provided in the timing controller 8 and the data integrated circuit of the liquid crystal display. In this case, the clock embedded interface device formed in the timing controller 8 and the data integrated circuit has a phase difference between the delimiter transmission period and the image data transmission period when the image data packet is transmitted, so that the reconstructed generated clock signal is also transmitted. It can be made to have a phase difference with the. Accordingly, the restored generated clock signal may be used as a latch signal, thereby reducing data transmission lines or simplifying the configuration of the clock signal generator. In addition, when reducing the data transmission line or simplifying the configuration of the clock signal generator, electromagnetic interference due to data transmission may be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (9)

A transmitter for aligning and transmitting data in series so that a first clock signal is included, and aligning and transmitting the data such that a phase difference occurs between the delimiter transmission period and the image data transmission period of the data; And
And a receiver configured to generate and output a second clock signal by restoring a first clock signal included in the data from the transmitter, and to output the serially aligned data in parallel according to the second clock signal. Clock embedded interface device. The method of claim 1,
The transmitting unit
A clock signal generator for generating the first clock signal using a phase locked loop or a delay locked loop according to a reference clock signal from an external device; and
Arrange and transmit the data serially so that the first clock signal is included in the data, wherein at least 0.5 UI (Unit 2) is transmitted in the delimiter transmission period and the image data transmission period of the image data packets during the transmission period of the aligned data. And a data alignment unit for transmitting the data to have a phase difference of an interval. The method of claim 2,
The receiving unit
A clock signal recovery unit for restoring the first clock signal from the image data packet of the serially supplied data to generate and output a second clock signal having a phase difference of at least 0.5 UI from the image data of the image data packet; And
And a data recovery unit for outputting the serially aligned data in parallel according to the second clock signal. The method of claim 3, wherein
The second clock signal generated by restoring the first clock signal from the image data packet is a low or high pulse phase locked loop generated to have a phase difference difference of at least 50% from each image data of the image data packet. Clock embedded interface device, characterized in that the signal. The method of claim 4, wherein
The second clock signal is
The image data arranged and output in parallel with each other and having a period of at least 0.5 UI or a phase difference of at least 50%, and used as a latch signal so that the restored image data can be latched to a storage means including a register or a memory. Clock embedded interface device, characterized in that. The method of claim 5, wherein
The data sorter
Outputting a clock training signal such that the data recovery unit is locked or disabled in an initialization period of every horizontal line;
Outputs control data for controlling the driver or integrated circuit in the enable period of each horizontal line.
And an image data packet serially generated and outputted in the data supply period in units of horizontal lines, wherein the delimiter and the image data have a phase difference of at least 0.5 UI period. The method according to claim 6,
The data sorter
By generating and outputting at least 0.5 UI periods for each consecutive signal of the same bit ("00" and "11") among the bit signals of the delimiter so that the delimiter and each image data have a phase difference by at least 1 UI period. And a clock embedded interface device generating and outputting the image data packet. A display panel including a plurality of pixel areas to display an image;
A data driver for driving data lines of the display panel; And
And a timing controller for aligning the image data from outside with the driving of the display panel and supplying the data data to the data driver in series and generating a data control signal to control the data driver.
The timing controller is provided with a transmitter having at least one of the technical features of claim 1, and the data driver is provided with a receiver having the technical features of at least one of the claims 1 to 7. And receiving and sorting and transmitting image data from the outside through a receiving unit. The method of claim 8,
The data driver
The video display device as claimed in claim 1, wherein the video data from the transmitter is latched to its latch unit by using the second clock signal of at least one of the claims 1 to 7 as a latch signal.

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