KR20160061537A - Display Device and Driving Method thereof - Google Patents

Abstract

A display device includes a display panel, a first to an n-th timing controller, a transmission part, and a first to an n-th receiving part. The display panel includes a first to an n-th panel (n is a natural number). The first to the n-th timing controller independently operates the first to the n-th panel. The transmission part transmits digital video data displayed on the display panel with a Vbyone interface standard. And, the timing controller outputs a lock synchronization signal (LOCKNsync) to the transmission part when all the first to the n-th receiving part perform CDR training. So, a problem that an abnormal screen is displayed can be solved.

Description

DISPLAY DEVICE AND DRIVING METHOD THEREOF

The present invention relates to a display device and a driving method thereof.

The display device includes a plurality of source drive integrated circuits (hereinafter referred to as "IC") for supplying data voltages to the data lines of the display panel, gate pulses (or scan pulses) A plurality of gate drive ICs for supplying the drive ICs, and a timing controller for controlling the drive ICs.

The timing controller is mounted on the control board, and the ICs of the data driving circuit are placed on the source PCB (Printed Circuit Board). Between the control board and the source PCB, an FPC (Flexible Printed Circuit) through which digital video data and timing control signals are transmitted is installed. The control board is connected to the system board via an interface cable. A scaler is mounted on the system board. The scaler converts the resolution of the data according to the resolution of the display panel and transmits it to the control board.

The number of wires of the interface cable connecting between the system board and the control board is determined by the amount of data to be transmitted and the clock signals. Currently, the interface cable between the system board and the control board requires 48 lines when applying a low-voltage differential signaling (LVDS) interface method when driving a liquid crystal display device at full-HD 120 Hz. Even though the LVDS interface method is applied, the number of interface cables is large and the number of pins of the connector for connecting the interface cable to the system board and the control board is large. Therefore, the conventional liquid crystal display device has difficulties in cost reduction due to the cost of the interface cable and the connector, and EMI (electromagnetic interference) is high due to a high-frequency clock signal transmitted through the interface cable. In order to improve this, an interface method having a smaller EMI and a smaller number of transmission lines than LVDS interface is being developed.

For example, the Vbyone interface developed by THine Electronics has improved signal transmission quality compared to existing LVDS interfaces due to the introduction of the equalizer function, resulting in a faster speed of 3.75Gbps per 1Pair. In addition, the Vbyone interface solves the skew adjustment problem caused by the clock transmission of the LVDS interface due to the adoption of CDR (Clock Data Recovery). And since the Vbyone interface does not have the clock transmission that was necessary in the existing LVDS, the EMI noise caused by the clock transmission can be reduced. These Vbyone interfaces can be effectively used to cope with the increase in data amount and the trend toward high speed.

In recent years, ultra high resolution display devices such as QHD or UHD have appeared. An ultra-high resolution display includes four panels and includes a timing controller for driving each of the panels. When a Vbyone interface is used for data transmission in an ultra-high resolution display device, a transmitter belonging to the system board communicates independently with a receiver formed in each timing controller. The transmission unit transmits pixel data to all the reception units when one of the reception units completes preparation for receiving data. Accordingly, the receiving unit, which is not ready to receive data, can not perform a normal operation and thus displays an abnormal screen on the panel.

An object of the present invention is to provide a display device for improving the problem that an abnormal screen is displayed by receiving data in a state in which a part of the timing controller fails to perform a normal operation in a display device including a plurality of timing controllers.

The display apparatus according to the present invention includes a display panel, first to n-th timing controllers, a transmitter, and first to n-th receivers. The display panel includes first to n-th (n is a natural number) panel. The first to n-th timing controllers independently drive the first to n-th panels. The transmitting unit transmits the digital video data displayed on the display panel in the Vbyone interface standard. Each of the first to nth receiving units performs Vbyone interface communication with the transmitting unit, and performs CDR training corresponding to the CDR training pattern signal transmitted by the transmitting unit. The timing controller outputs a lock synchronization signal (LOCKNsync) to the transmission unit when the first to nth reception units have performed the CDR training.

In the driving method of a display device according to the present invention, after a physical connection between a transmitter and a plurality of receivers is confirmed, a transmitter transmits a CDR (Clock Data Recovery) training pattern signal to receivers. Then, the receiver performs CDR training in which the clock is recovered from the CDR circuit using the CDR training pattern signal. Receiving units that have completed CDR training then output a lock synchronization signal. When all the receiving units output the lock synchronization signal, the lock synchronization signal is transmitted to the transmission unit. In response to the lock synchronization signal, the transmitter transmits an Align training pattern signal to the receivers.

The present invention receives data from the system board and displays the received data in a state in which all the timing controllers are ready to receive data. Accordingly, it is possible to prevent an abnormal image from being displayed on the display panel by receiving and displaying data in a state in which some timing controllers are not normally operable.

1 is a view showing a display device according to the present invention.
2 shows a link of a communication interface according to the invention;
FIGS. 3 to 5 are diagrams for explaining a sequence of a communication interface according to the present invention; FIG.
6 is a diagram showing a comparison example with a sequence of a communication interface according to the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Although the present invention is described below with reference to a liquid crystal display device as an example, the present invention is also applicable to a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode And a flat panel display device such as an organic light emitting display (OLED).

Referring to FIG. 1, a liquid crystal display device according to the present invention includes a display panel 100, first to fourth control boards CTRB1 to CTRB4, and a system board SB.

The display panel 100 includes first to fourth panels 100-1 to 100-4. The liquid crystal cells of the first to fourth panels 100-1 to 100-4 are arranged in a matrix by the intersection structure of the data lines DL and the gate lines GL. The lower glass substrate of the display panel 100 is connected to data lines DL, gate lines GL, TFTs and TFTs and driven by an electric field between the pixel electrodes 1 and the common electrode 2 Liquid crystal cells Clc, a storage capacitor Cst, and the like are formed. On the upper glass substrate of the display panel 100, a black matrix, a color filter, and a common electrode 2 are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system. On the upper glass substrate and the lower glass substrate of the display panel 100, a polarizing plate having an optical axis orthogonal to the polarizing plate is formed, and an alignment film is formed to set a pre-tilt angle of the liquid crystal at an interface with the liquid crystal.

The first control board CTRB1 drives the first display panel 100 and may be implemented as a printed circuit board (PCB) including the first timing controller 100-1.

The first timing controller 100-1 receives Vbyone data from the system board SB and transmits the received data to the source drive ICs. The first timing controller also generates a data timing control signal for controlling the operation timing of the source drive ICs and a gate timing control signal for controlling the operation timing of the gate drive ICs. The first timing controller TCON1 controls the operation timing of the source drive ICs using the timing signals, i.e., the vertical and horizontal synchronization signals, the data enable signal, and the dot clock, and controls the polarity of the data voltage supplied to the display panel 100 And generates a gate timing control signal for controlling the operation timing of the gate drive ICs 151 to 153. [

The data drive ICs and gate drive ICs of the first control board CTRB1 can be mounted together in integrated circuits (ICs) of a chip-on-film (COF). The input terminal of the chip on film (COF) is connected to a PCB (Printed Circuit Board), and the output terminal of the COF is connected to the upper end of the lower substrate of the display panel (PNL).

The source drive ICs of the first control board CTRB1 receive digital video data from the first control board CTRB1. The source driver IC converts the data into an analog data voltage in response to a data timing control signal received from the control board CTRB1, and then supplies the data to the data lines DL of the display panel 100. [

The gate drive ICs of the first control board CTRB1 generate gate pulses in response to the gate timing control signals supplied from the first control board CTRB1 and sequentially supply the gate pulses to the gate lines.

The second to fourth control boards CTRB2 to CTRB4 are for driving the second to fourth panels 100-2 to 100-4 respectively and the details of the second to fourth control boards CTRB2 to CTRB4 Is substantially the same as the configuration of the first control board CTRB1, and thus a detailed description thereof will be omitted.

The system board SB converts the resolution of the digital video data according to the resolution of the display panel 100 and transmits the digital video data and the timing signals in the Vbyone interface standard.

2 is a diagram showing a communication interface device of the timing controller TCON of the system board SB and the control board CTRB. Figs. 3 and 4 are diagrams showing the sequence of the communication interface shown in Fig. 2. Fig. Since the first to fourth transmission units Tx1 to Tx4 belonging to the first to fourth timing controllers TCON1 to TCON4 communicate with the transmission unit Tx in substantially the same manner, (Rx) are unified and displayed.

Referring to FIG. 2, the system board SB includes a transmission unit Tx, and the timing controller TCON includes a reception unit Rx. The transmitting unit Tx and the receiving unit Rx are interface devices for performing the Vbyone communication protocol. The links of the Vbyone interface connecting the transmitter Tx and the receiver Rx include an auxiliary signal transmission link through which the main link and auxiliary signals LOCKN and HTPDN through which data is transmitted are transmitted.

Referring to FIG. 3, the procedure of transmitting data from the system board SB to the control board CTRB will be described below.

According to the Vbyone interface, after power-on, the receiving unit Rx lowers the HTPDN signal (Hot Plug Detect Signal) to a low potential level (S301).

The transmitting unit Tx transmits the CDR training pattern signal to the receiving unit Rx in response to the low level HTPDN signal (S302)

The receiver Rx includes a CDR circuit (not shown) for restoring the clock. The CDR circuit of the receiver Rx receives the CDR training pattern signal, locks the phase and frequency of the output, and lowers the LOCKN signal to the low potential level. That is, when the CDR training is completed, the first receiving unit Rx1 of the first timing controller TCON1 lowers the LOCKN1 to the low potential level and the second receiving unit Rx2 of the second timing controller TCON2 completes the CDR training LOCKN2 is lowered to a low potential level. Similarly, when the CDR training is completed, the third receiver Rx of the third timing controller TCON3 lowers the LOCKN3 to the low potential level and the fourth receiver Rx4 of the fourth timing controller TCON4 lowers the LOCKN4 To the low potential level (S303).

The timing controller TCON outputs the lock synchronizing signal LOCKNsync in response to the lock signal LOCKN being lowered to the low potential level. That is, the first timing controller TCON1 outputs the first lock synchronous signal LOCKNsync in response to the first lock signal LOCKN1 being lowered to the low potential level, and the second timing controller TCON2 outputs the second lock synchronous signal LOCKNsync, And outputs the second lock synchronization signal LOCKNsync2 in response to the signal LOCKN2 being lowered to the low potential level. Likewise, the third timing controller TCON3 outputs the third lock synchronization signal LOCKNsync3 in response to the third lock signal LOCKN3 being lowered to the low potential level, and the fourth timing controller TCON4 outputs the third lock synchronization signal LOCKNsync3, And outputs the fourth lock synchronization signal LOCKNsync4 in response to the signal LOCKN4 being lowered to the low potential level. Then, the first to fourth timing controllers TCON1 to TCON4 determine whether all the first to fourth lock signals LOCKN1 to LOCKN4 are synchronized (S304)

The first to fourth timing controllers TCON1 to TCON4 transmit the lock synchronization signal LOCKNsync to the high level lock synchronization signal transmission unit Tx when all of the first to fourth lock signals LOCKN are synchronized. )

The transmission unit Tx transmits an Align (ALN) training pattern signal to the reception unit Rx for a predetermined time after receiving the lock synchronization signal LOCKNsync, and then transmits the display data to the display unit. Alignment data (ALNDATA) which is not displayed on the display device is transmitted to the alignment pattern signal. The alignment data (ALNDATA) is determined by the communication protocol of the Vbyone interface, and allows the reception unit (Rx) to determine the data reception start timing. The receiving unit Rx determines the start timing of the pixel data to be displayed on the display panel when the alignment data ALNDATA is received. Pixel data received by the receiving unit Rx following the aligned pattern signal is displayed on the display panel (S306, S307). [

5 is a diagram showing an output terminal of a lock sync signal (LOCKNsync) of the first to fourth timing controllers (TCON). Referring to FIGS. 4 and 5, a process of outputting the lock synchronization signal LOCKNsync will be described.

The receiver Rx1 of the first timing controller TCON1 inverts the first lock signal LOCKN1 to the low potential level when the CDR training is completed. The first timing controller TCON1 outputs the first lock synchronization signal LOCKNsync1 having the high level potential in response to the first lock signal LOCKN having the low potential level.

Likewise, when the CDR training is completed, the second to fourth receiving units Rx2 to Rx4 of the second to fourth timing controllers TCON2 to TCON4 inverts the second to fourth lock signals LOCKN2 to LOCKN4 to a low potential level . The second to fourth timing controllers TCON2 to TCON4 receive the second to fourth lock synchronous signals LOCKNsync2 to LOCKNsync4 having the high level potential corresponding to the second to fourth lock signals LOCKN2 to LOCKN4 having the low potential level Output.

The first to fourth lock synchronization signals LOCKNsync1 to LOCKNsync4 are connected to an open drain using a pull-up resistor Rpu. Therefore, when any one of the first to fourth lock synchronization signals LOCKNsync1 to LOCKNsync4 is at the low potential level, the output of the lock synchronization signal LOCKNsync is maintained at the low potential level. Since the first to fourth lock synchronization signals LOCKNsync1 to LOCKNsync4 are signals indicating that the CDR training is completed in the first to fourth reception units Rx1 to Rx4, if the CDR training is not completed in any one of the reception units, The output of the synchronizing signal LOCKNsync maintains the low potential level.

When all of the first to fourth lock synchronization signals LOCKNsync1 to LOCKNsync4 are at the high level, the timing controller TCON transmits the lock synchronization signal LOCKNsync to the transmission unit Tx. In other words, the timing controller TCON transmits the lock synchronization signal LOCKNsync to the transmission unit Tx when the first to fourth reception units Rx1 to Rx4 complete the CDR training.

As described above, in the display device according to the present invention, when all of the first to fourth receiving units Rx1 to Rx4 complete the CDR training, the transmitting unit Tx transmits the pixel data to the first to fourth receiving units Rx1 to Rx4 It begins to transmit. Therefore, only a part of the receiver Rx completes the CDR training, and valid pixel data is transmitted to all the receivers Rx1 to Rx4, thereby improving the phenomenon of displaying an abnormal screen.

For example, FIG. 6 shows a display device of a comparative example with the present invention, and FIG. 6 shows an example in which a transmitting section provides an ALN training signal when only one receiving section completes CDR training. In the comparative example of FIG. 6, when only the first receiving unit has completed the CDR training and the second to fourth receiving units have not normally completed the CDR training, only the first receiving unit has turned the first lock signal LOCKN1 to the low potential level Lower. If the transmitting unit Tx transmits the valid data to all the receiving units on the basis of the lock signal LOCKN transmitted by any one of the receiving units, the receiving unit that has not normally completed the CDR training performs normal driving can not do it. That is, the first timing controller TCON1 performs normal driving, whereas the second through fourth timing controllers TCON2 through TCON4 do not perform normal driving. Accordingly, the first panel 100-1 displays a normal screen, whereas the second through fourth panels 100-2 through 100-4 fail to display a normal screen. As a result, the display panel 100 is abnormal Display the screen.

On the other hand, according to the present invention, only when the CDR training is completed in all the reception units Rx, the lock synchronization signal LOCKNsync is outputted, and the transmission unit Tx transmits the pixel data based thereon, Can be prevented from being displayed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (5)

A display panel including first to n-th (n is a natural number) panels;
First to n-th timing controllers for independently driving the first to n-th panels, respectively;
A transmitter for transmitting the digital video data displayed on the display panel according to the Vbyone interface standard; And
And first to nth receiving units for performing Vbyone interface communication with the transmitting unit and performing CDR training corresponding to CDR training pattern signals transmitted by the transmitting unit,
Wherein the timing controller outputs a lock synchronization signal (LOCKNsync) to the transmission unit when the first to n < th > receiving units have performed the CDR training. The method according to claim 1,
The i-th (i is a natural number less than or equal to n) receiving unit lowers the i-th lock signal LOCKNi to the low potential level when the CDR training is completed,
And the i-th timing controller outputs the i-th lock synchronizing signal (LOCKNsynci) when the i-th lock signal (LOCKNi) is lowered to the low potential level. The method according to claim 1,
And the lock sync signal output terminals of the first to the n-th timing controllers are connected to each other by an open drain. The method according to claim 1,
And the transmission unit transmits the digital video data to the receiver in response to the lock synchronization signal (LOCKNsync). Transmitting a CDR (Clock Data Recovery) training pattern signal to the receiving units after the physical connection between the transmitting unit and the plurality of receiving units is confirmed;
Performing CDR training in which the receiving units recover the clock from the CDR circuit using the CDR training pattern signal;
Outputting a lock synchronization signal by the receiving units that have completed the CDR training;
Transmitting the lock synchronization signal to the transmission unit when all the reception units output the lock synchronization signal; And
And transmitting the alignment pattern signal to the receiver in response to the lock synchronization signal.

Images