KR102237140B1 - Display Device and Driving Method thereof - Google Patents

Abstract

The display device includes a display panel, first to nth timing controllers, a transmitting unit, and first to nth receiving units. The display panel includes first to nth (n is a natural number) panel. Each of the first to nth timing controllers independently drives the first to nth panels. The transmitter transmits digital video data displayed on the display panel according to the Vbyone interface standard. Each of the first to nth receiving units performs Vbyone interface communication with the transmitting unit, and performs CDR training in response to the CDR training pattern signal transmitted by the transmitting unit. In addition, the timing controller outputs a lock synchronization signal (LOCKNsync) to the transmitter when all of the first to nth receivers perform CDR training.

Description

Display device and driving method thereof TECHNICAL FIELD

The present invention relates to a display device and a driving method thereof.

In the display device, a plurality of source drive integrated circuits (Integrated Circuit hereinafter referred to as "IC") for supplying data voltages to data lines of the display panel, and gate pulses (or scan pulses) are sequentially applied to the gate lines of the display panel. And a plurality of gate drive ICs for supplying to and a timing controller for controlling the drive ICs.

The timing controller is mounted on the control board, and the ICs of the data driving circuit are actually mounted on the source PCB (Printed Circuit Board). FPC (Flexible Printed Circuit) through which digital video data and timing control signals are transmitted is installed between the control board and the source PCB. The control board is connected to the system board through an interface cable. A scaler is mounted on the system board. The scaler converts the resolution of data to match the resolution of the display panel and transmits it to the control board.

The number of interface cables connecting the system board and the control board is determined by the amount of data to be transmitted and clock signals. When driving the current LCD device at Full-HD 120Hz, the interface cable between the system board and the control board requires 48 lines when the LVDS (Low-Voltage Differential Signaling) interface method is applied. Even if the LVDS interface method is applied, the number of interface cables is large, and the number of connector pins for connecting the interface cable to the system board and control board is large. For this reason, the conventional liquid crystal display device has difficulty in cost reduction due to the cost of an interface cable and a connector, and there is a problem of high electromagnetic interference (EMI) due to a high frequency clock signal transmitted through an interface cable. In order to improve this, recently, an interface method having less EMI and a smaller number of transmission lines than LVDS interfaces has been developed.

For example, the Vbyone interface developed by THine Electronics Inc. has improved signal transmission quality compared to the existing LVDS interface due to the introduction of an equalizer function, and has been further accelerated by realizing a maximum speed of 3.75 Gbps per pair. In addition, the Vbyone interface solves the problem of skew adjustment caused by clock transmission of the LVDS interface due to the adoption of CDR (Clock Data Recovery). In addition, the Vbyone interface can reduce EMI noise caused by clock transmission because there is no clock transmission, which was necessary in the existing LVDS. This Vbyone interface is in the spotlight as an alternative technology to the existing LVDS interface because it can effectively cope with the trend of increasing data volume and increasing high speed.

In recent years, ultra-high resolution display devices such as QHD or UHD have appeared. The ultra-high resolution display device includes four panels, and includes a timing controller for driving each of the panels. When the Vbyone interface is used for data transmission in an ultra-high resolution display device, a transmitting unit belonging to a system board communicates independently with a receiving unit formed in each timing controller. In addition, the transmitter transmits pixel data to all receivers when any one receiver completes the data reception preparation. Accordingly, since the receiving unit, which is not ready to receive data, cannot perform normal driving, an abnormal screen is displayed on the panel.

An object of the present invention is to provide a display device for improving the problem of displaying an abnormal screen by receiving data in a state in which some timing controllers cannot operate normally in a display device including a plurality of timing controllers.

A display device according to the present invention includes a display panel, first to nth timing controllers, a transmitter, and first to nth receivers. The display panel includes first to nth (n is a natural number) panel. Each of the first to nth timing controllers independently drives the first to nth panels. The transmitter transmits digital video data displayed on the display panel according to the Vbyone interface standard. Each of the first to nth receiving units performs Vbyone interface communication with the transmitting unit, and performs CDR training in response to the CDR training pattern signal transmitted by the transmitting unit. In addition, the timing controller outputs a lock synchronization signal (LOCKNsync) to the transmitter when all of the first to nth receivers perform CDR training.

In a method of driving a display device according to the present invention, after physical connection between a transmitter and a plurality of receivers is first checked, the transmitter transmits a clock data recovery (CDR) training pattern signal to the receivers. Then, the receivers perform CDR training to restore a clock from the CDR circuit by using the CDR training pattern signal. Subsequently, receiving units that have completed the CDR training output a lock synchronization signal. When all the receivers output the lock synchronization signal, they transmit the lock synchronization signal to the transmitter. Then, in response to the lock synchronization signal, the transmitter transmits an alignment training pattern signal to the receivers.

The present invention receives data from a system board when all timing controllers are ready to receive data, and displays the received data. Accordingly, it is possible to prevent an abnormal image from being displayed on the display panel by receiving and displaying data in a state in which some timing controllers are not normally operable.

1 is a view showing a display device according to the present invention.
2 is a diagram showing a link of a communication interface according to the present invention.
3 to 5 are diagrams for explaining a sequence of a communication interface according to the present invention.
6 is a diagram showing an example of comparison with a sequence of a communication interface according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

The present invention to be described later describes a liquid crystal display device as an example, but the features of the present invention include a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode other than the liquid crystal display device. It may be implemented as a flat panel display device such as an organic light emitting display (OLED).

Referring to FIG. 1, a liquid crystal display device according to the present invention includes a display panel 100, first to fourth control boards CTRB1 to CTRB4, and a system board SB.

The display panel 100 includes first to fourth panels 100-1 to 100 to 4. The liquid crystal cells of the first to fourth panels 100-1 to 100 to 4 are arranged in a matrix form by a cross structure of the data lines DL and the gate lines GL. The lower glass substrate of the display panel 100 is connected to the data lines DL, the gate lines GL, TFTs, and TFTs, and is driven by an electric field between the pixel electrodes 1 and the common electrode 2. Liquid crystal cells Clc, storage capacitors Cst, and the like are formed. A black matrix, a color filter, and a common electrode 2 are formed on an upper glass substrate of the display panel 100. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode. It is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving method. A polarizing plate having an orthogonal optical axis is attached to the upper glass substrate and the lower glass substrate of the display panel 100, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal.

The first control board CTRB1 drives the first display panel 100 and may be implemented as a printed circuit board (PCB) including the first timing controller 100-1.

The first timing controller 100-1 receives Vbyone data from the system board SB and transmits the received data to source drive ICs. Further, the first timing controller generates a data timing control signal for controlling the operation timing of the source drive ICs and a gate timing control signal for controlling the operation timing of the gate drive ICs. The first timing controller TCON1 controls the operation timing of the source drive ICs using timing signals, that is, vertical and horizontal synchronization signals, data enable signals, and dot clocks, and polarity of the data voltage supplied to the display panel 100. In addition to generating a data timing control signal for controlling the signal, a gate timing control signal for controlling the operation timing of the gate drive ICs 151 to 153 is generated.

Data drive ICs and gate drive ICs of the first control board CTRB1 may be mounted together on integrated circuits ICs of a chip-on-film COF. The input terminal of the chip-on film (COF) is bonded to a printed circuit board (PCB), and the output terminal of the COF is bonded to the top of the lower substrate of the display panel (PNL).

Source drive ICs of the first control board CTRB1 receive digital video data from the first control board CTRB1. In addition, the source drive IC converts the data into an analog data voltage in response to a data timing control signal provided from the control board CTRB1 and supplies the data to the data lines DL of the display panel 100.

The gate drive ICs of the first control board CTRB1 generate a gate pulse in response to a gate timing control signal provided from the first control board CTRB1, and sequentially supply the gate pulse to the gate lines.

The second to fourth control boards CTRB2 to CTRB4 are for driving the second to fourth panels 100-2 to 100-4, respectively, and the detailed configuration of the second to fourth control boards CTRB2 to CTRB4 Since is substantially the same as the configuration of the first control board CTRB1, a detailed description will be omitted.

The system board SB converts the resolution of digital video data according to the resolution of the display panel 100 and transmits the digital video data and timing signals according to the Vbyone interface standard.

2 is a diagram showing a communication interface device of a timing controller TCON of a system board SB and a control board CTRB. 3 and 4 are diagrams showing a sequence of the communication interface shown in FIG. 2. Since the first to fourth transmitters Tx1 to Tx4, each belonging to the first to fourth timing controllers TCON1 to TCON4, communicate with the transmitter Tx in a substantially the same manner, FIGS. 2 and 3 are The reference numerals for (Rx) are unified and indicated.

Referring to FIG. 2, the system board SB includes a transmission unit Tx, and the timing controller TCON includes a reception unit Rx. The transmission unit Tx and the reception unit Rx are interface devices for performing the Vbyone communication protocol. Links of the Vbyone interface connecting the transmission unit Tx and the reception unit Rx include a main link through which data is transmitted and an auxiliary signal transmission link through which auxiliary signals LOCKN and HTPDN are transmitted.

Referring to FIG. 3, a procedure of transmitting data from the system board SB to the control board CTRB will be described as follows.

According to the Vbyone interface, after power-on, the receiving unit Rx lowers the HTPDN signal (Hot Plug Detect Signal) to a low potential level (S301).

The transmitter Tx transmits the CDR training pattern signal to the receiver Rx in response to the low-level HTPDN signal (S302).

The receiver Rx has a built-in CDR circuit (not shown) for restoring a clock. The CDR circuit of the receiver Rx receives the CDR training pattern signal, locks the phase and frequency of the output, and lowers the LOCKN signal to a low potential level. That is, when the CDR training is completed, the first receiver Rx1 of the first timing controller TCON1 lowers the LOCKN1 to the low potential level, and the second receiver Rx2 of the second timing controller TCON2 completes the CDR training. Lower LOCKN2 to low potential level. Similarly, when the CDR training is completed, the third receiving unit Rx of the third timing controller TCON3 lowers the LOCKN3 to the low potential level, and the fourth receiving unit Rx4 of the fourth timing controller TCON4 performs LOCKN4 when the CDR training is completed. Is lowered to the low potential level (S303)

The timing controller TCON outputs a lock synchronization signal LOCKNsync in response to the lock signal LOCKN signal being lowered to a low potential level. That is, the first timing controller TCON1 outputs the first lock synchronization signal LOCKNsync in response to the first lock signal LOCKN1 being lowered to the low potential level, and the second timing controller TCON2 outputs the second lock. In response to the signal LOCKN2 being lowered to a low potential level, a second lock synchronization signal LOCKNsync2 is output. Likewise, the third timing controller TCON3 outputs a third lock synchronization signal LOCKNsync3 in response to the third lock signal LOCKN3 being lowered to a low potential level, and the fourth timing controller TCON4 outputs a fourth lock. In response to the signal LOCKN4 being lowered to a low potential level, a fourth lock synchronization signal LOCKNsync4 is output. Then, the first to fourth timing controllers TCON1 to TCON4 determine whether all of the first to fourth lock signals LOCKN1 to LOCKN4 are synchronized (S304).

Then, the first to fourth timing controllers TCON1 to TCON4 transmit the lock synchronization signal LOCKNsync of the high potential level to the transmission unit Tx when all the first to fourth lock signals LOCKN are synchronized (S305). )

Upon receiving the lock synchronization signal LOCKNsync, the transmitter Tx transmits the alignment (ALN) training pattern signal to the receiver Rx for a predetermined time and then transmits display data displayed on the display device. Alignment data ALNDATA that is not displayed on the display device is transmitted to the alignment pattern signal. The alignment data ALNDATA is determined by the communication protocol of the Vbyone interface so that the reception unit Rx determines the start timing of data reception. When the alignment data ALNDATA is received, the receiver Rx determines a start timing of pixel data to be displayed on the display panel. Following the alignment pattern signal, pixel data received by the receiver Rx is displayed on the display panel (S306, S307).

5 is a diagram illustrating an output terminal of a lock synchronization signal LOCKNsync of the first to fourth timing controllers TCON. 4 and 5, a process of outputting a lock synchronization signal (LOCKNsync) will be described as follows.

When the CDR training is completed, the receiver Rx1 of the first timing controller TCON1 inverts the first lock signal LOCKN1 to a low potential level. The first timing controller TCON1 outputs a first lock synchronization signal LOCKNsync1 having a high level potential in response to the first lock signal LOCKN having a low potential level.

Likewise, the second to fourth receivers (Rx2 to Rx4) of the second to fourth timing controllers (TCON2 to TCON4) reverse the second to fourth lock signals (LOCKN2 to LOCKN4) to a low potential level when the CDR training is completed. Let it. The second to fourth timing controllers TCON2 to TCON4 transmit second to fourth lock synchronization signals LOCKNsync2 to LOCKNsync4 of high level potential in response to the second to fourth lock signals LOCKN2 to LOCKN4 of low potential level. Print it out.

The first to fourth lock synchronization signals LOCKNsync1 to LOCKNsync4 are connected through an open drain using a pull-up resistor Rpu. Accordingly, when any one of the first to fourth lock synchronization signals LOCKNsync1 to LOCKNsync4 has a low potential level, the output of the lock synchronization signal LOCKNsync is maintained at the low potential level. Since the first to fourth lock synchronization signals (LOCKNsync1 to LOCKNsync4) are signals indicating that the CDR training has been completed in the first to fourth receivers (Rx1 to Rx4), respectively, the lock is locked if the CDR training is not completed in any one receiver. The output of the synchronization signal (LOCKNsync) maintains a low potential level.

In addition, when all of the first to fourth lock synchronization signals LOCKNsync1 to LOCKNsync4 are at high levels, the timing controller TCON transmits the lock synchronization signal LOCKNsync to the transmitter Tx. In other words, the timing controller TCON transmits the lock synchronization signal LOCKNsync to the transmitter Tx when all of the first to fourth receivers Rx1 to Rx4 have completed CDR training.

As described above, in the display device according to the present invention, when all of the first to fourth receiving units Rx1 to Rx4 have completed CDR training, the transmitting unit Tx transfers the pixel data to the first to fourth receiving units Rx1 to Rx4. Begin to transmit. Accordingly, it is possible to improve a phenomenon in which an abnormal screen is displayed because only some of the receiving units Rx complete the CDR training and valid pixel data is transmitted to all of the receiving units Rx1 to Rx4.

For example, it is a diagram showing a display device of a comparative example with the present invention, and FIG. 6 shows an example in which the transmitter provides an ALN training signal when only one of the receivers has completed CDR training. In the comparative example of FIG. 6, when only the first receiver completes the CDR training and the second to fourth receivers do not normally complete the CDR training, only the first receiver sets the first lock signal LOCKN1 to a low potential level. Lower it. If, as such, if the transmission unit (Tx) transmits the pixel data (valid data) to all the receiving units based on the lock signal (LOCKN) transmitted from one of the receiving units, the receiving unit that does not normally complete the CDR training does not perform normal driving. can not do it. That is, while the first timing controller TCON1 performs normal driving, the second to fourth timing controllers TCON2 to TCON4 cannot perform normal driving. Accordingly, while the first panel 100-1 displays a normal screen, the second to fourth panels 100-2 to 100-4 do not display a normal screen, and as a result, the display panel 100 is abnormal. Display the screen.

In contrast, the present invention outputs a lock synchronization signal (LOCKNsync) only when CDR training is completed in all of the receiving units (Rx), and based on this, the transmitting unit (Tx) transmits pixel data. This can prevent the phenomenon from being displayed.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

Claims (5)

A display panel including first to nth (n is a natural number) panel;
First to nth timing controllers for independently driving the first to nth panels, respectively;
A transmitter for transmitting digital video data displayed on the display panel according to a Vbyone interface standard; And
Each of the transmitting unit and Vbyone interface communication, and including first to n-th receiving units for performing CDR training in response to the CDR training pattern signal transmitted by the transmitting unit,
When all of the first through n-th receiving units perform the CDR training, the transmitting unit receives a lock synchronization signal (LOCKNsync). The method of claim 1,
The i-th (i is a natural number less than or equal to n) receiver lowers the i-th lock signal LOCKNi to a low potential level when the CDR training is completed,
The i-th timing controller outputs an i-th lock synchronization signal LOCKNsynci when the i-th lock signal LOCKNi is lowered to a low potential level. The method of claim 1,
The output terminals of the lock synchronization signal of the first to nth timing controllers are connected to each other through open drain. The method of claim 1,
The display device transmits the digital video data to the receiver in response to the lock synchronization signal (LOCKNsync). Transmitting, by the transmitting unit, a clock data recovery (CDR) training pattern signal to the receiving units after the physical connection between the transmitting unit and the plurality of receiving units is confirmed;
Performing CDR training in which the receivers restore a clock from a CDR circuit using the CDR training pattern signal;
Outputting a lock synchronization signal by the receiving units having completed the CDR training;
When all the receiving units output the lock synchronization signal, transmitting the lock synchronization signal to the transmitting unit; And
And transmitting, by the transmission unit, an alignment training pattern signal to the receiving units in response to the lock synchronization signal.

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