KR102288529B1 - Display device - Google Patents

Abstract

According to the present invention, data transmission and processing are possible based on the EPI transmission protocol, regardless of whether the number of source drive ICs is odd or even, thereby improving the utility of the EPI data transmission method.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device having a new transmission method.

A display device is a device that displays an image or information. Among display devices, a liquid crystal display displays an image by adjusting the light transmittance of liquid crystal using an electric field.

In the liquid crystal display device, a data voltage is supplied to the liquid crystal display panel from a source drive based on a timing control signal provided from a timing controller, and an image is displayed.

The timing controller transmits a plurality of timing control signals and digital video data to the source drive ICs. In this case, R data transmission wiring, G data transmission wiring, B data transmission wiring, control wirings for controlling the operation timing of the output and polarity conversion operation of the source drive ICs, and clock transmission between the timing controller and the source drive ICs A lot of wiring is needed, such as wiring. As an example of RGB data transmission in the mini-LVDS interface method, the mini-LVDS interface method transmits the digital video RGB data and the clock as a differential signal pair that are out of phase with each other, so that the odd data and even data are transmitted at the same time. In this case, at least 14 wires are needed for RGB data transmission between the timing controller and the source drive ICs. Accordingly, it is difficult to reduce the width of a printed circuit board (PCB) disposed between the timing controller and the source drive ICs because many wires must be formed.

SUMMARY OF THE INVENTION The present invention aims to solve the above and other problems.

Another object of the present invention is to provide a display device configured to minimize signal transmission lines between a timing controller and source drive ICs.

Another object of the present invention is to provide a display device that enables data processing based on an EPI protocol transmission method regardless of the number of source drive ICs.

According to one aspect of the present invention to achieve the above or other objects, a display device includes a plurality of source drive ICs. When the total number of the source drive ICs is an odd number, a first output port among a plurality of output ports allocated to the timing controller is connected to the odd number of source drive ICs, and a first output port among the plurality of output ports allocated to the timing controller is an odd number. Two output ports may be connected to the odd number of source drive ICs.

The effects of the terminal according to the present invention will be described as follows.

According to at least one of the embodiments of the present invention, the utility of the EPI data transmission method can be improved by enabling data processing based on the EPI protocol transmission method regardless of whether the number of source driver ICs is even or odd. There is this.

Further scope of applicability of the present invention will become apparent from the following detailed description. However, it should be understood that the detailed description and specific embodiments such as preferred embodiments of the present invention are given by way of illustration only, since various changes and modifications within the spirit and scope of the present invention may be clearly understood by those skilled in the art.

1 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating wirings between the timing controller and source drive ICs shown in FIG. 1 .
3 is a block diagram illustrating a timing controller (TCON) and a source drive IC (SDIC).
FIG. 4 shows a signal transmission protocol between the timing controller shown in FIG. 2 and the source drive ICs.
5 is a block diagram illustrating a liquid crystal display device according to a second embodiment of the present invention.
FIG. 6 is a diagram illustrating wirings between the timing controller and the source drive ICs shown in FIG. 5 .
FIG. 7 is a block diagram illustrating the timing control unit shown in FIG. 5 in detail.
FIG. 8 shows a signal transmission protocol between the timing controller shown in FIG. 6 and source drive ICs.
9 is a block diagram illustrating a liquid crystal display device according to a third embodiment of the present invention.
FIG. 10 is a diagram illustrating wirings between the timing controller and the source drive ICs shown in FIG. 9 .
FIG. 11 shows a signal transmission protocol between the timing controller shown in FIG. 10 and seventh to ninth source drive ICs.
FIG. 12 is a diagram illustrating wirings between a timing controller and source drive ICs in a liquid crystal display according to a fourth exemplary embodiment of the present invention.
13 shows a signal transmission protocol between the timing controller shown in FIG. 12 and seventh to ninth source drive ICs.

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and overlapping descriptions thereof will be omitted. The suffixes "module" and "part" for the components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have a meaning or role distinct from each other by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical spirit disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

1 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 1 , a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel 10, a timing controller TCON, source drive ICs SDIC#1 to SDIC#8, and gate drive ICs ( GDIC#1 to GDIC#4) are provided.

A liquid crystal layer is formed between the glass substrates of the liquid crystal display panel 10 . The liquid crystal display panel 10 includes m×n liquid crystal cells Clc arranged in a matrix form by an intersecting structure of m data lines DL and n gate lines GL.

A pixel array including data lines DL, gate lines GL, TFTs, and a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 10 . The liquid crystal cells Clc are driven by an electric field between the pixel electrode 1 to which the data voltage is supplied through the TFT and the common electrode 2 to which the common voltage Vcom is supplied. The gate electrode of the TFT is connected to the gate line GL, and its source electrode is connected to the data line DL. The drain electrode of the TFT is connected to the pixel electrode 1 of the liquid crystal cell. The TFT is turned on according to a gate pulse supplied through the gate line GL to supply positive/negative analog video data voltage from the data line DL to the pixel electrode 1 of the liquid crystal cell Clc. .

A black matrix, a color filter, and a common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 10 .

The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode and It is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving method.

A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10 , and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed. A spacer for maintaining a cell gap of the liquid crystal cell Clc is formed between the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10 .

The liquid crystal mode of the liquid crystal display panel applicable to the present invention may be implemented in any liquid crystal mode as well as TN mode, VA mode, IPS mode, and FFS mode. In addition, the liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display.

The timing control unit (TCON) provides vertical/horizontal synchronization signals (Vsync, Hsync) and external data enable signals (Data Enable, DE) through interfaces such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling (TMDS) interface. Timing control for controlling the operation timing of the source drive ICs SDIC#1 to SDIC#8 and the gate drive ICs GDIC#1 to GDIC#4 by receiving an external timing signal such as , dot clock CLK, etc. generate signals. The timing control signals are a gate timing control signal for controlling the operation timing of the gate drive ICs GDIC#1 to GDIC#4, and a gate timing control signal for controlling the operation timing of the source drive ICs SDIC#1 to SDIC#8. Includes source control signal.

The timing controller TCON is connected to the source drive ICs SDIC#1 to SDIC#8 in a point-to-point manner, which will be described later. The timing control unit (TCON) transmits a pre-amble signal, a source control signal, a clock, and digital video RGB data to initialize the source drive ICs (SDIC#1 to SDIC#8). to-point Interface) as a data signal and transmitted to the source drive ICs (SDIC#1 to SDIC#8) through one pair of data wires.

This data transmission is based on the EPI protocol transmission method.

EPI (Embedded clock Point-to-point Interface) protocol satisfies the interface regulations of (1) to (3) below.

(1) The transmitting end of the timing controller TCON and the receiving end of the source drive ICs SDIC#1 to SDIC#8 are connected in a point-to-point manner via a pair of data lines.

(2) Do not connect a separate pair of clock wires between the timing controller TCON and the source drive ICs SDIC#1 to SDIC#8. The timing controller TCON transmits a timing control signal and a video data signal along with a clock signal to the source drive ICs SDIC#1 to SDIC#8 through a pair of data lines.

(3) DLL (Delay Locked Loop, hereinafter referred to as DLL) for CDR (Clok and Data Recovery) is built in each of the source drive ICs (SDIC#1 to SDIC#8). The timing controller TCON transmits a preamble signal (also called a clock training signal) to the source drive ICs SDIC#1 to SDIC#8 so that the output phase and frequency of the DLL can be locked. The DLL built in the source drive ICs (SDIC#1 to SDIC#8) generates an internal clock when the preamble signal and the clock signal are input through the data wire pair after the phase of the output is fixed.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the first gate drive IC GDIC#1. The gate start pulse GSP indicates a start time at which the scan starts so that the first gate pulse is generated from the first gate drive IC GDIC#1. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The shift registers of the gate drive ICs GDIC#1 to GDIC#4 shift the gate start pulse GSP at the rising edge of the gate shift clock GSC. The second to fourth gate drive ICs GDIC#1 to GDIC#4 receive the carry signal of the previous gate drive IC as a gate start pulse and start to operate. The gate output enable signal GOE controls output timing of the gate drive ICs GDIC#1 to GDIC#4. The gate drive ICs GDIC#1 to GDIC#4 output gate pulses during the low level period of the gate output enable signal GOE, that is, from immediately after the falling time of the previous pulse to immediately before the rising time of the next pulse. do.

One period of the gate output enable signal GOE is approximately one horizontal period.

The source control signal is transmitted to the source drive ICs (SDIC#1 to SDIC#8) through the data wire pair during the time between the preamble signal transmission time and the RGB data signal transmission time, and includes control data related to polarity control and the source output. and related control data. The polarity control related control data includes control information for controlling a polarity control signal (POL) in the form of a pulse generated in the source drive ICs SDIC#1 to SDIC#8. The digital to analog converter (hereinafter referred to as "DAC") of the source drive ICs (SDIC#1 to SDIC#8) converts digital video RGB data to positive analog video in response to a polarity control signal (POL). Converts data voltage or negative analog video data voltage. The source output related control data includes control information for controlling a source output enable signal (SOE) in the form of a pulse generated in the source drive ICs. The source output enable signal SOE controls the timing at which positive/negative analog video data voltages are output from the source drive ICs SDIC#1 to SDIC#8.

Each of the gate drive ICs GDIC#1 to GDIC#4 sequentially supplies a gate pulse to the gate lines GL in response to gate timing control signals.

The source drive ICs SDIC#1 to SDIC#8 lock the output frequency and phase of the built-in data sampling unit according to the preamble signal supplied from the timing controller TCON through the data line pair. Subsequently, after the output frequency and phase of the data sampling unit are fixed, the source drive ICs SDIC#1 to SDIC#8 restore a clock from a source control packet input as a digital bit stream through the pair of data lines to obtain a serial clock. and sample the control data related to the source output. In addition, the source drive ICs SDIC#1 to SDIC#8 output a polarity control signal POL and a source output enable signal SOE using control data.

After restoring the polarity control signal POL and the source output enable signal SOE, the source drive ICs SDIC#1 to SDIC#8 receive data from the RGB data packet input as a digital bit stream through the pair of data lines. Extracts digital video RGB data, and samples the digital video RGB data according to the serial clock extracted and generated from the source control packet. In addition, the source drive ICs (SDIC#1 to SDIC#8) convert the sequentially sampled digital video RGB data into a parallel system and then convert the data into positive/negative analog video data in response to the polarity control signal (POL). It is converted into a voltage and supplied to the data lines DL in response to the source output enable signal SOE.

FIG. 2 is a diagram illustrating wirings between the timing controller and source drive ICs shown in FIG. 1 .

Referring to FIG. 2 , between the timing controller TCON and the source drive ICs SDIC#1 to SDIC#8, a data wire pair (DATA&CLK), a control wire pair (SCL/SDA), a lock check wire (LCS), etc. wirings are formed.

At least as many ports as the number of source drive ICs SDIC#1 to SDIC#8 may be allocated to the timing controller TCON. Accordingly, each port of the timing controller TCON and each of the source driver ICs SDIC#1 to SDIC#8 may be connected 1:1.

The timing controller TCON sequentially transmits the preamble signal, the source control packet, and the RGB data packet to the source drive ICs SDIC#1 to SDIC#8 through the data line pair DATA&CLK. The source control packet is a bit stream including clock bits, polarity control related control data bits, and source output related control data. An RGB data packet is a bit stream containing clock bits, internal data enable bits, RGB data bits, and the like. The data line pair DATA&CLK serially connects the timing controller TCON to each of the source drive ICs SDIC#1 to SDIC#8 in a 1:1, that is, a point-to-point method. Each of the source drive ICs SDIC#1 to SDIC#8 restores clocks input through the data line pair DATA&CLK. Accordingly, there is no need for a wire for transferring the clock carry and RGB data between the neighboring source drive ICs SDIC#1 to SDIC#8.

The timing controller TCON controls the chip identification code (CID) of the source drive ICs SDIC#1 to SDIC#8 and individual chip control for controlling each function of the source drive ICs SDIC#1 to SDIC#8. Data is transmitted to the source drive ICs SDIC#1 to SDIC#8 through the control wire pair (SCL/SDA). The control wiring pair SCL/SDA is commonly connected between the timing controller TCON and the source drive ICs SDIC#1 to SDIC#8. A detailed description of the individual chip control data will be described later.

The timing controller TCON transmits a lock signal LOCK for checking whether the output of the data sampling unit of the source drive ICs SDIC#1 to SDIC#8 is stably fixed through the lock check wire LCS1. It is supplied to the source drive IC (SDIC#1). The source drive ICs SDIC#1 to SDIC#8 are connected in a cascade through wires for transmitting the lock signal LOCK. When the frequency and phase of the clock output for data sampling are fixed, the first source drive IC (SDIC#1) transmits a high-level lock signal (LOCK) to the second source drive IC (SDIC#2), and the second source The drive IC (SDIC#2) transfers the high-level lock signal LOCK to the second source drive IC (SDIC#2) after fixing the frequency and phase of the DLL output clock. In this way, after the clock output frequency and phase of the source drive ICs (SDIC#1 to SDIC#8) are fixed, when the clock output frequency and phase of the last source drive IC (SDIC#8) are fixed, the last source drive IC (SDIC# 8) feedback-inputs the high level lock signal LOCK to the timing controller TCON through the feedback lock check line LCS2. After receiving the feedback input of the lock signal LOCK, the timing controller TCON transmits a source control packet and an RGB data packet to the source drive ICs SDIC#1 to SDIC#8.

3 is a block diagram illustrating a timing controller (TCON) and a source drive IC (SDIC). The source drive IC SDIC shown in FIG. 3 means any one of the source drive ICs SDIC#1 to SDIC#8.

Referring to FIG. 3 , the timing controller TCON receives digital video data RGB of an input image from a host system through an LVDS interface or a TMDS interface. The timing controller TCON generates a timing control signal including a source control signal and a gate timing control signal based on an external timing signal input from the host system. The timing controller (TCON) controls a preamble signal, a source control signal, a clock, digital video RGB data, etc. for initializing the source drive ICs SDIC#1 to SDIC#8 in order to satisfy the EPI interface protocol. As an EPI data signal, it is transmitted to the source drive ICs SDIC#1 to SDIC#8 through one data line pair DATA&CLK. The timing controller TCON generates serialized clocks having n (2≤n<k) phases and having a frequency 'k/n' times faster than the data clock input from the host system, and using the serialized clocks It serializes digital video data (RGB) at a frequency that is 'k' times faster than the data clock. Here, 'k' is determined as a value obtained by dividing the number of bits of one packet data including digital video data (RGB) by two. The timing controller TCON transmits the serialized serial data RGB as an EPI data signal converted into a difference signal pair. The difference signal pair is transmitted through the data wire pair DATA&CLK.

The source drive IC SDIC receives the EPI data signal transmitted from the timing controller TCON through the data line pair DATA&CLK.

The source drive IC (SDIC) includes a data receiving unit 4 , a data sampling unit 21 , a Digital-to-Analog Converter (DAC) 22 , and an output circuit 23 .

An operation of the data receiving unit 4 will be described with reference to FIG. 4 .

As shown in FIG. 4 , the EPI data signal may be divided into a first stage including the preamble signal, a second stage including the source control packet, and a third stage including the RGB data packet.

The data receiving unit 4 extracts the preamble signal from the EPI data signal provided through the data line pair DATA&CLK from the timing control unit TCON in the first step Phase 1, and outputs the DLL according to the extracted preamble signal. The phase and frequency of the clock are fixed, and in the second step (Phase 2), the polarity control related control data and the source output related control data are separated from the source control packet of the EPI data signal, and based on the polarity control related control data, the polarity control signal ( POL) and generates a source output enable signal SOE based on the source output related data. The polarity control signal POL may be supplied to the DAC 22 and the source output enable signal SOE may be supplied to the output circuit 23 .

The data receiver 4 checks whether the DLL output clock is stably fixed by using the lock signal LOCK provided from the timing controller TCON through the lock check line LCS1. When the DLL output clock is stably fixed, a high-level lock signal LOCK is output, otherwise, a low-level lock signal LOCK is output.

Whether or not the corresponding source drive ICs SDIC#1 to SDIC8 is abnormal may be checked through the state (level) of the lock signal LOCK output from each of the source drive ICs SDIC#1 to SDIC8.

Meanwhile, the data receiver 4 may extract a clock from the source control packet of the EPI data signal and generate a serial clock based on the clock according to the reference clock signal generated in the first step. This serial clock may be supplied to the data sampling unit.

The data receiving unit 4 extracts the digital video RGB data signal from the RGB data packet of the EPI data signal in the third step (Phase 3) and supplies it to the data sampling unit 21 .

The data sampling unit 21 samples and latches each bit of RGB data serially input through the data line pair DATA&CLK according to the serial clock, and then outputs the latched data at the same time to generate the serial transmission data system in parallel transmission data. convert to system

The DAC 22 converts the digital video RGB data from the data sampling unit 21 into a positive gamma compensation voltage GH or a negative gamma compensation voltage GL in response to the polarity control signal POL, and converts the digital video RGB data to a positive polarity/ Converts to negative analog video data voltage.

The output circuit 23 supplies a charge share voltage or a common voltage Vcom to the data lines D1 to Dk through an output buffer during the high level period of the source output enable signal SOE. Also, the output circuit 23 supplies the positive/negative analog video data voltage to the data lines D1 to Dk through the output buffer during the low level period of the source output enable signal SOE. The charge share voltage is generated when the data line to which the positive voltage is supplied and the data line to which the negative voltage is supplied are short-circuited, and has an average voltage level of the positive voltage and the negative voltage.

5 is a block diagram illustrating a liquid crystal display device according to a second embodiment of the present invention.

The second embodiment is almost the same as the first embodiment except that two or more source drive ICs are connected to each port of the timing controller TCON. Accordingly, in the second embodiment, the same reference numerals are assigned to components having the same functions as those of the first embodiment.

As shown in FIG. 5 , each port P1 to P4 of the timing controller TCON may be commonly connected to two source drive ICs. For example, the first port P1 of the timing controller TCON is connected to the first and second source drive ICs SDIC#1 and SDIC#2, and the second port P2 of the timing controller TCON is connected to the first and second source drive ICs SDIC#1 and SDIC#2. It may be connected to the third and fourth source drive ICs SDIC#3 and SDIC#4. The third port P3 of the timing controller TCON is connected to the fifth and sixth source drive ICs SDIC#5 and SDIC#6, and the fourth port P4 of the timing controller TCON is connected to the seventh and eighth source drive ICs SDIC#7 and SDIC#8.

In the present invention, for convenience of explanation, it is described that two source drive ICs SDIC#1 to SDIC#8 are connected to each port P1 to P4 of the timing controller TCON, but the present invention is not limited thereto. As described above, two or more source drive ICs SDIC#1 to SDIC#8 may be connected to each port P1 to P4 of the timing controller TCON.

As shown in FIG. 6 , the timing controller TCON is mounted on a printed circuit board (hereinafter referred to as a PCB, 30), and the first to eighth source drive ICs SDIC#1 to SDIC#8 are connected to the board. It may be mounted on the film 32 . The board may be a chip on board (COB), and the film may be a chip on film (COF).

As shown in FIG. 7 , the timing controller TCON may include a receiver 42 , a receiver 44 , a data aligner 46 , and a transmitter 48 .

The receiver 42 may receive video data RGB and a timing signal from an external system, and transmit the video data RGB to the data aligner 46 . The timing signal received through the receiving unit 42 may be directly transmitted from the receiving unit 42 to the receiving unit 44 , or may be transmitted to the receiving unit 44 through the data alignment unit 46 .

The receiver 44 uses the timing signal received from the receiver 42 to control the timing of the gate drive ICs GDIC#1 to GDIC#4, and a gate control signal to control the timing of the gate drive ICs and the source drive ICs SDIC#1 to SDIC. A gate control signal to control the timing of #8) can be generated.

When the respective ports P1 to P4 of the transmitter 48 are commonly connected to the two source drive ICs SDIC#1 to SDIC#8, the receiving unit 44 is a source drive IC from which the image data group is to be received. In order to identify the SDIC#1 to SDIC#8, selection signals to be inserted between the image data groups to be transmitted for each of the source drive ICs SDIC#1 to SDIC#8 may be generated. Each image data group may include image data for one line.

The image data group refers to a bundle of image data to be transmitted to each of the source drive ICs SDIC#1 to SDIC#8.

The selection signal refers to a signal for distinguishing the two source drive ICs SDIC#1 to SDIC#8 connected to one port P1 to P4 of the transmitter 48 from each other.

That is, the receiver 44 may generate a first selection signal to be matched with the first image data group Active Data#1 to be transmitted to the first source drive IC SDIC#1. In the same way, the receiver 44 may generate second to eighth selection signals SEL2 to SEL8 to be transmitted to the second to eighth source drive ICs SDIC#2 to SDIC#8.

The data aligning unit 46 may align the video data RGB received through the receiving unit 42 according to the size and structure of the liquid crystal display panel 10 to output the aligned image data.

The transmitter 48 may include a plurality of ports P1 to P4 allocated to transmit video data RGB and a control signal to the plurality of source drive ICs SDIC#1 to SDIC#8.

When one port is connected to two source drive ICs, the transmitter 48 corresponds to the two image data groups to be transmitted to the two source drive ICs connected to the one port through the one port. can be output to two source drive ICs.

The transmitter 48 may insert the selection signals between the image data groups to be transmitted for each of the source drive ICs SDIC#1 to SDIC#8, and then output them through the corresponding ports P1 to P4.

The selection signals may be transmitted from the receiver 44 to the transmitter 48 to identify the source drive ICs SDIC#1 to SDIC#8. That is, when one port of the transmitter 48 is connected to two source drive ICs, the receiver 44 intervenes between the image data groups to be transmitted for each of the two source drive ICs in order to identify the two source drive ICs. Selection signals to be inserted may be generated and transmitted to the transmitter 48 .

As shown in FIG. 8 , the first port P1 of the transmitter includes a pre-amble signal, a source control signal CTR, a first selection signal SEL#1, and a first image data group Active. Data#1), the second selection signal SEL#2, and the second image data group Active Data#2 may be sequentially output.

Although not shown, in the same manner, the pre-amble signal (Pre-amble), the source control signal (CTR), the third selection signal (SEL#3), and the third image data group (Active Data#1) are sent to the second port P2 in the same manner. ), the fourth selection signal SEL#4, and the fourth image data group Active Data#4 may be sequentially output. Subsequently, to the third port P3, the preamble signal, the source control signal CTR, the fifth selection signal SEL#5, the fifth image data group Active Data#5, and the sixth selection signal SEL#6 ) and the sixth image data group (Active Data #6) may be sequentially output. Subsequently, to the fourth port P4 , the preamble signal, the source control signal CTR, the seventh selection signal SEL#7, the seventh image data group Active Data#7, and the eighth selection signal SEL#8 ) and the eighth image data group (Active Data #8) may be sequentially output.

On the other hand, when the ports P1 to P4 are commonly connected to the two source drive ICs SDIC#1 to SDIC#8, the driving frequency of the transmitter 48 is determined by the ports P1 to P4 as the source drive ICs. It may be set to be greater than the driving frequency of the transmitter when connected in a one-to-one manner to a multiple corresponding to the number of source drive ICs SDIC#1 to SDIC#8 connected to one port.

For example, when one source drive IC is connected to one port, when the transmitter 48 is driven at 100 Hz to transmit image data to the source drive IC, two The source drive ICs SDIC#1 to SDIC#8 are connected, and the first selection signal SEL#1, the first image data group Active Data#1, the second selection signal SEL#2 and When the second image data group (Active Data #2) is output, the driving frequency of the transmitter 48 may be driven at 200 Hz, twice 100 Hz.

If three source drive ICs are connected to one port, the first selection signal SEL#1, the first image data group Active Data#1, the second selection signal SEL#2, the second When the image data group (Active Data #2), the third selection signal, and the third image data group are output, the driving frequency of the transmitter 48 may be driven at 300 Hz, which is three times 100 Hz.

The driving method of the timing control unit TCON configured as described above is as follows.

First, as described above, when two source drive ICs are commonly connected to each port of the timing controller TCON, the receiver 44 of the timing controller TCON includes two source drive ICs connected to one port. It is possible to generate two selection signals to identify them.

Next, the data arranging unit 46 of the timing controller TCON may generate two image data groups to be transmitted to the two source drive ICs SDIC#1 to SDIC#8 connected to one port.

Here, each of the two image data groups refers to a bundle of image data to be transmitted to any one source drive IC. The image data group is a term defined for convenience of description, and a special process for creating the image data group is not performed. That is, image data to be transmitted to any one source drive IC among the image data generated by the data alignment unit 46 may be defined as one image data group.

Finally, the transmitter 48 of the timing controller TCON may insert a corresponding selection signal between the two image data groups and output the selected signal through the port.

Meanwhile, referring again to FIG. 6 , two source drive ICs SDIC#1 to SDIC#8 may be connected to each port P1 to P4 allocated to the timing controller TCON.

That is, the first port P1 is connected to the first and second source drive ICs SDIC#1 and SDIC#2, and the second port P2 is connected to the third and fourth source drive ICs SDIC#. 3, SDIC#4) can be connected. The third port P3 is connected to the fifth and sixth source drive ICs SDIC#5 and SDIC#6, and the fourth port P4 is connected to the seventh and eighth source drive ICs SDIC#7, SDIC#8).

In this case, the first and second selection signals SEL#1 and SEL#2 to the transmitter 48 of the timing controller TCON, and the first and second source drives connected to the first port P1 The first and second image data groups Active Data#1 and Active Data#2 to be transmitted to the ICs SDIC#1 and SDIC#2 may be received. The transmitter 48 selects the first selection signal SEL#1 and outputs it to the first and second source drive ICs SDIC#1 and SDIC#2, and then the first image data group Active Data# 1) may be output to the first and second source drive ICs SDIC#1 and SDIC#2. The first and second source drive ICs SDIC#1 and SDIC#2 may check whether the value of the first selection signal SEL#1 is an identification value assigned to them. For example, when the first selection signal SEL#1 is an identification value for the first source drive IC SDIC#1, the first source drive IC SDIC#1 is the first image data group Active Data#1 ) is processed and supplied to the liquid crystal display panel 10, whereas in the second source drive IC (SDIC#2), since the first selection signal SEL#1 is not an identification value for itself, the first image data group ( Active Data#1) is not processed.

Next, the transmitter 48 selects the second selection signal SEL#2 and outputs it to the first and second source drive ICs SDIC#1 and SDIC#2, followed by the second image data group Active DataD2) may be output to the first and second source drive ICs SDIC#1 and SDIC#2. The first and second source drive ICs SDIC#1 and SDIC#2 may check whether the value of the second selection signal SEL#2 is an identification value assigned to them. For example, when the second selection signal SEL#2 is an identification value for the second source drive ICs SDIC#1 and SDIC#2, the second source drive ICs SDIC#1 and SDIC#2 are While the second image data group (Active Data#2) is processed and supplied to the liquid crystal display panel 10, the first source drive ICs SDIC#1 and SDIC#2 receive the second selection signal SEL#2. Since it is not an identification value for itself, the second image data group (Active Data #2) is not processed.

In the same way, the transmitter 48 transmits the third selection signal SEL#3 and the third image data group Active Data#3 to the third and fourth source drive ICs SDIC#3 and SDIC#4. and output the fourth selection signal SEL#4 and the fourth image data group Active Data#4 to the third and fourth source drive ICs SDIC#3 and SDIC#4. The third source drive IC (SDIC#3) processes the third image data group (Active Data#3) based on the value of the third selection signal (SEL#3), and the fourth source drive IC (SDIC#4) may process the fourth image data group Active Data#4 based on the value of the fourth selection signal SEL#4.

The transmitter 48 outputs the fifth selection signal SEL#5 and the fifth image data group Active Data#5 to the fifth and sixth source drive ICs SDIC#5, SDIC#6, The sixth selection signal SEL#6 and the sixth image data group Active Data#6 may be output to the fifth and sixth source drive ICs SDIC#5 and SDIC#6. The fifth source drive IC (SDIC#5) processes the fifth image data group (Active Data#5) based on the value of the fifth selection signal (SEL#5), and the sixth source drive IC (SDIC#6) may process the sixth image data group Active Data #6 based on the value of the sixth selection signal SEL#6.

The transmitter 48 outputs the seventh selection signal SEL#7 and the seventh image data group Active Data#7 to the seventh and eighth source drive ICs SDIC#7 and SDIC#8, The eighth selection signal SEL#8 and the eighth image data group Active Data#8 may be output to the seventh and eighth source drive ICs SDIC#7 and SDIC#8. The seventh source drive IC (SDIC#7) processes the seventh image data group (Active Data#7) based on the value of the seventh selection signal (SEL#7), and the eighth source drive IC (SDIC#8) may process the eighth image data group Active Data#8 based on the value of the eighth selection signal SEL#8.

9 is a block diagram illustrating a liquid crystal display device according to a third embodiment of the present invention.

The third embodiment is almost similar to the second embodiment ( FIGS. 5 to 8 ) except that the total number of the source drive ICs SDIC#1 to SDIC#9 is odd. That is, in the third embodiment, compared to the second embodiment, the ninth source drive IC (SDIC#9) may be further added. Accordingly, in the third embodiment, the same reference numerals are given to components having the same functions as those of the second embodiment, and detailed descriptions thereof will be omitted.

As shown in FIG. 9 , first to ninth source driver ICs SDIC#1 to SDIC#9 may be disposed between the timing controller TCON and the liquid crystal display panel.

The timing controller TCON shown in FIG. 9 may include a receiver 42 , a receiver 44 , a data aligner 46 , and a transmitter 48 , as shown in FIG. 7 .

In this case, the first to sixth source drive ICs SDIC#1 to SDIC#6 may be commonly connected to one port of the timing controller TCON in pairs. That is, the first port P1 of the timing controller TCON is commonly connected to the first and second source drive ICs SDIC#1 and SDIC#2, and the second port P2 of the timing controller TCON is connected in common. ) is commonly connected to the third and fourth source drive ICs SDIC#3 and SDIC#4, and the third port P3 of the timing controller TCON is connected to the fifth and sixth source drive ICs SDIC. #5, SDIC#6) may be commonly connected.

All of the seventh to ninth source drive ICs SDIC#7 to SDIC#9 may be commonly connected to one port of the timing controller TCON. That is, the fourth port P4 of the timing controller TCON is commonly connected to the seventh to ninth source drive ICs SDIC#7 to SDIC#9 and the fifth port P5 of the timing controller TCON is connected to the fifth port P5 of the timing controller TCON. Also, it may be commonly connected to the seventh to ninth source drive ICs SDIC#7 to SDIC#9.

The first half image data among the image data for one line of the image data group is transferred to the seventh to ninth source drive ICs SDIC#7 to SDIC#9 through the fourth port P4 of the timing controller TCON. are sequentially output, and the second half image data among the image data corresponding to one line of the image data group is transmitted to the seventh to ninth source drive ICs SDIC#7 through the fifth port P5 of the timing controller TCON. ~SDIC#9) can be output sequentially.

The first to fifth ports P1 to P5 may be allocated to the transmitter 48 of the timing controller TCON.

In this case, each of the seventh to ninth source drive ICs SDIC#7 to SDIC#9 processes the first half image data among the image data corresponding to one line of the image data group to process the seventh to ninth source drive ICs. are supplied and displayed to the first half area of the corresponding display area of the liquid crystal display panel 10 connected to each of the SDIC#7 to SDIC#9, and the seventh to ninth source drive ICs SDIC#7 to SDIC# 9) Each of the liquid crystal display panel 10 connected to each of the seventh to ninth source drive ICs SDIC#7 to SDIC#9 by processing the second half image data among the image data for one line of the image data group may be supplied and displayed to the second half area of the corresponding display area.

More specifically, as shown in FIG. 11 , the fourth port P4 of the timing controller TCON includes a pre-amble signal, a source control signal CTR, and a seventh selection signal SEL. #7), the seventh image data group (Active Data#7), the eighth selection signal SEL#8, the eighth image data group (Active Data#8), the ninth selection signal SEL#9, and the ninth An image data group (Active Data #9) may be sequentially output.

In addition, the fifth port P5 of the timing controller TCON includes a pre-amble signal, a source control signal CTR, a tenth selection signal SEL#10, and a tenth image data group (Active Data#). 10), the eleventh selection signal SEL#11, the eleventh image data group (Active Data#11), the twelfth selection signal SEL#12, and the twelfth image data group (Active Data#12) are sequentially output can be

Here, each of the seventh to twelfth image data groups (Active Data #7 to Active Data #12) may have half of image data for one line.

The seventh source drive IC (SDIC#7) divides the seventh image data group (Active Data#7) having the first half image data and the tenth image data group (Active Data#10) having the second half image data into one. The image data group for each line may be processed, for example, converted into analog data voltage and supplied to the liquid crystal display panel 10 .

The eighth source drive IC (SDIC#8) divides the eighth image data group (Active Data#8) having the first half image data and the eleventh image data group (Active Data#11) having the second half image data into one. It can be processed as a group of image data for lines.

The ninth source drive IC (SDIC#9) divides the ninth image data group (Active Data#9) having the first half image data and the twelfth image data group (Active Data#12) having the second half image data into one. It can be processed as a group of image data for lines.

If the seventh selection signal SEL#7 and the seventh image data group Active Data#7 are supplied to the seventh to ninth source drive ICs SDIC#7 to SDIC#9, the seventh source drive The IC (SDIC#7) recognizes that the seventh selection signal SEL#7 is an identification value assigned to it and processes the seventh image data group (Active Data#7) according to the recognition result, but the eighth and ninth The source drive ICs SDIC#8 and SDIC#9 recognize that the seventh selection signal SEL#7 is not an identification value assigned to them and do not process the seventh image data group Active Data#7. .

Similarly, if the eighth selection signal SEL#8 and the eighth image data group Active Data#8 are supplied to the seventh to ninth source drive ICs SDIC#7 to SDIC#9, the eighth The source drive IC (SDIC#8) recognizes that the eighth selection signal (SEL#8) is an identification value assigned to it and processes the eighth image data group (Active Data#8) according to the recognition result, but the seventh and The ninth source drive ICs (SDIC#7, SDIC#9) recognize that the eighth selection signal SEL#8 is not an identification value assigned to them and do not process the eighth image data group (Active Data#8). won't

In the same manner, the seventh to ninth source driver ICs SDIC#7 to SDIC#9 receive the ninth to twelfth image data groups (Active Data#) suitable for themselves according to the identification values of the ninth to twelfth selection signals. 9~Active Data#12) can be processed.

Although not shown, the data transmission protocol of the EPI data signal output to the first port P1 of the timing controller TCON is the same as that shown in FIG. 8 .

Although not shown, the transmission protocol of the EPI data signal output to the second port P2 of the timing controller TCON includes a pre-amble signal, a source control signal CTR, and a third selection signal SEL#3. ), a third image data group (Active Data#3), a fourth selection signal (SEL#4), and a fourth image data group (Active Data#4) may be included.

Although not shown, the transmission protocol of the EPI data signal output to the third port P3 of the timing controller TCON includes a pre-amble signal, a source control signal CTR, and a fifth selection signal SEL#5. ), a fifth image data group (Active Data #5), a sixth selection signal SEL#6, and a sixth image data group (Active Data #6) may be included.

Here, each of the first to sixth image data groups (Active Data#1 to Active Data#6) may have image data corresponding to one line.

As described above, since each of the seventh to twelfth image data groups (Active Data #7 to Active Data#12) has half of image data for one line, the seventh to twelfth image data groups (Active Data#) Each of 7 to Active Data#12) may have data corresponding to half of each of the first to sixth image data groups (Active Data#1 to Active Data#6).

According to the third embodiment of the present invention, by connecting each of the fourth and fifth ports P4 and P5 of the timing controller TCON to an odd number of source drive ICs SDIC#7 to SDIC#9, the source Even when the number of driver ICs SDIC#1 to SDIC#9 is odd, data transmission and data processing based on the EPI protocol transmission method are possible.

FIG. 12 is a diagram illustrating wirings between the timing controller TCON and source drive ICs in the liquid crystal display according to the fourth exemplary embodiment of the present invention.

In the fourth embodiment, an odd number of source drive ICs SDIC#1 to SDIC#9 may be provided in the same manner as in the third embodiment. In addition, in the third embodiment, an odd number of source drive ICs SDIC#1 to SDIC#9 to process the image data group (Active Data#1 to Active Data#9) are selected by software, while the fourth In the embodiment, an odd number of source drive ICs SDIC#1 to SDIC#9 to process the image data group Active Data#1 to Active Data#9 may be selected in hardware.

The timing controller TCON shown in FIG. 12 may include a receiver 42 , a receiver 44 , a data aligner 46 , and a transmitter 48 as shown in FIG. 7 .

Referring to FIG. 12 , first to fifth demultiplexers DEMUX#1 to DEMUX#5 are disposed between the timing controller TCON and the first to ninth source drive ICs SDIC#1 to SDIC#9. can

The first to fifth demultiplexers DEMUX#1 to DEMUX#5 may be disposed on the printed circuit board 30, but is not limited thereto.

For example, the first input terminal of the first demultiplexer DEMUX#1 is connected to the first output port P1 of the timing controller TCON, and the second input terminal is connected to the first control port P11 of the timing controller TCON. connected, and the first and second output terminals may be commonly connected to the first and second source drive ICs SDIC#1 and SDIC#2. The first demultiplexer DEMUX#1 sequentially from the first output port P1 of the timing controller TCON according to the first selection control signal S1 output from the first output port P1 of the timing controller TCON The timing controller TCON so as to supply each of the first and second image data groups (Active Data#1, Active Data#2) output to the first and second source drive ICs SDIC#1 and SDIC#2 The first output port P1 of the may be selectively connected to the first and second source drive ICs SDIC#1 and SDIC#2. For example, when the first selection control signal S1 is 0, the first output port P1 of the timing controller TCON is connected to the first source drive IC SDIC#1 and is output from the first output port P1. The output first image data group Active Data#1 may be supplied to the first source drive IC SDIC#1. For example, when the first selection control signal S1 is 1, the first output port P1 of the timing controller TCON is connected to the second source drive IC SDIC#2 and is output from the first output port P1. The output second image data group Active Data#2 may be supplied to the second source drive IC SDIC#2.

For example, the first input terminal of the second demultiplexer DEMUX#2 is connected to the second output port P2 of the timing controller TCON, and the second input terminal is connected to the second control port P22 of the timing controller TCON. connected, and the first and second output terminals may be commonly connected to the third and fourth source drive ICs SDIC#3 and SDIC#4. The second demultiplexer DEMUX#2 sequentially from the second output port P2 of the timing controller TCON according to the second selection control signal S2 output from the second output port P2 of the timing controller TCON The timing controller TCON so as to supply the third and fourth image data groups (Active Data#3, Active Data#4) output to the third and fourth source drive ICs SDIC#3 and SDIC#4, respectively. The second output port P2 of the may be selectively connected to the third and fourth source drive ICs SDIC#3 and SDIC#4. For example, when the second selection control signal S2 is 0, the second output port P2 of the timing control unit TCON is connected to the third source drive IC SDIC#3 and is output from the second output port P2. The output third image data group (Active Data#3) may be supplied to the third source drive IC (SDIC#3). For example, when the second selection control signal S2 is 1, the second output port P2 of the timing controller TCON is connected to the fourth source drive IC SDIC#4 to be output from the second output port P2. The output fourth image data group Active Data#4 may be supplied to the fourth source drive IC SDIC#4.

For example, the first input terminal of the third demultiplexer DEMUX#3 is connected to the third output port P3 of the timing controller TCON, and the second input terminal is connected to the third control port P33 of the timing controller TCON. connected, and the first and second output terminals may be commonly connected to the fifth and sixth source drive ICs SDIC#5 and SDIC#6. The third demultiplexer DEMUX#3 sequentially from the third output port P3 of the timing controller TCON according to the third selection control signal S3 output from the third output port P3 of the timing controller TCON The timing controller TCON so as to supply the fifth and sixth image data groups (Active Data#5, Active Data#6) output to the fifth and sixth source drive ICs SDIC#5 and SDIC#6, respectively. The third output port P3 of the may be selectively connected to the fifth and sixth source drive ICs SDIC#5 and SDIC#6. For example, when the third selection control signal S3 is 0, the third output port P3 of the timing controller TCON is connected to the fifth source drive IC SDIC#5 and is output from the third output port P3. The output fifth image data group Active Data#5 may be supplied to the fifth source drive IC SDIC#5. For example, when the third selection control signal S3 is 1, the third output port P3 of the timing controller TCON is connected to the sixth source drive IC SDIC#6 and is output from the third output port P3. The output sixth image data group Active Data#6 may be supplied to the sixth source drive IC SDIC#6.

As described above, since each of the first to third selection control signals S1 to S3 selects two source drive ICs, they may have 1 bit, that is, 0 or 1, but is not limited thereto.

For example, the first input terminal of the fourth demultiplexer DEMUX#4 is connected to the fourth output port P4 of the timing controller TCON, and the second input terminal is connected to the fourth control port P44 of the timing controller TCON. connected, and the first and second output terminals may be commonly connected to the seventh to ninth source drive ICs SDIC#7 to SDIC#9. The fourth demultiplexer DEMUX#4 sequentially from the fourth output port P4 of the timing controller TCON according to the fourth selection control signal S4 output from the fourth output port P4 of the timing controller TCON The fourth output port of the timing controller TCON so as to supply each of the seventh to ninth image data groups (Active Data#9) output to the seventh to ninth source drive ICs (SDIC#7 to SDIC#9) (P4) may be selectively connected to the seventh to ninth source drive ICs SDIC#7 to SDIC#9. For example, when the fourth selection control signal S4 is 01, the fourth output port P4 of the timing controller TCON is connected to the seventh source drive IC SDIC#7 and is output from the fourth output port P4. The output seventh image data group Active Data#7 may be supplied to the seventh source drive IC SDIC#7. For example, when the fourth selection control signal S4 is 10, the fourth output port P4 of the timing controller TCON is connected to the eighth source drive IC SDIC#8 and is output from the fourth output port P4. The output eighth image data group Active Data#8 may be supplied to the eighth source drive IC SDIC#8. For example, when the fourth selection control signal S4 is 11, the fourth output port P4 of the timing controller TCON is connected to the ninth source drive IC SDIC#9 and is output from the fourth output port P4. The output ninth image data group Active Data#9 may be supplied to the ninth source drive IC SDIC#9.

For example, the first input terminal of the fifth demultiplexer DEMUX#5 is connected to the fifth output port P5 of the timing controller TCON, and the second input terminal is connected to the fifth control port P55 of the timing controller TCON. connected, and the first and second output terminals may be commonly connected to the seventh to ninth source drive ICs SDIC#7 to SDIC#9. The fifth demultiplexer DEMUX#5 sequentially from the fifth output port P5 of the timing controller TCON according to the fifth selection control signal S5 output from the fifth output port P5 of the timing controller TCON The timing controller TCON so as to supply each of the tenth to twelfth image data groups (Active Data #10 to Active Data #12) output to the seventh to ninth source drive ICs SDIC#7 to SDIC#9 The fifth output port P5 may be selectively connected to the seventh to ninth source drive ICs SDIC#7 to SDIC#9. For example, when the fifth selection control signal S5 is 01, the fifth output port P5 of the timing controller TCON is connected to the seventh source drive IC SDIC#7 and is output from the fifth output port P5. The output tenth image data group (Active Data#10) may be supplied to the seventh source drive IC (SDIC#7). For example, when the fifth selection control signal S5 is 10, the fifth output port P5 of the timing controller TCON is connected to the eighth source drive IC SDIC#8 and is output from the fifth output port P5. The output eleventh image data group (Active Data#11) may be supplied to the eighth source drive IC (SDIC#8). For example, when the fifth selection control signal S5 is 11, the fifth output port P5 of the timing controller TCON is connected to the ninth source drive IC SDIC#9 and is output from the fifth output port P5. The output twelfth image data group (Active Data#12) may be supplied to the ninth source drive IC (SDIC#9).

As described above, since each of the fourth and fifth selection control signals S4 and S5 selects three source drive ICs SDIC#7 to SDIC#9, it has 2 bits, that is, 01, 10, or 11. However, it is not limited thereto.

Each of the first to fifth selection control signals S1 to S5 may be supplied to the corresponding demultiplexer before the corresponding image data group, simultaneously with the corresponding image data group, or after the corresponding image data group.

For example, the first selection control signal S1, which is 0, precedes the first image data group (Active Data#1), simultaneously with the first image data group (Active Data#1), or at the same time as the first image data group (Active Data#) 1) may be supplied to the first demultiplexer (DEMUX#1) later. Similarly, the first selection control signal S1 equal to 1 is transmitted to the first demultiplexer (S1) before the second image data group (Active Data #2), simultaneously with the second image data group (Active Data #2), or after the second image data It can also be supplied as DEMUX#1).

The second and third selection control signals S2 and S3 may also be supplied to the corresponding demultiplexers DEMUX#2 and DEMUX#3 as described above.

For example, the fourth selection control signal S4 equal to 01 may be transmitted before the seventh image data group Active Data#7, simultaneously with the seventh image data group Active Data#7, or at the same time as the seventh image data group Active Data#7. 7) may be supplied to the seventh source drive IC (SDIC#7) later. Similarly, the fourth selection control signal S4 equal to 10 is transmitted before the eighth image data group Active Data#8, simultaneously with the eighth image data group Active Data#8, or at the same time as the eighth image data group Active Data#8. 8) It can be supplied to the 8th source drive IC later. Similarly, the fourth selection control signal S4 equal to 11 is transmitted before the ninth image data group (Active Data#9), simultaneously with the ninth image data group (Active Data#9), or at the ninth image data group (Active Data#) 9) may be supplied to the ninth source drive IC (SDIC#9) later.

The fifth selection control signal S5 may also be supplied to the corresponding demultiplexer as described above.

13, from the fourth output port P4 of the timing controller TCON, the preamble signal (Pre-amble), the source control signal (CTR), the seventh image data group (Active Data #7), The eighth image data group Active Data #8 and the ninth image data group Active Data #9 may be sequentially output. For example, the fourth selection control signal S4 equal to 01 is supplied to the fourth demultiplexer DEMUX#4 before the seventh image data group Active Data #7, and the fourth selection control signal S4 equal to 10 is supplied to the fourth demultiplexer DEMUX#4. The eighth image data group (Active Data#8) is supplied to the fourth demultiplexer (DEMUX#4), and the fourth selection control signal S4 equal to 11 is supplied to the fourth demultiplexer (DEMUX#4) before the ninth image data group (Active Data#9). It may be supplied to the demultiplexer (DEMUX#4), but is not limited thereto.

A pre-amble signal, a source control signal CTR, a tenth image data group (Active Data #10), and an eleventh image data group (Active Data) from the fifth output port P5 of the timing controller TCON #11) and the twelfth image data group (Active Data#12) may be sequentially output. For example, the fifth selection control signal S5 equal to 01 is supplied to the fifth demultiplexer DEMUX#5 before the tenth image data group Active Data #10, and the fifth selection control signal S5 equal to 10 is supplied to the first The 11th image data group (Active Data#11) is supplied to the fifth demultiplexer (DEMUX#5), and the fifth selection control signal (S5) equal to 11 is supplied to the fifth demultiplexer (DEMUX#5) before the twelfth image data group (Active Data#12). It may be supplied to the demultiplexer (DEMUX#5), but is not limited thereto.

As described above, according to the third embodiment of the present invention, the image data group can be processed in the corresponding source driver IC by the selection signal inserted into the EPI data signal.

On the other hand, according to the fourth embodiment of the present invention, instead of inserting any selection signal into the EPI data signal, a plurality of demultiplexers are interposed between the timing controller TCON and the source drive ICs SDIC#1 to SDIC#9. The demultiplexers DEMUX#1 to DEMUX#5 are arranged and the demultiplexers DEMUX#1 to the demultiplexers DEMUX#1 to The image data group may be sequentially supplied to at least two or more source drive ICs connected to DEMUX#5).

The present invention inserts a selection signal into the EPI data signal so that each of at least one or more image data groups output from a specific port is sequentially supplied to at least one or more source drive ICs (the software method of the third embodiment), or to the selection control signal A selectable demultiplexer may be provided according to the (hardware method of the fourth embodiment). With the configuration according to the third and fourth embodiments, it is possible to process data based on the EPI protocol transmission method even when the number of source driver ICs is an even number as well as an odd number.

The above detailed description should not be construed as restrictive in all respects and should be considered as illustrative. The scope of the present invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the present invention are included in the scope of the present invention.

Claims (9)

a timing controller each including a plurality of output ports for outputting an EPI data signal including an image data group composed of a plurality of image data;
a panel including a plurality of liquid crystal cells defined by crossing a plurality of gate lines and a plurality of data lines; and
a plurality of source drive ICs for supplying a data signal extracted from the EPI data signal to the data lines;
Each output port of the timing controller is connected to at least two source drive ICs,
When the total number of the source drive ICs is odd, a first output port of the plurality of output ports is connected to an odd number of source drive ICs, and a second output port of the plurality of output ports is the odd number of source drive ICs. connected to drive ICs, wherein each of the odd number of source drive ICs is connected to the first output port and the second output port;
The first output port outputs some of the image data to be output to each of the odd number of source drive ICs, and the second output port outputs the plurality of image data to be output to each of the odd number of source drive ICs. A display device that outputs the remaining image data among the image data of According to claim 1,
Each of the output ports other than the first and second output ports among the output ports is connected to an even number of source drive ICs. 3. The method of claim 2,
The EPI data signal includes at least two selection signals and at least two image data groups, and the EPI data signal output to each of the first and second output ports includes an odd number of selection signals and an odd number of image data groups. display device. 4. The method of claim 3,
The EPI data signal output to each of the remaining output ports includes an even number of selection signals and an even number of image data groups. 5. The method of claim 4,
each of the source drive ICs processes a corresponding image data group based on the selection signal. 3. The method of claim 2,
The EPI data signal includes at least two image data groups,
The timing control unit further comprises a plurality of control ports,
and a plurality of demultiplexers disposed between the timing controller and the source drive ICs and connected to the control ports in correspondence to the control ports. 7. The method of claim 6,
The EPI data signal output to each of the first and second output ports includes an odd number of image data groups, and the EPI data signal output to each of the remaining output ports includes an even number of image data groups. 8. The method of claim 7,
Each of the demultiplexers,
A display device for sequentially supplying the image data groups to corresponding source drive ICs according to a selection control signal output from each of the control ports. 8. The method of claim 4 or 7,
The partial image data input from the first output port to one source drive IC among the odd number of source drive ICs and the remaining image data input from the second output port to the one source drive IC are one line. A display device that makes up the video data of minutes.

Images