KR20180028818A - Driver ic and display using the same - Google Patents

Abstract

According to an embodiment of the present invention, provided are a controller for receiving a digital data signal, a data driver IC and a display device using the same, wherein a copy image signal, which copies at least one bit among a plurality of bits of the digital image signal, is arranged between a clock signal and the digital image signal. According to embodiments of the present invention, even though a state is changed in a case of conversion into a transmitted clock signal and a transmitted image signal, distortion of data can be prevented and accordingly noise can be prevented from being generated on a screen of the display device.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a controller, a driver IC,

The embodiments relate to a controller, a driver IC, and a display using the same.

BACKGROUND ART Demands for a display device for displaying an image have been increasing in various forms as an information society has developed. In addition, a liquid crystal display device (LCD), a plasma display device (Plasma Display Device) OLED (Organic Light Emitting Display Device), and the like.

Such a display device may transmit a data signal from a data driver to a display device based on a timing signal provided from a timing controller so that an image is displayed. In order to transmit a plurality of timing control signals and digital video signals to the data driver, the timing controller may include data transmission lines for transmitting digital video signals related to R data, G data, and B data between the timing controller and the data driver, Control wirings for controlling the operation timing of the output and polarity conversion operation of the clock signal, and transmission wirings for transmitting the clock signal.

In order to solve the above problem, the clock signal and the digital video signals are transmitted together by the protocol between the timing controller and the data driver to reduce the number of wirings. However, when the clock signal and the digital video signal are transmitted through the same wiring, the digital video signal can be transmitted after the clock signal and the state of the signal can be changed when the transmitted signal is switched from the clock signal to the digital video signal . If the state of the signal changes during the transmission of the signal, distortion may occur in the digital video signal following the clock signal, which may cause noise in the image displayed on the display device.

It is an object of the present embodiments to provide a controller, a data driver IC, and a display device using the same that minimizes the occurrence of noise to prevent the deterioration of image quality.

It is still another object of the present embodiments to provide a data transfer method that does not require the controller and the driver IC to be redesigned by making no change in the data transfer packet.

In one aspect, the present embodiments provide a method for receiving a digital data signal including a clock signal and a digital video signal by a predetermined protocol, wherein at least one bit among a plurality of bits of the digital video signal is provided between the clock signal and the digital video signal And a data signal supply unit for receiving the digital data signal received by the data signal receiving unit and changing a plurality of digital video signals into analog data signals and outputting the digital data signals, And a data driver IC.

According to another aspect of the present invention, there is provided a method of generating a digital video signal by receiving a digital video signal and generating a duplicated video signal in which at least one bit of the plurality of bits of the digital video signal is copied, And a controller for generating a digital data signal including a duplicated video signal between the clock signal and the digital video signal and transmitting the generated digital data signal through one wiring line.

In another aspect, the present embodiments provide a display panel including a plurality of pixels formed in a region where a gate line and a data line intersect, a digital data signal including a clock signal and a plurality of digital video signals by a predetermined protocol A controller for transmitting a digital data signal between a clock signal and a digital video signal, the digital data signal including a duplicate video signal replicating an image signal of at least one bit of the digital video signal, a gate driver for transmitting a gate signal to the gate line, And a data driver that extracts a plurality of digital video signals from the digital data signal, converts the digital video signals into analog data signals, and outputs the analog data signals to the data lines.

According to another aspect of the present invention, there is provided a data transmission method for transmitting data for transmitting a clock signal and a digital video signal by dividing a section in which a data signal is transmitted into a first section, a second section, Receiving a digital video signal and a control signal from a host device, receiving a digital video signal and a control signal, and replicating at least one bit of the digital video signal to generate a duplicated video signal, The dummy signal is transmitted in the third section, and the dummy signal is transmitted in the third section so that the third section is shorter than the first section. And transmitting the signal.

According to the present exemplary embodiments, it is possible to prevent data distortion from being generated even when a state change occurs when being converted into a transmitted clock signal and a video signal, thereby suppressing generation of noise on the screen of the display apparatus 100 A controller, a data driver IC, and a display device using the same can be provided.

In addition, according to the present embodiments, it is possible to provide a data transmission method capable of setting data packets in the same manner as a protocol used in the prior art, have.

1 is a structural view showing an embodiment of a display device according to the present embodiment.
2 is a structural diagram showing a first embodiment of the data driver shown in FIG.
3 is a structural diagram showing a second embodiment of the data driver shown in FIG.
4A is a timing diagram showing a first embodiment of a data packet transmitted by a signal transmission protocol between the control unit and the data driver shown in FIG.
4B is a timing diagram showing a second embodiment of a data packet transmitted by a signal transmission protocol between the control unit and the data driver shown in FIG.
5 is a graph illustrating a state change of a clock signal and a digital data signal in a data packet transmitted to the data driver shown in FIG.
6A is a graph showing a degree of distortion of a digital video signal not adjacent to a clock signal when a signal is transmitted.
6B is a graph showing a degree of distortion of a digital video signal adjacent to a clock signal when a signal is transmitted.
7 is a flowchart showing an embodiment of a data transmission method according to the present embodiment.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a structural view showing an embodiment of a display device according to the present embodiment.

1, the display device 100 may include a display panel 110, a control unit 120, a gate driver 130, and a data driver 140.

The display panel 110 includes a plurality of gate lines G1, G2, ..., Gn-1, Gn and a plurality of data lines D1, D2, ..., Dm- And may include a pixel 101. Also, the display panel 110 may be a liquid crystal display panel or an organic light emitting display panel using an organic light emitting diode. However, the present invention is not limited thereto. In addition, the display panel 110 may further include a plurality of power supply lines, and when the organic light emitting display panel is used, the display panel 110 may further include a plurality of emission signal lines and an initialization signal line. However, the wiring of the display panel 110 is not limited thereto.

The control unit 120 receives the digital video signal RGB from an external host device (not shown) and transmits the digital video signal RGB to the data driver 140. The control unit 120 receives control signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync and a clock signal ck from the host device and controls the gate driver 130 and the data driver 140 The control signals GCS and DCS. The control signals GSC and DSC for controlling the gate driver 130 and the data driver 140 generated by the control unit 120 are input to the gate driver 130 and the data driver 140 through the clock signal ck, gate enable, gate start pulse, data enable, , And a polarity signal (POL). However, the present invention is not limited thereto. Also, the control unit 120 may be a timing controller. However, the present invention is not limited thereto.

The control unit 120 can receive the control signals GCS and DCS and the digital video signal RGB through the predetermined interface protocol. The controller 120 may transmit the digital data signal including the clock signal ck and the plurality of digital video signals RGB by communicating with the data driver 140 through the predetermined interface protocol . In addition, the controller 120 may transmit a digital data signal between the clock signal and the digital image signal, in which a duplicate image signal replicating the image signal of at least one bit among the plurality of bits of the digital image signal is disposed. The control unit 120 may cause the data driver 140 to transmit the clock signal ck and the digital video signal RGB through the same line by a predetermined protocol. Thus, the number of wirings disposed between the control unit 120 and the data driver 140 can be reduced. However, it is not limited to reducing the number of wirings so that the clock signal ck and the digital video signal RGB flow through the same wiring. Here, the clock signal ck and the digital video signal RGB are transmitted together to the data driver 140, which means that the digital video signal RGB is transmitted through the same line after the clock signal ck is transmitted .

In addition, there may be one or more communication interfaces between the control unit 120 and the data driver 140, and a corresponding protocol is defined for each communication interface. The interface between the controller 120 and the data driver 140 may include at least one of an Embedded Clock Point to Point Interface (EPI) and a Low-Voltage Differential Signaling (LVDS). However, the interface is not limited thereto.

The gate driver 130 is connected to the plurality of gate lines G1, G2, ..., Gn-1, Gn and is connected to each pixel 101 through a plurality of gate lines G1, G2, ..., Gn- Lt; / RTI > The gate driver 130 may be connected to the emission signal line to transmit the emission signal if the emission signal line is wired to the display panel 110. [ However, the present invention is not limited thereto. The gate driver 130 may receive the gate driver control signal (GCS) from the controller 120. Here, the gate driver 130 is shown as a separate component from the display panel 110, but the present invention is not limited thereto. The gate driver 130 may be formed by a gate-in-panel (GIP) method on the side of the display panel 110.

The data driver 140 is connected to a plurality of data lines D1, D2, ..., Dm-1 and Dm and is connected to each pixel 101 through a plurality of data lines D1, D2, ..., Dm- As shown in FIG. The data driver 140 may receive the digital video signal RGB and the data driver control signal DCS from the controller 120. [ Here, the data driver 140 is shown as one component, but the present invention is not limited thereto, and the data driver 140 may be implemented in a plurality of units according to the resolution of the display panel 110. The data driver 140 can receive the clock signal ck among the digital image signal RGB and the data driver control signal DCS through the same wiring line, The number of wirings can be reduced.

The data driver 140 serves as a receiver for receiving the digital image signals RGB and the data driver control signals DCS transmitted from the controller 120. The controller 120 controls the digital image signals RGB and data And may generate a driver control signal DCS and transmit the driver control signal DCS to the data driver 140. Accordingly, the controller 120 and the data driver 140 may be driven in pairs.

2 is a structural diagram showing a first embodiment of the data driver shown in FIG.

Referring to FIG. 2, the data driver 240 may include a data signal receiving unit 241 and a data signal supplying unit 242.

The data signal receiving unit 241 receives the digital data signal including the digital video signal RGB and the data driver control signal DCS including the clock signal ck according to a predetermined protocol, And a digital data signal in which a duplicate video signal in which at least one bit of the plurality of digital video signals is replicated is disposed between the plurality of digital video signals. The data signal receiving unit 241 may receive the digital video signals serially and transmit them to the data signal supply unit 242 in parallel. The data signal receiving unit 241 can receive the digital video signal RGB and the clock signal ck through the same line and thus the number of lines connected to the control unit 120 can be reduced.

The data signal supply unit 242 receives the digital data signal received by the data signal receiving unit 241 and converts a plurality of digital image signals into analog data signals and outputs the analog data signals. The data signal supply unit 242 may output the analog data signals in parallel to the plurality of data lines D1, D2, ..., Dm-1, and Dm.

3 is a structural diagram showing a second embodiment of the data driver shown in FIG.

Referring to FIG. 3, the data driver 340 may include a shift register 341a, a latch 341b, a digital to analog converter 342a, and an output buffer 342b. The shift register 341a receives the data driver control signal DCS and stores the serial digital image signal RGB in the latch 341b. The latch 341b receives the digital image signal RGB, Can be output in parallel. The DAC 342a receives the polarity signal POL and converts the digital image signal RGB into an analog data signal and transmits the analog data signal to the output buffer 342b. In addition, the output buffer 342b can transmit analog data signals output from the DAC 342a to a plurality of data lines in parallel. Here, the shift register 341a and the latch 341b may be the data signal receiving unit 241 of FIG. 2, and the DAC 342a and the output buffer 342b may be the data signal supplying unit 242 of FIG.

FIG. 4A is a timing diagram showing a first embodiment of a data packet transmitted by a signal transmission protocol between the control unit and the data driver shown in FIG. 1, FIG. 4B is a timing chart showing a signal transmission between the control unit and the data driver shown in FIG. Figure 5 is a timing diagram showing a second embodiment of a data packet transmitted by a protocol;

The data packet of the data signal transmitted from the controller 120 to the data driver 140 may include a video signal, a clock signal, and a dummy signal composed of a plurality of bits. The transfer time of 1 bit may take 1 UI (Unit Interval), but it may vary depending on the resolution of the display panel 110 or the bit rate of the data. Also, the data packet is divided into three transmission periods (1phase, 2phase, 3phase) by a predetermined protocol, and the clock signal (ck) is transmitted in the first period (1phase) The digital image signal RGB is transmitted from the first section 2phase and the dummy signal DMY is transmitted from the third section 3phase. The digital video signals R0, R1, R2, ..., G0, G1, G2, ..., B5, B6 and B7 may be differential signals. In addition, the digital image signal RGB may be composed of a total of 24 bits, in which data for red (R), green (G), and blue (B) are represented by 8 bits, respectively. However, the present invention is not limited thereto, and if the R, G, and B data each include 10-bit data, the digital video signal may include 30 bits in total, and if the R, G, and B data each include 6-bit data The digital video signal may include a total of 18 bits.

Referring to FIG. 4A, it is assumed that a digital image signal is represented by 8 bits of red (R), green (G), and blue (B) data, The data packet includes a clock signal, a digital image signal, and a dummy signal. The clock signal may be assigned 2 bits and the dummy signal may be assigned 1 bit. The dummy signal and the clock signal may have logic values of 0 1 1 (L H H) by a predetermined protocol. In addition, the data packet may include a 1-bit replicated image bit (R0 '). Accordingly, the data packet may include a total of 28 bits, which are 2 bits of the clock signal (CK), 1 bit of the duplicated video signal (R0`), 24 bits of the digital video signal (RGB), and 1 bit of the dummy signal (DMY) Transmission time can take up to 28 UI. The first interval (1phase) takes 2UI because the clock signal (ck) is 2 bits and the third interval (3phase) takes 1UI time because the dummy signal (DMY) ) May be shorter than the first period (1phase).

Referring to FIG. 4B, the data packet of the data signal may include a dummy signal, a clock signal, and a digital image signal. The data packet includes a clock signal, a digital image signal, and a dummy signal, and each of the clock signal and the dummy signal can be assigned 2 bits. The dummy signal and the clock signal of the data packet may have logic values of 0 0 1 1 (L L H H) by a predetermined protocol. Therefore, the data packet can be composed of 2 bits of the clock signal, 24 bits of the digital video signal, and 2 bits of the dummy signal, so that a total of 28 UIs can be required for transmission of the data packet. In this case, 2UI is required for the first period (1phase) because the clock signal (ck) is 2 bits and 2UI is required for the third period (3phase) because the dummy signal DMY is 2 bits. The interval (1phase) and the third interval (3phase) may take the same time. Here, the same does not mean that it is completely identical in terms of time but may include a case where a slight parallax has occurred.

Therefore, both of FIGS. 4A and 4B can take the same time to transmit data packets, so that data packets can be transmitted by the same interface protocol.

As shown in FIG. 5, the clock signal ck may be transmitted in the T1 and T2 periods and the digital video signal RGB may be transmitted in the T3 period. At this time, since the clock signal ck is fixed to the high state (H) signal and the digital video signal is a differential signal, the signal of the high state (H) is transmitted in the T1 and T2 periods, and the first digital video signal (R0) It can be seen that a signal having both the high state (H) and the low state (L) is being transmitted. Therefore, it can be seen that the state of the signal transmitted at the time point when the clock signal ck is switched to the digital video signal R0 (the time point when the T3 section starts) is changed. However, although not shown, since the digital video signal is transmitted as a differential signal, the state change does not appear between the respective bits of the digital video signal.

Therefore, when the transmitted signal is converted from the clock signal ck to the digital video signal RGB, distortion may occur in the digital video signal RGB. More specifically, distortion may occur in the first digital video signal R0 adjacent to the clock signal ck. The digital image signals R0, R1, R2, ..., G0, G1, G2, ..., B5, B6, B7 adjacent to the clock signal ck are all displayed on the display panel 110, Noise may be displayed on the display panel 110 due to distortion generated in the first digital video signal R0. ..., G0, G1, G2, ..., B5, B6, B7, ..., B7) between the clock signal (ck) and the first digital video signal (R0) The replicated image data R0 'may be distorted when the replica image data R0' is replicated. However, when the data packet is constructed as shown in FIG. 4A, distortion occurs only in the reproduced image data R0 ', which is not actually used in the display of the image, and distortion is not generated in the digital image signal actually used in the image So that the noise may not be displayed on the display panel 110.

Here, the duplicated image data is shown to duplicate the first bit R0 of the digital image signal, but the present invention is not limited thereto. It is also possible to duplicate any one of the twenty-four bits of the digital image signal. It is also possible to store one bit of a digital video signal and to insert a bit stored between a clock signal and a digital video signal which are generated later.

FIG. 6A is a graph showing a degree of distortion of a digital video signal not adjacent to a clock signal when a signal is transmitted, and FIG. 6B is a graph showing a degree of distortion of a digital video signal adjacent to a clock signal, Graph.

6A and 6B, the x-axis is the time axis and the y-axis is the axis for the magnitude of the voltage. Since the digital video signal is a differential signal, a high state and a low state appear simultaneously in 1 UI, and a rhombus-shaped empty space may be displayed in the center. Here, the diamond shape is not an exact diamond shape, but connects a virtual line to an empty space to display a diamond shape. Then, it is possible to judge whether or not the signal is distorted by using the size of the diamond shape.

The length up to the upper vertex and the length up to the lower vertex are referred to as d11 and d12 in FIG. 6A and d21 and d22 in FIG. 6B, respectively, with reference to a virtual horizontal line at the center of the diamond to determine the size of the diamond, In FIG. 6A, the length to the left vertex and the length to the right vertex are referred to as c11 and c21, respectively, with reference to the imaginary vertical line at the center of the rhombus. In FIG. 6B, the length to the left vertex and the right vertex Can be referred to as c21 and c22, respectively. In the case of a normal range in which no distortion occurs, it is necessary that each of d11, d21, d12, and d22 should take 0.25UI or more and each of c11, c21, c12, and c22 should have a difference of 90 mV or more.

6A and 6B, it can be seen that the diamond shape shown in FIG. 6A is larger than the diamond shape shown in FIG. 6B, and the diamond shape shown in FIG. 6A has dimensions d11 and d12 of 0.25 UI And c11 and c12 are larger than 90 mV. However, in the case of Fig. 6 (b), it can be seen that d21 and d22 are smaller than 0.25 UI and c21 and c22 are smaller than 90 mV.

Therefore, when the replica video signal is adjacent to the clock signal, the signal may be distorted only in the replica video signal, and the signal is not distorted in the actually used video signal, and noise is not generated in the video displayed on the display panel 110 .

7 is a flowchart showing an embodiment of a data transmission method according to the present embodiment.

7, a period during which a data signal is transmitted is divided into a first period (1 phase), a second period (2 phase), and a third period (3 phase) to transmit a clock signal (ck) (S700) receiving the digital image signal and the control signal from the host device, receiving the digital image signal RGB and the data driver control signal DSC, and receiving at least one of the digital image signals A clock signal ck is transmitted in a first interval 1phase and a duplicated video signal and a digital video signal RGB are transmitted in a second interval 2phase in step S710. (S720) transmitting the dummy signal DMY in the third period (3phase) and the third period (3phase) in the third period (3phase) shorter than the first period (1phase). Since the clock signal ck and the digital video signal RGB are transmitted in series, the video signal generated due to the state change of the digital video signal RGB in the clock signal ck may be distorted. However, The clock signal and the digital image signal actually used in the image displayed on the display panel are caused to be distorted so that noises are generated. Further, although the time required for the second section (2phase) can be increased by 1US by the duplicated video signal, the third section (3phase) through which the dummy signal is transmitted can be made shorter, It is not necessary to change the design or protocol of the control unit 120 or the data driver 140.

In one embodiment, the bit of the video signal copied by the duplicate video signal may be at least one bit adjacent to the clock signal among the plurality of bits of the digital video signal.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: Display device 100
110: Display panel
101: pixel
120:
130: gate driver
140: Data driver

Claims (12)

A duplicated video signal which is obtained by duplicating at least one bit among a plurality of bits of the digital video signal between the clock signal and the digital video signal, A data signal receiving unit receiving the digital data signal; And
And a data signal supply unit for receiving the digital data signals received by the data signal receiving unit and converting the plurality of digital image signals into analog data signals and outputting the analog data signals. The method of claim 1, wherein
According to the predetermined protocol, the digital data signal is divided into three transmission periods, the clock signal is transmitted in a first interval, the duplicated video signal and the digital video signal are transmitted in a second interval, And the third section is shorter than the first section. The method according to claim 1,
Wherein the duplicated video signal is a signal in which at least one bit transmitted closest to the clock signal among the plurality of bits of the digital video signal is copied. Receiving a digital video signal, generating a duplicated video signal in which at least one bit of the plurality of bits of the digital video signal is duplicated,
Generating a digital data signal including a clock signal and a digital video signal by a predetermined protocol and generating the digital data signal in which the duplicate video signal is disposed between the clock signal and the digital video signal, A controller that transmits data signals through a single wire. The method of claim 4, wherein
According to the preset protocol, the digital data signal is divided into three transmission periods, the clock signal is transmitted in a first interval, the duplicated video signal and the digital video signal are transmitted in a second interval, A dummy signal is transmitted in a third interval, and the third interval is shorter than the first interval. 5. The method of claim 4,
Wherein the duplicated video signal is a signal in which at least one bit transmitted closest to the clock signal among the plurality of bits of the digital video signal is copied. A display panel including a plurality of pixels formed in a region where gate lines and data lines intersect;
And transmitting a digital data signal including a clock signal and a digital video signal according to a predetermined protocol, wherein the video signal of at least one bit among the plurality of bits of the digital video signal is copied between the clock signal and the digital video signal, A control unit for transmitting the digital data signal in which a video signal is arranged;
A gate driver for transferring a gate signal to the gate line; And
And a data driver receiving the digital data signal from the control unit, extracting a plurality of digital video signals from the digital data signal, converting the digital video signal into an analog data signal, and outputting the analog data signal to the data line. 8. The method of claim 7,
Wherein the data driver comprises: a data signal receiving unit receiving the digital data signal transmitted from the control unit through one wiring; And
And a data signal supply unit for extracting a plurality of digital video signals from the digital data signal received by the data signal receiving unit, converting the digital video signals into analog data signals, and outputting the analog data signals. The method of claim 7, wherein
According to the preset protocol, the digital data signal is divided into three transmission periods, the clock signal is transmitted in a first interval, the duplicated video signal and the digital video signal are transmitted in a second interval, Wherein the third section is shorter than the first section. 8. The method of claim 7,
Wherein the duplicated video signal is a signal in which at least one bit transmitted closest to the clock signal among the plurality of bits of the digital video signal is copied. A data transmission method for transmitting a clock signal and a digital video signal by dividing a section in which a data signal is transmitted into a first section, a second section, and a third section,
Receiving a signal including a digital video signal from a host device;
Reproducing at least one bit of the digital video signal to generate a duplicate video signal; And
The duplicated video signal and the digital video signal are transmitted so that the duplicated video signal is adjacent to the clock signal in the second section and the dummy signal is transmitted in the third section And transmitting a data signal such that the third section is shorter than the first section. 12. The method of claim 11,
Wherein the bit of the video signal copied by the duplicated video signal is at least one bit of the plurality of bits of the digital video signal adjacent to the clock signal.

Images