KR101853736B1 - Display apparatus - Google Patents

Abstract

The present invention relates to a display device, and more particularly, to a display device capable of transmitting data and parameters transmitted between two integrated circuits (ICs) through an LVDS interface. To this end, a display device according to the present invention includes: a panel having data lines and gate lines crossed to output an image; A data driver driving the data lines; A gate driver for driving the gate lines; And a plurality of integrated circuits for driving at least one of the data driver, the gate driver, and the panel, the integrated circuits being adapted to receive data according to a selection signal for selecting whether to transmit data or transmit parameters, A main integrated circuit for incorporating data or parameters into the LVDS signal and for transmitting the LVDS signal over the LVDS line; And a sub-integrated circuit for extracting the data or the parameter from the LVDS signal transmitted from the main integrated circuit using the selection signal.

Description

Display device {DISPLAY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device composed of a plurality of integrated circuits (ICs).

With the development of information technology (IT), display devices have become more important as visual information delivery media, and in order to secure more competitive power in the future, low power consumption, thinness, light weight, and high image quality are required.

Examples of such a display device include a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode display (OLED) display device.

On the other hand, the above-described display device is composed of various types of integrated circuits (hereinafter simply referred to as "IC") such as a timing controller, a source drive IC, a data drive IC, .

1 is a diagram illustrating a communication method between two integrated circuits applied to a conventional display device, in which a main IC and a sub IC are shown.

In order to transmit data and parameters between two ICs in a conventional display device, as shown in FIG. 1, in addition to data interfaces (LVDS interfaces) 11 and 21 for transmitting data, a parameter interface (12C or SIP) 12, 22 must be provided independently.

That is, the main IC 10 transmits data to the sub IC 20 through the LVDS interface composed of the LVDS transmission section (LVDS Tx) 11 and the data transmission line, A separate parameter interface is used to transmit the parameter. I2C or SPI is used as the parameter interface, and the parameter interface uses a clock different from the data clock for data transmission.

The sub IC 20 receives data from the main IC 10 through an LVDS interface composed of an LVDS receiver 21 (LVDS Rx) 21 and a data transmission line, A separate parameter interface is used to receive the parameter. In this parameter interface, I2C or SPI is used as in the main IC 10. Hereinafter, for convenience of explanation, I2C is described as an example of a parameter interface.

Here, the LVDS interface (LVDS interface) is an interface for transmitting data, as described above, and can transmit data and a sync signal. Therefore, it is impossible to transmit signals and parameters other than data and sync signals (DE, Hsync, Vsync).

On the other hand, the I2C interface used as the parameter interface is an interface using two lines (SDA, SCL), and in particular, the SCL uses a frequency of about 100 KHz (10 μs).

In addition, the I2C interface performs a function of transferring parameters only after a plurality of check processes such as a device address check, a bus check, and a register check are performed.

The operation sequence (Opreation Sequence) of the I2C interface and the time spent in each step are as follows.

First, 140 μs is consumed for SCL toggling, 250 μs is consumed for soft reset, and 250 μs is consumed for device address write. After that, 250 μs is consumed for register address write and device address read (Register Address Write & Device Address Read (Write)). Finally, Data Read (Write) ) Operation (100 占 퐏) is performed.

As described above, the I2C interface takes about 890 μs in the previous stage for reading or writing 8-bit data, and takes about 100 μs in one cycle in the data operation for data writing or reading.

Therefore, in the conventional display device as described above, a timing of more than 1,000 μs (1.0 ms) is required for transmitting 16 bits of parameters between two ICs.

This timing is considerably long considering that the driving frequency of a high definition (HD) display device is 60 Hz (1-line time? 20 mu s).

That is, the above-described conventional display device uses a high-speed LVDS interface and a low-speed parameter interface (I2C) to transfer data and parameters between two ICs.

Therefore, the conventional flat panel display device can not immediately reflect the driving result of the algorithm in the main IC in the sub IC. In addition, since the interface between the main IC and the sub IC of the conventional flat panel display device is formed in a large size for a complicated protocol, the manufacturing cost of the conventional display device is high.

In the prior art in which the application number is 10-2009-0126902, a method of allocating data format information to idle bits of image data transmitted from an external system to a timing controller using an LVDS interface is described. However, the prior art simply assigns specific information to the idle bits of the image data, and fails to transmit various parameters through the LVDS interface.

SUMMARY OF THE INVENTION It is a general object of the present invention to provide a display device capable of transmitting data and parameters transmitted between two integrated circuits (ICs) through an LVDS interface.

According to an aspect of the present invention, there is provided a display device including: a panel having data lines and gate lines crossed to output an image; A data driver driving the data lines; A gate driver for driving the gate lines; And a plurality of integrated circuits for driving at least one of the data driver, the gate driver, and the panel, the integrated circuits being adapted to receive data according to a selection signal for selecting whether to transmit data or transmit parameters, A main integrated circuit for incorporating data or parameters into the LVDS signal and for transmitting the LVDS signal over the LVDS line; And a sub-integrated circuit for extracting the data or the parameter from the LVDS signal transmitted from the main integrated circuit using the selection signal.

According to the above-mentioned solution, the present invention provides the following effects.

That is, by transmitting data and parameters transmitted between two integrated circuits (ICs) through an LVDS interface, it is possible to transmit and receive a large number of parameters in a short time.

In addition, since the present invention can transmit and receive both data and parameters through the LVDS interface, it is possible to delete a separate block and pin in the IC for transmitting and receiving parameters. Lt; / RTI >

1 is an exemplary view showing a communication method between two integrated circuits applied to a conventional display device.
2 is an exemplary view showing a configuration of a display device according to the present invention;
FIG. 3 is an exemplary view showing the format of an LVDS signal transmitted and received between two integrated circuits applied to a display device according to the present invention; FIG.
FIG. 4 is a diagram for explaining a state in which two integrated circuits transmit and receive data and parameters through the LVDS signal shown in FIG. 3;
FIG. 5 is a timing chart for explaining a state in which parameters are transmitted and received through the LVDS signal shown in FIG. 3; FIG.
Fig. 6 is a timing chart continuously showing the states shown in Figs. 5 (a) and 5 (b). Fig.
FIG. 7 is another exemplary diagram showing the format of an LVDS signal transmitted and received between two integrated circuits applied to a display device according to the present invention during one cycle of a clock pulse. FIG.
8 is an exemplary diagram schematically showing parameters transmitted during two periods of a clock pulse of the LVDS signal shown in Fig. 7; Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is an exemplary view showing a configuration of a display device according to the present invention.

2, the display device according to the present invention includes a data driver 300 for driving data lines DL1 to DLm, a gate driver 200 for driving gate lines GL1 to GLn, A timing controller 400 for controlling the data driving unit 300 and the gate driving unit 200, a storage unit 500 for storing information required by the timing controller, and a power IC 600).

First, the panel 100 may be formed in various forms depending on what kind of display device the present invention is made of. That is, the panel 100 can be manufactured in a variety of types such as a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode display (OLED) The flat panel display device of the present invention may be configured in various forms depending on what type of flat panel display device is used.

For example, when the present invention is constituted by a liquid crystal display (LCD), the panel 100 may be configured such that a liquid crystal layer is formed between two glass substrates. In addition, when the present invention is configured as an organic light emitting diode display (OLED), the panel 100 may be configured such that organic light emitting diodes, data lines, and gate lines are formed on two glass substrates.

Next, the gate driver 200 shifts a gate start pulse (GSP) transmitted from the timing controller 400 according to a gate shift clock (GSC), sequentially shifts the gate lines GL1 to GLn On voltage Von is supplied to the scan electrodes Y1 through Yn. The gate driver 200 supplies the gate-off voltage Voff to the gate lines GL1 to GLn during the remaining period when the scan pulse of the gate-on voltage Von is not supplied.

Meanwhile, the gate driver 200 applied to the present invention may be configured to be independent from the panel and be electrically connected to the panel in various ways. However, the gate driver 200, which is a gate in panel : GIP) method. In this case, the gate control signal for controlling the gate driver 200 may be a start signal VST and a gate clock GCLK.

Next, the data driver 300 converts the video data input from the timing controller into an analog pixel signal (video data signal), and supplies a video data signal for one horizontal line in each horizontal period supplied with a scan signal to the gate line, . That is, the data driver 300 converts image data into image data signals using gamma voltages supplied from a gamma voltage generator (not shown), and outputs the image data signals to a data line.

That is, the data driver 300 generates a sampling signal by shifting a source start pulse (SSP) from the timing controller 400 according to a source shift clock (SSC). The data driver 300 latches the pixel data RGB (image data) input according to the source shift clock SSC in response to the sampling signal and then responds to a source output enable (SOE) signal Supply in horizontal line units.

To this end, the data driver 300 may include a data sampling unit, a latch unit, a digital-analog converter, and an output buffer.

Next, the timing controller 400 controls the data driver 300 using synchronous signals such as vertical and horizontal synchronizing signals (Vsync, Hsync), data enable (DE) and dot clock (DCLK) And a gate control signal GCS for controlling the gate driver 200 are generated. In addition, the timing controller 400 performs a function of rearranging the image data input from the external system and outputting the rearranged image data to the data driver 300.

Here, the data control signal DCS includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, and a source output enable signal SOE.

The gate control signal GCS may include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE or the like in accordance with the configuration of the gate driver, (VST), a gate clock (GCLK), and the like.

Next, the storage unit (EEPROM) 500 stores data and various parameters necessary for driving the timing controller. When the display device according to the present invention is powered and the display device according to the present invention is driven, And transmits the above-described data and various parameters to the timing controller 400.

In addition, the storage unit 500 may store image data transmitted from an external system, and may transmit the image data to the timing controller 400 together with various parameters.

In addition, the storage unit 500 may store various data and parameters transmitted from the other controller 400.

That is, the storage unit 500 can transmit and receive various data and parameters through communication with the timing controller 400.

To this end, the storage unit may be configured as an EEPROM (Electrically Erasable Programmable ROM).

Finally, the power IC 600 functions to supply various driving voltages required for driving the panel 100.

That is, the power IC 600 generates various levels of power supply voltages necessary for driving the above-described components by using a low potential supply voltage (Vcc) of 0 to 3.3 V input from a system power supply unit .

For example, the power IC 600 may change the level of the driving voltage transmitted to the gate driver using the timing signals transmitted from the timing controller 400, and may change the level of the gamma voltage transmitted to the data driver It is possible.

In addition, the power IC 600 may perform communication with the timing controller to supply an optimal power supply voltage to the above-described components.

For example, the display device according to the present invention may detect the ambient temperature and change the drive voltage level of each component according to the sensed temperature. In this case, the power IC 600 may receive data transmitted from the timing controller The driving voltage changing function as described above can be performed according to the parameters. This function can be effectively executed especially in an organic light emitting diode display. That is, since the organic material characteristics of the organic light emitting diodes applied to the organic light emitting diode display device can be sensitively changed according to the external temperature, a method of changing the level of the panel driving voltage according to the external temperature in the organic light emitting diode display device . However, the above-described functions may be performed in a liquid crystal display device or a plasma display device. In addition, the display device may vary various driving voltage levels by applying various algorithms.

Accordingly, the power IC 600 communicates with the timing controller 400 to transmit and receive various data and parameters. That is, since the above-described algorithm is generally performed in the timing controller, the power IC 600 receives data and parameters generated according to various algorithms performed in the timing controller 400, It is possible to perform the function of changing and outputting. However, in addition to the timing controller, the power IC can transmit / receive various data and parameters to / from the data driver 300 or the gate driver 200, and can transmit and receive various data and parameters to and from other components.

The display device according to the present invention includes a timing controller 400, a storage unit 500, and a power IC 600 as described above, and these components are formed of an integrated circuit (IC) . In addition, the display device according to the present invention includes various kinds of integrated circuits in addition to the components 400, 500, and 600 as described above.

Meanwhile, the display device according to the present invention is characterized in that two integrated circuits that exchange data and parameters among the various kinds of integrated circuits as described above transmit and receive both data and parameters using only the LVDS interface .

That is, the two integrated circuits that receive both the data and the parameters among the integrated circuits applied to the present invention do not have an interface for transmitting and receiving data and an interface for transmitting and receiving parameters, And the data and parameters are transmitted using only the LVDS interface.

Here, the parameter is, for example, a case where two ICs are referred to as the timing controller 400 and the storage unit 500, respectively, and the resolution that the timing controller must access from the EEPROM at power- Information (vertical and horizontal), rising and falling time of control signals, look up table, and the like. Further, for example, when two ICs are respectively referred to as a timing controller 400 and a power IC (gamma IC, etc.), the parameter can be a set value of various addresses.

Also, data may be various information transmitted between two ICs. For example, the data is R, G, B image data when the two ICs are the timing controller 400 and the scaler IC, and when the two ICs are the timing controller 400 and the storage unit 500, And may be partition information between VDD and ground voltage when the two ICs are timing controller 400 and power IC (in particular, gamma IC).

However, the present invention can also be applied to a case where only a parameter is transmitted between two ICs. That is, the present invention uses the LVDS interface used for transmitting only data in the conventional display device as it is to the transmission unit 913 shown in FIG. 3 to be described later, while the control unit 914 and the selection unit 912 are used as the main By configuring it in the IC, parameters can be transmitted using the conventional LVDS interface.

In more detail, the present invention is configured by using two LVDS interfaces for transmitting and receiving data and parameters and transmitting and receiving only parameters by using an LVDS interface for transmitting data. In the conventional LVDS interface, Can also be used to transmit parameters.

Therefore, although the present invention may transmit only parameters between two integrated circuits, the present invention will be described hereinbelow assuming that both parameters and data are transmitted for convenience of explanation. As described above, the data transmitted between the two integrated circuits to which the parameters are transferred differs according to the function of each integrated circuit. Hereinafter, for convenience of explanation, the data is simply represented by the image data (R, G, B) The present invention is explained. That is, as described above, the data transmitted between the two ICs may be various types of information such as image data (R, G, and B), address information, or division information between VDD and ground voltage, The present invention is described by assuming that various types of data are R, G, and B type image data. However, as described above, the data applied to the present invention is not necessarily limited to the image data composed of R, G, and B.

An integrated circuit for transmitting data and parameters is referred to as a main IC, and an integrated circuit for receiving data and parameters is referred to as a sub IC.

FIG. 3 is a diagram illustrating a format of an LVDS signal transmitted and received between two integrated circuits applied to a display device according to the present invention, wherein (a) is an example of a format of an LVDS signal transmitting data, and ) Is an example showing the format of the LVDS signal transmitting the parameter.

3 (a) and 3 (b) illustrate the format of an LVDS signal transmitted and received between two integrated circuits. Particularly, (a) includes 8 bits of red, green and blue data (B) shows the format of an LVDS signal including an 8-bit address, an 8-bit first parameter, and an 8-bit second parameter.

That is, as shown in FIG. 3A, one period (A) of the LVDS signal for transmitting data (image data each having 8 bits of R, G, and B) is a 1-bit data enable signal 8 bits of green data (G10 to G17) and 8 bits of blue data (red data) (B10 to B17) and one bit of idle bit (including the selection signal EN).

Accordingly, each of the differential signal transmission lines LVDS_TA, LVDS_TB, LVDS_TC, and LVDS_TD transmits data by 7 bits during one period A of the clock pulse TCLK transmitted through the clock pulse transmission line LVDS_TCLK.

For example, the first differential signal transmission line LVDS_TA sequentially transmits 6-bit red data R10 to R15 and 1-bit green data G10 during one period of the clock pulse CLK, The signal transmission line LVDS_TB sequentially transmits five bits of green data G11 to G15 and two bits of blue data B10 and B11 for one period of the clock pulse CLK and the third differential signal transmission line LVDS_TC Bit data B12 to B15, a 1-bit horizontal synchronizing signal Hsync, a 1-bit vertical synchronizing signal Vsync, and a 1-bit data enable signal Vsync for one period of the clock pulse CLK, And the fourth differential signal transmission line LVDS_TD sequentially outputs 2 bits of red data R16 and R17, 2 bits of green data G16 and G17, and 2 bits of green data G16 and G17 for one period of the clock pulse CLK. 1 bit of the idle bit (unused bit) in which the blue data B16 and B17 of the bit and the selection signal EN are set to the value of '0' It will be simply referred to as sending a "idle-bit").

As described above, the LVDS signal transmitting the image data composed of R, G, and B includes 8 bits of R, 8 bits of G, 8 bits of B, 1 bit of data enable signal DE, A total of 28 bits including a vertical synchronizing signal Vsync, a 1-bit horizontal synchronizing signal Hsync, and a 1-bit idle bit.

That is, there is a 1-bit idle bit during one period (A) of the LVDS signal transmitting 8-bit video data. In the case of transmitting data through the LVDS line, (EN) is set to '0'.

In other words, since '0' is assigned to the idle bit which is the least significant bit of one period (A) of the LVDS signal shown in FIG. 3A, this LVDS signal transmits data .

On the other hand, as shown in FIG. 3 (b), the LVDS signal for transmitting the parameter includes an 8-bit address signal, a 8-bit first parameter and an 8-bit second parameter.

For example, the first differential signal transmission line LVDS_TA sequentially transmits 6-bit address signals A10 to R15 and 1-bit first parameter P10 during one period of the clock pulse CLK, The differential signal transmission line LVDS_TB sequentially transmits the 5-bit first parameters P11 to P15 and the 2-bit second parameters P20 and P11 for one period of the clock pulse CLK, The line LVDS_TC includes a 4-bit second parameter P22 to P25, a 1-bit horizontal synchronizing signal Hsync, a 1-bit vertical synchronizing signal Vsync, and a 1-bit vertical synchronizing signal Vsync for one period of the clock pulse CLK The fourth differential signal transmission line LVDS_TD sequentially transmits 2-bit address signals A16 and A17 for one period of the clock pulse CLK and a 2-bit first parameter P16 , G17), the 2-bit second parameters P26 and P27, and the 1-bit idle bit set to 1.

That is, one bit of idle bit is present during one period (A) of the LVDS signal transmitting two parameters of 8 bits. In the case of transmitting a parameter through the LVDS line, EN) is set to '1'.

In other words, since the idle bit, which is the least significant bit of one period (A) of the LVDS signal shown in FIG. 3B, is assigned as '1', it can be seen that this LVDS signal is transmitting the parameter .

FIG. 4 is a diagram for explaining a state in which two integrated circuits transmit and receive data and parameters through the LVDS signal shown in FIG. 3. The LVDS transmission interface 911 and the LVDS The configuration of the receiving interface 921 is shown.

As described above, the configuration of two integrated circuits for setting data and parameters by setting '0' or '1' as the selection signal EN to the idle bit of the LVDS signal is shown in FIG.

Hereinafter, an integrated circuit for transmitting data and parameters is referred to as a main IC 910, and an integrated circuit for receiving data and parameters from the main IC 900 is referred to as a sub IC 920. [

4, the main IC 910 supplies data or parameters via the LVDS line in accordance with the selection signal EN generated by the control section 914 and the control section 914 for generating the selection signal EN, And an LVDS transmit interface 911 for transmitting to the IC 920.

The control unit 914 performs a function of setting the selection signal EN to '0' or '1' according to an algorithm executed in the main IC 910.

For example, when the main IC 910 is the storage unit 500 and the sub IC 920 is the timing controller 400, when power is applied to the display device, the main IC 910 controls the sub IC ) 920 to the sub IC 920. The data and parameters necessary for driving the sub- In this case, the controller may perform an algorithm for determining whether power is applied to the display device, and may set the selection signal to '0' or '1'.

As another example, when the main IC 910 is the timing controller 400 and the sub IC 920 is the storage 500, the main IC (timing controller) 910 may be arranged in one frame unit or one horizontal The main IC 910 needs to transmit the image data of one frame or the image data of one horizontal line to the storage unit 500 and store the image data in the storage unit 500, It is necessary to transmit the parameters related to the storage of the data to the storage unit 500. [ In this case, the control unit may set the selection signal to '0' or '1' according to the above-described algorithm.

In addition to the above example, the main IC 910 needs to transmit data and parameters to the sub IC by various algorithms. In this case, the controller 914 sets the selection signal to '0' according to the above- Or " 1 ".

That is, when it is determined that the data needs to be transmitted to the sub IC 920 by executing the above-described algorithm, the control unit 914 of the main IC 910 sets the selection signal EN to 0 If it is determined that it is necessary to transmit the parameter to the sub IC 920, the selection signal EN is set to '1', and the LVDS transmission interface 911 transmits the parameter to the LVDS transmission interface 911 Lt; / RTI >

At this time, the control unit 914 can set the selection signal EN to '1' only when the data enable (DE) signal is '0'. That is, when the data enable (DE) signal is '1', the currently used data is useful. In this case, only data must be transmitted. Therefore, the control unit can set the selection signal EN to '1' when necessary in the state that the data enable (DE) signal is '0', so that the parameter can be transmitted to the sub IC.

The LVDS transmission interface 911 carries out the function of including the image data in the LVDS signal according to the selection signal EN transmitted through the control unit, or transmitting the LVDS signal including the parameter.

3, the LVDS transmission interface 911 includes a selection unit 912 for selecting data and parameters according to a selection signal, and a data or parameter selected through the selection unit in an LVDS signal to be transmitted to a sub IC And a transmitting unit 913 for transmitting the data.

For example, when '0' is input as the selection signal EN, the selection unit 912 transmits the data to the transmission unit 913. When '1' is input as the selection signal EN, To the transmission unit 913.

The transmission unit 913 changes the selected data or parameter selected by the selection unit and the selection signal EN transmitted from the control unit to the LVDS signal format as described with reference to FIG. 3 and transmits the LVDS signal format to the sub IC 920 through the LVDS line .

The low voltage differential signaling (LVDS) interface 913 used in the present invention refers to a high-speed digital interface. In the LVDS interface, two signals having opposite polarities are generated, and two signals are referenced to each other And transmits the data. Therefore, the LVDS interface is capable of realizing data transmission at a low voltage, has low power consumption, has a high transmission speed, and is excellent in immunity against noise.

The transmitter 913 of the LVDS transmission interface 911 having the above-described characteristics includes a plurality of transmitters Tx0 to Tx4, as shown in Fig. The transmitters Tx0 to Tx4 change data or parameters supplied thereto to LVDS signals and transmit the LVDS signals to the sub IC through a plurality of differential signal transmission lines LVDS_TCLK, LVDS_TA, LVDS_TB, LVDS_TC, and LVDS_TD send. Here, each differential signal transmission line is composed of two differential lines, and these differential signal transmission lines are collectively referred to as LVDS lines.

The LVDS transmission interface 911 shown in FIG. 4 is for transmitting 8-bit data or parameters, as described with reference to FIG. 3. The LVDS transmission interface 911 includes first to fourth differential signal transmission lines (LVDS_TCLK, LVDS_TA, LVDS_TB, LVDS_TC, and LVDS_TD), and includes a zero-th differential signal transmission line (LVDS_TCLK) for transmitting a clock serving as a reference of the LVDS signal.

That is, the transmitter 913 of the LVDS transmission interface 911 for transmitting data or parameters composed of 8 bits includes a total of five transmitters and a total of five differential signal transmission lines (ten differential lines).

Accordingly, the LVDS transmission interface 911 shown in FIG. 4 forms one port of five differential signal transmission lines, and the LVDS transmission interface 911 shown in FIG. It is possible to transmit video data or two parameters consisting of 8 bits.

Here, the number of differential signal transmission lines may vary depending on the change in the number of bits of data or parameters to be transmitted.

4 shows one transmitter 913 forming one port for transmitting data or parameters composed of 8 bits in one cycle of the clock pulse as described above, In order to transmit the above data or parameters, it may include two or more ports.

4, the sub IC 920 includes an LVDS receiving interface 921 for receiving the LVDS signal transmitted from the transmitting unit 913 through the LVDS line and extracting data or parameters from the LVDS signal .

The LVDS receiving interface 921 receives data or parameters from the LVDS signal received through the receiving unit 922 and the receiving unit 922 for receiving the LVDS signal transmitted from the transmitting unit 913 through the LVDS line And a data sorting unit 923 for extracting and sorting the data.

Here, the receiving unit 922 includes a plurality of receivers Rx0 to Rx4, as shown in Fig. The receivers Rx0 to Rx4 receive the LVDS signal transmitted from the main IC 910 through the plurality of differential signal transmission lines LVDS_TCLK, LVDS_TA, LVDS_TB, LVDS_TC and LVDS_TD, .

Therefore, the receiver 922 includes receivers of the same number as the transmitter 913 of the LVDS transmit interface 911, and performs functions opposite to those performed by the transmitter 913.

On the other hand, the data sorting unit 923 extracts and arranges data, parameters and addresses from the reception information transmitted from the receiving unit 922 using the reception selection signal transmitted from the reception unit.

That is, when the reception selection signal EN is '0', the data sorting unit 923 determines that the information included in the LVDS signal is data, and outputs the LVDS signal to the next stage of the LVDS receiving interface 921 When the reception selection signal EN is '1', the parameter is determined as a parameter included in the LVDS signal, and the parameter is transmitted to the next stage component of the LVDS reception interface 921 .

If the received selection signal EN is '1', the data sorting unit 923 compares the two parameters included in the LVDS signal with each other, and outputs the received parameter to the next stage Or to a component.

For example, the LVDS signal shown in FIG. 3 (b) includes the bits P10 to P15 and P20 to P25 constituting the two parameters as described above, and the two parameters may be different from each other But it may be the same.

That is, two parameters may be transmitted from the main IC 910 to the sub IC 920 for one period (A) in FIG. 3 (b), but the present invention is not limited to the one parameter (A) twice, and then the data sorting unit may compare the transmitted parameters twice. If the comparison result is the same, one parameter can be regarded as normally received, and if it is not the same, it can be judged that an error has occurred in the transmission process.

In other words, the present invention can transmit two different parameters to the LVDS signal as shown in FIG. 3 (b) as a first parameter and a second parameter to the sub IC 920, May be transmitted to the sub IC 920 twice as a first parameter and a second parameter.

In the former case, the data arrangement unit 923 of the LVDS reception interface 921 transmits two different parameters to the next stage component without a separate verification procedure.

However, in the latter case, the sorting unit 923 compares the first parameter with the second parameter, and determines that only one normal parameter is received when the two parameters coincide with each other, Component.

FIG. 5 is a timing chart for explaining a state in which parameters are transmitted and received through the LVDS signal shown in FIG. 3, wherein (a) is a timing chart showing a state in which a parameter is included in the LVDS signal, (b) Is a timing chart showing a state in which a parameter is not included. 6 is a timing chart continuously showing the states shown in Figs. 5 (a) and 5 (b).

As described above, according to the present invention, the selection signal EN is added to the idle bit of the LVDS signal and transmitted. When '0' is input to the idle bit as the selection signal EN, The information included in the LVDS signal of one period included in the LVDS signal is sorted and determined as data, and when '1' is input as the selection signal EN to the idle bit, the selection signal EN is included The information included in the LVDS signal of one period is determined by the parameter and is arranged.

For example, FIG. 5A shows a timing chart of various signals when a parameter includes a parameter in the LVDS signal. In FIG. 5, a bit having information on a data enable (DE) signal is If it has a value of '1', it indicates that the LVDS signal is transmitting data, and therefore, if the data enable (DE) signal is '1', the parameter is not transmitted.

However, when the bit of the selection signal EN becomes '1' in a state where the data enable (DE) signal has a value of '0', this means that the LVDS signal This means that the parameter is being transmitted.

On the other hand, if the bit value of the selection signal EN has a value of '0' even if the data enable signal DE has a value of '0', it means that, as shown in FIG. 5B, It means that no data and parameters are included.

Therefore, the data sorting unit 923 of the LVDS receiving interface 921 refers to both the data enable (DE) signal and the selection signal EN as described above, and the LVDS signal currently being transmitted transmits the data Or whether the parameter is being transmitted.

6 shows an LVDS signal transmitted / received between two ICs over a plurality of periods via the LVDS line. When the data enable (DE) signal included in the LVDS signal is '1', the data It can be known that the parameter is transmitted / received only when the data enable (DE) signal is '0' and the selection signal EN is '1'. Also, even when the data enable (DE) signal is '0', it can be seen that neither the data nor the parameters are transmitted or received when the selection signal EN is '0'.

7 is a view illustrating another format of an LVDS signal transmitted and received between two integrated circuits applied to a display device according to the present invention during one cycle of a clock pulse. In particular, when an LVDS signal is transmitted through two ports Respectively. 8 is an exemplary diagram schematically showing parameters transmitted during two periods of a clock pulse of the LVDS signal shown in FIG.

3 to 6, data or parameters included in the LVDS signal are composed of 8 bits, and five differential signal transmission lines for transmitting and receiving 8-bit data or parameters are constituted by one Port. That is, in the present invention described with reference to FIGS. 3 to 6, the LVDS signal is transmitted through one port.

Thus, in this case, the number of total parameters that can be transmitted during one period of the clock pulse is two.

7 and 8 illustrate a state in which the LVDS signal is being transmitted through two ports. In the following description, the LVDS signal transmitted through the first port (Port # 1) is referred to as a first LVDS signal , And the LVDS signal transmitted through the second port (Port # 2) is referred to as a second LVDS signal.

The first LVDS signal transmitted through the first port shown in FIG. 7 includes first bits A10 through A17 of 8 bits, first parameters P110 through P117 of 8 bits, and second parameters P110 through P117 of 8 bits, Parameters P120 to 127 are included.

In addition, the second LVDS signal being transmitted through the second port shown in FIG. 7 includes 8-bit second addresses A20 to A27, 8-bit third parameters P210 to P217, and 8- Parameters P220 to P227 are included.

That is, in the first embodiment of the present invention described with reference to FIGS. 3 to 6, two parameters can be transmitted during one period of the clock pulse, but in the second embodiment of the present invention described with reference to FIGS. 7 and 8, In an embodiment, four parameters may be transmitted during one period of the clock pulse.

On the other hand, as mentioned in the first embodiment of the present invention described with reference to Figs. 3 to 6, in order to increase the reliability of transmitted parameters, the LVDS transmission interface 911 transmits one parameter to the first Parameter and the second parameter, the LVDS receiving interface 921 compares the first parameter and the second parameter, and can determine that one parameter is normally received only when the two are matched.

Therefore, the above-described verification process can be performed in the same manner in the second embodiment of the present invention shown in FIGS.

For example, FIG. 8 shows a state in which a parameter is being transmitted through a first LVDS signal and a second LVDS signal during two periods (B) of a clock pulse. Particularly, the first LVDS signal includes a first port Port # 1 And the second LVDS signal is being transmitted through the second port.

The first parameter (Param1_1_1) and the second parameter (Param1_1_2) are transmitted together with the first address (ADDR1_1) during one period (A) of the clock pulse of the first LVDS signal, The third parameter (Param1_2_1) and the fourth parameter (Param1_2_2) are transmitted together with the second address ADDR1_2 during one period (A ').

The fifth parameter (Param2_1_1) and the sixth parameter (Param2_1_2) are transmitted together with the third address ADDR2_1 during one period (A) of the clock pulse of the second LVDS signal, and another pulse of the clock pulse of the second LVDS signal The seventh parameter Param2_2_1 and the eighth parameter Param2_2_2 are transmitted along with the fourth address ADDR2_2 during one period A '.

At this time, as a first method, the present invention can transmit a total of eight parameters during two periods of a clock pulse.

As a second method, the present invention transmits an A parameter to a first parameter and a second parameter, transmits a B parameter to a third parameter and a fourth parameter, transmits a C parameter to a fifth parameter and a sixth parameter, The D parameter can be transmitted to the seventh parameter and the eighth parameter. In this case, the present invention can transmit a total of four parameters during two cycles of the clock pulse.

As a third method, the present invention transmits A parameters to the first parameter (Param1_1_1) and the second parameter (Param1_1_2) of the first LVDS signal, the fifth parameter (Param2_1_1) and the sixth parameter (Param2_1_2) of the second LVDS signal, The B parameter can be transmitted to the third parameter (Param1_2_1) and the fourth parameter (Param1_2_2) of the first LVDS signal and the seventh parameter (Param2_2_1) and the eighth parameter (Param2_2_2) of the second LVDS signal. In this case, the present invention can transmit a total of two parameters for two cycles of the clock pulse.

As a fourth method, the present invention transmits an A parameter to a first parameter and a third parameter, transmits a B parameter to a second parameter and a fourth parameter, transmits a C parameter to a fifth parameter and a seventh parameter, The D parameter can be transmitted to the sixth parameter and the eighth parameter. In this case, the present invention can transmit a total of four parameters during two cycles of the clock pulse.

As a fifth method, the present invention transmits an A parameter to a first parameter and a fifth parameter, transmits a B parameter to a second parameter and a sixth parameter, transmits a C parameter to a third parameter and a seventh parameter, D parameter to the fourth parameter and the eighth parameter. In this case, the present invention can transmit a total of four parameters during two cycles of the clock pulse.

Meanwhile, when the second, fourth, and fifth methods of the above methods are applied, the present invention can transmit four data or parameters of 16 bits in total.

Also, in the second method, the fourth method and the fifth method, the total number of parameters transmitted in (B) during two periods of the clock pulse is the same, but the transmission order of the parameters applied to verify one parameter is different . That is, in the second method and the fifth method, a verification process for one parameter is performed by comparing two parameters transmitted in the same period. In the fourth method, however, two parameters transmitted in different periods are compared A verification process is performed on the parameters of < / RTI >

That is, various methods other than the above-described methods can be applied to the method of performing the verification process for one parameter of the present invention.

The present invention as described above can be summarized as follows.

The present invention is characterized in that an LVDS line for data transmission is commonly used when transmitting parameters between two ICs 910 and 920. [

That is, the present invention transmits parameters through an LVDS interface used only for data transmission in a conventional display device. In other words, the present invention uses a section in which data is not transmitted (Invalid Data section) as a section for transmitting a parameter.

Therefore, the present invention does not need to change the structure of the LVDS interface used for general purpose, and is capable of deleting an I2C or SPI block having a complicated and large size that is conventionally required for parameter transmission.

To this end, according to the present invention, when the selection signal EN is high ('1') in an interval in which the data enable (DE) signal is low ('0' (DE) signal is high ('1'), the data is transferred to the LVDS signal.

Meanwhile, in an LVDS interface including five differential signal transmission lines for transmitting 8-bit data or parameters, an unused idle bit of an LVDS signal being transmitted through a fourth differential signal transmission line ), The bits of the data to which the values R10 to R17 are input are allocated to the addresses of the parameters, and the bits to which the values of G10 to G17 are input are assigned the first parameter of 8 bits (Parameter 1), and 8 bits of the second parameter (Parameter 2) are allocated to bits to which values B10 to B17 of the data are input.

That is, according to the present invention, an address and a parameter are associated with the position of the bit to which the data (R, G, B) values of each bit of the LVDS signal are input, A selection signal EN is assigned to an idle bit which has not been used in the apparatus to identify whether the current LVDS signal is transmitting data or whether it is transmitting a parameter.

Also, the present invention can transmit 16-bit parameters using the 8-bit first parameter (Parameter 1) and the second parameter (Parameter 2).

Further, in order to prevent an error in transmission of a parameter caused by noise or the like, the present invention is characterized in that, in order to prevent an error in transmission of parameters due to noise or the like, the A parameter is transmitted by overlapping with the first parameter and the second parameter, It may be determined that the A parameter has been normally transmitted only when the parameters are the same.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

910: Main IC 911: LVDS transmit interface
912: selection unit 913:
914: control unit 920; Sub IC
921: LVDS reception interface 922:

Claims (14)

A panel in which data lines and gate lines are formed so as to intersect to output an image;
A data driver driving the data lines;
A gate driver for driving the gate lines; And
And a plurality of integrated circuits for driving at least one of the data driver, the gate driver, and the panel,
The integrated circuits include:
A main integrated circuit for incorporating data or parameters in an LVDS signal and for transmitting the LVDS signal via an LVDS line, in accordance with a selection signal for selecting whether to transmit data or parameters; And
And a sub-integrated circuit for extracting the data or the parameter from the LVDS signal transmitted from the main integrated circuit using the selection signal. The method according to claim 1,
The main integrated circuit includes:
A control unit for generating the selection signal; And
And an LVDS transmission interface for transmitting the data or the parameter via the LVDS line to the sub-integrated circuit according to the selection signal transmitted from the control unit. 3. The method of claim 2,
Wherein,
When the data enable (DE) signal is '1' and the data is to be transmitted according to an algorithm executed in the main integrated circuit, the selection signal is set to '0'
The display device according to claim 1, wherein the data enable (DE) signal is '0', and when the parameter is transmitted according to an algorithm executed in the main integrated circuit, the selection signal is set to '1'. The method of claim 3,
The LVDS transmission interface includes:
A selector for selecting the data or the parameter according to the selection signal; And
And a transmitter for transmitting the data or the parameter selected through the selection unit to the sub-integrated circuit by including the selected data or the parameter in the LVDS signal. 5. The method of claim 4,
Wherein the selection unit comprises:
And transmits the data to the transmission unit when '0' is input as the selection signal,
And transmits the parameter to the transmission unit when '1' is input as the selection signal. 6. The method of claim 5,
The transmitter may further comprise:
A plurality of transmitters for changing the select signal and the data or parameter into the LVDS signal; And
And a plurality of differential signal transmission lines connected to each of the plurality of transmitters by two differential lines,
And a first port including the differential signal transmission lines forms the LVDS line. The method according to claim 6,
Wherein the first port forming the transmitter comprises:
A zero-th differential signal transmission line for transmitting a clock pulse; And
And a plurality of differential signal transmission lines for transmitting 7 bits each during one period of the clock pulse,
Wherein the selection signal is included in one of the differential signal transmission lines. 8. The method of claim 7,
The transmitter may further comprise:
For one period of the clock pulse transmitted to the LVDS line through the first port, to the LVDS line,
And transmits the data including R, G, and B each consisting of 8 bits and the selection signal set to transmit the data,
And transmits the 8-bit address, the first parameter and the second parameter, and the selection signal set to transmit the parameters, respectively. 9. The method of claim 8,
The transmitter may further comprise:
A parameter to the first parameter and the second parameter twice,
Wherein the sub-
And determines that the A parameter has been normally transmitted when it is determined that the first parameter and the second parameter are identical. 9. The method of claim 8,
The transmitter may further comprise:
Transmits the selection signal set to transmit the third parameter and the fourth parameter and the parameters via the LVDS line for another one consecutive period after the one period,
Wherein the sub-
When it is determined that the first parameter and the third parameter are identical, it is determined that the A parameter is normally transmitted, and when it is determined that the second parameter and the fourth parameter are identical, it is determined that the B parameter is normally transmitted And the display device. 9. The method of claim 8,
The transmitter may further comprise:
A zero-th differential signal transmission line for transmitting another clock pulse; And a second port including a plurality of differential signal transmission lines for transmitting 7 bits each during one period of the another clock pulse,
And transmitting the selection signal set to transmit the another data and another data including R, G, and B composed of 8 bits, respectively, through the plurality of differential signal transmission lines of the second port,
And transmits the address composed of 8 bits, the third parameter and the fourth parameter, and the selection signal set to transmit the parameters. 12. The method of claim 11,
The transmitter may further comprise:
A parameter is transmitted twice as the first parameter and the third parameter, and the B parameter is transmitted twice as the second parameter and the fourth parameter,
Wherein the sub-
When it is determined that the first parameter and the third parameter are identical to each other, it is determined that the A parameter is normally transmitted, and when it is determined that the second parameter and the fourth parameter are identical, And judges that the display device is in the standby state. The method according to claim 1,
Wherein the sub-
A receiver for receiving the LVDS signal transmitted from the main integrated circuit through the LVDS line; And
(DE) signal included in the LVDS signal is '1' and the selection signal is '0', the data included in the LVDS signal is extracted and aligned, and the data enable And a data arrangement unit for extracting and arranging the parameters included in the LVDS signal when the DE signal is '0' and the selection signal is '1'. The method according to claim 1,
Wherein the R, G, and B values constituting the data are input to each bit of the LVDS signal, or an address and a parameter value constituting the parameter are input.

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