KR102519822B1 - Organic Light Emitting Diode Display - Google Patents

Abstract

The present invention provides a display panel including a plurality of pixels each having a light emitting diode, a data driver supplying a plurality of data signals to the plurality of pixels, and a gate unit supplying a plurality of gate signals to the plurality of pixels. And, a gate driver including an emission unit for supplying a plurality of emission signals to the plurality of pixels using a charge pumping element to control the length of the light emitting section of the light emitting diode, and image data and data control to the data driver An organic light emitting diode display device including a timing control unit supplying a signal and supplying a gate control signal to the gate driver, wherein a high potential voltage is continuously applied to an emission QB node of the gate driver using a charge pumping capacitor. By doing so, the length of the light emitting section of the light emitting diode is controlled, power consumption is reduced, the bezel is reduced, and the display quality is improved.

Description

Organic Light Emitting Diode Display {Organic Light Emitting Diode Display}

The present invention relates to an organic light emitting diode display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and recently, liquid crystal displays (LCDs), plasma display panels (PDPs), Various flat display devices such as organic light emitting diode devices (DEs) are being utilized.

Among them, the organic light emitting diode display uses a self-emitting element that emits light by itself. It has the advantages of fast response speed, high luminous efficiency, luminance and viewing angle. In such an organic light emitting diode display device, a current driving method in which the amount of current is controlled and the luminance of the organic light emitting diode is controlled is generally used.

However, in the organic light emitting diode display device, the light emitting diode continuously emits light during each frame period to display an image, and for this purpose, the driving thin film transistor continuously maintains a turn-on state, so the driving thin film transistor of deterioration occurs.

That is, in order to induce the driving TFT to turn-on, a data signal of the same polarity is applied to the gate electrode of the driving TFT for a long time (gate bias stress), and thus the interface characteristics between the gate electrode of the driving TFT and the gate insulating film. As a result, the threshold voltage (Vth) of the driving thin film transistor and the characteristics of the display panel are changed, thereby degrading the display quality of the organic light emitting diode display.

In order to prevent the degradation of the display quality of organic light emitting diode display devices, a driving method for detecting and compensating for changes in threshold voltage and characteristics of a display panel has been proposed. In order to detect, one frame is divided into a compensation period and a display period, and the image data is modulated by detecting the characteristic change of each pixel without operating the light emitting diode during the compensation period, and the modulated image during the remaining display period except for the compensation period An image is displayed by operating the light emitting diode according to the data.

In order to prevent the light emitting diodes from emitting light during the compensation period and to make the light emitting diodes emit light during the display period, the gate driver includes a gate part outputting a scan signal and an emission part outputting an emission signal, which will be described with reference to the drawings. do.

1 is a view showing a gate part of a gate driving part of a conventional organic light emitting diode display device, and FIG. 2 is a view showing an emission part of a gate driving part of a conventional organic light emitting diode display device.

As shown in FIG. 1, the gate part of the gate driver of the conventional organic light emitting diode display device is composed of a shift register including a plurality of stages, and the nth stage (GD(n) of the shift register )) is the n-th gate signal using the gate start voltage (GVST), the first, third, and fifth gate clocks (GCLK1, GCLK3, and GCLK5), the gate high potential voltage (GVDD), and the gate low potential voltage (GVSS). produces (GS(n)).

Specifically, the nth stage GD(n) of the shift register includes first to eighth transistors T1 to T8 and a first capacitor C1.

The gate of the first transistor T1 is connected to the terminal to which the gate start voltage GVST is supplied, the drain of the first transistor T1 is connected to the terminal to which the gate high potential voltage GVDD is supplied, and The source of (T1) is connected to the drain of the second transistor (T2).

The gate of the second transistor T2 is connected to the terminal to which the fifth gate clock GCLK5 is supplied, the drain of the second transistor T2 is connected to the source of the first transistor T1, and the second transistor T2 ) is connected to the drain of the third transistor T3.

The gate of the third transistor T3 is connected to the gate QB node GQB, the drain of the third transistor T3 is connected to the source of the second transistor T2, and the source of the third transistor T3 is connected to the gate. It is connected to low potential voltage (GVSS).

The gate of the fourth transistor T7 is connected to the terminal to which the third gate clock GCLK3 is supplied, the drain of the fourth transistor T7 is connected to the terminal to which the gate high potential voltage GVDD is applied, and The source of transistor T7 is connected to the gate QB node GQB.

The gate of the fifth transistor T5 is connected to the terminal to which the gate start voltage GVST is supplied, the drain of the fifth transistor T5 is connected to the gate QB node GQB, and the source of the fifth transistor T5. is connected to the terminal to which the gate low potential voltage (GVSS) is supplied.

The gate of the sixth transistor T6 is connected to the gate Q node GQ, the drain of the sixth transistor T6 is connected to the terminal to which the first gate clock GCLK1 is supplied, and the The source is connected to the drain of the seventh transistor T7.

The gate of the seventh transistor T7 is connected to the gate QB node GQB, the drain of the seventh transistor T7 is connected to the source of the sixth transistor T6, and the source of the seventh transistor T7 is connected to the gate. It is connected to the terminal to which low potential voltage (GVSS) is supplied.

Here, the nth gate signal GS(n) is output from the node between the sixth and seventh transistors T6 and T7, and the node between the sixth and seventh transistors T6 and T7 and the gate Q node ( A first capacitor C1 is connected between GQ).

The gate of the ninth transistor T8 is connected to the gate Q node GQ, the drain of the ninth transistor T8 is connected to the gate QB node GQB, and the source of the ninth transistor T8 is connected to the gate low potential. It is connected to the terminal to which the voltage (GVSS) is supplied.

And, as shown in FIG. 2, the emission part of the gate driver of the conventional organic light emitting diode display device is composed of an inverter including a plurality of stages, and the nth stage (ED(n) of the inverter )) is the n-th gate signal GS(n) generated in the gate unit, the first, second, third, and fifth emission clocks ECLK1, ECLK2, ECLK3, and ECLK5, and the emission reset voltage ERST , an nth emission signal ES(n) is generated using the emission high potential voltage EVDD and the emission low potential voltage EVSS.

Specifically, the nth stage ED(n) of the inverter includes ninth to eighteenth transistors T9 to T18 and a second capacitor C2.

The gate of the ninth transistor T9 is connected to a terminal to which the first emission clock ECLK1 is supplied, and the drain of the ninth transistor T9 is connected to a terminal to which the emission high potential voltage EVDD is supplied. The source of the ninth transistor T9 is connected to the emission Q node EQ.

The gate of the tenth transistor T10 is connected to the emission QB node EQB, the drain of the tenth transistor T10 is connected to the emission Q node EQ, and the source of the tenth transistor T10 is connected to the emission Q node EQB. It is connected to the terminal to which the voltage switcher potential (EVSS) is supplied.

The gate of the eleventh transistor T11 is connected to the terminal to which the third emission clock ECLK3 is supplied, and the drain of the eleventh transistor T11 receives the (n−1)th gate signal GS(n−1). is connected to the supply terminal, and the source of the eleventh transistor T11 is connected to the emission QB node EQB.

The gate of the twelfth transistor T12 is connected to the emission Q node EQ, the drain of the twelfth transistor T12 is connected to a terminal to which the emission high potential voltage EVDD is supplied, and the twelfth transistor T12 The source of ) is connected to the drain of the thirteenth transistor T13.

The gate of the thirteenth transistor T13 is connected to the emission QB node EQB, the drain of the thirteenth transistor T13 is connected to the source of the twelfth transistor T12, and the source of the thirteenth transistor T13 is It is connected to the drain of the 14th transistor T14.

Here, the nth emission signal ES(n) is output from the node between the 12th and 13th transistors T12 and T13, and the node between the 12th and 13th transistors T12 and T13 and the emission Q A second capacitor C2 is connected between the nodes EQ.

The gate of the 14th transistor T14 is connected to the emission QB node EQB, the drain of the 14th transistor T14 is connected to the source of the 13th transistor T13, and the source of the 14th transistor T14 is It is connected to the terminal to which the emission low potential voltage (EVSS) is supplied.

The gate of the fifteenth transistor T15 is connected to the terminal to which the nth gate signal GS(n) is supplied, and the drain of the fifteenth transistor T15 is connected to the terminal to which the emission return voltage ERST is supplied. , the source of the 15th transistor T15 is connected to the emission QB node EQB.

The gate of the sixteenth transistor T16 is connected to the terminal to which the fifth emission clock ECLK5 is supplied, the drain of the sixteenth transistor T16 is connected to the emission QB node EQB, and the sixteenth transistor T16 ) is connected to the terminal to which the emission low potential voltage (EVSS) is supplied.

The gate of the 17th transistor T17 is connected to a node between the 13th and 14th transistors T13 and T14, the drain of the 17th transistor T17 is connected to the emission high potential voltage EVDD, and A source of the transistor T17 is connected to a node between the fourteenth and fifteenth transistors T14 and T15.

The gate of the 18th transistor T18 is connected to the terminal to which the second emission clock ECLK2 is supplied, the drain of the 18th transistor T18 is connected to the emission QB node EQB, and the 18th transistor T18 ) is connected to the terminal to which the emission low potential voltage (EVSS) is supplied.

As described above, in the conventional organic light emitting diode display device, while keeping the light emitting diode of each pixel in an off state according to the emission signal of the emission part of the gate driving part during the compensation period of one frame, the characteristic change is sensed and image data is obtained. modulated, and maintains the light emitting diode of each pixel in an on state according to the emission signal of the emission part of the gate driver during the display period set as the rest of the frame except for the compensation period to display the image.

However, as the resolution of display devices has recently increased, the total number of pixels has increased and the driving current for peak luminance emitted by one pixel has decreased. However, there is a problem in that there is a limit to lowering the voltage supplied by the driving unit.

In addition, at a lower level of driving current for low gradation display, variation in the characteristics of the plurality of thin film transistors of the display device further increases, resulting in deterioration in display quality such as stains.

In order to improve this, a driving method has been proposed in which the entire luminance of the display device is maintained constant by emitting light with a higher level of driving current instead of emitting light only in a partial section of one frame.

In addition, as the resolution increases, the area allocated to one pixel decreases and the size of the storage capacitor of each pixel decreases. As a result, display quality degradation such as flicker may occur. Even in this case, the display period of one frame Deterioration in display quality can be improved by applying a driving method of increasing driving current instead of reducing the middle light emission period.

In addition, since response characteristics act as the most important factor in display devices in some special fields such as virtual reality that have recently been proposed, duty driving (duty driving or A driving method such as a rolling shutter) is required.

However, the driving unit capable of freely adjusting the emission period among the display periods of one frame, which has been proposed up to now, has problems such as increased power consumption, increased bezel, or signal distortion.

The present invention is to solve the above problems, and to provide an organic light emitting diode display device in which the length of the light emitting section of the light emitting diode is controlled by continuously applying a high potential voltage to the emission QB node of the gate driver. do.

In addition, in the present invention, by continuously applying a high potential voltage to the emission QB node of the gate driver using a charge pumping capacitor, the length of the light emitting section of the light emitting diode is controlled, power consumption is reduced, the bezel is reduced, and the display Another object is to provide an organic light emitting diode display with improved quality.

In order to achieve the above object, the present invention provides a display panel including a plurality of pixels each having a light emitting diode, a data driver supplying a plurality of data signals to the plurality of pixels, and a plurality of pixels. a gate driver including a gate unit supplying a plurality of gate signals to a gate unit and an emission unit supplying a plurality of emission signals to the plurality of pixels using a charge pumping device to control the length of a light emitting section of the light emitting diode; and a timing controller supplying image data and a data control signal to the data driver and supplying a gate control signal to the gate driver.

In addition, the emission unit includes a plurality of stages connected to each other dependently, and each of the plurality of stages includes a Q node for determining that the plurality of emission signals are output at a high level, and the plurality of emission signals are It may include a QB node that determines the low level output, a Q' node that determines that the QB node has the high level, and the charge pumping element connected to the Q' node.

In addition, an emission clock may be supplied to the charge pumping device, and the Q' node may be switched from a floating state to the high level by the emission clock and the charge pumping device.

Also, the charge pumping element may be a charge pumping capacitor or a charge pumping thin film transistor.

In addition, the emission unit generates the plurality of emission signals using an emission start voltage, an emission reset voltage, a plurality of emission clocks, and the plurality of gate signals, and the plurality of emission clocks are first to and a fifth emission clock, wherein the plurality of gate signals include nth and (n−1)th gate signals, and the plurality of emission signals include nth and (n−1)th emission signals. The plurality of stages may include an nth stage, and the nth stage may include ninth to twentieth transistors, a second capacitor, and the charge pumping device.

The gate, drain, and source of the ninth transistor are respectively connected to the first emission clock, the emission high potential voltage, and the drain of the tenth transistor, and the gate, drain, and source of the tenth transistor are respectively connected to the The (n−1)th emission signal or the emission start voltage is connected to the source of the ninth transistor and the Q node, and the gate, drain, and source of the eleventh transistor are connected to the QB node, the Q node and the Q node, respectively. The gate of the twelfth transistor is connected to the (n−1)th gate signal, the emission high potential voltage, and the QB node, respectively, and the drain and source of the gate of the twelfth transistor are connected to the gate of the thirteenth transistor. , the drain and source are connected to the Q node, the emission high potential voltage and the drain of the 14th transistor, respectively, and the gate, drain and source of the 14th transistor are connected to the QB node, the source and the source of the 13th transistor, respectively. connected to the drain of the 15th transistor, the gate, drain and source of the 15th transistor connected to the QB node, the source and the emission low potential voltage of the 14th transistor, respectively, and the gate and drain of the 16th transistor and a source connected to the n-th gate signal, the emission-receive voltage, and the QB node, respectively, and the gate, drain, and source of the 17th transistor are respectively connected to a node between the 13th and 14th transistors, the emission classic above voltage and a node between the 14th and 15th transistors, and the gate, drain and source of the 18th transistor are connected to the second emission clock, the QB node and the emission low potential voltage, respectively. The gate, drain, and source of the 19th transistor are connected to the Q' node, the emission high potential voltage, and the QB node, respectively, and the gate, drain, and source of the 20th transistor are respectively connected to the (n-1)th transistor. connection signal or the emission start voltage, the Q' node and the emission low potential voltage, the second capacitor is connected between a node between the 13th and 14th transistors and the Q node, and the charge pumping An element may be connected between the first emission clock and the Q′ node, and the nth emission signal may be output from a node between the 13th and 14th transistors.

In addition, the emission unit generates the plurality of emission signals using an emission start voltage and a plurality of emission clocks, the plurality of emission clocks include first and second emission clocks, and the plurality of emission clocks The emission signal of includes the nth and the (n−1)th emission signals, the plurality of stages includes an nth stage, and the nth stages include 9th to 11th, 13th to 15th, Seventeenth to twentieth transistors, a second capacitor, and the charge pumping device may be included.

The gate, drain, and source of the ninth transistor are respectively connected to the first emission clock, the emission high potential voltage, and the drain of the tenth transistor, and the gate, drain, and source of the tenth transistor are respectively connected to the The (n−1)th emission signal or the emission start voltage is connected to the source of the ninth transistor and the Q node, and the gate, drain, and source of the eleventh transistor are connected to the QB node, the Q node and the Q node, respectively. The gate, drain and source of the thirteenth transistor are connected to the Q node, the emission high potential voltage and the drain of the fourteenth transistor, respectively, and the gate, drain, and source of the fourteenth transistor are connected to the low emission potential voltage. A source is connected to the QB node, the source of the thirteenth transistor and the drain of the fifteenth transistor, respectively, and the gate, drain, and source of the fifteenth transistor are connected to the QB node, the source of the fourteenth transistor, and the emitter, respectively. a potential voltage, and the gate, drain, and source of the seventeenth transistor are respectively connected to a node between the thirteenth and fourteenth transistors, the emission high potential voltage, and a node between the fourteenth and fifteenth transistors, The gate, drain and source of the 18th transistor are respectively connected to the second emission clock, the QB node and the emission low potential voltage, and the gate, drain and source of the 19th transistor are respectively connected to the Q'node and the emission low potential voltage. connected to the emission high potential voltage and the QB node, and the gate, drain, and source of the twentieth transistor are respectively the (n-1)th emission signal or the emission start voltage, the Q' node, and the emitter a potential voltage, the second capacitor is connected between a node between the 13th and 14th transistors and the Q node, and the charge pumping device is connected between the first emission clock and the Q'node; , the n-th emission signal may be output from a node between the 13th and 14th transistors.

As described above, the length of the light emitting section of the light emitting diode is controlled by continuously applying the high potential voltage to the emission QB node of the gate driver.

In addition, in the present invention, by continuously applying a high potential voltage to the emission QB node of the gate driver using a charge pumping capacitor, the length of the light emitting section of the light emitting diode is controlled, power consumption is reduced, the bezel is reduced, and the display It has the effect of improving quality.

1 is a view showing a gate part of a gate driving part of a conventional organic light emitting diode display device;
2 is a view showing an emission part of a gate driving part of a conventional organic light emitting diode display device;
3 is a view showing an organic light emitting diode display device according to a first embodiment of the present invention.
4 is a diagram illustrating pixels of an organic light emitting diode display device according to a first embodiment of the present invention.
5 is a diagram illustrating a gate driver of an organic light emitting diode display device according to a first embodiment of the present invention.
6 is a view showing one stage of an emission unit of a gate driving unit of an organic light emitting diode display device according to a first embodiment of the present invention.
7 is a timing diagram of signals related to one stage of an emission unit of a gate driver of an organic light emitting diode display device according to a first embodiment of the present invention.
8 is a view showing a gate driver of an organic light emitting diode display device according to a second embodiment of the present invention.
9 is a view showing one stage of an emission unit of a gate driving unit of an organic light emitting diode display device according to a second embodiment of the present invention.
10 is a timing diagram of signals related to one stage of an emission unit of a gate driver of an organic light emitting diode display device according to a second embodiment of the present invention.
11 is a view showing one stage of an emission unit of a gate driving unit of an organic light emitting diode display device according to a third embodiment of the present invention.
12 is a timing diagram of signals related to one stage of an emission unit of a gate driver of an organic light emitting diode display device according to a third embodiment of the present invention.
13 is a diagram illustrating pixels of an organic light emitting diode display device according to a second embodiment of the present invention.
14 is a timing diagram illustrating driving signals of the pixels shown in FIG. 13;
15 is a view showing a gate driver according to a second embodiment of the present invention.
16 is a diagram showing one stage of an emission unit according to a fourth embodiment of the present invention.
17 is a timing diagram of signals related to one stage of the emission unit shown in FIG. 16;
18 is a diagram illustrating one stage of an emission unit according to a fifth embodiment;
19 is a diagram showing gate-off voltage delay of an emission signal;
20 is a diagram showing a pixel structure according to a third embodiment.
21 is a diagram illustrating driving signals of the pixels shown in FIG. 20;

Hereinafter, an organic light emitting diode display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Switch elements in the gate driving circuit of the present invention may be implemented as n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structured transistors. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in an n-type MOSFET, the direction of the current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on the applied voltage. Accordingly, the source and drain of the transistor may be referred to as a first electrode (or second electrode) and a second electrode (or first electrode), respectively. The invention should not be limited by the sources and drains of the transistors in the following embodiments.

In this specification, gate-on voltage refers to an operating voltage capable of turning on a transistor. Accordingly, the gate-on voltage in the n-type MOSFET means a high voltage level, and the gate-on voltage in the p-type MOSFET means a low-level voltage. Similarly, a gate-off voltage in an n-type MOSFET means a low voltage level, and a gate-off voltage in a p-type MOSFET means a high-level voltage.

3 is a diagram illustrating an organic light emitting diode display device according to a first embodiment of the present invention.

As shown in FIG. 3 , the organic light emitting diode display device 110 according to the first embodiment of the present invention includes a timing controller 120, a data driver 130, a gate driver 140 and a display panel 150. includes

The timing controller 120 includes a video signal IS, a data enable signal DE, a horizontal synchronization signal HSY, a vertical synchronization signal VSY, and a clock signal CLK transmitted from an external system such as a graphic card or a TV system. ) are used to generate a gate control signal (GCS), a data control signal (DCS), and image data (RGB), and the generated data control signal (DCS) and image data (RGB) are data is supplied to the driver 130, and the generated gate control signal GCS is supplied to the gate driver 130.

The data driver 130 generates a data signal using the data control signal DCS and the image data RGB supplied from the timing controller 120, and transmits the generated data signal to the data wiring ( DL) is supplied.

The gate driver 140 generates a gate signal and an emission signal using the gate control signal (GCS) supplied from the timing controller 120, and transmits the generated gate signal and emission signal to the display panel 150, respectively. The gate driver 140 is a display panel on which the gate line GL, data line DL, emission line EL, and pixel P are formed. It may be a gate in panel (GIP) type formed together with the substrate of (150).

The display panel 150 displays an image using a gate signal and a data signal.

Specifically, the display panel 150 includes gate lines GL and data lines DL that cross each other to define the pixel area P, and pixels (connected to the gate lines GL and data lines DL). P) and an emission line EL connected to the pixel P.

This organic light emitting diode display device 110 compensates for the characteristic change of each pixel P using a gate signal, data signal, and emission signal, and displays an image while simultaneously controlling the length of an emission section. to explain.

FIG. 4 is a diagram showing pixels of an organic light emitting diode display according to the first embodiment of the present invention, and a 4T2C structure in which one pixel P includes four transistors and two capacitors will be described as an example.

As shown in FIG. 4, the pixel P of the organic light emitting diode display device 110 according to the first embodiment of the present invention includes a switching transistor Ts, an emission transistor Te, and a driving transistor Td. , an initial transistor Ti, a light emitting diode De, and first and second pixel capacitors Cp1 and Cp2.

In FIG. 4, the switching transistor (Ts), the emission transistor (Te), the driving transistor (Td), and the initial transistor (Ti) are each negative type (n type) as an example, but in another embodiment, the switching transistor (Ts), The emission transistor Te, the driving transistor Td, and the initial transistor Ti may be configured as a positive type (p type).

The switching transistor Ts transfers the m-th data signal of the m-th data line DLm to the driving transistor Td according to the n-th gate signal GS(n). The source is connected to the nth gate line GLn, the mth data line DLm, and the first node N1, respectively.

The emission transistor Te transfers the high potential voltage Vdd to the second node N2 according to the nth emission signal ES(n). The gate, drain and source of the emission transistor Te are Each is connected to the nth emission line ELn, the high potential voltage Vdd input terminal, and the second node N2.

The driving transistor Td transfers the voltage of the second node N2 to the third node N3 according to the voltage of the first node N2, and the gate, drain, and source of the driving transistor Td are respectively It is connected to the node N1, the second node N2, and the third node N3.

The initial transistor Ti transfers the initial voltage Vinit to the third node N3 according to the (n-1)th gate signal, and the gate, drain, and source of the initial transistor Ti are each the (n-1)th node. ) is connected to the gate wiring GL(n-1), the input terminal of the initial voltage Vinit, and the third node N3.

The organic light emitting diode E emits light according to the voltage of the third node N3, and the anode and cathode of the organic light emitting diode E are respectively connected to the third node N3 and the input terminal of the low potential voltage Vss.

The first pixel capacitor Cp1 is connected between the first and third nodes N1 and N3, and the second pixel capacitor Cp2 is connected between the input terminal of the high potential voltage Vdd and the third node N3. .

The first pixel capacitor Cp1 has a threshold voltage of the driving transistor Td during the compensation period according to the nth emission signal ES(n) and the (n−1)th gate signal GS(n−1). (Vth) and maintains the voltage of the gate of the driving transistor Td constant for one frame according to the nth emission signal ES(n) and the nth gate signal GS(n). do.

The second pixel capacitor Cp2 serves to stabilize the voltage of the gate of the driving transistor Td and to increase the efficiency of the mth data signal DS(m).

In this way, the gate driver 140 of the organic light emitting diode display device 110 according to the first embodiment of the present invention generates a gate signal and an emission signal and supplies them to each pixel P, and the organic light emitting diode display device The pixel (P) of (110) detects the threshold voltage of the driving transistor (Td) during the compensation period of one frame according to the gate signal and the emission signal and transfers it to the timing control unit 120, the gate signal and the emission signal According to this method, an image is displayed using modulated image data generated by the timing controller 120 by reflecting a change in the threshold voltage during a display period of one frame, thereby preventing the display quality of the image from deteriorating.

In addition, the gate driver 140 of the organic light emitting diode display device 110 according to the first embodiment of the present invention adjusts the high level section and the low level section of the emission signal so that each pixel It is possible to control the length of the light emitting section among the display sections of (P), which will be described with reference to the drawings.

5 is a view showing the gate driving unit of the organic light emitting diode display device according to the first embodiment of the present invention, and FIG. 6 is the emission unit of the gate driving unit of the organic light emitting diode display device according to the first embodiment of the present invention. 7 is a timing diagram of signals related to one stage of the emission unit of the gate driver of the organic light emitting diode display according to the first embodiment of the present invention.

As shown in FIG. 5, the gate driver 140 of the organic light emitting diode display 110 according to the first embodiment uses a start voltage, a clock, a reset voltage, a high potential voltage, and a low potential voltage to A gate unit 142 for generating a gate 1 signal (G1S(n)) and a plurality of gate 2 signals (G2S(n)) and an emission unit 144 for generating a plurality of emission signals (ES(n)) include

The gate unit 142 includes a first shift register including a plurality of stages GD1(n) and generating a plurality of gate 1 signals G1S(n), and a plurality of stages GD2(n). )) and a second shift register for generating a plurality of gate 2 signals (G2S(n)), and the emission unit 144 includes a plurality of stages (ED(n)) to generate a plurality of emission signals It consists of an inverter that generates (ES(n)).

Specifically, the first shift register of the gate unit 142 includes the gate 1 start voltage (G1VST) or the output of the previous stage (G1S(n-1)), the first to fifth gate 1 clocks (G1CLK1 to G1CLK5), the gate A plurality of gate 1 signals (G1S(n)) are generated using the high potential voltage and the gate low potential voltage, and the second shift register of the gate unit 142 is the gate 2 start voltage (G2VST) or the output of the previous stage ( G2S(n-1)), the first to fifth gate 2 clocks (G2CLK1 to G2CLK5), the gate high potential voltage (GVDD) and the gate low potential voltage (GVSS) using a plurality of gate 2 signals (G2S(n)). ) to create

In addition, the inverter of the emission unit 144 outputs the first and second emission start voltages EVST1 and EVST2 or the previous stage outputs ES(n-1) and ES(n-2), and the first to fifth A plurality of emission signals (ES(n)) are generated using the emission clocks (ECLK1 to ECLK5), the emission reset voltage (ERST), the emission high potential voltage (EVDD), and the emission low potential voltage (EVSS). .

For example, the first stage GD(1) of the first shift register of the gate unit 142 includes the gate 1 start voltage G1VST, the first, third, and fifth gate 1 clocks G1CLK1, G1CLK3, G1CLK5), the gate high potential voltage (GVDD) and the gate low potential voltage (GVSS) are used to generate the first gate 1 signal (G1S(1)), and the first stage of the second shift register of the gate unit 142 (GD(2)) is the gate 2 start voltage (G2VST), the first, third and fifth gate 2 clocks (G2CLK1, G2CLK3, G2CLK5), the gate high potential voltage (GVDD) and the gate low potential voltage (GVSS). The first gate 2 signal (G2S(1)) is generated by using the first gate 2 signal (G2S(1)), and the first stage (ED(1)) of the inverter of the emission unit 144 is the first emission start voltage (EVST1) and the gate 2 start voltage ( G2VST), emission reset voltage (ERST), first, second and third emission clocks (ECLK1, ECLK2, ECLK3), emission high potential voltage (EVDD) and emission low potential voltage (EVSS). 1 emission signal ES(1) can be generated.

As such, multiple stages (GD1(n)) of the first shift register of the gate unit 142, multiple stages (GD2(n)) of the second shift register, and multiple stages (ED) of the emission unit 144 (n)) forms a mutually dependent connection relationship, and through each output node, a plurality of gate 1 signals (G1S (n)), a plurality of gate 2 signals (G2S (n)), and a plurality of emission signals (ES (n)) may be sequentially supplied to the pixels P of the display panel 150 .

Meanwhile, each of the stages G1D(n) and G2D(n) of the first and second shift registers of the gate unit 142 of the gate driver 140 includes the first to eighth transistors and the first to eighth transistors as shown in FIG. 1 . Capacitors may be included.

And, as shown in FIG. 6, each stage ED(n) of the inverter, which is the emission unit 144 of the gate driver 140, includes the 9th to 16th transistors T9 to T16 and the second capacitor ( C2).

The gate of the ninth transistor T9 is connected to a terminal to which the first emission clock ECLK1 is supplied, and the drain of the ninth transistor T9 is connected to a terminal to which the emission high potential voltage EVDD is supplied. The source of the ninth transistor T9 is connected to the drain of the tenth transistor T10.

The gate of the tenth transistor T10 is connected to a terminal to which the (n-2)th emission signal ES(n-2) (or the first and second emission start voltages EVST1 and EVST2) are supplied. , The drain of the tenth transistor T10 is connected to the source of the ninth transistor T9, and the source of the tenth transistor T10 is connected to the emission Q node EQ.

The gate of the eleventh transistor T11 is connected to the emission QB node EQB, the drain of the eleventh transistor T11 is connected to the emission Q node EQ, and the source of the eleventh transistor T11 is connected to the emission QB node EQB. It is connected to the terminal to which the voltage switcher potential (EVSS) is supplied.

The gate of the twelfth transistor T12 is connected to the terminal to which the third emission clock ECLK3 is supplied, and the drain of the twelfth transistor T12 receives the (n−1)th gate second signal G2S(n−1). ) (or the gate 2 start voltage G2VST) is connected to the terminal supplied, and the source of the twelfth transistor T12 is connected to the emission QB node EQB.

The gate of the thirteenth transistor T13 is connected to the emission Q node EQ, the drain of the thirteenth transistor T13 is connected to a terminal to which the emission high potential voltage EVDD is supplied, and the thirteenth transistor T13 The source of ) is connected to the drain of the 14th transistor T14.

The gate of the 14th transistor T14 is connected to the emission QB node EQB, the drain of the 14th transistor T14 is connected to the source of the 13th transistor T13, and the source of the 14th transistor T14 is It is connected to the drain of the fifteenth transistor T15.

Here, the nth emission signal ES(n) is output from the node between the 13th and 14th transistors T13 and T14, and the node between the 13th and 14th transistors T13 and T14 and the emission Q A second capacitor C2 is connected between the nodes EQ.

The gate of the fifteenth transistor T15 is connected to the emission QB node EQB, the drain of the fifteenth transistor T15 is connected to the source of the fourteenth transistor T14, and the source of the fifteenth transistor T15 is It is connected to the terminal to which the emission low potential voltage (EVSS) is supplied.

The gate of the sixteenth transistor T16 is connected to a terminal to which the nth gate 1 voltage GS1(n) is supplied, and the drain of the sixteenth transistor T16 is connected to a terminal to which the emission receiving voltage ERST is supplied. and the source of the sixteenth transistor T16 is connected to the emission QB node EQB.

The gate of the 17th transistor T17 is connected to a node between the 13th and 14th transistors T13 and T14, the drain of the 17th transistor T17 is connected to the emission high potential voltage EVDD, and A source of the transistor T17 is connected to a node between the fourteenth and fifteenth transistors T14 and T15.

The gate of the 18th transistor T18 is connected to the terminal to which the second emission clock ECLK2 is supplied, the drain of the 18th transistor T18 is connected to the emission QB node EQB, and the 18th transistor T18 ) is connected to the terminal to which the emission low potential voltage (EVSS) is supplied.

Here, although the plurality of transistors of the gate unit 142 and the emission unit 144 are of the negative type (n type) as an example, in another embodiment, the plurality of transistors of the gate unit 142 and the emission unit 144 are positive. It can also be composed of a type (p type).

Looking at the operation timing of the emission unit 144, as shown in FIG. 7, the (n-1)th gate 2 signal (G2S(n-1)) (or gate 2 start) at the first timing (TM1) When the voltage (G2VST) and the third emission clock (ECLK3) become high level, the emission QB node (EQB) becomes high level and the fourteenth and fifteenth transistors (T14, T15) are turned on. on), the emission low potential voltage EVSS is output as the nth emission signal ES(n) of low level, and the initial voltage Vinit is applied to the third node N3 of each pixel P. do.

At the second timing TM2, the (n-2)th emission signal ES(n-2) (or the first and second emission start voltages EVST1 and EVST2) and the first emission clock ECLK1 When this high level is reached, the ninth and tenth transistors (T9, T10) are turned on, the emission Q node (EQ) becomes high level, and the thirteenth transistor (T13) is turned on, resulting in high emission potential. The voltage EVDD is output as the high-level nth emission signal ES(n), and the voltage of the third node N3 of each pixel P is sensed.

When the emission reset voltage ERST becomes high level at the third timing TM3, the emission QB node EQB becomes high level and the fourteenth and fifteenth transistors T14 and T15 are turned on, and The voltage EVSS is output as the low-level n-th emission signal ES(n), and image data is modulated by reflecting the characteristic change of each pixel P.

When the first emission clock ECLK1 becomes high level at the fourth timing TM4, the ninth and tenth transistors T9 and T10 are turned on so that the emission Q node EQ becomes high level, The thirteenth transistor T13 is turned on and the emission high potential voltage EVDD is output as the high level nth emission signal ES(n), and the light emitting diode De of each pixel is turned on. ) and emits light.

Then, at the fifth and sixth timings TM5 and TM6 before the first emission clock ECLK1 becomes high, the (n-1)th gate 2 signal G2S(n-2) (or gate 2 start When the voltage (G2VST) and the third emission clock (ECLK3) become high level, the emission QB node (EQB) becomes high level and the fourteenth and fifteenth transistors (T14, T15) are turned on. on), the emission low potential voltage EVSS is output as the nth emission signal ES(n) of low level, and the light emitting diode De of each pixel P is turned off to generate light does not emit

As such, in the organic light emitting diode display device 110 according to the first embodiment of the present invention, one frame F is divided into a compensation period CP and a display period DP to drive each pixel P. , Image data is modulated by sensing the threshold voltage of the driving transistor Td during the compensation period CP, and an image is displayed using the modulated image data during the display period DP.

Also, the display period DP is divided into an emission period EP and a non-emission period NEP, and the gate 2 start voltage having a plurality of pulses (high level) is applied to the gate part 142 during the non-emission period NEP. (G2VST) is supplied so that a plurality of gate 2 signals (G2S(n)) output from the gate unit 142 have a plurality of pulses (high level) (toggling), so that the emission QB node (EQB) is continuously A high level may be applied, and the emission signal ES(n) output from the emission unit 144 of the gate driving unit 140 may have a low level during the non-emission period NEP.

That is, the length of the emission period EP of each pixel P (or the ratio of the emission period EP and the non-emission period NEP) can be controlled, and the display quality of the organic light emitting diode display 110 can be improved. and can easily apply the organic light emitting diode display 110 to a high resolution.

However, in the organic light emitting diode display device 110 according to the first embodiment of the present invention, since the plurality of gate 2 signals G2S(n) output from the gate driver 140 have a plurality of pulses, the high level Power consumption may increase and an output signal may be delayed according to an increase in the number of conversions between the low level and the low level.

In addition, since the gate driver 140 has the first and second shift registers, the area of the gate driver 140 may increase and thus the bezel of the organic light emitting diode display 110 may increase.

In another embodiment, a self-charging method using charge pumping is used instead of a toggling method using a plurality of gate 2 signals (G2S(n)), which are outputs of the second shift register. By controlling the length of the light emitting section, it is possible to prevent an increase in power consumption, an increase in a bezel, and signal distortion, which will be described with reference to the drawings.

8 is a view showing the gate driving unit of the organic light emitting diode display device according to the second embodiment of the present invention, and FIG. 9 is the emission unit of the gate driving unit of the organic light emitting diode display device according to the second embodiment of the present invention. 10 is a timing diagram of signals related to one stage of the emission unit of the gate driving unit of the organic light emitting diode display according to the second embodiment of the present invention. Since the configuration and pixel configuration are the same as those of FIGS. 3 and 4 of the first embodiment, a description thereof will be omitted.

As shown in FIG. 8 , the gate driver 240 of the organic light emitting diode display device according to the second embodiment uses a start voltage, a clock, a reset voltage, a high potential voltage, and a low potential voltage to generate a plurality of gate signals ( It includes a gate unit 242 that generates GS(n) and an emission unit 244 that generates a plurality of emission signals ES(n).

The gate unit 242 is composed of a shift register including a plurality of stages GD(n), and the emission unit 244 is an inverter including a plurality of stages ED(n) consists of

Specifically, the shift register of the gate unit 242 is the gate start voltage (GVST) or the output of the previous stage (GS (n-1)), the first to fifth gate clocks (GCLK1 to GCLK5), the gate high potential voltage ( GVDD) and the gate low potential voltage (GVSS) are used to generate a plurality of gate signals (GS(n)), and the inverter of the emission unit 244 generates the emission start voltage (EVST) or the output of the previous stage (ES( n-1)), the first to fifth emission clocks ECLK1 to ECLK5, the emission reset voltage ERST, the emission high potential voltage EVDD, and the emission low potential voltage EVSS. An option signal ES(n) is generated.

For example, the first stage GD(1) of the shift register of the gate unit 242 includes the 0th gate signal GS(0), the first, fourth and fifth gate clocks G1CLK1, G1CLK4, G1CLK5), the gate high potential voltage (GVDD) and the gate low potential voltage (GVSS) are used to generate the first gate signal (GS(1)), and the first stage (ED(1) of the inverter of the emission unit 244 )) is the emission start voltage (EVST), the zeroth gate signal (GS (0)), the emission reset voltage (ERST), the first and fourth emission clocks (ECLK1, ECLK4), the emission high potential voltage ( The first emission signal ES(1) may be generated using the EVDD and the emission low potential voltage EVSS.

In this way, the plurality of stages (GD(n)) of the shift register of the gate unit 242 and the plurality of stages (ED(n)) of the emission unit 244 form a mutually dependent connection relationship, and each output node Through this, a plurality of gate signals GS(n) and a plurality of emission signals ES(n) can be sequentially supplied to the pixels of the display panel.

Meanwhile, each stage GD(n) of the shift register of the gate unit 242 of the gate driver 240 may include first to eighth transistors and a first capacitor as shown in FIG. 1 .

And, as shown in FIG. 9, each stage ED(n) of the inverter, which is the emission unit 244 of the gate driver 240, includes the ninth to twentieth transistors T9 to T20 and the second capacitor ( C2) and a charge pumping capacitor (Ccp).

The gate of the ninth transistor T9 is connected to a terminal to which the first emission clock ECLK1 is supplied, and the drain of the ninth transistor T9 is connected to a terminal to which the emission high potential voltage EVDD is supplied. The source of the ninth transistor T9 is connected to the drain of the tenth transistor T10.

The gate of the tenth transistor T10 is connected to a terminal to which the (n−1)th emission signal ES(n−1) (or the emission start voltage EVST) is supplied, and the tenth transistor T10 The drain of is connected to the source of the ninth transistor T9, and the source of the tenth transistor T10 is connected to the emission Q node EQ.

The gate of the eleventh transistor T11 is connected to the emission QB node EQB, the drain of the eleventh transistor T11 is connected to the emission Q node EQ, and the source of the eleventh transistor T11 is connected to the emission QB node EQB. It is connected to the terminal to which the voltage switcher potential (EVSS) is supplied.

The gate of the twelfth transistor T12 is connected to the terminal to which the (n−1)th gate signal GS(n−1) is supplied, and the drain of the twelfth transistor T12 is the emission high potential voltage EVDD. is connected to the supplied terminal, and the source of the twelfth transistor T12 is connected to the emission QB node EQB.

The gate of the thirteenth transistor T13 is connected to the emission Q node EQ, the drain of the thirteenth transistor T13 is connected to a terminal to which the emission high potential voltage EVDD is supplied, and the thirteenth transistor T13 The source of ) is connected to the drain of the 14th transistor T14.

The gate of the 14th transistor T14 is connected to the emission QB node EQB, the drain of the 14th transistor T14 is connected to the source of the 13th transistor T13, and the source of the 14th transistor T14 is It is connected to the drain of the fifteenth transistor T15.

Here, the nth emission signal ES(n) is output from the node between the 13th and 14th transistors T13 and T14, and the node between the 13th and 14th transistors T13 and T14 and the emission Q A second capacitor C2 is connected between the nodes EQ.

The gate of the fifteenth transistor T15 is connected to the emission QB node EQB, the drain of the fifteenth transistor T15 is connected to the source of the fourteenth transistor T14, and the source of the fifteenth transistor T15 is It is connected to the terminal to which the emission low potential voltage (EVSS) is supplied.

The gate of the sixteenth transistor T16 is connected to a terminal to which the nth gate signal GS(n) is supplied, and the drain of the sixteenth transistor T16 is connected to a terminal to which the emission receiving voltage ERST is supplied. , the source of the sixteenth transistor T16 is connected to the emission QB node EQB.

The gate of the 17th transistor T17 is connected to a node between the 13th and 14th transistors T13 and T14, the drain of the 17th transistor T17 is connected to the emission high potential voltage EVDD, and A source of the transistor T17 is connected to a node between the fourteenth and fifteenth transistors T14 and T15.

The gate of the eighteenth transistor T18 is connected to the emission Q node EQ, the drain of the eighteenth transistor T18 is connected to the emission QB node EQB, and the source of the eighteenth transistor T18 is connected to the emission Q node EQ. It is connected to the terminal to which the voltage switcher potential (EVSS) is supplied.

Further, the gate of the 19th transistor T19 is connected to the emission Q′ node EQ′, the drain of the 19th transistor T19 is connected to a terminal to which the emission high potential voltage EVDD is supplied, and The source of 19 transistor T19 is connected to the emission QB node EQB.

Here, the charge pumping capacitor Ccp is connected between the first emission clock ECLK1 and the emission Q' node EQ'.

The gate of the twentieth transistor T20 is connected to a terminal to which the emission start voltage EVST (or the (n−1)th emission signal ES(n−1)) is supplied, and the twentieth transistor T20 The drain of is connected to the emission Q' node EQ', and the source of the twentieth transistor T20 is connected to a terminal to which the emission low potential voltage EVSS is supplied.

Here, although the plurality of transistors of the gate unit 242 and the emission unit 244 are of the negative type (n type) as an example, in another embodiment, the plurality of transistors of the gate unit 142 and the emission unit 144 are positive. It can also be composed of a type (p type).

Looking at the operation timing of the emission unit 244, as shown in FIG. 10, the (n−1)th gate signal GS (n−1) (or gate start voltage ( GVST) becomes high level, the emission QB node EQB becomes high level and the fourteenth and fifteenth transistors T14 and T15 are turned on, and the emission low potential voltage EVSS The low-level nth emission signal ES(n) is output, and the initial voltage Vinit is applied to the third node N3 of each pixel P.

When the (n−1)th emission signal ES(n−1) (or emission start voltage EVST) and the first emission clock ECLK1 become high level at the second timing TM2, the The ninth and tenth transistors T9 and T10 are turned on so that the emission Q node EQ becomes high level, and the 13th transistor T13 is turned on so that the emission high potential voltage EVDD becomes high level. is output as the nth emission signal ES(n) of , and the voltage of the third node N3 of each pixel P is sensed.

When the nth gate signal GS(n) and the emission reset voltage ERST become high level at the third timing TM3, the emission QB node EQB becomes high level and the 14th and 15th transistors ( T14 and T15) are turned on, the emission low potential voltage (EVSS) is output as the low-level n-th emission signal ES(n), and image data is converted by reflecting the characteristic change of each pixel P. modulate

When the (n−1)th emission signal ES(n−1) (or the emission start voltage EVST) and the first emission clock ECLK1 become high level at the fourth timing TM4, the th The ninth and tenth transistors T9 and T10 are turned on so that the emission Q node EQ becomes high level, and the 13th transistor T13 is turned on so that the emission high potential voltage EVDD becomes high level. is output as the nth emission signal ES(n) of , and the light emitting diode De of each pixel is turned on and emits light.

At this time, the twentieth transistor T20 is turned on by the high-level (n−1)th emission signal ES(n−1) (or the emission start voltage EVST), and the emission Q′node (EQ′) becomes low level, and the eighteenth transistor T18 is turned on by the high-level emission Q node EQ, so that the emission QB node EQB becomes low level.

Then, before the fifth timing (TM5), the twentieth transistor (T20) is turned by the (n−1)th emission signal (ES(n−1)) (or the emission start voltage (EVST)) of low level. - Turned off, the emission Q'node (EQ') is floating, and when the fourth emission clock (ECLK4) becomes high level at the fifth timing (TM5), the high level through the charge pumping capacitor (Ccp) The fourth emission clock ECLK4 is accumulated in the emission Q' node EQ', the 19th transistor T19 is turned on, and the emission QB node EQB becomes high level, resulting in the 14th and 14th transistors T19. 15 Transistors T14 and T15 are turned on, the emission low potential voltage EVSS is output as the low-level n-th emission signal ES(n), and the The light emitting diode De is turned off and does not emit light.

As such, in the organic light emitting diode display device according to the second embodiment of the present invention, one frame (F) is divided into a compensation period (CP) and a display period (DP) to drive each pixel (P). During (CP), the threshold voltage of the driving transistor (Td) is sensed to modulate image data, and during the display period (DP), an image is displayed using the modulated image data.

Then, the display period DP is divided into an emission period EP and a non-emission period NEP, and the (n-1)th emission signal ES(n-1) (or By accumulating a high level at the emission Q' node (EQ') using the emission clock and the charge pumping capacitor (Ccp) according to the swing between the high level and the low level of the emission start voltage (EVST) (self- charging), a high level can be continuously applied to the emission QB node (EQB), and the emission signal (ES(n)) output from the emission unit 244 of the gate driver 240 is in the non-emission period (NEP ) can be made to have a low level.

That is, a separate shift register (the second shift register in the first embodiment) is omitted from the gate unit 242, and the fourth emission clock CLK4 and the charge pumping capacitor Ccp used in the emission unit 244 are used. by changing the gate of the 19th transistor (T19) connected between the emission high potential voltage (EVDD) and the emission QB node (EQB) from a floating state to a high level state, thereby increasing power consumption, increasing bezel and signal distortion In a state where this is prevented, the length of the emission period EP of each pixel P (or the ratio between the emission period EP and the non-emission period NEP) can be controlled, and the display quality of the organic light emitting diode display can be improved. and can be easily applied to high-resolution organic light emitting diode displays.

In the second embodiment, charge to change the voltage of the emission Q'node (EQ'), which is the gate of the 19th transistor T19 connected between the emission high potential voltage (EVDD) and the emission QB node (EQB) Although a passive device such as a pumping capacitor (Ccp) has been used as an example of a charge pumping device, in another embodiment, an active device such as a charge pumping thin film transistor including a MOS capacitor between a gate and an active in addition to a capacitor is taken up. It can also be used as a pumping element.

And, in the second embodiment, the emission unit 244 applied to the pixel P composed of 4 transistors and 2 capacitors is taken as an example, but in another embodiment, charge pumping is applied to the pixel composed of 6 transistors and 1 capacitor As a result, an emission unit capable of adjusting the length of the light emitting section can be applied.

On the other hand, in the organic light emitting diode display device according to the second embodiment of the present invention, the first to fifth emission clocks ECLK1 to ECLK5 are used (5-phase) as an example, but the characteristic variation is not compensated for. In another embodiment, only the first and second emission clocks ECLK1 and ECLK2 may be used (2-phase), which will be described with reference to the drawings.

11 is a view showing one stage of the emission unit of the gate driver of the organic light emitting diode display device according to the third embodiment of the present invention, and FIG. 12 is a view of the organic light emitting diode display device according to the third embodiment of the present invention. As a timing diagram of a signal related to one stage of the emission part of the gate driver, the overall configuration of the organic light emitting diode display device is the same as that of FIG. 3 of the first embodiment, so a description thereof will be omitted.

Although not shown, the pixel of the organic light emitting diode display device according to the third embodiment may have a structure in which the initial transistor (Ti) is omitted from the pixel of the first embodiment of FIG. length can be adjusted.

In addition, the gate driver of the organic light emitting diode display according to the third embodiment includes a gate unit generating a plurality of gate signals using a start voltage, a clock, a reset voltage, a high potential voltage, and a low potential voltage, and a plurality of emission It includes an emission part that generates a signal, the gate part is composed of a shift register including a plurality of stages, and the emission part is composed of an inverter including a plurality of stages (ED(n)). can

Further, each stage of the shift register of the gate unit of the gate driver may include first to eighth transistors and a first capacitor as shown in FIG. 1 .

As shown in FIG. 11, each stage ED(n) of the inverter, which is the emission part of the gate driver, includes 9th to 11th transistors T9 to T11, 13th to 15th transistors T13 to T15, It includes 17th to 20th transistors T17 to T20, a second capacitor C2 and a charge pumping capacitor Ccp.

In each stage ED(n) of the emission unit of the third embodiment, the twelfth and sixteenth transistors T12 and T16 are omitted, and the gate of the ninth transistor T9 is the second emission clock ECLK2. Except for being connected to the supply terminal, since it has the same connection configuration as each stage ED(n) of the emission unit 244 of the second embodiment of FIG. 9, a description thereof will be omitted.

Looking at the operation timing of the emission unit, as shown in FIG. 12, before the first timing TM1, the (n-1)th emission signal ES(n-1) (or emission The twentieth transistor (T20) is turned off by the start voltage (EVST), so that the low-level emission Q' node (EQ') is floating, and the first emission clock is generated at the first timing (TM1). When (ECLK1) becomes high level, the first emission clock (ECLK1) of high level is accumulated in the emission Q' node (EQ') through the charge pumping capacitor (Ccp), and the 19th transistor (T19) turns- On, the emission QB node EQB becomes high level, the fourteenth and fifteenth transistors T14 and T15 are turned on, and the emission low potential voltage EVSS becomes low level control n It is output as an emission signal ES(n), and the light emitting diode De of each pixel P is turned off and does not emit light.

When the second emission clock ECLK2 and the (n−1)th emission signal ES(n−1) (or the emission start voltage EVST) become high level at the second timing TM2, the first The ninth and tenth transistors T9 and T10 are turned on so that the emission Q node EQ becomes high level, and the 13th transistor T13 is turned on so that the emission high potential voltage EVDD becomes high level. is output as the nth emission signal ES(n) of , and the light emitting diode De of each pixel P is turned on and emits light.

As described above, in the organic light emitting diode display device according to the third embodiment of the present invention, each pixel P is driven by using the entire frame F as the display period DP, and the display period DP emits light. It is divided into a period (EP) and a non-emission period (NEP), and during the non-emission period (NEP), the (n-1)th emission signal (ES (n-1)) (or emission start voltage (EVST)) By accumulating the high level in the emission Q' node (EQ') using the emission clock and the charge pumping capacitor (Ccp) according to the swing between the high level and the low level (self-charging), the emission QB node (EQB ) may be continuously applied with a high level, and the emission signal ES(n) output from the emission unit of the gate driver may have a low level during the non-emission period NEP.

That is, a separate shift register (the second shift register in the first embodiment) is omitted in the gate part, and the emission high potential is obtained by using the first emission clock (CLK1) and the charge pumping capacitor (Ccp) used in the emission part. By changing the gate of the 19th transistor T19 connected between the voltage EVDD and the emission QB node EQB from a floating state to a high level state, an increase in power consumption, an increase in bezel, and signal distortion are prevented. The length of the emission period (EP) of the pixel P (or the ratio of the emission period (EP) and the non-emission period (NEP)) can be controlled, the display quality of the organic light emitting diode display device is improved, and the organic light emitting diode The display device can be easily applied to a high resolution.

In the third embodiment, charge to change the voltage of the emission Q'node (EQ'), which is the gate of the 19th transistor T19 connected between the emission high potential voltage (EVDD) and the emission QB node (EQB) Although a passive device such as a pumping capacitor (Ccp) has been used as an example of a charge pumping device, in another embodiment, an active device such as a charge pumping thin film transistor including a MOS capacitor between a gate and an active in addition to a capacitor is taken up. It can also be used as a pumping element.

The gate driver according to the first to third embodiments described above has been described based on the embodiments applied to the N-type 4T2C pixel structure. As mentioned above, the emission unit according to the second embodiment shown in FIG. 9 and the emission unit according to the third embodiment shown in FIG. 11 shift for driving the P-type 6T1C pixel structure organic light emitting display device. Can be applied to registers.

Hereinafter, an embodiment in which the gate driver according to the present invention is applied to an organic light emitting display device having a 6T1C pixel structure will be described.

First, an organic light emitting display device having a 6T1C pixel structure will be described with reference to FIGS. 13 and 14 .

FIG. 13 is a diagram showing pixels of an organic light emitting display device according to a second embodiment of the present invention, and FIG. 14 is a diagram showing timing of driving signals for driving the pixels shown in FIG. 13 .

Referring to FIG. 13 , each of the pixels PXL according to the second embodiment includes an organic light emitting diode (DE) driving transistor DT, first to fifth transistors T1 to T5, and a capacitor Cst. .

The organic light emitting diode DE emits light by a driving current supplied from the driving transistor DT. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting device DE. The anode electrode of the organic light emitting device DE is connected to the fourth node N4, and the cathode electrode of the organic light emitting device is connected to the input terminal of the low potential voltage VSS.

The driving transistor DT controls the driving current applied to the organic light emitting device DE according to its source-gate voltage Vsg. The source electrode of the driving transistor DT is connected to the input terminal of the high potential voltage VDD, the gate electrode is connected to the second node N2, and the drain electrode is connected to the third node N3.

The first transistor T1 includes a gate connected to the input terminal of the gate signal GS, a source connected to the data line DL for supplying the data voltage Vdata, and a drain connected to the first node N1. As a result, the first transistor T1 applies the data voltage Vdata supplied from the data line DL to the first node N1 in response to the gate signal GS.

The second transistor T2 includes a source connected to the third node N3, a drain connected to the second node N2, and a gate connected to the input terminal of the gate signal GS. The second transistor T2 diode-connects the gate-drain electrode of the driving transistor DT in response to the gate signal GS.

The third transistor T3 includes a gate connected to the input terminal of the emission signal ES, a source connected to the first node N1, and a drain connected to the input terminal of the reference voltage Vref. As a result, the third transistor T3 applies the reference voltage Vref to the first node N1 in response to the emission signal EM.

The fourth transistor T4 includes a source connected to the third node N3, a drain connected to the fourth node N4, and a gate connected to an input terminal of the emission signal ES. As a result, the fourth transistor T4 forms a current path between the third node N3 and the fourth node N4 in response to the emission signal EM.

The fifth transistor T5 includes a drain connected to the fourth node N4, a source connected to the reference voltage Vref input terminal, and a gate connected to the reference voltage Vref input terminal. The fifth transistor T5 applies the reference voltage Vref to the fourth node N4 in response to the gate signal GS.

The storage capacitor Cst includes a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

Referring to FIGS. 13 and 14 , the driving of the organic light emitting display device according to the second embodiment is as follows.

In the organic light emitting display device according to the second embodiment, one frame period may be divided into an initial period Ti, a sampling period Ts, and an emission period Te. The initial period Ti is a period for initializing the gate voltage of the driving transistor DT. The sampling period Ts is a period during which the voltage of the anode electrode of the organic light emitting diode DE is initialized, and the threshold voltage of the driving transistor DT is sampled and stored in the second node N2. The emission period (Te) programs the source-gate voltage of the driving transistor (DT) including the sampled threshold voltage, and emits the organic light emitting diode (DE) with a driving current according to the programmed source-gate voltage. is the period

During the initial period Pi, the nth gate signal GS(n) and the nth emission signal ES(n) are applied as gate-on voltages. As a result, the first transistor T1 and the second transistor T2 are turned on by the nth gate signal GS(n), and the third to fifth transistors T5 are turned on by the nth emission signal ( It is turned on by ES(n)). During the initial period Ti, the first node N1 simultaneously receives the reference voltage Vref and the data voltage Vdata, and the second node N2 to fourth node N4 use the reference voltage Vref. initialized The reference voltage Vref may be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting diode DE, and may be set to a voltage equal to or lower than the low potential voltage VSS.

During the sampling period Ts, the nth gate signal GS(n) maintains the gate-on voltage, and the nth emission signal ES(n) is inverted to the gate-off voltage. As a result, the first transistor T1, the second transistor T2, and the fifth transistor T5 remain turned on, and the third transistor T3 and the fourth transistor T4 are turned off. .

When the third transistor T3 is turned on, the voltage of the first node N1 rises due to the data voltage Vdata passing through the first transistor T1, and the second node N2 is the first node. The voltage rises as the voltage of (N1) rises. As a result, the difference between the gate-source voltage of the driving transistor DT is greater than or equal to the threshold voltage Vth and turned on.

The voltage of the third node N3 gradually rises due to the current passing through the source-drain of the driving transistor DT. Also, since the gate electrode and the drain electrode of the driving transistor DT are in a diode-connected state, the voltage at the second node N2 increases along with the voltage at the third node N3. As the voltage of the second node N2 increases, the gate-source voltage difference of the driving transistor DT gradually decreases, and when the gate-source voltage difference of the driving transistor DT becomes less than the threshold voltage Vth, the driving transistor (DT) is turned off. As a result, during the sampling period Ts, the second node N2 and the third node N3 become "VDD+Vth" corresponding to the voltage difference between the high potential voltage VDD and the threshold voltage Vth.

During the sampling period Ts, the first transistor T1 charges the first node N1 with the data voltage Vdata in response to the nth gate signal GS(n).

Also, during the sampling period Ts, the fifth transistor T5 initializes the fourth node N4 to the reference voltage Vref in response to the nth gate signal GS(n).

During the holding period Th, the nth gate signal GS(n) is inverted to the gate-off voltage, and the nth emission signal ES(n) maintains the gate-off voltage. As a result, the voltage of the first node N1 to the fourth node N4 maintains the voltage of the sampling period Ts.

During the emission period Pe, the nth gate signal GS(n) maintains the gate-off voltage, and the nth emission signal ES(n) is inverted to the gate-on voltage.

The third transistor T3 applies the reference voltage Vref to the first node N1 in response to the nth emission signal ES(n). During the sampling period Ts, since the first node N1 is the data voltage Vdata, the amount of voltage change at the first node N1 becomes “Vdata−Vref”. Due to the coupling phenomenon between the second node N2 and the first node N1, the voltage variation of the first node N1 is reflected on the second node N2, and as a result, the voltage of the second node N2 becomes "VDD-Vth-(Vdata-Vref)". According to the voltage change of the second node N2, the driving current Ioled passing through the source-drain of the driving transistor DT is applied to the organic light emitting diode DE through the fourth node N4.

During the emission period Pe, a relational expression for the drive current IDE flowing through the organic light emitting device DE is as shown in Equation 1 below.

[Equation 1]

IDE=k/2(Vgs-|Vth|) ² = k/2(Vg-Vs-|Vth|) ² = k/2(VDD+Vth-Vdata+Vref-VDD-|Vth|) ² = k/ 2(Vref-Vdata) ²

In Equation 1, k/2 represents a proportionality constant determined by the electron mobility, parasitic capacitance, and channel capacitance of the driving transistor DT.

As shown in [Equation 1], the threshold voltage (Vth) component of the driving transistor (DT) is eliminated in the relational expression of the driving current (IDE), which means that the threshold voltage (Vth) of the organic light emitting display according to the present invention is changed. Even if it does, it means that the drive current (IDE) does not change.

As described above, the organic light emitting display according to the present invention can program the data voltage regardless of the amount of change in the threshold voltage Vth during the sampling period Ts.

15 is a diagram illustrating a gate driver according to a third embodiment. FIG. 15 illustrates a gate driver for generating the gate signal GS and the emission signal ES shown in FIG. 14 .

Referring to FIG. 15 , the gate driver of the organic light emitting diode display device according to the third embodiment generates a plurality of gate signals GS using a start voltage, a clock, a reset voltage, a high potential voltage, and a low potential voltage. It includes a gate unit 342 and an emission unit 344 generating a plurality of emission signals ES.

The gate unit 342 includes a plurality of gate stages GD that are cascadedly connected, and the emission unit 344 includes a plurality of emission stages ED that are cascadedly connected.

Each gate stage GD of the gate unit 342 has a gate start voltage GVST or an output of the previous gate stage GS(n-1), first and second gate clocks GCLK1 and GCLK2, and gate high potential. The gate signal GS is generated using the voltage GVDD and the gate low potential voltage GVSS. For example, the nth gate stage GD(n) of the gate unit 242 includes the (n−1)th gate signal GS(n−1), the first and second gate clocks GCLK1 and G1CLK2, the gate An nth gate signal GS(n) is generated using the high potential voltage GVDD and the gate low potential voltage GVSS.

Each emission stage ED of the emission unit 344 outputs the emission start voltage EVST or the output of the previous stage ES(n-1), the first to fifth emission clocks ECLK1 to ECLK5, the EMI A plurality of emission signals ES(n) are generated using the reset voltage ERST, the emission high potential voltage EVDD, and the emission low potential voltage EVSS. For example, the n-th emission stage ED(n) of the emission unit 344 includes the emission start voltage EVST, the (n−1)th emission signal ES(n−1), and the first and second emission signals ED(n−1). 2 An nth emission signal ES(n) is generated using the emission clocks ECLK1 and ECLK2, the emission high potential voltage VEH and the emission low potential voltage VEL.

As such, the gate stages GD of the gate unit 242 and the emission stages ED of the emission unit 244 sequentially transmit the gate signals GS and the emission signals ES to the pixels of the display panel. can supply

Meanwhile, the gate stages GD of the gate unit 242 output the gate signal GS as shown in FIG. 14, and any known circuit configuration may be used as a detailed circuit configuration.

16 is a view showing an emission unit according to a fourth embodiment. The emission unit according to the fourth embodiment is substantially the same as the emission unit according to the third embodiment shown in FIG. 11 , and unlike the third embodiment, the transistors are P-type. FIG. 17 is a diagram illustrating a driving signal for driving the emission unit shown in FIG. 16 . Since FIG. 16 is based on a Pmos transistor, the gate-on voltage becomes the emission low potential voltage (VEL), and the gate-off voltage becomes the emission high potential voltage (VEH).

Referring to FIG. 16, the nth stage ED(n), which is the emission unit 344 according to the fourth embodiment, includes 9th to 15th transistors T9 to T15 and 17th to 20th transistors T17 to T20. ), a second capacitor C2 and a charge pumping capacitor Ccp.

The start controllers T9 and T10 charge the emission Q node EQ with a gate-on voltage during a period in which the emission start voltage EVST and the first emission clock ECLK1 are synchronized. The start controllers T9 and T10 include a ninth transistor T9 and a tenth transistor T10.

The gate of the ninth transistor T9 is connected to a terminal to which the first emission clock ECLK1 is supplied, and the drain of the ninth transistor T9 is connected to a terminal to which the emission low potential voltage VEL is supplied. The source of the ninth transistor T9 is connected to the drain of the tenth transistor T10.

The gate of the tenth transistor T10 is connected to a terminal to which the (n−1)th emission signal ES(n−1) (or emission start voltage EVST) is supplied, and the tenth transistor T10 The drain of is connected to the source of the ninth transistor T9, and the source of the tenth transistor T10 is connected to the emission Q node EQ.

The gate of the eleventh transistor T11 is connected to the emission QB node EQB, the drain of the eleventh transistor T11 is connected to the emission Q node EQ, and the source of the eleventh transistor T11 is It is connected to the terminal to which the high potential voltage (VEH) is supplied.

The gate of the twelfth transistor T12 is connected to a terminal to which the (n−1)th gate signal GS(n−1) is supplied, and the drain of the twelfth transistor T12 is connected to the emission high potential voltage EVDD. is connected to the supply terminal, and the source of the twelfth transistor T12 is connected to the emission QB node EQB.

The pull-up transistor T13 (hereinafter referred to as a thirteenth transistor) outputs the voltage of the output terminal Nout as a gate-on voltage in response to the emission Q node EQ voltage. The gate of the thirteenth transistor T13 is connected to the emission Q node EQ, the drain of the thirteenth transistor T13 is connected to a terminal to which the emission high potential voltage EVDD is supplied, and the thirteenth transistor T13 The source of ) is connected to the drain of the 14th transistor T14.

The pull-down transistors T14 and T15 output the voltage of the output terminal Nout as a gate-off voltage in response to the voltage of the emission QB node EQB. The gate of the fourteenth transistor T14 is connected to the emission QB node EQB, the drain of the fourteenth transistor T14 is connected to the source of the thirteenth transistor T13, and the source of the fourteenth transistor T14 is It is connected to the drain of the fifteenth transistor T15.

The nth emission signal ES(n) is output through the output terminal Nout, and a second capacitor C2 is connected between the node between the 13th and 14th transistors T13 and T14 and the emission Q node EQ. ) is connected.

The gate of the fifteenth transistor T15 is connected to the emission QB node EQB, the drain of the fifteenth transistor T15 is connected to the source of the fourteenth transistor T14, and the source of the fifteenth transistor T15 is It is connected to the terminal to which the emission high potential voltage (VEH) is supplied.

The gate of the seventeenth transistor T17 is connected to a node between the thirteenth and fourteenth transistors T13 and T14, the drain of the seventeenth transistor T17 is connected to the emission low potential voltage VEL, and the seventeenth transistor The source of (T17) is connected to the node between the fourteenth and fifteenth transistors T14 and T15.

The gate of the eighteenth transistor T18 is connected to the emission Q node EQ, the drain of the eighteenth transistor T18 is connected to the emission QB node EQB, and the source of the eighteenth transistor T18 is connected to the emission Q node EQ. It is connected to the terminal to which the high potential voltage (VEH) is supplied.

The first QB node control transistor T19 (hereinafter referred to as a 19th transistor) charges the emission QB node EQB with a gate-on voltage in response to the emission Q′ node EQ′ voltage. The gate of the nineteenth transistor T19 is connected to the emission Q'node (EQ'), the drain of the nineteenth transistor T19 is connected to a terminal to which the emission low potential voltage VEL is supplied, and the nineteenth transistor ( The source of T19) is connected to the emission QB node (EQB).

The gate of the twentieth transistor T20 is connected to a terminal to which the emission start voltage EVST or the (n−1)th emission signal ES(n−1) is supplied, and the drain of the twentieth transistor T20 is connected to the emission Q' node EQ', and the source of the twentieth transistor T20 is connected to a terminal to which the emission high potential voltage VEH is supplied.

The charge pumping capacitor Ccp is connected between the first emission clock ECLK1 and the emission Q' node EQ'.

Referring to FIG. 17, the operation of the nth emission stage ED(n) is as follows.

The first timing TM1 is the starting point of the sampling period Ts shown in FIG. 14 . When the first emission clock ECLK1 is inverted to a low level at the first timing TM1, the low level first emission clock ECLK1 is transmitted to the emission Q'node EQ' through the charge pumping capacitor Ccp. ) is charged. The nineteenth transistor T19 charges the emission QB node EQB to the emission low potential voltage VEL in response to the low-level emission Q′ node EQ′ voltage, which is the gate-on voltage. The fourteenth and fifteenth transistors T14 and T15 charge the output terminal Nout to the emission high potential voltage VEH, which is the gate-off voltage, in response to the low-level emission QB node EQB voltage, which is the gate-on voltage. do.

When the second emission clock ECLK2 and the (n−1)th emission signal ES(n−1) (or the emission start voltage EVST) become low level at the second timing TM2, the The ninth and tenth transistors T9 and T10 are turned on so that the emission Q node EQ becomes a low level. As a result, the thirteenth transistor T13 is turned on and the emission low potential voltage VEL is output as the nth emission signal ES(n) through the output terminal Nout.

The emission unit according to the fourth embodiment charges the emission Q'node (EQ') with a low-level gate-on voltage using the charge pumping capacitor (Ccp) (self-charging), and the emission QB node (EQB) A high level can be continuously applied to

At this time, after the 19th transistor T19 is turned on by the first emission clock ECLK1 at the first timing TM1, the gate off voltage of the first emission clock ECLK1 during the first period t1 is reversed to If there is no charge pumping capacitor Ccp, the emission Q′ node E1′ becomes a gate-off voltage and the nineteenth transistor T19 can be turned off. Even during the first period t1, the emission QB node EQB needs to maintain the gate-off voltage. When the 19th transistor T19 is turned off, the voltage of the emission QB node EQB becomes unstable.

In contrast, the embodiment of the present invention can prevent the voltage of the emission Q' node EQ' from being charged to the gate-off voltage during the first period t1 by the charge pumping capacitor Ccp. That is, even if the first emission clock ECLK1 connected to one electrode of the charge pumping capacitor Ccp is inverted to a high level, the emission Q' node EQ' has only a slight voltage change due to the coupling effect. Therefore, rapid change to the gate-off voltage can be prevented. As a result, the nineteenth transistor T19 can stably maintain a turned-on state from the first timing TM1 to the second timing TM2.

18 is a view showing an emission unit according to a fifth embodiment. The embodiment shown in FIG. 18 shows an embodiment in which a twenty-first transistor T21 is added to the embodiment shown in FIG. 16 . In the fifth embodiment shown in FIG. 18, the same reference numerals are used for substantially the same components as those in the fourth embodiment shown in FIG. 16, and detailed descriptions thereof will be omitted. In addition, the first and second emission clocks ECLK2 shown in FIG. 17 are used as the emission clock for driving the emission unit shown in FIG. 18 .

17 and 18, the emission stage ED according to the fifth embodiment includes 9th to 15th transistors T9 to T15, 17th to 21st transistors T17 to T21, and a second capacitor ( C2) and a charge pumping capacitor (Ccp). In the emission stage of the fifth embodiment, the same reference numerals are used for the same components as those of the fourth embodiment shown in FIG. 16, and detailed descriptions will be omitted.

The second QB node control transistor T21 (hereinafter referred to as a 21st transistor) of the nth emission stage ED(n) is connected to an input terminal supplying the (n+1)th gate signal GS(n+1). It includes a gate, a drain connected to an input terminal supplying the first emission clock ECLK1, and a source connected to the emission QB node EQB. The twenty-first transistor T21 charges the emission QB node EQB with the gate-on voltage of the first emission clock ECLK1 in response to the (n+1)th gate signal GS(n+1). . As a result, the twenty-first transistor T21 enables the voltage of the emission QB node EQB to quickly fall to the gate-on voltage.

The operation of the twenty-first transistor T21 will be described in more detail.

As shown in FIG. 17, in the emission unit, at the first timing TM1, the emission QB node EQB becomes the emission low potential voltage VEL, and the fourteenth transistor T14 and the fifteenth transistor T15 ) should be turned on.

However, right before the first timing TM1 , the emission Q node EQ is at the emission low potential voltage VEL, and as a result, the eighteenth transistor T18 maintains a turned-on state. Therefore, at the moment of the first timing TM1, the emission high potential voltage VEH is applied to the emission QB node EQB through the eighteenth transistor T18. As a result, even if the nineteenth transistor T19 is turned on at the first timing TM1, the point at which the emission QB node EQB is polled to the emission low potential voltage VEL is delayed.

As the timing at which the emission QB node EQB is polled to the emission low potential voltage VEL is delayed, the timing at which the fourteenth transistor T14 and the fifteenth transistor T15 are turned on is delayed. As a result, as shown in FIG. 19, the point at which the nth emission signal ES(n) rises to the gate high potential voltage VEH, which is the gate-off voltage, is delayed by the delay time Δt.

The first timing TM1 is the starting point of the sampling period Ts shown in FIG. 14 . Accordingly, the sampling period Ts is shortened by the delay time Δt of the nth emission signal ES(n). If the sampling period Ts is shortened, the threshold voltage compensation is incomplete and the period for writing the data voltage is shortened. Accordingly, it becomes difficult to express an image having a desired luminance.

The twenty-first transistor T21 charges the emission QB node EQB with the voltage of the first emission clock ECLK1 in response to the (n+1)th gate signal GS(n+1). At the first timing Ts, the first emission clock ECLK1 has a gate-on voltage at a low level. That is, since the twenty-first transistor T21 charges the emission QB node EQB with the gate-on voltage at the first timing TM1, the time for the emission QB node EQB to be charged with the gate-on voltage is shortened. . As a result, the turn-on time of the ninth transistor T9 and the tenth transistor T10 responding to the voltage of the emission QB node EQB is shortened, so that the gate of the nth emission signal ES(n) The delay time of the off voltage output can be reduced.

FIG. 20 is a diagram showing pixels of an organic light emitting display device according to a third embodiment of the present invention, and FIG. 21 is a diagram showing timing of driving signals for driving the pixels shown in FIG. 20 .

Referring to FIG. 21 , each of the pixels PXL according to the third embodiment includes an organic light emitting diode (DE) driving transistor DT, first to fifth transistors T1 to T5, and a capacitor Cst. . In the third embodiment shown in FIG. 20, the same reference numerals are used for the same components as those in the FIG. 13 embodiment, and detailed descriptions will be omitted.

20 and 21, the gate of the first transistor T1 is connected to an input terminal supplying the second gate signal GS2(n), and the second transistor T2 and the fifth transistor T5 The gate is connected to an input terminal supplying the first gate signal GS1(n).

That is, since the second gate signal GS(2n) maintains the gate-off voltage during the initial period Ti, the first transistor T1 is turned off. As a result, during the initial period Ti, the first node n1 is initialized to the reference voltage Vref in which the data voltage Vdata is not mixed.

The gate unit for applying the embodiments shown in FIGS. 20 and 21 may use any known configuration. And, the emission unit may apply the embodiments shown in FIGS. 15 to 18 . At this time, the gate of the twenty-first transistor T21 of the emission stage may operate by receiving the (n+1)th gate 1 signal GS(n+1).

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the technical spirit and scope of the present invention described in the claims below. You will understand that it can be done.

110: organic light emitting diode display device 120: timing control unit
130: data driving unit 150: display panel
240: gate driving unit 242: gate unit
244: emission part Ccp: charge pumping capacitor

Claims (14)

a display panel including a plurality of pixels each having a light emitting diode;
a data driver supplying a plurality of data signals to the plurality of pixels;
A gate unit supplying a plurality of gate signals to the plurality of pixels, and an emission unit supplying a plurality of emission signals to the plurality of pixels using a charge pumping device to control the length of the light emitting section of the light emitting diode. a gate driving unit;
A timing controller supplying image data and a data control signal to the data driver and supplying a gate control signal to the gate driver
including,
The emission unit includes a plurality of stages connected to each other dependently,
Each of the plurality of stages,
a Q node for determining that the plurality of emission signals are output at a high level;
a QB node for determining that the plurality of emission signals are output at a low level;
a Q' node for determining that the QB node has the high level;
The charge pumping element connected to the Q' node
An organic light emitting diode display comprising a.

delete According to claim 1,
An emission clock is supplied to the charge pumping element;
The Q'node is switched from a floating state to the high level by the emission clock and the charge pumping device.
According to claim 3,
The organic light emitting diode display device of claim 1, wherein the charge pumping element is a charge pumping capacitor or a charge pumping thin film transistor.
According to claim 1,
The emission unit generates the plurality of emission signals using an emission start voltage, an emission reset voltage, a plurality of emission clocks, and the plurality of gate signals;
The plurality of emission clocks include first to fifth emission clocks,
The plurality of gate signals include nth and (n−1)th gate signals,
The plurality of emission signals include nth and (n−1)th emission signals,
The plurality of stages include an nth stage,
The nth stage includes ninth to twentieth transistors, a second capacitor, and the charge pumping element.
According to claim 5,
The gate, drain, and source of the ninth transistor are connected to the first emission clock, the emission high potential voltage, and the drain of the tenth transistor, respectively;
The gate, drain, and source of the tenth transistor are connected to the (n−1)th emission signal or the emission start voltage, the source of the ninth transistor, and the Q node, respectively;
The gate, drain, and source of the eleventh transistor are connected to the QB node, the Q node, and an emission low potential voltage, respectively;
The drain and source of the gate of the twelfth transistor are connected to the (n−1)th gate signal, the emission high potential voltage, and the QB node, respectively;
The gate, drain, and source of the thirteenth transistor are connected to the Q node, the emission high potential voltage, and the drain of the fourteenth transistor, respectively;
The gate, drain and source of the 14th transistor are connected to the QB node, the source of the 13th transistor and the drain of the 15th transistor, respectively;
The gate, drain and source of the 15th transistor are connected to the QB node, the source and the emission low potential voltage of the 14th transistor, respectively;
The gate, drain, and source of the sixteenth transistor are connected to the nth gate signal, the emission reset voltage, and the QB node, respectively;
The gate, drain, and source of the seventeenth transistor are connected to a node between the thirteenth and fourteenth transistors, the emission high potential voltage, and a node between the fourteenth and fifteenth transistors, respectively;
The gate, drain, and source of the eighteenth transistor are connected to the second emission clock, the QB node, and the emission low potential voltage, respectively;
The gate, drain, and source of the 19th transistor are connected to the Q' node, the emission high potential voltage, and the QB node, respectively;
The gate, drain, and source of the twentieth transistor are connected to the (n-1)th emission signal or the emission start voltage, the Q' node, and the emission low potential voltage, respectively;
The second capacitor is connected between a node between the 13th and 14th transistors and the Q node;
The charge pumping element is connected between the first emission clock and the Q'node;
The n-th emission signal is output from a node between the 13th and 14th transistors.
According to claim 1,
The emission unit generates the plurality of emission signals using an emission start voltage and a plurality of emission clocks;
The plurality of emission clocks include first and second emission clocks,
The plurality of emission signals include nth and (n−1)th emission signals,
The plurality of stages include an nth stage,
The nth stage includes 9th to 11th, 13th to 15th, 17th to 20th transistors, a second capacitor, and the charge pumping element.
According to claim 7,
The gate, drain, and source of the ninth transistor are connected to the first emission clock, the emission high potential voltage, and the drain of the tenth transistor, respectively;
The gate, drain, and source of the tenth transistor are connected to the (n−1)th emission signal or the emission start voltage, the source of the ninth transistor, and the Q node, respectively;
The gate, drain, and source of the eleventh transistor are connected to the QB node, the Q node, and an emission low potential voltage, respectively;
The gate, drain, and source of the thirteenth transistor are connected to the Q node, the emission high potential voltage, and the drain of the fourteenth transistor, respectively;
The gate, drain and source of the 14th transistor are connected to the QB node, the source of the 13th transistor and the drain of the 15th transistor, respectively;
The gate, drain and source of the 15th transistor are connected to the QB node, the source and the emission low potential voltage of the 14th transistor, respectively;
The gate, drain, and source of the seventeenth transistor are connected to a node between the thirteenth and fourteenth transistors, the emission high potential voltage, and a node between the fourteenth and fifteenth transistors, respectively;
The gate, drain, and source of the eighteenth transistor are connected to the second emission clock, the QB node, and the emission low potential voltage, respectively;
The gate, drain, and source of the 19th transistor are connected to the Q' node, the emission high potential voltage, and the QB node, respectively;
The gate, drain, and source of the twentieth transistor are connected to the (n-1)th emission signal or the emission start voltage, the Q' node, and the emission low potential voltage, respectively;
The second capacitor is connected between a node between the 13th and 14th transistors and the Q node;
The charge pumping element is connected between the first emission clock and the Q'node;
The n-th emission signal is output from a node between the 13th and 14th transistors.
a display panel including a plurality of pixels each having a light emitting diode;
a data driver supplying a plurality of data signals to the plurality of pixels;
A gate unit supplying a plurality of gate signals to the plurality of pixels, and an emission unit supplying a plurality of emission signals to the plurality of pixels using a charge pumping device to control the length of the light emitting section of the light emitting diode. a gate driving unit;
A timing controller supplying image data and a data control signal to the data driver and supplying a gate control signal to the gate driver
including,
The emission unit includes a plurality of emission stages connected in a dependent manner,
Each of the emission stages is
a start control unit that sets the emission Q node to a gate-on voltage during a period in which the emission start voltage and the first emission clock are synchronized;
a pull-up transistor that outputs a voltage at an output terminal as a gate-on voltage in response to the emission Q node voltage;
a pull-down transistor that outputs the voltage of the output terminal as a gate-off voltage in response to the emission QB node voltage;
a first QB node control transistor configured to set the emission QB node to the gate-on voltage in response to an emission Q' node voltage; and
and a charge pumping device configured to set the emission Q′ node to a gate-on voltage in response to a second emission clock having a phase opposite to that of the first emission clock.
According to claim 9,
The start controller includes a ninth transistor and a tenth transistor,
The ninth transistor includes a gate receiving the first emission clock, a first electrode connected to an input terminal of the gate-on voltage, and a second electrode connected to the first electrode of the tenth transistor;
The tenth transistor is composed of a gate receiving an emission start voltage or an emission signal of a previous stage, a first electrode connected to the second electrode of the ninth transistor, and a second electrode connected to the emission Q node. light emitting diode display.
According to claim 10,
A twentieth transistor including a gate receiving the emission start voltage or the emission signal of the previous stage, a first electrode connected to the emission Q'node, and a second electrode connected to the gate-off voltage input terminal. organic light emitting diode display.
According to claim 11,
The nth emission stage generating the nth (n is a natural number) emission signal is
and a second QB node control transistor configured to set the emission QB node to a gate-on voltage in response to a (n+1)th gate signal.
According to claim 12,
The second QB node control transistor includes a gate receiving a (n+1)th gate signal, a first electrode connected to an input terminal receiving the second emission clock, and a second electrode connected to the emission QB node. An organic light emitting diode display device comprising a.
According to claim 13,
The driving period of the n-th pixel disposed on the n-th pixel line in one frame includes an initial period, a sampling period, and an emission period controlled by an n-th gate signal and an n-th emission signal;
During the initial period, an n-th gate signal and an n-th emission signal applied to the n-th pixel maintain a gate-on voltage;
During the sampling period, an n-th gate signal applied to the n-th pixel maintains a gate-on voltage;
The second emission clock is inverted to a gate-on voltage at the start of the sampling period.

Images