CN111696482B

CN111696482B - OLED pixel compensation circuit and driving method

Info

Publication number: CN111696482B
Application number: CN202010522531.2A
Authority: CN
Inventors: 郑剑花; 郭平昇
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2020-06-10
Filing date: 2020-06-10
Publication date: 2023-10-03
Anticipated expiration: 2040-06-10
Also published as: CN111696482A

Abstract

An OLED pixel compensation circuit and a driving method, wherein the pixel compensation circuit comprises thin film transistors T1, T2, T3, T4, T5, T6, T7, T8 and T9, wherein the source electrode of the T1 is connected with the source electrodes of on-chip high voltages VGH and T7 and the source electrode of the T6, the grid electrode of the T1 is connected with the grid electrodes of clock signals ECK1 and T5, and the drain electrode of the T1 is connected with the source electrode of the T2, the grid electrode of the T7 and one end of a capacitor CB; compared with the prior art, the driving circuit capable of generating an EM compensation signal at each stage is realized, and the loss generated by RC delay is compensated, so that the input signal is simplified, and the display effect is better.

Description

OLED pixel compensation circuit and driving method

Technical Field

The invention relates to the field of panel design, in particular to an OLED pixel compensation circuit and a driving method design.

Background

The problem of uniformity of brightness of OLED displays is caused by the difference in brightness between TFTs at different positions due to the difference in electrical parameters such as threshold voltage Vth. Therefore, the current AMOLED compensation problem is of paramount importance.

The compensation method of the AMOLED can be divided into an internal compensation method and an external compensation method, wherein the internal compensation method is a method of compensating a sub-circuit built by using TFTs in a pixel, and the current internal compensation circuit has circuit structures of 6T1C, 7T1C and the like. In the existing N-type compensation circuit, a compensation waveform required by the compensation circuit is shown as fig.1, T1/T2 is reset, T3 is data writing, and T4 is compensation and OLED luminescence. Besides SCAN signals, the circuit also needs EM signals, so the patent proposes a driving circuit capable of realizing the EM signals needed by the N-type OLED internal compensation circuit.

Disclosure of Invention

Therefore, it is desirable to provide an internal compensation circuit that solves the EM compensation driving signal problem of the OLED internal compensation circuit.

For this purpose, we provide an OLED pixel compensation circuit comprising thin film transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, the source of T1 being connected to the source of the on-chip high voltage VGH, T7 and the source of T6, the gate of T1 being connected to the gates of the clock signals ECK1 and T5, the drain of T1 being connected to the source of T2, the gate of T7 and one end of the capacitor CB; the drain electrode of the T7 is connected with the other end of the capacitor CB, the grid electrode of the T6 and the source electrode of the T8, the drain electrode of the T6 is connected with the drain electrode of the T8 and the source electrode of the T9, the grid electrode of the T2 is connected with the drain electrode of the T4, the grid electrode of the T8, the grid electrode of the T9 and the source electrode of the T5, the source electrode of the T4 is connected with the reset signal RST, the grid electrode is connected with the driving signal Gn of the previous stage, and the drain electrodes of the T2, the T5 and the VGL are connected; the drain electrode of the T7 is also connected with the output end of the compensation signal EMn.

The OLED pixel compensation circuit driving method is suitable for the OLED pixel compensation circuit and comprises the following steps:

the first stage, the upper driving signal is high level, the clock signal is low level, and the reset signal is high level;

the second stage, the input signal of the previous stage keeps the high level, reset signal and clock signal low level;

the third stage, the input signal of the previous stage is low level, the clock signal is low level, the reset signal is pulled high level after being kept low level for a short time, and then the reset signal is changed into low level;

a fourth stage, the input signal of the previous stage is low level, the reset signal and the clock signal are high level;

and in the fifth stage, the input signal of the previous stage is low-level, the clock signal is low-level, and the reset signal is reduced to low level after being temporarily kept high-level.

Specifically, the method comprises the step that when the panel is in a first frame of startup, the control chip sends out a simulation signal E_STV to simulate a previous stage input signal.

Compared with the prior art, the driving circuit capable of generating an EM compensation signal at each stage is realized, and the loss generated by RC delay is compensated, so that the input signal is simplified, and the display effect is better.

Drawings

FIG.1 is a schematic diagram of a compensation circuit according to an embodiment;

fig. 2 is a schematic diagram of a driving waveform according to an embodiment.

Detailed Description

In order to describe the technical content, constructional features, achieved objects and effects of the technical solution in detail, the following description is made in connection with the specific embodiments in conjunction with the accompanying drawings.

Referring to fig.1, an OLED pixel compensation circuit includes thin film transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9, wherein a source of the T1 is connected to sources of on-chip high voltages VGH and T7 and a source of the T6, a gate of the T1 is connected to gates of clock signals ECK1 and T5, and a drain of the T1 is connected to a source of the T2, a gate of the T7, and one end of a capacitor CB; the drain electrode of the T7 is connected with the other end of the capacitor CB, the grid electrode of the T6 and the source electrode of the T8, the drain electrode of the T6 is connected with the drain electrode of the T8 and the source electrode of the T9, the grid electrode of the T2 is connected with the drain electrode of the T4, the grid electrode of the T8, the grid electrode of the T9 and the source electrode of the T5, the source electrode of the T4 is connected with the reset signal RST, the grid electrode is connected with the driving signal Gn-1 of the previous stage, and the drain electrode of the T2, the drain electrode of the T5 and the drain electrode of the T9 are connected with VGL; the drain electrode of the T7 is also connected with the output end of the compensation signal EMn. Such an OLED pixel compensation circuit, after being properly driven, is capable of generating one compensation signal EMn for each stage (n).

The driving method of the pixel compensation circuit is as follows: in the embodiment shown in fig. 2, the following phases are included:

first stage t1: the previous stage driving signal has advanced to a high level, the clock signal is low, the reset signal is high, T4, T2, T8, T9 are on, and EMn is pulled low by VGL.

Second stage t2: the driving signal of the previous stage keeps high level, the reset signal and clock signal low level; t4 is turned on and EMn maintains the low level of the previous stage.

Third stage t3: the input signal of the previous stage is low level, the clock signal is low level, the reset signal is pulled high level after being kept low level for a short time, then the reset signal is changed into low level, gn time sequence at the moment reaches high level, all TFTs are turned off, and EMn maintains the low level of the previous stage. Gn is the gate TFT driving signal, and Gn is the next gate driving signal of Gn-1 when Gn is high.

Fourth stage t4: the input signal of the previous stage is low level, the reset signal and the clock signal are high level; T1/T5/T6/Tpu is turned on and EMn is pulled to high by VGH.

Fifth stage t5: the input signal of the previous stage is low level, the clock signal is low level, and the reset signal is reduced to low level after being temporarily kept high level. T6 is turned on and EMn is maintained at a high level.

Wherein EMn is pulled down by ECK1 to Gao Zhun bits by superposition of the upper input signal Gn-1 and the reset signal RST. When T6 is opened, the middle of T8 and T9 is at a high level, so that the EMn is not pulled down at the high level.

In other embodiments, the control chip sends out the emulation signal E_STV to emulate the previous stage input signal for the pixels of the first column, and the OLED display IC can provide a start signal E_STV, gn-1 signal behind the E_STV waveform because there is no Gn-1 signal.

When the panel is at the first frame of starting up at this time, the EMn has no high level of the previous frame in the first stage, and at this time, the two OLED driving voltages OVDD/OVSS are supplied with voltage one frame later, so that the human eyes can not see the non-uniformity of the initial stage of the first frame.

It should be noted that, although the foregoing embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solution, directly or indirectly, to other relevant technical fields, all of which are included in the scope of the invention.

Claims

1. The OLED pixel compensation circuit driving method is characterized by being suitable for an OLED pixel compensation circuit, wherein the OLED pixel compensation circuit comprises thin film transistors T1, T2, T4, T5, T6, T7, T8 and T9, a source electrode of the T1 is connected with a source electrode of on-chip high voltage VGH and T7 and a source electrode of the T6, a grid electrode of the T1 is connected with grid electrodes of clock signals ECK1 and T5, and a drain electrode of the T1 is connected with a source electrode of the T2, a grid electrode of the T7 and one end of a capacitor CB; the drain electrode of the T7 is connected with the other end of the capacitor CB, the grid electrode of the T6 and the source electrode of the T8, the drain electrode of the T6 is connected with the drain electrode of the T8 and the source electrode of the T9, the grid electrode of the T2 is connected with the drain electrode of the T4, the grid electrode of the T8, the grid electrode of the T9 and the source electrode of the T5, the source electrode of the T4 is connected with the reset signal RST, the grid electrode is connected with the driving signal Gn-1 of the previous stage, and the drain electrode of the T2, the drain electrode of the T5 and the drain electrode of the T9 are connected with VGL; the drain of T7 is also connected to the output of the compensation signal EMn, the method comprising the following phases:

2. The method of driving an OLED pixel compensation circuit according to claim 1, comprising the step of, for a first row of pixels, the control chip issuing an emulation signal e_stv to emulate the previous stage input signal.