KR20200049677A - Gate driver and organic light emitting display device including the same - Google Patents

Abstract

According to embodiments of the present invention, a gate driver includes stages that output an image scan signal in a vertical active period of one frame, output a sensing scan signal in a vertical blank period of the one frame, and have an M node, a Qh node, a Q node, and a QB node. Each of the stages includes: a pixel line selection unit that charges the M node with a front-end carry signal according to a pixel line selection signal in the vertical active period, and charges the Q node with a high potential power voltage level according to a charging voltage of the M node and a sensing start signal in the vertical blank period; a Q node strengthening unit that prevents leakage of the charging voltage of the Q node according to the charging voltage of the M node and a sensing end signal in the vertical blank period; and an output unit that outputs the sensing scan clock at the high potential power voltage level into the sensing scan signal while the Q node is maintained in a charged state in the vertical blank period.

Description

Gate driver and organic light emitting display device including the same {GATE DRIVER AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a gate driver and an organic light emitting display device including the same.

The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has a fast response speed, high luminous efficiency, brightness, and a large viewing angle.

The organic light emitting display device includes a gate driver to drive switch elements provided in the pixels. The gate electrodes of the switch elements are connected to the gate driver through the gate lines. The gate driver generates gate signals (scan signals) and sequentially supplies them to the gate lines.

In organic light emitting display devices, external compensation technology is used to enhance image quality. The external compensation technology compensates for driving characteristic deviation between pixels by sensing the pixel voltage or current according to the driving characteristic (or electrical characteristic) of the pixel and modulating the data of the input image based on the sensed result. The gate driver outputs a gate signal for sensing driving by operating a specific stage within the predetermined time so that a driving characteristic of a pixel can be sensed within a predetermined time when an input image is not written. During sensing driving, in order to output a desired gate signal, a Q node of a specific stage must be maintained at a gate-on voltage. In a specific stage, a plurality of transistors are connected between the Q node and the input terminal of the low potential power voltage. During sensing driving, a plurality of transistors must be completely turned off while the Q node is charged with the gate-on voltage. However, due to various factors such as threshold voltage shift, a leakage current may flow in a plurality of transistors. This leakage current may distort the charge level of the Q node and distort the sensing gate signal. If a desired gate signal is not applied during sensing driving, the driving characteristics of the pixel cannot be accurately sensed, which results in deterioration of compensation performance.

Accordingly, the present invention has been devised to solve the conventional problems, and provides a gate driver and an organic light emitting display device including the same to stabilize the charging state of the Q node during sensing driving so that desired gate output characteristics can be secured.

The gate driver according to an exemplary embodiment of the present invention outputs a scan signal for an image in a vertical active period in one frame, outputs a scan signal for sensing in a vertical blank period in the one frame, It includes stages with QB nodes.

Each of the stages charges the M node with a front end carry signal according to a pixel line selection signal in the vertical active period, and a high potential power voltage level according to the charging voltage of the M node and a sensing start signal in the vertical blank period. A pixel line selector to charge the Q node; A Q node strengthening unit preventing leakage of the charging voltage of the Q node according to the charging voltage of the M node and the sensing end signal in the vertical blank period; And an output unit which outputs a scan clock for sensing of the high potential power voltage level as the scan signal for sensing while the Q node maintains a charge state in the vertical blank period.

The present invention includes a Q node reinforcement unit in each stage that prevents leakage of the charging voltage of the Q node according to the charging voltage of the M node and the sensing end signal in the vertical blank period, thereby stabilizing the charging state of the Q node during sensing driving to thereby obtain a desired gate Output characteristics can be ensured. The present invention can greatly improve sensing and compensation performance for driving characteristics of pixels by securing gate output characteristics during sensing driving.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 shows an organic light emitting display device according to an exemplary embodiment of the present invention.
FIG. 2 shows a pixel array included in the organic light emitting display of FIG. 1.
FIG. 3 shows an equivalent circuit of one pixel included in the pixel array of FIG. 2.
4 to 6 show a black image insertion technology applied to the organic light emitting display device of FIG. 1.
7 is a timing diagram of a gate signal and a data signal for implementing IDW driving and BDI driving of FIG. 6.
8A is an equivalent circuit diagram of pixels corresponding to the programming period of FIG. 7.
8B is an equivalent circuit diagram of pixels corresponding to the light emission period of FIG. 7.
8C is an equivalent circuit diagram of pixels corresponding to the black period of FIG. 7.
FIG. 9 is a diagram illustrating an example in which a pixel array is dividedly driven into a plurality of first regions and a plurality of second regions based on a phase-separated first clock group and a second clock group.
FIG. 10 is a view showing that image data and black data are simultaneously written in different areas according to the first clock group and the second clock group.
11 is a view showing a stage connection configuration of a gate driver according to an embodiment of the present invention.
12 is a diagram for explaining timing of IDW driving, BDI driving, and SDW driving based on the gate signal output from the stages of FIG. 11.
13 is a timing diagram of a gate signal and a data signal for driving SDW.
14A is an equivalent circuit diagram of pixels corresponding to the setup period of FIG. 13.
14B is an equivalent circuit diagram of pixels corresponding to the sensing period of FIG. 13.
14C is an equivalent circuit diagram of pixels corresponding to the reset period of FIG. 13.
15 is a first equivalent circuit diagram of one stage connected to the first region among the stages of FIG. 11.
16 is an operation timing diagram of the equivalent circuit diagram shown in FIG. 15.
17 is a first equivalent circuit diagram of one stage connected to the second region among the stages of FIG. 11.
18 is an operation timing diagram of the equivalent circuit diagram shown in FIG. 17.
FIG. 19 is a second equivalent circuit diagram of one stage connected to the first region among the stages of FIG. 11.
20 is an operation timing diagram of the equivalent circuit diagram shown in FIG. 19.
21 is a second equivalent circuit diagram of one stage connected to the second region among the stages of FIG. 11.
22 is an operation timing diagram of the equivalent circuit diagram shown in FIG. 21.
23A is a diagram showing the voltage between the gate and the source of the transistor T56 while the scan signal for sensing the high potential power voltage level is output in FIGS. 19 and 21.
23B is a diagram illustrating the voltage between the gate and the source of the transistor T62 while the scan signal for sensing the high potential power voltage level is output in FIGS. 19 and 21.
23C is a diagram showing the voltage between the gate and the source of the transistor T64 while the scan signal for sensing the high potential power voltage level is output in FIGS. 19 and 21.

Advantages and features of the present specification, and a method of achieving them will be apparent with reference to embodiments described below in detail together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present specification to be complete, and common knowledge in the art to which this specification belongs It is provided to completely inform the person having the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present specification are exemplary, and the present specification is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. When 'include', 'have', 'consist of', etc. mentioned in this specification are used, other parts may be added unless '~ only' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as '~ on', '~ on top', '~ on the bottom', '~ next to', etc., 'right' Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

The first, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be the second component within the technical spirit of the present specification.

In the present specification, the pixel circuit and the gate driver formed on the substrate of the display panel may be implemented as a TFT of an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but are not limited thereto and may be implemented as a TFT of a p-type MOSFET structure. have. TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers begin to flow from the source. The drain is an electrode through which the carrier exits from the TFT. That is, the carrier flow in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), since the carrier is electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In the n-type TFT, since electrons flow from the source to the drain, the direction of the current flows from the drain to the source. In contrast, in the case of the p-type TFT (PMOS), the source voltage is higher than the drain voltage so that holes can flow from the source to the drain because the carrier is a hole. In the p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be changed according to the applied voltage. Therefore, in the description of the embodiment of the present specification, any one of the source and the drain is described as the first electrode, and the other of the source and the drain is described as the second electrode.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be mainly described with an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present specification is not limited to the organic light emitting display device, and can be applied to other display devices such as a liquid crystal display device.

In the following description, when it is determined that a detailed description of known functions or configurations related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description is omitted.

In the following description, “shear stages” refers to stages positioned above the reference stage and generating gate signals having a phase higher than that of the gate signal output from the reference stage. In addition, the "back stages" refer to stages that are positioned below the reference stage and generate gate signals that are out of phase compared to the gate signal output from the reference stage. In the following description, the switch elements constituting the gate driver of the present invention may be implemented as at least one of an oxide element, an amorphous silicon element, and a polysilicon element. And, that a specific stage is activated means that the Q node of the stage is charged with a gate-on voltage, and that a specific stage is deactivated means that the Q node of the stage is discharged with a gate-off voltage.

1 is a view showing an organic light emitting display device according to an exemplary embodiment of the present specification. FIG. 2 is a diagram illustrating a pixel array included in the organic light emitting display of FIG. 1. And, FIG. 3 is an equivalent circuit of one pixel included in the pixel array of FIG. 2.

1 to 3, a display device according to an exemplary embodiment of the present specification may include a display panel 10, a timing controller 11, and panel drivers 12 and 13. The panel driving units 12 and 13 include a data driving unit 12 driving data lines 15 of the display panel 10 and a gate driving unit 13 driving gate lines 17 of the display panel 10. It includes.

The display panel 10 may be provided with a plurality of data lines 15 and reference voltage lines 16 and a plurality of gate lines 17. In addition, pixels PXL may be disposed in the crossing areas of the data lines 15, the reference voltage lines 16, and the gate lines 17. A pixel array as shown in FIG. 2 may be formed in the display area AA of the display panel 10 by the pixels PXL arranged in a matrix form.

In the pixel array, pixels PXL may be divided for each line based on one direction. For example, the pixels PXL may be divided into a plurality of pixel lines (Line 1 to Line 4, etc.) based on the gate line extension direction (or horizontal direction). Here, the pixel line is not a physical signal line, but an aggregate of pixels PXL arranged adjacent to each other along a horizontal direction. Therefore, pixels PXL constituting the same pixel line may be connected to the same gate line 17.

In the pixel array, each of the pixels PXL is connected to a digital-to-analog converter (hereinafter, DAC) 121 through a data line 15, and a sensing unit (SU) 122 through a reference voltage line 16 Can be connected to. The reference voltage line 16 may be further connected to the DAC 121 for supply of the reference voltage. The reference voltage line 16 may be selectively connected to the DAC 121 and the sensing unit SU through a switch (not shown). The DAC 121 and the sensing unit SU may be built in the data driving unit 12, but are not limited thereto.

In the pixel array, each of the pixels PXL may be connected to the high potential pixel power EVDD through the power line 18. In addition, each of the pixels PXL may be connected to the gate driver 13 through the gate line 17.

Each pixel PXL may be implemented as shown in FIG. 3. One pixel (PXL) disposed in the k (k is an integer) th pixel line includes an OLED, a driving thin film transistor (DT), a storage capacitor (Cst), a first switch TFT (ST1), and a second switch TFT (ST2), the first switch TFT (ST1) and the second switch TFT (ST2) may be connected to the same gate line 17, but is not limited thereto. The first switch TFT ST1 and the second switch TFT ST2 may be connected to different gate lines.

The OLED includes an anode electrode connected to the source node Ns, a cathode electrode connected to the input terminal of the low potential pixel power source EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode. The driving TFT DT controls the driving current flowing through the OLED according to the voltage difference between the gate node Ng and the source node Ns. The driving TFT DT includes a gate electrode connected to the gate node Ng, a first electrode connected to the input terminal of the high potential pixel power supply EVDD, and a second electrode connected to the source node Ns. The storage capacitor Cst is connected between the gate node Ng and the source node Ns to store the voltage between the gate and source of the driving TFT DT.

The first switch TFT ST1 is turned on according to the scan signal SCAN (k) to apply the data voltage charged in the data line 15 to the gate node Ng. The first switch TFT ST1 includes a gate electrode connected to the gate line 17, a first electrode connected to the data line 15, and a second electrode connected to the gate node Ng. The second switch TFT ST2 is turned on according to the scan signal SCAN (k) to apply a reference voltage charged in the reference voltage line 16 to the source node Ns, or a source node according to the pixel current (Ns) The voltage change is transferred to the reference voltage line 16. The second switch TFT ST2 includes a gate electrode connected to the gate line 17, a first electrode connected to the reference voltage line 16, and a second electrode connected to the source node Ns.

The number of gate lines 17 connected to each pixel PXL may vary according to the structure of the pixel PXL. Hereinafter, for convenience of description, a 1-scan pixel structure is used as an example, but the technical idea of the present specification is not limited to the pixel structure or the number of gate lines.

The timing controller 11 of the data driver 12 is based on timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, and a data enable signal DE input from the host system 14. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the gate driver 13 may be generated. The gate control signal GDC may include a gate start signal, gate shift clocks, a pixel line selection signal, a sensing start signal, and a sensing end signal. The data control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the data driver 12. The source sampling clock controls the sampling timing of data based on the rising or falling edge. The source output enable signal controls the output timing of the data driver 12.

The timing controller 11 controls display driving timing and sensing driving timing for the pixel lines of the display panel 10 based on the timing control signals GDC and DDC, thereby realizing driving characteristics of pixels in real time during image display. It can be sensed.

Here, the sensing driving means that sensing data SD is written to pixels PXL disposed on a specific pixel line to sense driving characteristics of the corresponding pixels PXL, and the corresponding pixels PXL are based on the sensing result. ) To update the compensation value to compensate for changes in driving characteristics. Hereinafter, an operation for writing the sensing data SD to the pixels PXL disposed in a specific pixel line in the sensing driving is referred to as a sensing data writing (SDW) driving.

The display driving is a driving in which the input image and black images are sequentially reproduced on the display panel 10 by writing the input image data ID and the black image data BD in pixel lines with a certain time difference within one frame. Display driving includes driving IDW (Image Data Writing) to write input image data (ID) to pixel lines, and driving Black Data Insertion (BDI) to write black image data (BD) to pixel lines. . BDI driving may be started before IDW driving is completed in one frame so that a display device optimized for high-speed driving can be implemented. That is, in one frame, IDW driving for the first pixel line and BDI driving for the second pixel line may be achieved by overlapping in time.

The timing controller 11 may adjust the time difference between the start timing of the IDW driving and the start timing of the BDI driving, that is, the emission duty, by controlling the start timing of the BDI driving within one frame.

The timing controller 11 may control the start timing of the BDI driving within one frame in synchronization with the inter-frame change amount of the input image data ID. The timing controller 11 detects the inter-frame change amount of the input image data ID through various known image processing techniques, and then, the greater the inter-frame change amount of the input image data ID, the larger the start timing of BDI driving within one frame. You can reduce the luminous duty by advancing. Through this, MPRT performance may be improved and motion blurring may be alleviated when there is a sudden image change. Meanwhile, when there is no image change, the maximum instantaneous luminance of the pixel may be lowered by delaying the start timing of BDI driving within one frame and increasing the emission duty.

The timing controller 11 may implement IDW driving in the vertical active period of one frame, and implement BDI driving using both the vertical active period and the vertical blank period. Therefore, the BDI driving timing can overlap with the IDW driving timing in the vertical active period.

The timing controller 11 separates the gate shift clocks into A clock groups and B clock groups having different phases, and controls the operation of the gate driver 13 based on the A clock groups and the B clock groups, thereby controlling the pixel array to include at least one pixel array. The first region and the at least one second region may be dividedly driven. That is, the timing controller 11 BDI drives the second area while the IDW / SDW driving is performed on the first area, and vice versa, IDW / the second area while the BDI driving is performed on the first area. SDW can be driven. The A clock group is input to the first stages of the gate driver 13 connected to the pixel lines of the first region, and the B clock group is second stages of the gate driver 13 connected to the pixel lines of the second region. Is entered in. The A clock group and the B clock group may include IDW / SDW carry clocks, BDI carry clocks, IDW / SDW scan clocks, and BDI scan clocks, respectively.

At this time, the timing controller 11 may generate gate shift clocks such that the pulse period of the BDI scan clocks (on-voltage period) and the pulse periods of the IDW / SDW scan clocks do not overlap each other. By doing this, in a technique for inserting a black image to improve MPRT performance, unwanted data mixing (ie, data collision) between input image data (ID) and black image data (BD), sensing data (SD), and black image It is possible to prevent unwanted data collision between data BD.

The timing controller 11 may output a plurality of BDI scan clocks at the same time to control a plurality of pixel lines to be simultaneously BDI-driven in the first region or the second region. Through this, in the technique of improving MPRT performance, the insertion time of the black image data BD is reduced, and instead, the writing time of the input image data ID can be sufficiently secured.

The timing controller 11 separates a pixel line selection signal into a first pixel line selection signal and a second pixel line selection signal having different phases to prevent data collision between SDW driving and BDI driving, and the pixel line in the first area The first pixel line selection signal is input to the first stages of the gate driver 13 connected to the field, and the second pixel line selection signal is input to the second stages of the gate driver 13 connected to the pixel lines of the second region. You can enter Then, the timing controller 11 selectively activates one of the first pixel line selection signal and the second pixel line selection signal with an on voltage. When the BDI driving is performed on the first area, the timing controller 11 activates only the second pixel line selection signal to drive the SDW only on the second area, and conversely, when the BDI driving is performed on the second area. Only the first region can be driven by SDW by activating only one pixel line selection signal. As a result, in a technique for improving MPRT performance by inserting a black image, unwanted data mixing between the sensing data SD and the black image data BD is prevented, and the driving characteristics of the pixel can be more accurately sensed.

The timing controller 11 outputs the input image data ID input from the host system 14 to the data driver 12. The timing controller 11 outputs the black image data BD generated internally (or preset to a specific value) to the data driver 12. The black image data BD corresponds to the lowest grayscale data of the input image data ID, and is used to display a black image when the BDI is driven.

The gate driver 13 generates an IDW / SDW scan signal SCAN based on IDW / SDW carry clocks and IDW / SDW scan clocks, and BDI based on BDI carry clocks and BDI scan clocks. Generates a scan signal (SCAN). In order to implement IDW driving and BDI driving, the gate driver 13 sequentially supplies the IDW scan signal SCAN to the gate lines 17 of the first area (or the second area) while the second area is The BDI scan signal SCAN is simultaneously supplied to the predetermined number of gate lines 17 (or the first region). In addition, the gate driving unit 13 is synchronized with the timing at which the scan signal SCAN for the SDW is supplied to the specific gate line 17 of the first area (or the second area) in order to implement SDW driving and BDI driving. The BDI scan signal SCAN is simultaneously supplied to a predetermined number of gate lines 17 in the 2 regions (or the first region).

The gate driver 13 may be formed in the non-display area NA of the display panel 10 according to a gate in panel method (GIP).

The data driver 12 includes a plurality of DACs 121 and a plurality of sensing units (SU) 122. The DAC 121 converts the input image data ID to the IDW data voltage VIDW based on the data control signal DDC from the timing controller 11, and the black image data BD to the BDI data voltage. Convert to (VBDI), and convert the sensing data SD to the SDW data voltage VSDW. Then, the DAC 121 generates a reference voltage to be applied to the pixels PXL.

The DAC 121 outputs the IDW data voltage VIDW to the data lines 15 in synchronization with the IDW scan signal SCAN to implement IDW driving and BDI driving, and also applies a reference voltage to the reference voltage line. It outputs to the field 16, and outputs the data voltage VBDI for BDI to the data lines 15 in synchronization with the scan signal SCAN for BDI.

The DAC 121 outputs the data voltage (VSDW) for SDW to the data lines 15 in synchronization with the scan signal for SDW (SCAN) to implement SDW driving and BDI driving, and a reference voltage line for the reference voltage. It outputs to the field 16, and outputs the data voltage VBDI for BDI to the data lines 15 in synchronization with the scan signal SCAN for BDI.

4 to 6 show a black image insertion technology applied to the organic light emitting display device of FIG. 1.

Referring to FIG. 4, IDW driving and BDI driving based on the same pixel line are continuously performed at a predetermined time difference within one frame. The emission duty of the pixels PXL is determined by a time difference between the start timing of the IDW driving and the start timing of the BDI driving within the same frame. The start timing of IDW driving is a fixed factor, but the start timing of BDI driving is an adjustable design factor. The start timing of the IDW driving is determined by the first pulse of the gate start signal, and the start timing of the BDI driving is determined by the second pulse of the gate start signal that is out of phase with the first pulse. Accordingly, when the output timing of the second pulse of the gate start signal is advanced or slowed to adjust the start timing of the BDI driving, the emission duty of the pixels PXL can be controlled. In other words, as the time difference is increased by delaying the output timing of the second pulse of the gate start signal, the emission duty of the pixels PXL increases and the black duty decreases, and the output timing of the second pulse is advanced to advance the timing difference. As the value is smaller, the emission duty of the pixels PXL decreases and the black duty increases. When the emission duty of the pixels PXL is determined in this way, the emission duty is maintained regardless of the frame change. That is, the IDW driving timing and the BDI driving timing for the pixel lines are shifted equally while maintaining the emission duty over time.

Referring to FIG. 5, within one frame, the IDW scan signal SCAN and the BDI scan signal SCAN are output with a predetermined time difference corresponding to the emission duty. The scan signals for IDW (SCAN1 to SCAN10) are shifted in a line sequential manner to select pixel lines (Line 1 to Line 10) one line at a time, and IDW for the selected pixel lines (Line 1 to Line 10). The data voltage VIDW is sequentially applied. The scan signals for BDI (SCAN1 to SCAN10) are shifted in a block sequential manner to select a plurality of pixel lines (Line 1 to Line 10) simultaneously, and to the pixel lines (Line 1 to Line 8) of the selected block. The data voltage VBDI for BDI is applied at the same time.

Referring to FIG. 6, it is illustrated that the IDW driving timing and the BDI driving timing for the pixel lines Line 1 to Line z are shifted while maintaining the emission duty even when the frame is changed. When such a driving concept is employed, there is no need to add a separate frame to drive the BDI, so there is an advantage of not having to increase the frame rate.

However, since the IDW driving timing is advanced by the emission duty compared to the BDI driving timing, and the shift speed of the IDW driving timing and the BDI driving timing is substantially the same, IDW driving for the first pixel line and BDI driving for the second pixel line This overlapping overlapping OA occurs. In the overlap period OA, a plurality of pixel lines are driven overlapping.

7 is a timing diagram of a gate signal and a data signal for implementing IDW driving and BDI driving of FIG. 6 in the k-th pixel line. 8A is an equivalent circuit diagram of pixels corresponding to the programming period of FIG. 7. 8B is an equivalent circuit diagram of pixels corresponding to the light emission period of FIG. 7. 8C is an equivalent circuit diagram of pixels corresponding to the black period of FIG. 7.

7 illustrates IDW / BDI driving for a specific pixel of the k-th pixel line Line k. Referring to FIG. 7, one frame for driving IDW / BDI includes a programming period (Tp) for setting the voltage between the gate node (Ng) and the source node (Ns) to match the pixel current for gradation representation, and the OLED according to the pixel current It includes a light emitting period (Te) that emits light and a black period (Tb) in which light emission of the OLED is stopped. The emission duty corresponds to the emission period Te, and the black duty may correspond to the black period Tb. In FIG. 7, the scan signal for IDW (SCAN) is shown as P1, and the scan signal for BDI (SCAN) is shown as P2.

7 and 8A, in the programming period Tp, the first switch TFT ST1 of the pixel is turned on according to the scan signal P1 for the IDW, and the data voltage VIDW for the IDW to the gate node Ng. Is approved. In the programming period Tp, the second switch TFT ST2 of the pixel is turned on according to the scan signal P1 for IDW to apply the reference voltage Vref to the source node Ns. Through this, the voltage between the gate node Ng and the source node Ns of the pixel is set to the desired pixel current in the programming period Tp.

7 and 8B, in the light emission period Te, the first switch TFT ST1 and the second switch TFT ST2 of the pixel are turned off. In the programming period Tp, the voltage Vgs between the gate node Ng and the source node Ns preset in the pixel is maintained even in the light emission period Te. Since the voltage Vgs between the gate node Ng and the source node Ns is greater than the threshold voltage of the driving TFT DT of the pixel, the pixel current Ioled to the driving TFT DT of the pixel during the light emission period Te ) Flows. The potential of the gate node Ng and the potential of the source node Ns in the light emission period Te is maintained by the pixel current Ioled while maintaining the voltage Vgs between the gate node Ng and the source node Ns. Boosted. When the potential of the source node Ns is boosted to the operating point level of the OLED, the OLED of the pixel emits light.

Referring to FIGS. 7 and 8C, in the black period Tb, the first switch TFT ST1 of the pixel is turned on according to the scan signal P2 for BDI, and the data voltage VBDI for BDI to the gate node Ng. Is approved. In the black period Tb, the second switch TFT ST2 of the pixel is turned on according to the scan signal P2 for BDI. At this time, the potential of the source node Ns maintains the operating point level of the OLED. The data voltage (BBDI) for BDI is a voltage lower than the operating point level of the OLED. Therefore, since the voltage Vgs between the gate node Ng and the source node Ns in the black period Tb is smaller than the threshold voltage of the driving TFT DT, the pixel current Ioled to the driving TFT DT of the pixel Does not flow, and the OLED stops emitting light.

FIG. 9 is a diagram illustrating an example in which a pixel array is dividedly driven into a plurality of first regions and a plurality of second regions based on a phase-separated first clock group and a second clock group. 10 is a diagram showing that image data and black data are simultaneously written in different areas according to the first clock group and the second clock group.

9 and 10, a plurality of first regions (A regions) and a plurality of second regions (B regions) may be alternately arranged in the pixel array of the display panel 10. When the pixel array is dividedly driven into A regions and B regions based on this arrangement, there is an advantage in that design freedom for adjusting the emission duty ratio is increased.

In the gate driver 13, first clock groups CLKA1 to CLKAk are input to first stages that drive gate lines of the first regions, and second to second stages that drive gate lines of the second regions. The clock group (CLKB1 to CLKBk) is input. All stages are cascaded so that pixel lines are sequentially driven at all boundaries of the first and second regions.

In FIG. 10, the writing timing of the IDW data voltage VIDW is sequentially shifted from the uppermost first region of the pixel array according to the first clock group CLKA1 to CLKAk and the first pulse of the gate start signal. The writing timing of the data voltage VBDI for BDI is shifted sequentially from the second region in the middle of the pixel array according to the second clock group CLKB1 to CLKBk and the second pulse of the gate start signal. When the second pulse of the gate start signal is applied to the second region of the middle of the pixel array at the time when the IDW driving according to the first pulse of the gate start signal starts in the specific first region, the driving may be performed as described above. In addition, when the first pulse of the gate start signal is applied to the uppermost first region of the pixel array when the BDI driving according to the second pulse of the gate start signal starts in a specific second region, the driving may be performed as described above.

11 is a view showing a connection configuration of stages included in the gate driver of FIG. 1.

Referring to FIG. 11, the gate driver 13 may be implemented as a gate shift register including a plurality of stages connected cascadely. The stages of the gate shift register may be GIP elements formed directly on the non-display area NA of the display panel 10.

The stages STG1 to STGn are connected one-to-one to the gate lines of the pixel array. The operations of the stages STG1 to STGn are activated according to the carry signal CR input from the front stage, and sequentially outputs the gate signal. The gate signal includes a scan signal and a carry signal. The " shear stage " means a stage that is activated before the reference stage and generates a gate signal whose phase is higher than the gate signal output from the reference stage.

The sensing start signal SRT and the sensing end signal SND, the global reset signal QRST, and the high potential power voltage GVDD and the low potential power voltage GVSS are commonly input to the stages STG1 to STGn. Can be. The global reset signal QRST is commonly input to all the stages STG1 to STGn when the display device is powered on, and serves to reset the stages STG1 to STGn simultaneously before normal driving. .

The first clock group CLKA and the first pixel line selection signal LSPA are input to the first stages ST1, ST2, ... connected to the A region of the pixel array. The sensing start signal SRT, the sensing end signal SND, and the first pixel line selection signal LSPA are control signals for SDW driving a specific pixel line in the A area. The first stages ST1, ST2, ... output a scan signal for driving IDW / BDI based on the front end carry signal and the first clock group CLKA. The first stages ST1, ST2, ... are based on a front end carry signal, a first clock group CLKA, a first pixel line selection signal LSPA, and a sensing start signal SRT and a sensing end signal SND. The scan signal for driving the SDW is output. The first stages ST1, ST2, ... may be reset according to a carry signal input from the rear stage. The "back stage" means a stage that is activated later than the reference stage and generates a gate signal that is later in phase than the gate signal output from the reference stage.

The second clock group CLKB and the second pixel line selection signal LSPB are input to the second stages STn-1, STn, ... connected to the B region of the pixel array. The sensing start signal SRT, the sensing end signal SND, and the second pixel line selection signal LSPB are control signals for SDW driving a specific pixel line in the B region. The second stages STn-1, STn, ... output a scan signal for IDW / BDI driving based on the front end carry signal and the second clock group CLKB. The second stages STn-1, STn, ... are the front end carry signal, the second clock group CLKB and the second pixel line selection signal LSPB, and the sensing start signal SRT and sensing end signal SND. A scan signal for driving the SDW is output based on the. The second stages STn-1, STn, ... may be reset according to a carry signal input from the rear stage.

The top and bottom stages may be implemented as dummy stages DST1 and DST2. A gate start signal VST may be input to the uppermost dummy stage DST1, and a gate reset signal RST may be input to the lowermost dummy stage DST2 at the end of each frame.

12 is a diagram for explaining timing of IDW driving, BDI driving, and SDW driving based on the gate signal output from the stages of FIG. 11.

Referring to FIG. 12, the SDW driving is performed within a vertical blank period (VBP) of each frame, and is performed by selecting one pixel line for each frame. Since the pixels stop emitting light when the SDW is driven, if the pixel lines are sequentially sensed, the sensed pixel line may be recognized as a line dim. When the pixel lines are sensed in a random order, the line dim is not visible due to the visual dispersion effect. For example, for random sensing as shown in FIG. 12, the present invention senses a specific pixel line in region A in the vertical blank period (VBP) of the k-th frame, and region B in the vertical blank period (VBP) of the k + 1 frame. A specific pixel line of can be sensed.

Referring to FIG. 12, prior to SDW driving, an SDW preparation operation is performed in a vertical active period (VAP) of each frame. The SDW preparation operation refers to an operation of pre-charging a memory node (M node in FIGS. 15, 17, 19, and 21) of a stage connected to a sensing target pixel line according to a pixel line selection signal LSPA or LSPB. The stage in which the memory node is precharged may charge the Q node when the sensing start signal SRT is activated in the vertical blank period VBP. And the stage outputs a scan clock for SDW as a scan signal for SDW while the Q node is charged.

Since the IDW driving and the BDI driving overlap in the vertical active period (VAP), the SDW preparation operation in the A area also charges the memory node of the stage connected to the pixel line to be unsensed in the B area. Similarly, due to the SDW preparation operation of the B region, the memory node of the stage connected to the pixel line to be unsensed in the A region is also charged. In this case, since two pixel lines are SDW-driven at the same time, sensing accuracy is deteriorated. In particular, since the non-sensing target pixel line of the A region and the non-sensing target pixel line of the B region connected to the mischarged stages are pixel lines to be BDI driven, BDI driving and SDW driving within the vertical blank period (VBP) Overlapping, unwanted data mixing between sensing data SD and black image data BD may occur. This problem occurs when the same pixel line selection signal is applied to all stages.

To solve this problem, in the present invention, different pixel line selection signals LSPA and LSPB are applied to the stages connected to the A region and the stages connected to the B region.

Referring to FIG. 12, the first pixel line selection signal LSPA is input to stages connected to pixel lines in region A, and the second pixel line selection signal LSPB is connected to pixel lines in region B. Field. The first pixel line selection signal LSPA and the second pixel line selection signal LSPB are activated at different timings.

The timing controller 11 activates only the first pixel line selection signal LSPA and deactivates the second pixel line selection signal LSPB when any one of the pixel lines LA in the area A needs to be sensed. On the other hand, the timing controller 11 activates only the second pixel line selection signal LSPB and deactivates the first pixel line selection signal LSPA when any one of the pixel lines LB of the region B needs to be sensed. . This can prevent the memory node of the stage connected to the non-sensing target pixel line of the B region from being mischarged during the SDW preparation operation of the A region, and similarly, the non-sensing target pixel line of the A region during the SDW preparation operation of the B region It can be prevented that the memory node of the stage connected to is overcharged.

The timing controller 11 may SDW only the B region while the BDI driving is performed on the A region, and, conversely, SDW only the A region while the BDI driving is performed on the B region. Accordingly, it is possible to prevent a plurality of pixel lines from being simultaneously selected during SDW driving, further preventing unwanted data mixing between sensing data SD and black image data BD, and driving characteristics of pixels are more accurately sensed. Can be.

On the other hand, the timing controller 11 activates the corresponding pixel line selection signal LSPA or LSPB one more time at the timing when the SDW driving is completed within the vertical blank period VBP to simultaneously activate the memory nodes of the first or second stages. Can be initialized. For example, the timing controller 11 applies the activated first pixel line selection signal LSPA to the first stages immediately after the SDW driving for the first pixel line in region A is completed within the vertical blank period VBP. The memory nodes of the first stages may be initialized at the same time. In addition, the timing controller 11 applies the second pixel line selection signal LSPB activated immediately after the SDW driving for the second pixel line of the B area is completed within the vertical blank period VBP to the second stages. The memory nodes of the second stages may be initialized simultaneously. When the initialization operation is performed by applying the pixel line selection signal LSPA or LSPB once more, stabilization of the SDW driving may be improved by preventing data collision that may occur in subsequent SDW driving.

13 is a timing diagram of a gate signal and a data signal for driving SDW. 14A is an equivalent circuit diagram of pixels corresponding to the setup period of FIG. 13. 14B is an equivalent circuit diagram of pixels corresponding to the sensing period of FIG. 13. 14C is an equivalent circuit diagram of pixels corresponding to the reset period of FIG. 13.

FIG. 13 shows SDW driving for a specific pixel of the j-th pixel line (Line j). Referring to FIG. 13, a vertical blank period (VBP) for driving the SDW samples a setup period (①) for setting the voltage between the gate node Ng and the source node Ns to match the pixel current for sensing, and the pixel current It includes a sensing period (②) and a reset period (③) to restore the voltage between the gate node (Ng) and the source node (Ns) to the state immediately before the setup period (①).

13 and 14A, the first switch TFT ST1 of the pixel is turned on according to the scan signal SCAN for the SDW during the setup period ①, and the data voltage VSDW for the SDW is applied to the gate node Ng. Is approved. In the setup period (①), the second switch TFT ST2 of the pixel is turned on according to the scan signal SCAN for SDW to apply the reference voltage Vref to the source node Ns. Through this, the voltage between the gate node Ng and the source node Ns of the pixel is set according to the pixel current for sensing in the setup period ①.

13 and 14B, in the sensing period ②, the first and second switch TFTs ST1 and ST2 of the pixel maintain a turn-on state. In addition, the reference voltage line 16 is connected from the DAC to the sensing unit SU. In the sensing period ②, the sensing unit SU samples the pixel current Ipix for sensing input through the second switch TFT ST2 and the reference voltage line 16.

13 and 14C, in the reset period ③, the first and second switch TFTs ST1 and ST2 of the pixel maintain a turn-on state. The first switch TFT ST1 applies the original data voltage VREC to the gate node Ng. The original data voltage VREC may be an IDW data voltage VIDW or a BDI data voltage VBDI. If the IDW data voltage VIDW is maintained in the corresponding pixel line immediately before the SDW driving, the data voltage VREC for the original data becomes the IDV data voltage VIDW. On the other hand, if the data voltage (VBDI) for BDI is maintained in the corresponding pixel line immediately before driving the SDW, the data voltage for remote recovery (VREC) becomes the data voltage for BDI (VBDI). In the reset period ③, the reference voltage line 16 is again connected to the DAC, and the second switch TFT ST2 of the pixel applies the reference voltage Vref to the source node Ns. Through this, the voltage between the gate node Ng and the source node Ns of the pixel is restored to the state immediately before the SDW driving in the reset period ③.

15 is a first equivalent circuit diagram of one stage connected to the first region among the stages of FIG. 11. The stage of FIG. 15 may be connected to the pixel PIX of the A region through the gate line 17. 16 is an operation timing diagram of the equivalent circuit diagram shown in FIG. 15.

Referring to FIGS. 15 and 16, one stage connected to the region A is an input unit BLK1, an inverter unit BLK2, an output unit BLK3, a stabilization unit BLK4, a pixel line selection unit BLK5, and Q node reinforcement Includes part BLK6.

The input unit BLK1 charges and discharges the Q node for driving IDW and SDW. The input unit BLK1 charges the Qh node to a high potential power voltage (GVDD) level according to the Q node charging voltage when driving IDW and driving SDW.

The input unit BLK1 charges the Q node to a high potential power voltage (GVDD) level in response to the front end carry signal CR (n-3) input through the start terminal when driving the IDW. The front-end carry signal CR (n-3) has a faster phase of the gate-on voltage than the front-end carry signal CR (n-1). To this end, the input BLK1 includes a plurality of transistors T11A, T11B, T13A, T13B, and T12.

The transistors T11A and T11B may be implemented as a dual gate transistor unit connected in series through a Qh node. The transistor T11A is connected to the gate electrode connected to the input terminal (start terminal) of the front end carry signal CR (n-3), the first electrode connected to the input terminal of the high potential power supply voltage GVDD, and connected to the Qh node. It includes a second electrode. The transistor T11B includes a gate electrode connected to the input terminal of the front end carry signal CR (n-3), a first electrode connected to the Qh node, and a second electrode connected to the Q node. The Qh node is connected to the high potential power voltage GVDD through the transistor T12 while the Q node is maintained at the charging voltage. The gate electrode of the transistor T12 is connected to the Q node, the first electrode is connected to the high potential power supply voltage GVDD, and the second electrode is connected to the Qh node. When the transistors T11A and T11B are implemented as a dual gate transistor unit connected to the Qh node in this way, the leakage current (Off Current) of the transistors T11A and T11B is reduced to stably maintain the charging voltage of the Q node.

In addition, the input unit BLK1 discharges the Q node to the low potential power voltage (GVSS) level in response to the rear stage carry signal CR (n + 3) input through the reset terminal. The rear carry signal CR (n + 3) has a slower gate-on voltage than the previous carry signal CR (n-1). To this end, the transistors T13A and T13B may be implemented as a dual gate transistor unit connected in series through a Qh node. The transistor T13A includes a gate electrode connected to the input terminal (reset terminal) of the rear carry signal CR (n + 3), a first electrode connected to the Q node, and a second electrode connected to the Qh node. . The transistor T13B includes a gate electrode connected to the input terminal of the rear carry signal CR (n + 3), a first electrode connected to the Qh node, and a first electrode connected to the input terminal of the low potential power voltage GVSS. Includes 2 electrodes. When the transistors T13A and T13B are implemented as a dual gate transistor unit connected to the Qh node in this way, the leakage current (Off Current) of the transistors T13A and T13B can be reduced to stably maintain the charging voltage of the Q node.

The inverter unit BLK2 blocks electrical connection between the input terminal of the high potential power voltage GVDD and the QB node while the Q node maintains a charge state when driving IDW and driving SDW. The inverter BLK2 may charge the QB node by applying a high potential power voltage GVDD to the QB node according to the voltage of the Nx node. The voltage at the Nx node is controlled opposite to the Q node. The Nx node is discharged to the low potential power voltage (GVSS) level while the Q node is maintaining the charge state, while the Q node is charged to the high potential power voltage (GVDD) level while the Q node is maintaining the discharge state. In other words, the potential of the QB node is charged to the high potential power voltage (GVDD) level while the low potential power voltage (GVSS) is applied to the Q node.

To this end, the inverter unit BLK2 includes a plurality of transistors T21 to T23. The transistor T21 includes a gate electrode connected to the Nx node, a first electrode connected to the input terminal of the high potential power voltage GVDD, and a second electrode connected to the QB node. The transistor T22 includes a gate electrode and a first electrode connected to the input terminal of the high potential power voltage GVDD, and a second electrode connected to the N1 node. The transistor T23 includes a gate electrode connected to the Q node, a first electrode connected to the Nx node, and a second electrode connected to the input terminal of the low potential power voltage GVSS.

The inverter unit BLK2 discharges the QB node to a low potential power voltage (GVSS) level while the Q node is charged during IDW driving and SDW driving. In addition, the inverter unit BLK2 may additionally discharge the QB node to the low potential power voltage (GVSS) level according to the front end carry signal CR (n-3) to increase reliability of operation.

To this end, the inverter unit BLK2 further includes a plurality of transistors T24 and T25. The transistor T24 includes a gate electrode connected to the Q node, a first electrode connected to the QB node, and a second electrode to which the low potential power voltage GVSS is applied. The transistor T25 includes a gate electrode to which the front end carry signal CR (n-3) is applied, a first electrode connected to the QB node, and a second electrode to which the low potential power voltage GVSS is applied.

The output unit BLK3 outputs a scan clock (SCCLK (n)) having a high potential power voltage (GVDD) level while the Q node maintains a charge state when driving IDW, as an image scan signal (SCAN (n)), The carry clock CRCLK (n) having a high potential power voltage (GVDD) level is output as an image carry signal CR (n). In addition, the output unit BLK3 outputs a scan clock (SCCLK (n)) having a high potential power voltage (GVDD) level while the Q node maintains a charge state when the SDW is driven as a sensing scan signal SCAN (n). do.

To this end, the output BLK3 includes first and second pull-up transistors T31 and T32 and a boosting capacitor Co. The first pull-up transistor T31 includes a gate electrode connected to the Q node, a first electrode connected to the input terminal of the carry clock CRCLK (n), and a second electrode connected to the first output node NO1. . The second pull-up transistor T32 includes a gate electrode connected to the Q node, a first electrode connected to the input terminal of the scan clock SCCLK (n), and a second electrode connected to the second output node NO2. . Since the gate electrodes of the first and second pull-up transistors T31 and T32 are connected to the same Q node, the configuration and mounting area of the stage is reduced, and it is advantageous to reduce the bezel area. The boosting capacitor Co is connected between the Q node and the second output node NO2 to synchronize the voltage of the Q node with the high potential power voltage (GVDD) level scan clock (SCCLK (n)). Boot strapping to a boosting voltage level (BSL) higher than (GVDD). When the voltage of the Q node bootstraps, the scan clock (SCCLK (n)) of the high potential power voltage (GVDD) level is rapidly and without distortion, the scan signal for image (SCAN (n)) or the scan signal for sensing (SCAN (n )).

The stabilization unit BLK4 applies a low potential power voltage GVSS to the Q node and the output nodes NO1 and NO2 while the QB node is charged, thereby the voltage state of the Q node and the output nodes NO1 and NO2 Stabilizes.

To this end, the stabilizer BLK4 includes a plurality of transistors T41, T42, T44A, and T44B. The transistor T41 includes a gate electrode connected to the QB node, a first electrode connected to the first output node NO1, and a second electrode to which the low potential power voltage GVSS is applied. The transistor T42 includes a gate electrode connected to the QB node, a first electrode connected to the second output node NO2, and a source electrode to which the low potential power voltage GVSS is applied. The transistor T43 includes a gate electrode connected to the QB node, a first electrode connected to the Q node, and a second electrode to which the low potential power voltage GVSS is applied. The transistors T44A and T44B may be implemented as a dual gate transistor unit connected in series through the Qh node. The transistor T44A includes a gate electrode connected to the QB node, a first electrode connected to the Q node, and a second electrode connected to the Qh node. The transistor T44B includes a gate electrode connected to the QB node, a first electrode connected to the Qh node, and a second electrode connected to the input terminal of the low potential power supply voltage GVSS. When the transistors T44A and T44B are implemented as a dual gate transistor unit connected to the Qh node in this way, the leakage current (off current) of the transistors T44A and T44B can be reduced to stably maintain the charging voltage of the Q node.

The pixel line selector BLK5 performs a front-end carry signal CR (n) according to a first pixel line select signal LSPA having a high potential power voltage (GVDD) level during IDW driving performed in a vertical active period (VAP) of one frame. -2)) is applied to the M node to charge the M node to a high potential power voltage (GVDD) level to prepare for SDW driving. Subsequently, the pixel line selector BLK5 connects the M node to the Q node according to the sensing start signal SRT of the high potential power voltage GVDD level in the vertical blank period VBP of one frame, thereby connecting the Q node to the high voltage. Charge with the above power supply voltage (GVDD) to start SDW operation.

The pixel line selector BLK5 may include first to sixth transistors T51 to T56 and a capacitor Cx. The first and second transistors T51 and T52 are turned on according to the first pixel line select signal LSPA of the high potential power voltage GVDD level in the vertical active period VAP, and the third and fourth transistors The fields T53 and T54 are turned on while the M node maintains the charge state, and the fifth transistor T55 is applied to the sensing start signal SRT of the high potential power voltage GVDD level in the vertical blank period VBP. It turns on.

The first transistor T51 and the second transistor T52 are connected in series between the input terminal of the front end carry signal CR (n-2) and the M node to select the first pixel line having a high potential power voltage (GVDD) level. It is turned on simultaneously according to the signal LSPA. The first pixel line selection signal LSPA of the high potential power supply voltage GVDD level is inputted twice in one frame, that is, during the SDW preparation operation and at the end of the SDW driving.

During the SDW preparation operation, the first pixel line selection signal LSPA having a high potential power voltage (GVDD) level is a gate-on voltage section (ie, a high potential power voltage (GVDD) level) of the previous carry signal CR (n-2). Interval). In this case, the first transistor T51 and the second transistor T52 apply a front-end carry signal CR (n-2) having a high-potential power voltage (GVDD) level to the M node, and thus the M-node is a high-potential power voltage. Charge to (GVDD) level.

When the SDW driving ends, the first pixel line selection signal LSPA having a high potential power voltage (GVDD) level is a gate-off voltage section (that is, a low potential power voltage (GVSS)) level section of the previous carry signal CR (n-2). ). In this case, the first transistor T51 and the second transistor T52 apply the front end carry signal CR (n-2) having a low potential power voltage (GVSS) level to the M node, and then the M node has a low potential power voltage. Discharge to (GVSS) level.

The first electrode of the third transistor T53 is connected to the input terminal of the high potential power voltage GVDD, and the second electrode of the third transistor T53 is between the first transistor T51 and the second transistor T52. It is connected to the Na node, and the gate electrode of the third transistor T53 is connected to the M node. The third transistor T53 is turned on according to the charging voltage of the M node, thereby applying the high potential power voltage GVDD to the Na node between the first transistor T51 and the second transistor T52. And reducing the off current of the second transistors T51 and T52, and stably maintaining the charging voltage of the M node until the vertical blank period VBP in which the SDW driving is performed.

The first electrode of the fourth transistor T54 is connected to the input terminal of the high potential power voltage GVDD, and the second electrode of the fourth transistor T54 is connected to one electrode of the fifth transistor T55, and the fourth electrode The gate electrode of the transistor T54 is connected to the M node. The fourth transistor T54 is turned on according to the charging voltage of the M node to apply a high potential power voltage GVDD to the first electrode of the fifth transistor T55.

The first electrode of the fifth transistor T55 is connected to the second electrode of the fourth transistor T54, the second electrode of the fifth transistor T55 is connected to the Q node, and the gate of the fifth transistor T55 The electrode is connected to the input terminal of the sensing start signal SRT. The fifth transistor T55 is turned on according to the sensing start signal SRT of the gate-on voltage to apply the high potential power voltage GVDD to the Q node.

The sixth transistor T56 is turned on according to the global reset signal QRST of the gate-on voltage to initialize the Q node to the low potential power voltage GVSS. The global reset signal QRST is a common signal input when the display device is powered on. The gate electrode of the sixth transistor T56 is connected to the input terminal of the global reset signal QRST, the first electrode of the sixth transistor T56 is connected to the Q node, and the second electrode of the sixth transistor T56 is It is connected to the input terminal of the low potential power supply voltage (GVSS).

The capacitor Cx is connected between the input terminal of the high-potential power voltage GVDD and the M node to stably maintain the charging voltage of the M node until the vertical blank period VBP in which the SDW driving is performed.

The Q node strengthening unit BLK6 prevents leakage of the charging voltage of the Q node according to the charging voltage of the M node and the sensing end signal SND in the vertical blank period VBP. In the period during which the M node maintains the charge state in the vertical blank period VBP, the Q node is charged with the high potential power voltage GVDD, and the sensing termination signal SND maintains the low potential power voltage GVDD. do.

To this end, the Q node enhancement unit BLK6 includes a plurality of transistors T62, T63A, and T63B. The gate electrode of the transistor T62 is connected to the M node, and one electrode of the transistor T62 is connected to the input terminal of the low potential power supply voltage GVSS. The gate electrode of the transistor T63A is connected to the sensing end signal SND, and one electrode of the transistor T63A is connected to the Q node. Further, the gate electrode of the transistor T63B is connected to the sensing end signal SND, and one electrode of the transistor T63B is connected to the other electrode of the transistor T62.

The sensing end signal SND is input to the high potential power voltage GVDD level after the sensing scan signal SCAN (n) is output in the vertical blank period VBP. While the Q node remains charged in the vertical blank period VBP, the other electrode of the transistor T63B is connected to the Qh node to which the high potential power voltage GVDD is applied. In addition, the transistors T63A and T63B are connected in series through the Qh node to implement a dual gate transistor unit, thereby reducing the leakage current (Off Current) of the transistors T44A and T44B to stably maintain the charging voltage of the Q node. have.

The Q node enhancement unit BLK6 further includes a transistor T64 to prevent the Q nodes of the stages connected to the second region from being discharged according to the sensing termination signal SND of the high potential power voltage GVDD level. . The gate electrode of the transistor T64 is connected to the M node, one electrode of the transistor T64 is connected to the other electrode of the transistor T63A, and the other electrode of the transistor T64 is connected to the Qh node.

The Q node enhancement unit BLK6 further includes a transistor T61 for discharging the QB node to the low potential power voltage GVSS according to the sensing start signal SRT of the high potential power voltage GVDD level. When the discharge state of the QB node is unstable, the charging state of the Q node is also unstable, so the Q node reinforcement unit BLK6 transistor T61 when the sensing start signal SRT of the high potential power voltage GVDD level is applied. Stably discharges the QB node through the low potential power supply voltage (GVSS). The gate electrode of the transistor T61 is connected to the input terminal of the sensing start signal SRT, one electrode of the transistor T61 is connected to the QB node, and the other electrode of the transistor T61 is connected to the other electrode of the transistor T62. Connected.

Among the stages connected to the pixel lines in the A region, the number of active stages in which the M node is charged by the front-end carry signal CR (n-2) is 1 for each frame, and the position of the active stage is changed for each frame. . When the position of the active stage is randomly changed for each frame, the degree to which the sensed pixel line is recognized as the line dim can be greatly reduced. Each of these stages, in accordance with the first pixel line selection signal LSPA synchronized with the sensing end signal SND of the high potential power voltage GVDD level in the vertical blank period VBP, carries the preceding carry signal CR (n- By discharging the M node with 2)), stability of operation is ensured.

17 is a first equivalent circuit diagram of one stage connected to the second region among the stages of FIG. 11. The stage of FIG. 17 may be connected to the pixel PIX of the second region through the gate line 17. 18 is an operation timing diagram of the equivalent circuit diagram shown in FIG. 17. Referring to FIGS. 17 and 18, one stage connected to the B region includes an input unit BLK1, an inverter unit BLK2, an output unit BLK3, and stabilization It includes a part BLK4, a pixel line selection part BLK5, and a Q node enhancement part BLK6.

The first pixel line selection signal LSPA is applied to the stage of FIG. 15, while the second pixel line selection signal LSPB is applied to the stage of FIG. 17.

The first pixel line selection signal LSPA and the second pixel line selection signal LSPB are alternately activated at a high potential power voltage (GVDD) level, and the first pixel line selection signal LSPA and the second pixel line selection are performed. When one of the signals LSPB is activated, the other is deactivated to a low potential power voltage (GVSS) level. That is, when the pixel line connected to one stage of FIG. 15 is sensed, only the first pixel line selection signal LSPA is activated, and when the pixel line connected to one stage of FIG. 17 is sensed, the second pixel line selection signal ( LSPB) only.

The detailed configuration and operation of the stages of FIGS. 17 and 18 are similar to those described with reference to FIGS. 15 and 16 and are omitted.

FIG. 19 is a second equivalent circuit diagram of one stage connected to the first region among the stages of FIG. 11. 20 is an operation timing diagram of the equivalent circuit diagram shown in FIG. 19.

Referring to FIGS. 19 and 20, one stage connected to the A region includes an input unit BLK1, an inverter unit BLK2, an output unit BLK3, a stabilization unit BLK4, a pixel line selection unit BLK5, and a Q node enhancement Includes part BLK6.

The stages of FIGS. 19 and 20 are configured differently from the stages of FIGS. 15 and 16, and the Q node enhancement unit BLK6 is configured differently, and the sensing start signal SRT, sensing end signal SND, and global reset are performed. By configuring the gate off voltage of the signal QRST differently, it is possible to stably maintain the boosting voltage BSL of the Q node in a specific section DD within the vertical blank period VBP while simplifying the stage configuration. In other words, the stages of FIGS. 19 and 20 can exhibit similar effects while reducing the number of transistors compared to the stages of FIGS. 15 and 16. The specific section DD is a section in which the scan clock SCCLK (n) for sensing of the high potential power voltage GVDD level is output as the sensing scan signal SCAN (n).

19 and 20, the configuration and operation of the input unit BLK1, the inverter unit BLK2, the output unit BLK3, the stabilization unit BLK4, and the pixel line selection unit BLK5 are identical to the stages of FIGS. 15 and 16. It is substantially the same and is omitted.

Referring to FIGS. 19 and 20, the Q node enhancement unit BLK6 may include four transistors T61 to T64.

In the transistor T61, its gate electrode is connected to the M node, its one electrode is connected to the QB node, and its other electrode is connected to one electrode of the transistor T61. In the transistor T62, its gate electrode is connected to the input terminal of the sensing start signal SRT, one electrode thereof is connected to the other electrode of the transistor T61, and the other electrode thereof is connected to the input terminal of the low potential power voltage GVSS. Connected. In the transistor T63, its gate electrode is connected to the M node, its one electrode is connected to the Q node, and its other electrode is connected to one electrode of the transistor T64. In addition, the transistor T64 has its gate electrode connected to the input terminal of the sensing end signal SND, its one electrode connected to the other electrode of the transistor T63, and the other electrode of the transistor T64 having a low potential power voltage (GVSS). It is connected to the input terminal.

In a specific section DD, in order for the sensing scan signal SCAN (n) to be normally output, the Q node must maintain the boosting voltage BSL. For this, the Q node is connected to the input terminal of the low potential power voltage GVSS. It should not be connected. In a specific period DD, since the transistor T63 maintains the turn-on state by the voltage of the M node of the high potential power voltage GVDD level, the transistor T64 must stably maintain the turn-off state. The threshold voltage of the transistor T64 may be shifted in the (-) direction for various reasons. In this case, in a specific section DD, even if the same low potential power voltage (GVSS) level is applied to the gate electrode and the source electrode of the transistor T64, the transistor T64 may not be completely turned off. In a certain period DD, when the transistor T64 is not completely turned off, the boosting voltage BSL of the Q node is discharged to the input terminal of the low potential power voltage GVSS, and the potential of the Q node becomes unstable, and the scan for sensing The signal SCAN (n) cannot be output normally.

To solve this problem, the gate-off voltage of the sensing termination signal SND applied to the gate electrode of the transistor T64 in a specific period DD is a first low potential power voltage lower than a low potential power voltage (GVSS) level. (GVSS1) level. In this case, the gate-source voltage Vgs of the transistor T64 is greater than the threshold voltage of the transistor T64 so that the transistor T64 maintains a complete turn-off state in a specific period DD as shown in FIG. 23C. It becomes lower than politics. In a specific period DD, the gate-source voltage Vgs of the transistor T64 is a difference between the low potential power voltage GVSS level and the first low potential power voltage GVSS1 level. In a specific section DD, the first low potential power voltage (V) is such that the difference between the low potential power voltage (GVSS) level and the first low potential power voltage (GVSS1) level is greater than the maximum threshold voltage shift amount of the transistor T64. It is desirable to set the GVSS1) level sufficiently lower than the low potential power supply voltage (GVSS) level.

Meanwhile, the gate-off voltage of the sensing start signal SRT applied to the gate electrode of the transistor T62 in a specific period DD is also set to the first low potential power voltage GVSS1 level lower than the low potential power voltage GVSS level. Can be entered. When the gate-off voltage of the sensing start signal SRT is designed to the first low potential power voltage GVSS1 level, the threshold voltage shift of the transistor T62 can be minimized. In this case, the gate-source voltage Vgs of the transistor T62 is greater than the threshold voltage of the transistor T62 so that the transistor T62 maintains a complete turn-off state in a specific period DD as shown in FIG. 23B. It becomes lower than politics. In a specific period DD, the gate-source voltage Vgs of the transistor T62 becomes a difference between the low potential power voltage GVSS level and the first low potential power voltage GVSS1 level. In a specific section DD, the first low potential power voltage (V) is such that the difference between the low potential power voltage (GVSS) level and the first low potential power voltage (GVSS1) level is greater than the maximum threshold voltage shift amount of the transistor T62. It is desirable to set the GVSS1) level sufficiently lower than the low potential power supply voltage (GVSS) level.

Meanwhile, the transistor T56 in a specific period DD may also affect the voltage of the Q node. In order to maintain the boosting voltage BSL of the Q node in the specific period DD, the transistor T56 must be completely turned off. The threshold voltage of the transistor T56 may be shifted in the (-) direction for various reasons. In this case, in a specific section DD, even when the same low potential power voltage (GVSS) level is applied to the gate electrode and the source electrode of the transistor T56, the transistor T56 may not be completely turned off. In a certain period DD, when the transistor T56 is not completely turned off, the boosting voltage BSL of the Q node is discharged to the input terminal of the low potential power voltage GVSS, causing the potential of the Q node to become unstable and scanning for sensing. The signal SCAN (n) cannot be output normally.

To solve this problem, the gate-off voltage of the global reset signal QRST applied to the gate electrode of the transistor T56 in a specific period DD is the first low potential power voltage lower than the low potential power voltage (GVSS) level. (GVSS1) level. In this case, the gate-source voltage Vgs of the transistor T56 is greater than the threshold voltage of the transistor T56 so that the transistor T56 maintains a complete turn-off state in a specific period DD as shown in FIG. 23A. It becomes lower than politics. In a specific period DD, the gate-source voltage Vgs of the transistor T56 is the difference between the low potential power voltage GVSS level and the first low potential power voltage GVSS1 level. In a specific section DD, the first low potential power voltage (V) is such that the difference between the low potential power voltage (GVSS) level and the first low potential power voltage (GVSS1) level is greater than the maximum threshold voltage shift amount of the transistor T56. It is desirable to set the GVSS1) level sufficiently lower than the low potential power supply voltage (GVSS) level. FIG. 21 is a second equivalent circuit diagram of one stage connected to the second region among the stages in FIG. 22 is an operation timing diagram of the equivalent circuit diagram shown in FIG. 21.

Referring to FIGS. 21 and 22, one stage connected to the B region includes an input unit BLK1, an inverter unit BLK2, an output unit BLK3, a stabilization unit BLK4, a pixel line selection unit BLK5, and a Q node enhancement Includes part BLK6.

The first pixel line selection signal LSPA is applied to the stage of FIG. 19, while the second pixel line selection signal LSPB is applied to the stage of FIG. 21.

The first pixel line selection signal LSPA and the second pixel line selection signal LSPB are alternately activated at a high potential power voltage (GVDD) level, and the first pixel line selection signal LSPA and the second pixel line selection are performed. When one of the signals LSPB is activated, the other is deactivated to a low potential power voltage (GVSS) level. That is, when the pixel line connected to one stage of FIG. 19 is sensed, only the first pixel line selection signal LSPA is activated, and when the pixel line connected to one stage of FIG. 21 is sensed, the second pixel line selection signal ( LSPB) only.

The specific configuration and operation of the stages of FIGS. 21 and 22 are similar to those described with reference to FIGS. 19 and 20 and are omitted.

As described above, the present invention includes a Q node reinforcement unit that prevents leakage of the charging voltage of the Q node in each stage according to the charging voltage of the M node and the sensing end signal in the vertical blank period, thereby charging the Q node during sensing driving. To stabilize the desired gate output characteristics can be secured. The present invention can greatly improve sensing and compensation performance for driving characteristics of pixels by securing gate output characteristics during sensing driving.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

100: display panel 110: timing controller
130: gate shift register

Claims (21)

Outputs a scan signal for an image in a vertical active period in one frame, outputs a scan signal for sensing in a vertical blank period in one frame, and includes stages having an M node, a Qh node, a Q node, and a QB node,
Each of the stages,
In the vertical active period, the M node is charged with a preceding carry signal according to the pixel line selection signal, and the Q node is charged with a high potential power voltage level according to the charging voltage of the M node and the sensing start signal in the vertical blank period. A pixel line selecting unit;
A Q node strengthening unit preventing leakage of the charging voltage of the Q node according to the charging voltage of the M node and the sensing end signal in the vertical blank period; And
A gate driver including an output unit outputting a scan clock for sensing the high potential power voltage level as the scan signal for sensing while the Q node maintains a charge state in the vertical blank period. According to claim 1,
In the vertical blank period, while the M node maintains a charge state, the Q node is charged to the high potential power voltage level according to the sensing start signal, and the sensing end signal maintains a low potential power voltage level,
The Q node strengthening unit,
A first transistor having a gate electrode connected to the M node and one electrode connected to an input terminal of a low potential power voltage;
A second transistor having a gate electrode connected to the input terminal of the sensing end signal and one electrode connected to the Q node; And
A gate driver including a third transistor having a gate electrode connected to the input terminal of the sensing termination signal and one electrode connected to the other electrode of the first transistor. According to claim 2,
A gate driver connected to the Qh node of the high potential power supply voltage level while the other electrode of the third transistor is maintained while the Q node remains charged in the vertical blank period. The method of claim 3,
The second transistor and the third transistor are connected in series through the Qh node, a gate driver to implement a first dual gate transistor unit. According to claim 2,
The Q node strengthening unit,
The gate driver further includes a fourth transistor connected to the M node, one electrode connected to the other electrode of the second transistor, and a fourth electrode connected to the other electrode of the third transistor. According to claim 2,
The Q node strengthening unit,
The gate driver further includes a fifth transistor connected to the input terminal of the sensing start signal, one electrode connected to the QB node, and the other electrode connected to the other electrode of the first transistor. According to claim 1,
In the vertical blank period, while the M node maintains a charge state, the Q node is charged to the high potential power voltage level according to the sensing start signal, and the sensing end signal maintains a low potential power voltage level,
The Q node strengthening unit,
A first transistor having a gate electrode connected to the M node and one electrode connected to the QB node;
A second transistor having a gate electrode connected to the input terminal of the sensing start signal, one electrode connected to the other electrode of the first transistor, and the other electrode connected to an input terminal of a low potential power voltage;
A third transistor having a gate electrode connected to the M node and one electrode connected to the Q node; And
A gate driver including a fourth transistor having a gate electrode connected to the input terminal of the sensing termination signal, one electrode connected to the other electrode of the third transistor, and the other electrode connected to the input terminal of the low potential power voltage. The method of claim 7,
While the scan clock for sensing of the high potential power voltage level is output as the scan signal for sensing,
The sensing start signal and the sensing end signal are respectively maintained at a first low potential power voltage level lower than the low potential power voltage level. The method of claim 8,
While the scan clock for sensing of the high potential power voltage level is output as the scan signal for sensing,
The voltage between the gate and the source of the second transistor is lower than or equal to a threshold voltage by the threshold voltage of the second transistor so that the second transistor can remain turned off,
The gate-to-source voltage of the fourth transistor is lower than a threshold voltage of the fourth transistor to maintain the turn-off state of the fourth transistor by a gate driver. The method of claim 9,
A gate driver having a difference between the low potential power voltage level and the first low potential power voltage level is greater than a maximum threshold voltage shift amount for the second transistor and the fourth transistor. According to claim 1,
The Qh node is connected to the input terminal of the high potential power voltage through the sixth transistor T12,
The sixth transistor is a gate driver including a gate electrode connected to the Q node, one electrode connected to the input terminal of the high potential power voltage, and the other electrode connected to the Qh node. According to claim 1,
The pixel line selection signal,
In the vertical active period, it is applied to the high potential power voltage level in synchronization with the previous carry signal,
In the vertical blank period, a gate driver applied to the high potential power voltage level in synchronization with the sensing end signal. The method of claim 12,
Among the stages, the number of active stages in which the M node is charged by the preceding carry signal of the high potential power voltage level during the vertical active period is one per frame, and the position of the active stage is randomly changed per frame. Gate driver. According to claim 1,
In the vertical blank period,
Prior to the output of the sensing scan signal, the sensing start signal is simultaneously input to the stages at the high potential power voltage level,
After the output of the sensing scan signal is finished, the gate driver is input to the sensing end signal at the same time as the high potential power voltage level. According to claim 1,
The pixel line selection unit,
A first transistor and a second transistor connected in series between the input terminal of the front end carry signal and the M node and turned on simultaneously according to the pixel line selection signal of the high potential power voltage level;
A third transistor having a first electrode connected to an input terminal of a high potential power voltage and a second electrode connected between the first transistor and the second transistor, turned on according to the charging voltage of the M node;
A fourth transistor connected to an input terminal of the high potential power voltage and turned on according to a charging voltage of the M node;
A fifth transistor connected to a second electrode of the fourth transistor and a second electrode connected to the Q node to turn on according to the sensing start signal of the high potential power voltage level; And
A gate driver including a capacitor connected between the input terminal of the high potential power voltage and the M node. The method of claim 15,
The pixel line selection unit,
The gate driver further includes a sixth transistor connected to the Q node and a second electrode connected to an input terminal of a low potential power voltage, and turned on according to a global reset signal of the high potential power voltage level. The method of claim 15,
While the scan clock for sensing of the high potential power voltage level is output as the scan signal for sensing,
The global reset signal is maintained at a first low potential power voltage level lower than the low potential power voltage level. The method of claim 17,
While the scan clock for sensing of the high potential power voltage level is output as the scan signal for sensing,
The voltage between the gate and the source of the sixth transistor is lower than a threshold voltage by the threshold voltage of the sixth transistor so that the sixth transistor can maintain a turn-off state,
A gate driver having a difference between the low potential power voltage level and the first low potential power voltage level is greater than a maximum threshold voltage shift amount for the sixth transistor. The method of claim 12,
Each of the stages,
When the sensing termination signal and the pixel line selection signal are both applied to the high potential power voltage level in the vertical blank period, the M node is connected to the input terminal of the front end carry signal, so that the low potential power voltage level of the front end carry signal The gate driver to discharge the M node until. According to claim 1,
The pixel line selection signal,
A first pixel line selection signal input to first stages connected to pixel lines of the first area;
And a second pixel line selection signal input to second stages connected to pixel lines of the second region,
The first pixel line selection signal and the second pixel line selection signal are alternately activated to the high potential power voltage level, and within the same frame, either the first pixel line selection signal or the second pixel line selection signal is When one is activated, the other is a deactivated gate driver. The gate driver of any one of claims 1 to 20; And
An organic light emitting display device connected to the gate driver through gate lines and including a plurality of pixels driven according to the image scan signal and the sensing scan signal.

Images