CN114530115A

CN114530115A - Light emitting device and light emitting unit

Info

Publication number: CN114530115A
Application number: CN202110655763.XA
Authority: CN
Inventors: 丁景隆; 曾名骏; 罗闵馨; 廖宏昇
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2020-11-02
Filing date: 2021-06-11
Publication date: 2022-05-24

Abstract

The present disclosure provides a light emitting device and a light emitting unit. The light-emitting device comprises a carrier plate, a first light-emitting unit and a second light-emitting unit. The first light-emitting unit is arranged on the carrier plate and is provided with a first scanning circuit, a first emitting circuit, a first input end and a first output end. The second light-emitting unit is arranged on the carrier plate and is provided with a second input end. The second input end is electrically connected with the first output end of the first light-emitting unit. The first scanning circuit is used for providing a first scanning signal to the first emitting circuit and the second light emitting unit. The light-emitting device and the light-emitting unit can reduce the number of signal wires or have a circuit simplification effect.

Description

Light emitting device and light emitting unit

Technical Field

The present disclosure relates to a device, and more particularly, to a light emitting device having a light emitting unit and a light emitting unit.

Background

For a Light Emitting Diode (LED) unit in a conventional Light Emitting device, a pixel circuit and a gate driver circuit on a panel are separately disposed on a carrier. Since the gate driving circuit is non-transparent and is disposed at the peripheral region of the carrier or beside the corresponding pixel circuit, the excessive gate driving circuit and wiring arrangement will cause the waste of carrier space and the reduction of light emitting area. In addition, the number of signals on the carrier board of the light emitting device is too large, and the signals are likely to be coupled with each other.

Disclosure of Invention

The present disclosure provides a light emitting device and a light emitting unit. The light-emitting device comprises a carrier plate, a first light-emitting unit and a second light-emitting unit. The first light-emitting unit is arranged on the carrier plate and is provided with a first scanning circuit, a first emitting circuit, a first input end and a first output end. The second light-emitting unit is arranged on the carrier plate and is provided with a second input end. The second input end is electrically connected with the first output end of the first light-emitting unit. The first scanning circuit is used for providing a first scanning signal to the first emitting circuit and the second emitting unit.

Based on the above, the light emitting device and the light emitting unit of the present disclosure can reduce the number of signal traces or have a circuit simplification effect.

In order to make the aforementioned and other features and advantages of the disclosure more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic view of a light emitting device according to a first embodiment of the present disclosure;

fig. 2 is a circuit diagram of a light emitting unit according to a first embodiment of the disclosure;

FIG. 3 is a circuit diagram of a pixel circuit according to a first embodiment of the disclosure;

fig. 4 is a circuit diagram of a transmitting circuit according to a first embodiment of the disclosure;

FIG. 5 is a circuit diagram of a gate driving circuit according to a first embodiment of the disclosure;

fig. 6 is a partial routing layout diagram of a light emitting device according to a first embodiment of the disclosure;

fig. 7A is a circuit diagram of a light emitting unit according to a second embodiment of the disclosure;

fig. 7B is a circuit diagram of a light emitting unit according to a third embodiment of the disclosure;

fig. 7C is a circuit diagram of a light emitting unit according to a fourth embodiment of the disclosure;

fig. 8 is a circuit diagram of a light emitting device according to a third embodiment of the disclosure.

Description of the reference numerals

100. 600, 800, light-emitting device;

101. 600A carrier plate

110. 710A, 720A, 730A, 810A, 820A, 830A, 840A;

102, an active area;

110_1 to 110_ P, 710, 720, 730, 810, 820, 830, 840 light emitting units;

201. 203, an input end;

202, an output end;

210. p (1,1) to P (m, n), Pa (1,1) to Pa (m, n), Pb (1,1) to Pb (m, n), Pc (1,1) to Pc (m, n), Pd (1,1) to Pd (m, n): a pixel circuit;

211. 619_ 1-619 _3, 629_ 1-629 _3, 639_ 1-639 _3, 649_ 1-649 _3, light emitting diodes;

220. 712, 812, 822, 832 and 842 gate drive circuits;

221. 521, a scanning circuit;

222. 522 a transmitting circuit;

521_1 to 521_6 scanning units;

601-607, 601' -607;

610. 620, 630, 640, integrating the wafer;

611 to 618, 621 to 628, 631 to 638, 641 to 648;

SA, SA 1-SA 4 as the first scanning signal;

SB, SB 1-SB 5;

ES, transmitting signals;

SP, SP 1-SP 4 are starting signals;

CK1, a first clock signal;

CK2, second clock signal;

td, Te, Ts, T1-T8 transistors;

SL, SL 1-SLn are scanning signal lines;

EL, EL1 to ELn are emission signal lines;

cst, a storage capacitor;

vdd, Vss, VGH, VGL voltage;

DL is a data line;

d1, data signal; data of

C1-C4 is capacitance.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Certain terms are used throughout the description and following claims to refer to particular elements. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that differ in function but not name. In the following specification and claims, the words "comprise", "comprising", "includes" and "including" are open-ended words that should be interpreted as meaning "including, but not limited to …".

In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, with respect to bonding, connecting, and the like, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, unless otherwise specified, with respect to the structure between which they are disposed. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed. Furthermore, the terms "electrically connected" and "coupled" include any direct and indirect electrical connection.

The use of ordinal numbers such as "first," "second," etc., in the specification and claims to modify an element, is not itself intended to imply that the element, or any preceding element, is not necessarily the same order in which it is determined to be a member of the group consisting of the elements, or the order in which it is determined to be a member of the group consisting of the elements. The claims may not use the same language in the specification, and accordingly, a first element in the specification may be a second element in the claims. It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure.

It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure. Features of the various embodiments may be combined and matched as desired, without departing from the spirit or ambit of the invention.

The light emitting device of the present disclosure may include a display device, an antenna device, a sensing device, a touch display device (touch display), a curved display device (curved display), or a non-rectangular display device (free shape display), but is not limited thereto. The light emitting device can be a bendable or flexible display device. The Light Emitting device may include, for example, a liquid crystal, a Light Emitting Diode (LED), a Quantum Dot (QD), a fluorescent (fluorescent), a phosphorescent (Phosphor), other suitable materials, or a combination thereof, but is not limited thereto. The Light Emitting Diode may include, for example, an Organic Light Emitting Diode (OLED), a submillimeter Light Emitting Diode (Mini LED), a Micro LED (Micro LED), a quantum dot Light Emitting Diode (QLED or QDLED), or other suitable materials, and the materials may be arranged and combined arbitrarily, but not limited thereto. The light emitting device may include, for example, a tiled light emitting device, but is not limited thereto. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The antenna device may include, for example, but is not limited to, an antenna splicing device. It should be noted that the light emitting devices can be arranged and combined as described above, but not limited thereto. In addition, the light emitting device may have a rectangular shape, a circular shape, a polygonal shape, a shape with curved edges, or other suitable shapes. The lighting device may have a peripheral system such as a drive system, a control system, a light source system, a shelf system …, etc. to support a display device, an antenna device, or a tile device. In addition, the substrate and the carrier according to the embodiments of the disclosure may be a circuit substrate, a glass substrate of a display panel, or a flexible substrate.

Fig. 1 is a schematic view of a light emitting device according to a first embodiment of the disclosure. Referring to fig. 1, a light emitting device 100 includes a plurality of light emitting units 110_1 to 110_ P arranged in an array in an Active Area (AA) 102 of a carrier 101, where P is a positive integer. The light emitting device 100 may be a transparent display device, but is not limited thereto. In the present embodiment, at least a portion of the light emitting units 110_1 to 110_ P may respectively integrate a Gate driver On Panel (GOP) circuit and a pixel circuit. The regions of the carrier 101 other than the active region 102 are referred to as peripheral regions. In the embodiment, the light emitting device 100 may be in the form of the light emitting diode described above, such as an Active Matrix sub-millimeter light emitting diode (AM-Mini LED) display device, and the carrier 101 may be a transparent glass carrier, but the disclosure is not limited thereto. In the embodiment, since the light emitting units 110_1 to 110_ P can respectively integrate the gate driving circuit and the pixel circuit, and the gate driving circuit and the pixel circuit can receive the same start signal and the same clock signal, the light emitting device 100 can reduce the number of signal traces or the space occupied by the gate driving circuit on the carrier board 101, thereby having a circuit simplification effect.

Fig. 2 is a circuit diagram of a light emitting unit according to a first embodiment of the disclosure. Referring to fig. 1 and 2, the following description takes the light emitting unit 110_1 and the light emitting unit 110_2 as an example. The light emitting unit 110_1 includes a substrate 110, an input terminal 201, an output terminal 202, a pixel circuit 210, and a gate driving circuit 220. The gate driving circuit 220 includes a scan circuit 221 and an emission circuit 222, and the pixel circuit 210, the scan circuit 221 and the emission circuit 222 can be disposed on the substrate 110. The light emitting unit 110_2 includes an input terminal 203. The substrate 110 may be located on the carrier 101. More specifically, the substrate 110 of the light emitting unit 110_1 may have traces (not shown), and the scan circuit 221 may be electrically connected to the pixel circuit 210 and the emission circuit 222 through the traces on the substrate 110. The carrier 101 of the light emitting device 100 also has traces (not shown), the substrate 110 of the light emitting unit 110_1 can be electrically connected to the carrier 101, and the scan circuit 221 can be electrically connected to the light emitting unit 110_2 through the traces on the carrier 101. The emitting circuit 222 is electrically connected to the pixel circuit 210 and the scanning circuit 221. The input terminal 203 of the light emitting unit 110_2 is electrically connected to the output terminal 202 of the light emitting unit 110_ 1. In the embodiment, the scan circuit 221 and the emission circuit 222 can receive the same start signal SP, the clock signal CK1 and the clock signal CK2 from the input terminal 201, wherein the clock signal CK2 can be an inverse signal of the clock signal CK1, but the disclosure is not limited thereto. In the present embodiment, the start signal SP may be provided by a scan circuit of a light emitting unit of a previous stage of the light emitting units 110_1 or a driving circuit disposed in a peripheral region of the substrate 101. The scan circuit 221 may provide a second scan signal SB to the pixel circuit 210 for driving internal circuit elements of the pixel circuit 210. In the present embodiment, the emission circuit 222 generates the emission signal ES according to the start signal SP, the clock signal CK1, the clock signal CK2 and the first scan signal SA provided by the scan circuit 221, and provides the emission signal ES to the pixel circuit 210 to drive the pixel circuit 210. Similarly, the input terminal 203 of the light emitting unit 110_2 can receive the first scan signal SA, the clock signal CK1 and the clock signal CK2 from the light emitting unit 110_ 1. In this regard, the light emitting units of any two adjacent stages of the light emitting units 110_1 to 110_ P of fig. 1 may be configured as shown in fig. 2. As such, the light emitting device 100 can reduce the number of signal lines or reduce the circuit complexity. It should be noted that, although in fig. 2, the pixel circuit 210, the scan circuit 221 and the emission circuit 222 of the light emitting unit 110_1 are all disposed on the substrate 110, the substrate 110 is electrically connected to the carrier 101. However, in some embodiments, the pixel circuit 210, the scan circuit 221 and the emission circuit 222 of the light emitting unit 110_1 can be directly disposed in a smaller range on the carrier 101. That is, the light emitting unit 110_1 can be directly formed on the carrier 101.

Fig. 3 is a circuit diagram of a pixel circuit according to a first embodiment of the disclosure. Referring to fig. 2 and 3, an embodiment of the pixel circuit of the present disclosure may be, for example, but not limited to, the pixel circuit 210 shown in fig. 3. In the present embodiment, the pixel circuit 210 includes transistors Ts, Td, Te, a storage capacitor Cst, and a light emitting diode 211. The transistors Ts, Td, Te may be P-type transistors, respectively, but in some embodiments, some or all of the transistors may be N-type transistors. The light emitting diode 211 may be, but is not limited to, the light emitting diode type described above, such as a sub-millimeter light emitting diode. In this embodiment, a first terminal of the transistor Ts is electrically connected to the data line DL, and a second terminal of the transistor Ts is electrically connected to the control terminal of the transistor Td and the first terminal of the storage capacitor Cst. The control terminal of the transistor Ts is electrically connected to the scanning signal line SL. The first terminal of the transistor Td is electrically connected to the second terminal of the storage capacitor Cst and the voltage Vdd. The second terminal of the transistor Td is electrically connected to the first terminal of the transistor Te. The control terminal of the transistor Te is electrically connected to the emission signal line EL. The second terminal of the transistor Te is electrically connected to one terminal of the light emitting diode 211. The other end of the light emitting diode 211 is electrically connected to the voltage Vss. In the present embodiment, the scan signal line SL may receive the second scan signal SB. The transmission signal line EL can receive the transmission signal ES. The data line DL may receive a data signal D1. Therefore, the pixel circuit 210 can drive the light emitting diode 211 according to the second scan signal SB, the emission signal ES and the data signal D1.

Fig. 4 is a circuit diagram of a transmitting circuit according to a first embodiment of the disclosure. Referring to fig. 2 and 4, an embodiment of the transmitting circuit of the present disclosure may be, for example (but not limited to), the transmitting circuit 222 shown in fig. 4. In the present embodiment, the transmission circuit 222 includes transistors T1 to T8, and capacitors C1 to C4. The transistors T1 through T8 may be P-type transistors, respectively. A first terminal of the transistor T1 may receive the start signal SP. The second terminal of the transistor T1 is electrically connected to the first terminal of the transistor T3, the control terminal, and the first terminal of the capacitor C1. The control terminal of the transistor T1 is electrically connected to the first terminal of the transistor T2 and the second terminal of the capacitor C1. The control terminal of the transistor T2 may receive the first clock signal CK 1. The second terminal of the transistor T2 is electrically connected to the voltage VGL. The control terminal of the transistor T3 is electrically connected to the first terminal of the capacitor C1. The second terminal of the transistor T3 is electrically connected to the control terminal of the transistor T4, the first terminal of the transistor T5, the control terminal of the transistor T6 and the first terminal of the capacitor C3. The first terminal of the transistor T4 is electrically connected to the first terminal of the transistor T7, the control terminal of the transistor T8, the first terminal of the capacitor C2, and the first terminal of the capacitor C4. The second terminal of the capacitor C2 may receive the second clock signal CK 2. The second terminal of the transistor T4 is electrically connected to the voltage VGH. The control terminal of the transistor T5 can receive the first scan signal SA. The second terminal of the transistor T5 is electrically connected to the voltage VGH, the second terminal of the capacitor C3, and the first terminal of the transistor T6. The second terminal of the transistor T6 is electrically connected to the output terminal 202, the first terminal of the transistor T8, and the second terminal of the capacitor C4. The control terminal of the transistor T7 can receive the first scan signal SA. The second terminal of the transistor T7 is electrically connected to the voltage VGL. The second terminal of the transistor T8 is electrically connected to the voltage VGL. Therefore, the transmitting circuit 222 can provide the transmitting signal ES from the output terminal 202 according to the start signal SP, the first clock signal CK1, the second clock signal CK2 and the first scan signal SA.

Fig. 5 is a circuit diagram of a gate driving circuit according to a first embodiment of the disclosure. Referring to fig. 5, an embodiment of the gate driving circuit of the present disclosure may be, for example (but not limited to), the gate driving circuit 520 shown in fig. 5. In the present embodiment, the gate driving circuit 520 includes a scanning circuit 521 and an emission circuit 522. The scan circuit 521 may include a plurality of scan units 521_1 to 521_ 6. The scan units 521_1 to 521_6 and the transmitting circuit 522 respectively receive the same first clock signal CK1, second clock signal CK2, voltage VGH, and voltage VGL. In the present embodiment, the scan unit 521_1 receives the start signal SP and outputs the second scan signal SB1 to the pixel circuit (e.g., the pixel circuit 210 of fig. 2) and the scan unit 521_2 of the next stage as the start signal of the scan unit 521_ 2. The scan cell 521_2 receives the second scan signal SB1 and outputs the second scan signal SB2 to the pixel circuit and the scan cell 521_3 of the next stage as the start signal of the scan cell 521_ 3. The scan cell 521_3 receives the second scan signal SB2 and outputs the second scan signal SB3 to the pixel circuit and the scan cell 521_4 of the next stage as the start signal of the scan cell 521_ 4. The scan cell 521_4 receives the second scan signal SB3 and outputs the second scan signal SB4 to the pixel circuit and the scan cell 521_5 of the next stage as the start signal of the scan cell 521_ 5. The scan cell 521_5 receives the second scan signal SB4 and outputs the second scan signal SB5 to the pixel circuit and the scan cell 521_6 of the next stage as the start signal of the scan cell 521_ 6. The scanning unit 521_6 receives the second scanning signal SB5 and outputs the first scanning signal SA to the emission circuit 522 and the gate driving circuit of the light emitting unit of the next stage. In contrast, since the gate driving circuit 520 of the present embodiment is integrated with the scanning circuit 521 and the transmitting circuit 522, and the scanning circuit 521 and the transmitting circuit 522 receive the same start signal and the same clock signal, the gate driving circuit 520 of the present embodiment can reduce the number of signal lines or reduce the circuit complexity. In addition, the number of scan cells of the scan circuit of the present disclosure may be determined according to different signal requirements or circuit designs, and is not limited to that shown in fig. 5.

Fig. 6 is a partial routing layout diagram of a light emitting device according to a first embodiment of the disclosure. Each of the light emitting units 110_1 to 110_ P in fig. 1 can be in the form of an integrated chip shown in fig. 6, and the light emitting device 600 of the present embodiment takes 2 × 2

integrated chips

610, 620, 630, and 640 as an example to illustrate the wiring configuration result on the carrier 600A of the light emitting device 600. The integrated chip 610 may be the next stage of the integrated chip 630, the integrated chip 620 may be the next stage of the integrated chip 640, and the

integrated chips

610, 620, 630, and 640 respectively include the scanning circuit and the transmitting circuit as described above. Referring to fig. 6, the integrated chip 610 includes bonding pads (e.g., metal pads) 611 to 618 and light emitting diodes 619_1 to 619_ 3. The integrated chip 620 includes pads 621 to 628 and leds 629_1 to 629_ 3. The integrated chip 630 includes pads 631 to 638 and leds 639_1 to 639_ 3. The integrated chip 640 includes pads 641 to 648 and leds 649_1 to 649_ 3. The light emitting diodes 619_1, 629_1, 639_1, 649_1 may be, for example, red light emitting diodes. The light emitting diodes 619_2, 629_2, 639_2, 649_2 may be, for example, green light emitting diodes. The light emitting diodes 619_3, 629_3, 639_3, 649_3 may be, for example, blue light emitting diodes. In the embodiment, the pad 611 may be a first power pad. The pad 612 may be a second power pad. The pad 613 and the pad 618 can be respectively used for receiving the first clock signal CK1 and the second clock signal CK 2. The pad 614 may be a signal output pad. The pad 615 may be a signal input pad. The pads 616 may be data input pads. The pad 617 may be a third power pad. And 619_1 to 619_3, 629_1 to 629_3, 639_1 to 639_3, 649_1 to 649_3 are provided in the display areas in the

integrated wafers

610, 620, 630, 640, respectively. It should be noted that the number of pads included in each integrated chip, the type of signal corresponding to each pad, and the color and number of the leds are not limited to those shown in fig. 6 and described above.

In the present embodiment, the traces 601 and 601 'are respectively electrically connected to a portion of the

pads

612, 622, 632, 642 of the

integrated chips

610, 620, 630, 640, and the traces 607 and 607' are respectively electrically connected to a portion of the

pads

617, 627, 637, 647 of the

integrated chips

610, 620, 630, 640. The traces 601, 601 'may, for example, provide low voltage power supply signals, and the traces 607, 607' may, for example, provide high voltage power supply signals. As shown in fig. 6, the traces 601, 601 ', 607' do not cross the integrated chip 610 and the integrated chip 620, but are disposed along the peripheral regions of the

integrated chips

610, 620, 630, 640, respectively. In the present embodiment, the traces 602 and 602 'are respectively electrically connected to a portion of the

pads

613, 623, 633 and 643 of the

integrated chips

610, 620, 630 and 640, and the traces 606 and 606' are respectively electrically connected to a portion of the

pads

618, 628, 638 and 648 of the

integrated chips

610, 620, 630 and 640. The traces 602, 602 'may, for example, provide the second clock signal CK2, and the traces 606, 606' may, for example, provide the first clock signal CK 1. The traces 602, 602 ', 606' partially overlap the integrated chip 610 and a small portion of the integrated chip 620, respectively, and most of the traces are still disposed along the peripheral regions of the

integrated chips

610, 620, 630, 640. In the present embodiment, the traces 603 and 603 'are respectively electrically connected to a portion of the

pads

611, 621, 631 and 641 of the

integrated chips

610, 620, 630 and 640, and the traces 605 and 605' are respectively electrically connected to a portion of the

pads

616, 626, 636 and 646 of the

integrated chips

610, 620, 630 and 640. The traces 603, 603 'may, for example, provide another high voltage power supply signal, and the traces 605, 605' may, for example, provide a data signal.

In the present embodiment, the traces 604 are used to electrically connect the signal input pads 615 of the adjacent integrated chips 610 and the signal output pads 634 of the integrated chips 630. The trace 604' is used to electrically connect the signal input pad 625 of the adjacent integrated chip 620 and the signal output pad 644 of the integrated chip 640, so that the

integrated chips

610 and 620 use the scan signal provided by the

integrated chips

630 and 640 as the start signal to drive the internal scan circuit of the integrated chip 610. Similarly, the

pads

635 and 645 of the

integrated chips

630 and 640 respectively receive the scan signal of the previous stage (e.g., the previous integrated chip in a row, not shown), and the

pads

614 and 624 of the

integrated chips

610 and 620 respectively output the scan signal to the next integrated chip (e.g., the next integrated chip in the same row, not shown).

Therefore, in the present embodiment, the traces 601 to 603, 605 to 607, 601 ' to 603 ', 605 ' to 607 ' can be respectively connected in series to a plurality of integrated chips in a row, and the traces 604 and 604 ' are used for respectively electrically connecting the signal input pads and the signal output pads between two adjacent integrated chips. In this embodiment, since the scan signals of the

integrated chips

610, 620, 630, and 640 are provided by the corresponding previous integrated chips, there is no need to provide an external scan signal line electrically connecting all the integrated chips in the same row. The circuit configuration on the carrier 600A can be simplified or the space required for the wiring configuration can be reduced. Also, since the traces 601 to 602, 604, 606 to 607, 601 ' to 602 ', 604 ', 606 ' to 607 ' may be disposed along the peripheral region of the

integrated wafers

610, 620, 630, 640. Therefore, when the light emitting device 600 of the present embodiment is a transparent display device, the layout of the traces shown in fig. 6 can reduce the area occupied by the traces and improve the overall transparency of the light emitting device 600.

In the foregoing embodiments, one gate driving circuit corresponds to only one pixel circuit, and fig. 7A is a circuit diagram illustrating a second embodiment of the disclosure when one gate driving circuit corresponds to a plurality of pixel circuits. Referring to fig. 7A, the light emitting unit 710 includes a substrate 710A, a plurality of pixel circuits P (1,1) to P (m, n), wherein m and n are positive integers, respectively, and a gate driving circuit 712. In the present embodiment, the gate driving circuit 712 can receive the start signal SP, the first clock signal CK1 and the first clock signal CK2 provided by the external system circuit. The gate driving circuit 712 may generate a scan signal and an emission signal according to the start signal SP, the first clock signal CK1 and the first clock signal CK 2. The gate driving circuit 712 may be electrically connected to the scan signal line SL and the emission signal line EL through two output interfaces, respectively, and provides scan signals and emission signals to the pixel circuits P (1,1) to P (m, n) of multiple columns and multiple rows. In this regard, since the gate driving circuit 712 drives the pixel circuits P (1,1) to P (m, n) in a one-to-many manner, the light emitting device using the light emitting unit 710 of the present embodiment can reduce the total number of gate driving circuits or the number of wires in the light emitting device.

Fig. 7B is a circuit diagram of a light emitting unit according to a third embodiment of the disclosure. Similar to fig. 7A, the light emitting unit 720 in fig. 7B includes a substrate 720A, a plurality of pixel circuits P (1,1) to P (m, n), and a gate driving circuit 722. In the present embodiment, the gate driving circuit 722 can receive the start signal SP, the first clock signal CK1 and the first clock signal CK2 provided by the external system circuit. However, unlike fig. 7A, the gate driving circuit 722 may generate a plurality of scan signals and a plurality of emission signals according to the start signal SP, the first clock signal CK1 and the first clock signal CK 2. The gate driving circuit 722 may be electrically connected to the plurality of scan signal lines SL1 to SLn and the plurality of emission signal lines EL1 to ELn through a plurality of output interfaces (e.g., n scan signal output interfaces and n emission signal output interfaces), respectively, to provide a plurality of scan signals and a plurality of emission signals to the plurality of columns and rows of pixel circuits P (1,1) to P (m, n). In this regard, since the gate driving circuit 722 drives the pixel circuits P (1,1) to P (m, n) in a one-to-many manner, the light emitting device using the light emitting unit 720 of the present embodiment can reduce the total number of gate driving circuits or the number of wires in the light emitting device.

Fig. 7C is a circuit diagram of a light emitting unit according to a fourth embodiment of the disclosure. Similar to fig. 7A, the light emitting unit 730 in fig. 7C includes a substrate 730A, a plurality of pixel circuits P (1,1) to P (m, n), and a gate driving circuit 732. In the present embodiment, the gate driving circuit 732 may receive the start signal SP, the first clock signal CK1 and the first clock signal CK2 provided by the external system circuit. Unlike fig. 7A, the gate driving circuit 732 may generate a plurality of scan signals and an emission signal according to the start signal SP, the first clock signal CK1 and the first clock signal CK 2. The gate driving circuit 732 may electrically connect the plurality of scan signal lines SL1 to SLn and the one emission signal line EL through n scan signal output interfaces and one emission signal output interface, respectively, and provide a plurality of scan signals and one emission signal to the pixel circuits P (1,1) to P (m, n) of the plurality of columns and rows. Any two pixel circuits between two adjacent rows of the pixel circuits P (1,1) to P (m, n) may be electrically connected through an additional trace to transmit a transmission signal. In this regard, since the gate driving circuit 732 drives the pixel circuits P (1,1) to P (m, n) in a one-to-many manner, the light emitting device using the light emitting unit 730 of the present embodiment can reduce the total number of gate driving circuits or the number of wires in the light emitting device. It should be noted that the gate driving circuit 732 in the embodiment of fig. 7C may be a circuit that outputs one scan signal and a plurality of emission signals instead. It should be noted that in the embodiments of fig. 7A to 7C, two adjacent pixel circuits in the same column may be electrically connected by a shorter scan signal line and/or a shorter emission signal line. Instead of having the pixel circuits in the same row electrically connected to the same signal line (e.g., the same scan signal line or the same emission signal line), the disclosure is not limited thereto. In some embodiments, the pixel circuits in the same row may be electrically connected to the same signal line.

Fig. 8 is a circuit diagram of a light emitting device according to an embodiment of the disclosure. Referring to fig. 8, a light emitting device 800 includes a plurality of light emitting cells 810 to 840. In the present embodiment, the light emitting device 800 may be, for example, a tiled display, and the light emitting units 810 to 840 are fixed in the light emitting device 800 by, for example, disposing the light emitting units 810 to 840 on a carrier (not shown). The light emitting unit 810 includes a substrate 810A, a gate driving circuit 812, and a plurality of pixel circuits Pa (1,1) to Pa (m, n). The light emitting unit 820 includes a substrate 820A, a gate driving circuit 822, and a plurality of pixel circuits Pb (1,1) to Pb (m, n). The light emitting unit 830 includes a substrate 830A, a gate driving circuit 832, and a plurality of pixel circuits Pc (1,1) to Pc (m, n). The light emitting unit 840 includes a substrate 840A, a gate driving circuit 842, and a plurality of pixel circuits Pd (1,1) to Pd (m, n). In the present embodiment, the arrangement of the scan signal lines and the emission scan lines of the light emitting units 810 to 840 can be as described in the embodiment shown in fig. 7B, but the present disclosure is not limited thereto, and the arrangement of the scan signal lines and the emission scan lines of the light emitting units 810 to 840 can also be as described in the embodiment shown in fig. 7A or fig. 7C.

In the present embodiment, the

gate driving circuits

812, 822, 832, 842 can receive the same first clock signal CK1 and the same second clock signal CK 2. The gate driving circuit 812 of the light emitting unit 810 is electrically connected to the pixel circuits Pa (1,1) to Pa (m, n) and the gate driving circuit 832 of the light emitting unit 830. The gate driving circuit 832 is electrically connected to the pixel circuits Pc (1,1) to Pc (m, n) and a gate driving circuit of a next-stage light emitting unit (not shown). Specifically, the gate driving circuit 812 may receive a start signal SP1 provided by an external system circuit, and the gate driving circuit 812 may generate a first scan signal SA1 and a plurality of second scan signals according to the start signal SP1, the first clock signal CK1 and the second clock signal CK 2. The gate driving circuit 812 may provide the first scan signal SA1 to the gate driving circuit 832, and the gate driving circuit 812 provides a plurality of second scan signals to the pixel circuits Pa (1,1) to Pa (m, n). The gate driving circuit 832 may generate a plurality of second scan signals to the pixel circuits Pb (1,1) to Pb (m, n) according to the first scan signal SA1, the first clock signal CK1, and the second clock signal CK 2. The gate driving circuit 832 may use the first scan signal SA1 provided by the gate driving circuit 812 of the previous stage as the start signal SP3, and the gate driving circuit 832 may then output the first scan signal SA3 to the gate driving circuit of the light emitting unit of the next stage.

In the present embodiment, the gate driving circuit 822 of the light emitting unit 820 is electrically connected to the pixel circuits Pb (1,1) to Pb (m, n) and the gate driving circuit 842 of the light emitting unit 840. The gate driving circuit 842 is electrically connected to the pixel circuits Pc (1,1) to Pc (m, n) and a gate driving circuit of a next-stage light emitting unit (not shown). The gate driving circuit 822 can also receive a start signal SP2 provided by an external system circuit, and the gate driving circuit 822 can generate a first scan signal SA2 and a plurality of second scan signals according to the start signal SP2, the first clock signal CK1 and the second clock signal CK 2. The gate driving circuit 822 may provide a first scan signal SA2 to the gate driving circuit 842, and the gate driving circuit 822 may provide a plurality of second scan signals to the pixel circuits Pb (1,1) to Pb (m, n). The gate driving circuit 842 may generate a plurality of second scan signals to the pixel circuits Pb (1,1) to Pb (m, n) according to the first scan signal SA2, the first clock signal CK1 and the second clock signal CK 2. The gate driving circuit 842 may use the first scan signal SA2 provided by the gate driving circuit 822 of the previous stage as the start signal SP4, and the gate driving circuit 842 may then output the first scan signal SA4 to the gate driving circuit of the next stage of light emitting unit.

Therefore, the light emitting device 800 of the present embodiment can splice the light emitting cells 810 to 840, and the number of scanning signals and the number of traces provided by the external system circuit can be reduced or the circuit configuration of the light emitting device 800 can be simplified by using the first scanning signal output by the gate driving circuit of the previous stage of light emitting cell as the activation signal of the gate driving circuit of the present stage of light emitting cell.

In summary, the light emitting unit in the light emitting device of the present disclosure may use the scan signal output by the scan circuit of the previous light emitting unit as the start signal of the scan circuit of the current light emitting unit, and the scan circuit and the emission circuit of the light emitting unit of the present disclosure may receive the same start signal and/or clock signal, so as to reduce the number of the signal traces or simplify the circuit configuration.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced, or some of the technical features may be combined; such modifications, substitutions or combinations do not depart from the scope of the claims of the present disclosure.

Claims

1. A light-emitting device, comprising:

a carrier plate;

the first light-emitting unit is arranged on the carrier plate and is provided with a first scanning circuit, a first transmitting circuit, a first input end and a first output end; and

a second light emitting unit disposed on the carrier and having a second input end electrically connected to the first output end of the first light emitting unit,

the first scan circuit is used for providing a first scan signal to the first emitting circuit and the second emitting unit.

2. The light-emitting device according to claim 1, wherein the first light-emitting unit further comprises a first pixel circuit.

3. The light-emitting device according to claim 2, wherein the first pixel circuit comprises a plurality of light-emitting diodes of a plurality of colors.

4. The light-emitting device according to claim 2, wherein the first light-emitting unit further comprises a substrate, wherein the first scan circuit, the first emission circuit, and the first pixel circuit are disposed on the substrate, wherein the substrate is disposed on the carrier, and wherein the substrate is electrically connected to the carrier.

5. The light-emitting device according to claim 2, wherein the first scan circuit comprises a plurality of scan cells.

6. The light-emitting device according to claim 5, wherein a part of the plurality of scanning units is configured to generate a plurality of second scanning signals supplied to the first pixel circuit, and wherein a last one of the plurality of scanning units is configured to generate the first scanning signal.

7. The light-emitting device according to claim 1, wherein the first scan circuit and the first transmission circuit receive a same start signal and a same clock signal.

8. The light-emitting device according to claim 1, wherein the light-emitting device is a transparent display device.

9. The light-emitting device according to claim 1, wherein the carrier comprises a pad and a trace, and wherein the first light-emitting unit is electrically connected to the pad and the trace.

10. The light-emitting device according to claim 1, wherein the first light-emitting unit further comprises a plurality of first pixel circuits, wherein the first scan circuit is electrically connected to at least one of the plurality of first pixel circuits, and wherein the first emission circuit is electrically connected to the at least one of the plurality of first pixel circuits and the first scan circuit.