CN115831040A - Pixel island, display device and light field display device - Google Patents

Abstract

The present disclosure provides a pixel island, a display device and a light field display device. The pixel island includes: a driving layer including a power pad, a data pad, a clock pad and a chip select pad, and including a logic processing circuit and a plurality of pixel circuits, the power pad for supplying power to the logic processing circuit and the pixel circuits, the data pad for supplying a data voltage to the pixel circuits, the logic processing circuit for supplying a gate control signal to the pixel circuits according to a clock signal of the clock pad and a chip select signal of the chip select pad; and the sub-pixels are electrically connected with the pixel circuits in a one-to-one correspondence manner.

Description

Pixel island, display device and light field display device

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a pixel island, a display device and a light field display device.

Background

This section is intended to provide a background or context to the embodiments recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

In the related art, a huge number of LED chips are transferred onto a driving backplane, thereby obtaining a display panel for light field display. The transfer and die bonding processes are long in time consumption and low in yield, and the cost of the display panel is high.

Disclosure of Invention

The present disclosure provides a pixel island, a display device and a light field display device.

The present disclosure provides the following technical solutions: a pixel island comprising:

a driving layer including a power pad, a data pad, a clock pad and a chip select pad, and including a logic processing circuit and a plurality of pixel circuits, the power pad for supplying power to the logic processing circuit and the pixel circuits, the data pad for supplying a data voltage to the pixel circuits, the logic processing circuit for supplying a gate control signal to the pixel circuits according to a clock signal of the clock pad and a chip select signal of the chip select pad;

and the sub-pixels are electrically connected with the pixel circuits in a one-to-one correspondence manner.

In some embodiments, the logic processing circuitry is configured to: and sequentially generating gate control signals supplied to the pixel circuits under the excitation of the rising edge and the falling edge of the clock signal supplied by the clock liner in a period in which the chip selection signal is maintained at an effective voltage.

In some embodiments, the plurality of sub-pixels are divided into sub-pixels of a plurality of colors, the sub-pixels of the same color are distributed in the same rectangular region extending along a first direction, the sub-pixels of different colors are arranged along a second direction, and the first direction and the second direction are parallel to the plane where the driving layer is located and intersect in two directions.

In some embodiments, the light emitted by the sub-pixels is collimated light.

In some embodiments, the number of data pads is equal to the number of color types of the sub-pixels, each data pad for receiving a data voltage of a sub-pixel of one color.

In some embodiments, the sub-pixels comprise: an LED.

The present disclosure provides the following technical solutions: a display panel comprises a driving back plate and a plurality of pixel islands, wherein the driving back plate comprises a plurality of power lines, a plurality of chip selection signal lines and clock signal lines which extend along a third direction, and a plurality of data lines which extend along a fourth direction, the third direction and the fourth direction are two directions which are parallel to a plane where the display panel is located and intersect, the power lines are used for providing power supply voltages for power supply pads of the pixel islands, the chip selection signal lines are used for providing chip selection signals for chip selection pads of the pixel islands, the clock signal lines are used for providing clock signals for clock pads of the pixel islands, and the data lines are used for providing data voltages for data pads of the pixel islands.

In some embodiments, in the display panel, the sub-pixels of the same color are distributed in the same rectangular region extending along the third direction, and the sub-pixels of different colors are periodically arranged along the fourth direction.

In some embodiments, one or more data lines are connected to a column of the pixel islands arranged along the fourth direction.

The present disclosure provides the following technical solutions: a display device, comprising: the display panel comprises a source electrode driving chip, a grid electrode driving chip and the display panel, wherein the source electrode driving chip is used for driving the data line, and the grid electrode driving chip is used for driving the chip selection signal line and the clock signal line.

The present disclosure provides the following technical solutions: a light field display device comprising: the display panel comprises a source electrode driving chip, a grid electrode driving chip and the display panel, wherein the source electrode driving chip is used for driving the data line, and the grid electrode driving chip is used for driving the chip selection signal line and the clock signal line; the light field display device further comprises a lens structure arranged on the light emergent surface of the display panel.

In some embodiments of the present disclosure, the process of transferring the single LED chip to the display substrate is replaced with a process of transferring the pixel island to the display substrate. The workload of the transfer process is greatly reduced. Further, the quality inspection of a single LED chip is replaced by the quality inspection of a pixel island, and the pixel island is larger in size and easier to operate. Further, when a single sub-pixel or a pixel circuit of the single sub-pixel is defective, only one pixel island needs to be scrapped or replaced, and the whole display panel does not need to be scrapped. This also contributes to a reduction in the overall manufacturing cost of the display device.

Drawings

Fig. 1 is a top view of a pixel island of an embodiment of the disclosure.

Fig. 2 is a schematic diagram of the distribution of sub-pixels in a single LED chip in the pixel island of fig. 1.

Fig. 3 is a circuit diagram of a drive layer in a pixel island of an embodiment of the disclosure.

Fig. 4 is a cross-sectional view of a pixel island of an embodiment of the disclosure.

Fig. 5 is a schematic connection diagram of a partial structure in a display device according to an embodiment of the disclosure.

Fig. 6 is a driving timing diagram of a pixel island according to an embodiment of the present disclosure.

Fig. 7 is a variation of the drive layer in a pixel island of an embodiment of the disclosure.

Fig. 8 is a schematic structural diagram of a light field display device provided in an embodiment of the present disclosure.

Wherein the reference numerals are: r, red LED chips; G. a green LED chip; B. a blue LED chip; r1 to RN and independently controlled light emitting areas in the red LED chip; VDD, VSS, power supply voltage; RST, EM, gate1, gate2, gate T, gate control signal; c1, capacitance; m1 to M7, transistors; SCS, chip selection signal; CLK, a clock signal; data, data voltage; dataR, red subpixel data voltage; dataG, green subpixel data voltage; dataB, blue sub-pixel data voltage; 1. a base layer; 2. a circuit layer; 3. a sub-pixel; p1, P2, power supply pad; p5, data pad; p3, chip selection gasket; p4, a clock pad; LED1, light emitting diode; l1, a data line; l2, chip selection signal lines; l3, a clock signal line; IC1, source driver chip; IC2, a gate driving chip; I. a pixel island; 200. a lens structure.

Detailed Description

The disclosure will be further described with reference to the embodiments shown in the drawings.

Fig. 1 is a top view of a pixel island of an embodiment of the disclosure. Fig. 2 is a schematic diagram of the distribution of sub-pixels in a single LED chip in the pixel island of fig. 1. Fig. 3 is a circuit diagram of a drive layer in a pixel island of an embodiment of the disclosure. Fig. 4 is a cross-sectional view of a pixel island of an embodiment of the disclosure.

Referring to fig. 1 to 4, an embodiment of the present disclosure provides a pixel island. The pixel island packages or combines the plurality of sub-pixels, the pixel circuits of the plurality of sub-pixels, and the driving circuits of the pixel circuits independently. The display substrate can drive the sub-pixels in the pixel island to be lighted sequentially or simultaneously only by providing a power supply signal, a chip selection signal, a clock signal and a data voltage for the pixel island. The preparation process of the display panel is simplified into the connection process of the pixel island and the display substrate, and the workload of the transfer and die bonding processes is greatly reduced. The workload of detecting the yield of the pixel island is low, and the reliability of the pixel island is stable. This helps to improve the efficiency of display panel manufacture, also helps to improve the yield of display panels.

Referring to fig. 4, the driving layer in the pixel island includes a base layer 1 and a circuit layer 2. The material of the base layer 1 is, for example, a semiconductor material such as silicon, gallium arsenide, or a flexible insulating material such as polyimide. The pixel circuits and the logic processing circuits are disposed in the circuit layer 2. The sub-pixels 3 are, for example, light emitting areas of a single LED chip that can be independently controlled.

Referring to fig. 1, a single red LED chip R has a plurality of independently drivable light-emitting regions, thereby forming a plurality of red subpixels. The single green LED chip G has a plurality of independently drivable light emitting areas, thereby forming a plurality of green sub-pixels. The single blue LED chip B has a plurality of independently drivable light emitting regions, thereby forming a plurality of blue subpixels.

In other embodiments, a single LED chip comprises a single independently controllable light emitting area, i.e. a single LED chip forms one sub-pixel.

A single LED chip is fabricated on the driver layer, for example, by a transfer and die attach process. The pixel islands are then encapsulated. The pixel islands are thus used to prepare the display panel. The pixel islands can also be directly connected to the display substrate without packaging after the single LED chip is transferred to the driving layer. Specifically, the power supply pad, the data pad, the clock pad, the chip select pad and the exposed traces on the display substrate can be electrically connected by a bonding or welding process.

Note that the sub-pixels are not limited to being formed by LED chips. In other embodiments, the sub-pixels in the pixel island may also be formed of organic light emitting diodes or quantum dot light emitting diodes.

The power pad P1 is for receiving a first power voltage VDD, for example, and the power pad P2 is for receiving a second power voltage VSS, for example. The first power supply voltage VDD is, for example, a positive power supply voltage, and the second power supply voltage VSS is, for example, a negative power supply voltage. The power supply pads P1, P2 are used to power the logic processing circuit and the pixel circuit. The number of power pads is not limited to 2. In other embodiments, the pixel circuit also requires a half voltage (the median voltage of the high level supply voltage and the low level supply voltage). Accordingly, the pixel island further includes a pad (not shown in the drawing) receiving a half voltage.

The data pad P5 is used to supply a data voltage to the pixel circuit. The magnitude of the data voltage directly determines the brightness of the sub-pixels driven by the pixel circuit. The logic processing circuit is used for providing gate control signals to the pixel circuit according to the clock signals on the clock pad P4 and the chip selection signals on the chip selection pad P3.

Power supply pads P1, P2, data pads P5, chip select pads P3 and clock pads P4 are provided on the surface of the base layer 1 on the side remote from the circuit layer 2. The power pads P1, P2, the data pad P5, the chip select pad P3, and the clock pad P4 are electrically connected to the circuit layer 2, for example, by vias penetrating the base layer 1. In these embodiments, the light emitting direction of the sub-pixel is, for example, the direction in which the substrate layer 1 points to the circuit layer 2.

In other embodiments, the power pads P1, P2, the data pad P5, the chip select pad P3 and the clock pad P4 are disposed on a surface of the circuit layer 2 on a side away from the base layer 1. The power supply pads P1, P2, the data pad P5, the chip select pad P3 and the clock pad P4 extend beyond the sub-pixel 3, for example in a direction from the substrate layer 1 towards the circuit layer 2. In these embodiments, the light emitting direction of the sub-pixel 3 is, for example, the direction in which the circuit layer 2 points to the substrate layer 1.

The present disclosure does not limit how the sub-pixels and the driving layer are specifically encapsulated and the mechanical design of the power pads, data pads, clock pads and chip select pads.

The plurality of sub-pixels in the pixel island are electrically connected to the pixel circuits in one-to-one correspondence.

The 2 pixel circuits in a pixel island are exemplarily shown in fig. 3. The pixel circuit comprises 7P-type transistors M1 to M7, a capacitor C1 and a light emitting diode LED1. The two ends of the capacitor C1 receive the power voltage and the gate of the connection transistor M1, respectively. The gate of transistor M3 receives the gate control signal EM, the first pole of transistor M3 receives the supply voltage VDD, and the second pole of transistor M3 connects transistor M7 to the first pole of transistor M1. The second pole of the transistor M7 receives the Data voltage Data, and the Gate of the transistor M7 receives the Gate control signals Gate1, gate2. The second pole of transistor M1 is connected to the first pole of transistor M2 and the first pole of transistor M7. The second pole of the transistor M2 is connected to the Gate of the transistor M1, and the Gate of the transistor M2 receives the Gate control signals Gate1 and Gate2. The gate of the transistor M4 receives the gate control signal EM, the second pole of the transistor M4 is connected to the anode of the light emitting diode LED1, and the cathode of the light emitting diode LED1 receives the power supply voltage VSS. The gate of the transistor M5 and the gate of the transistor M6 both receive the gate control signal RST, and the first poles of the transistor M5 and the transistor M6 both receive the power supply voltage VSS. The second pole of the transistor M5 is connected to the gate of the transistor M1. The second pole of the transistor M6 is connected to the anode of the light emitting diode LED1.

Looking at the pixel circuit on the left side of fig. 3, when the gate control signal RST is a low level voltage, one end of the capacitor C1 (i.e., the gate of the transistor M1) is written with the power supply voltage VSS, and the transistor M6 is turned on, and the anode voltage of the light emitting diode LED1 is reset. When the Gate control signal Gate1 is a low level voltage, the corresponding transistor M7 is turned on, and the data voltage is written into the Gate of the transistor M1 after threshold compensation. When the gate control signal EM is a low level voltage, the transistors M3 and M4 are turned on, and the gate voltage of the transistor M1 controls the current of the light emitting diode LED1, thereby controlling the brightness of the light emitting diode LED1.

Looking at the pixel circuit on the right side of fig. 3, when the gate control signal RST is a low level voltage, one end of the capacitor C1 (i.e., the gate of the transistor M1) is written with the power supply voltage VSS, and the transistor M6 is turned on, and the anode voltage of the light emitting diode LED2 is reset. When the Gate control signal Gate2 is a low level voltage, the corresponding transistor M7 is turned on, and the data voltage is written into the Gate of the transistor M1 after threshold compensation. When the gate control signal EM is a low level voltage, the transistors M3 and M4 are turned on, and the gate voltage of the transistor M1 controls the current of the light emitting diode LED1, thereby controlling the brightness of the light emitting diode LED 2.

The transistors in the pixel circuits are all P-type transistors, and the effective voltage of the gate voltage is a low level voltage. In other embodiments, the transistors of the pixel circuit are all N-type transistors, and the effective voltage of the gate voltage is a high level voltage.

The logic processing circuit supplies gate control signals to the respective pixel circuits so that the respective pixel circuits sequentially receive the Data voltages Data.

In some embodiments, the logic processing circuitry is configured to: the gate control signals provided to the pixel circuits are sequentially generated upon activation of the rising and falling edges of the clock signal provided by the clock pad during the period in which the chip select signal is maintained at the active voltage.

In other words, each edge of the clock signal triggers a gate control signal during the period when the chip select signal is maintained at the active voltage. Therefore, the frequency of the clock signal can be properly adjusted to be low by fully utilizing the jump edge information of the clock signal.

In other embodiments, the logic processing circuitry is configured to: the gate control signals provided to the pixel circuits are sequentially generated at the assertion of the rising edge of the clock signal provided by the clock pad during the period that the chip select signal is maintained at the active voltage. The frequency of the clock signal needs to be adjusted to be high appropriately to shorten the data writing time of all the sub-pixels in the pixel island.

The logic processing circuit is configured to: the gate control signals provided to the pixel circuits are sequentially generated upon activation of a falling edge of a clock signal provided by a clock pad during a period in which the chip select signal is maintained at an active voltage. . The frequency of the clock signal needs to be adjusted to be high appropriately to shorten the data writing time of all the sub-pixels in the pixel island.

Fig. 6 is a driving timing diagram of a pixel island according to an embodiment of the present disclosure. In an exemplary embodiment, the operation timing of the logic processing circuit is as follows, in conjunction with fig. 3 and 6.

The high level voltage of the chip selection signal SCS is an effective voltage, and the data voltage required by each sub-pixel in the pixel island is sequentially written into each sub-pixel in the period of the high level voltage of the chip selection signal bit. In the low level voltage period of the chip selection signal SCS, each sub-pixel maintains a light emitting state. The detailed operation timing is as follows.

The voltage of the gate control signal EM supplied to each pixel circuit in the pixel island is set to a high level voltage at the first rising edge of the clock signal CLK after the rising edge of the chip select signal SCS. The transistors M3, M4 in all the pixel circuits in the pixel island are in the off state.

At the timing of the subsequent falling edge of the clock signal CLK, the voltages of the gate control signals RST supplied to the respective pixel circuits in the pixel island are each set to a low-level voltage. The gate voltage of the transistor M1 and the anode voltages of the light emitting diodes LED1, LED2 \8230;, of all the pixel circuits in the pixel island are reset.

At the second rising edge of the clock signal CLK after the rising edge of the chip select signal SCS, the voltages of the gate control signals RST supplied to the respective pixel circuits in the pixel island are all set to a high level voltage.

At the timing of the subsequent falling edge of the clock signal CLK, the Gate control signal Gate1 supplied to the first pixel circuit is set to a low level voltage.

The Gate control signal Gate1 supplied to the first pixel circuit is set to a high level voltage at the third rising edge timing of the clock signal CLK after the rising edge of the chip select signal SCS. In a period in which the Gate control signal Gate1 supplied to the first pixel circuit is maintained at the low level, the transistor M7 in the first pixel circuit is turned on, and the Gate of the transistor M1 of the pixel circuit is written with the threshold-compensated data voltage.

At the subsequent falling edge timing of the clock signal CLK, the Gate control signal Gate2 supplied to the second pixel circuit is set to a low level voltage.

The Gate control signal Gate2 supplied to the first pixel circuit is set to a high level voltage at a fourth rising edge timing of the clock signal CLK after the rising edge of the chip select signal SCS. In a period in which the Gate control signal Gate2 supplied to the second pixel circuit is held at the low level, the transistor M7 in the second pixel circuit is turned on, and the Gate of the transistor M1 of the pixel circuit is written with the threshold-compensated data voltage.

The chip select signal SCS supplied to the pixel island is set to a low-level voltage (in this embodiment, an inactive voltage) at the timing of the falling edge of the first clock signal CLK after the pixel voltage is thus written to all the pixel circuits in the pixel island in sequence, and the gate control signal EM supplied to all the pixel circuits in the pixel island is set to a low-level voltage (in this embodiment, an active voltage), so that all the sub-pixels in the pixel island enter a light-emitting state.

In other embodiments, the logic control circuit lights the sub-pixels in the same pixel island sequentially or in a time-sharing manner. The present disclosure does not limit the timing of the lighting of each sub-pixel in the pixel island.

The specific implementation form of the logic control circuit is not limited in the present disclosure. The circuit form of the logic control circuit can be designed, for example, by means of a state transition diagram. The logic control circuit also comprises a counter and a mapping table, for example. The mapping table records the mapping relationship between the counting result of the counter and the gate control signal received by each pixel circuit. As the count result of the counter increases, the state of the respective gate control signal received by each pixel circuit also changes. Also, for example, the logic control circuit includes a counter and a plurality of arithmetic circuits for obtaining respective gate control signals. Each arithmetic circuit is used to map a particular count result to a particular high state (digital 1) or low state (digital 0).

In some embodiments, the plurality of sub-pixels are divided into sub-pixels of a plurality of colors, the sub-pixels of the same color are distributed in the same rectangular region extending along a first direction, the sub-pixels of different colors are arranged along a second direction, and the first direction and the second direction are parallel to two directions in which the driving layer is located and intersect.

In the embodiment shown in fig. 1, a plurality of red LED chips R are contained in a single pixel island and are uniformly distributed in a rectangular area extending in the first direction. Since the size of the rectangular region in the first direction is limited, the plurality of red LED chips R are arranged in a staggered manner. If the size of the rectangular area in the first direction is sufficiently large, the plurality of red LED chips R are arranged in a row in the first direction.

Referring to fig. 2, N subpixels R1, R2, 823060, 8230rn, RN are integrated in each red LED chip R.

In other embodiments, 1 red LED chip R is included in a single pixel island, and N subpixels R1, R2 \8230; RN are integrated in the red LED chip R.

In other embodiments, a plurality of red LED chips R are contained within a single pixel island, with a single red LED making up one red sub-pixel.

In other embodiments, the subpixels in a single pixel island are organic light emitting diodes or quantum dot light emitting diodes.

In some embodiments, the light emitted by the sub-pixels is collimated light. For example, collimating structures (not shown) may be provided in the pixel islands. The collimating structure is for example a lens structure. The collimating structure is again for example a black matrix. The disclosure does not limit how to control the light emitting direction of the sub-pixels.

In some embodiments, the number of data pads is equal to the number of color types of the subpixels, and each data pad receives a data voltage of a subpixel of one color.

Fig. 7 is a variation of the drive layer in a pixel island of an embodiment of the disclosure. Referring to fig. 7, in these embodiments, the pixel island includes 3 data pads for receiving the data voltage DataR of the red sub-pixel, the data voltage DataG of the green sub-pixel, and the data voltage DataG of the blue sub-pixel, respectively. Accordingly, in the display panel, the pixel islands connect 3 data lines. Such a design may reduce the data writing time of the pixel islands.

Fig. 5 is a schematic connection diagram of a partial structure in a display device according to an embodiment of the disclosure.

Referring to fig. 5, an embodiment of the present disclosure provides a display panel, including a driving backplane P and a plurality of pixel islands I as described above, the driving backplane P includes a plurality of power lines (not shown), a plurality of chip select signal lines L2 and clock signal lines L3 extending along a third direction, and a plurality of data lines L1 extending along a fourth direction, the power lines are used for providing power voltages to power pads of the pixel islands, the third direction and the fourth direction are two directions parallel to a plane in which the display panel is located and intersecting, the chip select signal lines L2 are used for providing chip select signals to chip select pads of the pixel islands, the clock signal lines L3 are used for providing clock signals to clock pads of the pixel islands, and the data lines L1 are used for providing data voltages to data pads of the pixel islands.

Specifically, in the embodiment shown in fig. 5, the third direction is perpendicular to the fourth direction. The pixel islands I are arranged in an array along a third direction and a fourth direction.

The data line L1 extends in the fourth direction, which means that the entire segment of the data line L1 excluding the segment of the fan-out area extends in the fourth direction. The data line L1 is, for example, a straight line trace, or, for example, a serpentine trace except for the fan-out section.

The top view boundary of the pixel island I is not limited to a rectangular shape. In other embodiments, the top view boundaries of pixel island I are, for example, regular hexagons.

In some embodiments, in the display panel, the sub-pixels of the same color are distributed in the same rectangular region extending along the third direction, and the sub-pixels of different colors are periodically arranged along the fourth direction.

In other words, the first direction in fig. 1 is the same direction as the third direction in fig. 5. Specifically, in the display panel shown in fig. 5, the red LED chips R in a row of pixel islands arranged in the third direction are distributed within a rectangular region extending in the third direction; the LED chips G of the row of the pixel islands arranged along the third direction are distributed in a rectangular area extending along the third direction; the blue LED chips B in a row of pixel islands arranged in the third direction are distributed within a rectangular area extending in the third direction. In the display panel shown in fig. 5, the red sub-pixel, the green sub-pixel and the blue sub-pixel are periodically arranged along the fourth direction.

In addition, the arrangement of the pixel islands in the display panel is not particularly limited in the present disclosure.

In the display panel of some embodiments of the present disclosure, when the refresh frequency is 60Hz, the data writing time of all the pixel islands should be less than 16.67ms. Each LED chip R, G or B includes Q sub-pixels, and has Q data writing periods. The period of writing data is limited by the low-temperature polysilicon process level and is 0.8us at the shortest. It is assumed that the pixel island includes one red LED chip R, one blue LED chip G, and one green LED chip B, and thus the pixel island is set to have one data pad. Then the data write time for one pixel island is 3 × q × 0.8us. If M rows of pixel islands arranged in the third direction are set in the display panel, the total data writing time of the display panel is 3 × q × M × 0.8us. 3 × q × m 0.8us < 16.67ms should be satisfied. This limits the resolution of the display panel.

To improve the resolution of the display panel, in some embodiments, a plurality of data pads may be disposed in the pixel islands. Correspondingly, a column of pixel islands arranged along the fourth direction in the display panel are correspondingly connected with a plurality of data lines.

Referring to fig. 5, based on the same inventive concept, an embodiment of the present disclosure also provides a display apparatus including: the display panel comprises a source driving chip IC1, a gate driving chip IC2 and the display panel P, wherein the source driving chip IC1 is used for driving a data line L1 in the display panel P, and the gate driving chip IC2 is used for driving a chip selection signal line L2 and a clock signal line L8.

The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Fig. 8 is a schematic structural diagram of a light field display device provided in an embodiment of the present disclosure.

Referring to fig. 8, based on the same inventive concept, embodiments of the present disclosure also provide a light field display apparatus including: the display panel comprises a source driving chip IC1, a gate driving chip IC2 and the display panel, wherein the source driving chip IC1 is used for driving a data line L1, and the gate driving chip IC2 is used for driving a chip selection signal line L2 and a clock signal line L3; the light field display device further comprises a lens structure 200 disposed on the light exit surface of the display panel P.

One lens structure 200 in a light field display device is exemplarily shown in fig. 8. The plurality of lens structures 200 respectively cover a column of pixel islands I arranged in the fourth direction.

The design of the lens structure 200 is not limited in the present disclosure, and those skilled in the art can set the design according to the conventional design of the light field display device.

The embodiments in the disclosure are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments.

The scope of the present disclosure is not limited to the above-described embodiments, and it is apparent that various modifications and variations can be made to the present disclosure by those skilled in the art without departing from the scope and spirit of the present disclosure. It is intended that the present disclosure also cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (11)

1. A pixel island, comprising:

a driving layer including a power pad, a data pad, a clock pad and a chip select pad, and including a logic processing circuit and a plurality of pixel circuits, the power pad for supplying power to the logic processing circuit and the pixel circuits, the data pad for supplying a data voltage to the pixel circuits, the logic processing circuit for supplying a gate control signal to the pixel circuits according to a clock signal of the clock pad and a chip select signal of the chip select pad;

and the sub-pixels are electrically connected with the pixel circuits in a one-to-one correspondence manner.

2. The pixel island of claim 1, wherein the logic processing circuitry is configured to: and sequentially generating gate control signals supplied to the pixel circuits under the excitation of the rising edge and the falling edge of the clock signal in a period in which the chip selection signal is maintained at an effective voltage.

3. The pixel island of claim 1, wherein the plurality of sub-pixels are divided into sub-pixels of a plurality of colors, the sub-pixels of one color are distributed in a same rectangular region extending along a first direction, and the sub-pixels of different colors are arranged along a second direction, and the first direction and the second direction are parallel to and intersect with a plane in which the driving layer is located.

4. The pixel island of claim 1, wherein the light emitted by the sub-pixels is collimated light.

5. The pixel island of claim 2, wherein the number of data pads is equal to the number of color types of the subpixels, each data pad for receiving a data voltage of a subpixel of one color.

6. The pixel island of claim 1, wherein the sub-pixels comprise: an LED.

7. A display panel comprising a plurality of pixel islands according to any one of claims 1 to 6 and a driving backplane, wherein the driving backplane comprises a plurality of power lines for supplying power supply voltages to power supply pads of the pixel islands, a plurality of chip select signal lines and clock signal lines extending in a third direction, the third direction and the fourth direction being two directions parallel to a plane in which the display panel is located and intersecting, the chip select signal lines being for supplying chip select signals to chip select pads of the pixel islands, the clock signal lines being for supplying clock signals to clock pads of the pixel islands, and a plurality of data lines extending in a fourth direction, the data lines being for supplying data voltages to data pads of the pixel islands.

8. The display panel according to claim 7, wherein the sub-pixels of the same color are distributed in the same rectangular area extending along the third direction, and the sub-pixels of different colors are periodically arranged along the fourth direction.

9. The display panel according to claim 7, wherein one or more data lines are connected to a column of the pixel islands arranged along the fourth direction.

10. A display device, comprising: a source driver chip for driving the data lines, a gate driver chip for driving the chip select signal lines and the clock signal lines, and the display panel according to any one of claims 7 to 9.

11. A light field display device, comprising: a source driver chip for driving the data lines, a gate driver chip for driving the chip select signal lines and the clock signal lines, and the display panel according to any one of claims 7 to 9; the light field display device further comprises a lens structure arranged on the light emergent surface of the display panel.

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