CN113035927B

CN113035927B - Display substrate and display device

Info

Publication number: CN113035927B
Application number: CN202110259196.6A
Authority: CN
Inventors: 向炼; 冯佑雄
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-03-10
Filing date: 2021-03-10
Publication date: 2024-03-05
Anticipated expiration: 2041-03-10
Also published as: CN113035927A

Abstract

The disclosure provides a display substrate and a display device, belongs to the technical field of display, and can solve the problem that ELVSS power supply wiring has larger current density at corners in the existing display substrate. The display substrate of the present disclosure includes: comprising the following steps: the display device comprises a substrate base plate, a display area and a non-display area surrounding the display area, wherein the non-display area comprises a binding area, a first wiring area, a second wiring area and a third wiring area, the binding area is opposite to the first wiring area, and the second wiring area is opposite to the third wiring area; a light emitting device located in the display region and formed on the substrate; a first power line located in the non-display region and configured to supply a first power voltage to a cathode of the light emitting device; the first power line comprises a power line segment, and the power line segment is arranged in at least one of the second wiring area and the third wiring area; the line width of the power line segment monotonically increases along the direction of the first wiring area pointing to the binding area.

Description

Display substrate and display device

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a display substrate and a display device.

Background

In the conventional display device, ELVDD power supply wirings are arranged in a grid shape, and the ELVSS power supply wirings are lapped to the cathode of the OLED device through peripheral metal wires, which can be equivalently in a grid shape. The OLED is driven to emit light by a driving current of a driving thin film field effect transistor (thin film transistor, TFT) which flows from a power supply positive voltage VVDD to a power supply negative voltage VVSS. Because the ELVSS power trace has a large current density at the corner, the heating at this location is severe, which burns the organic film layers above and below the ELVSS power trace, resulting in poor products.

Disclosure of Invention

The present disclosure is directed to at least solving one of the technical problems in the prior art, and provides a display substrate and a display device.

In a first aspect, an embodiment of the present disclosure provides a display substrate, including:

the display device comprises a substrate base plate, a first display area, a second display area and a third display area, wherein the substrate base plate comprises a display area and a non-display area surrounding the display area, the non-display area comprises a binding area, a first wiring area, a second wiring area and a third wiring area, the binding area is opposite to the first wiring area, and the second wiring area is opposite to the third wiring area;

a light emitting device located in the display region and formed on the substrate;

a first power line located in the non-display region and configured to provide a first power voltage to a cathode of the light emitting device; the first power line comprises a power line segment, and the power line segment is arranged in at least one of the second wiring area and the third wiring area; wherein,

the line width of the power line segment monotonically increases along the direction of the first routing area pointing to the binding area.

Optionally, the display substrate further includes:

a plurality of pixel unit groups arranged side by side along the direction of the first routing area pointing to the binding area, wherein each pixel unit group comprises a plurality of rows of pixel units arranged side by side along the direction of the first routing area pointing to the binding area;

the control circuits are arranged side by side to form a plurality of control circuit groups corresponding to the pixel unit groups, and the number of the control circuits in the control circuit groups is singly reduced in the direction of pointing to the binding area along the first wiring area.

Optionally, the number of control circuits in the at least partially adjacently disposed control circuit groups is the same.

Optionally, the plurality of control circuit groups are divided into a plurality of control circuit units, and the number of control circuits in each control circuit group in the same control circuit unit is the same; wherein the number of the control circuit groups in different control circuit units is the same.

Optionally, the plurality of control circuit groups are divided into a plurality of control circuit units, and the number of control circuits in each control circuit group in the same control circuit unit is the same; wherein the number of the control circuits in the control circuit groups of the different control circuit units is different.

Optionally, the control circuit includes at least one or more of a gate driving circuit, a reset control circuit, and a light emission control circuit.

Optionally, the second wiring area and the third wiring area are both provided with the power line segments, and the power line segments are electrically connected with the cathode of the light emitting device.

Optionally, the first wire region is also provided with a power line segment, and the power line segment of the first wire region is electrically connected with the power line segments in the second wire region and the third wire region.

Optionally, the light emitting device comprises at least one of an OLED, mini-OLED or Micro-OLED.

In a second aspect, an embodiment of the present disclosure provides a display device including the display substrate described above.

Drawings

FIG. 1 is a schematic diagram of an exemplary display substrate;

FIG. 2 is a circuit diagram of an exemplary pixel circuit;

FIG. 3 is a schematic diagram of an exemplary lighting control circuit;

FIG. 4 is a schematic diagram of an exemplary gate drive circuit;

FIG. 5 is a circuit diagram of an exemplary first shift register E;

FIG. 6 is a circuit diagram of an exemplary second shift register G;

fig. 7 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure;

fig. 8 is a schematic structural diagram of another display substrate according to an embodiment of the disclosure;

fig. 9 is a schematic structural diagram of a display substrate according to another embodiment of the disclosure;

FIG. 10 is a schematic diagram of a control circuit arrangement of the display substrate shown in FIG. 9;

FIG. 11 is a schematic diagram of another control circuit arrangement of the display substrate shown in FIG. 9;

fig. 12 is a schematic diagram of another control circuit arrangement of the display substrate shown in fig. 9.

Detailed Description

In order that those skilled in the art will better understand the technical solutions of the present disclosure, the present disclosure will be described in further detail with reference to the accompanying drawings and detailed description.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The light emitting device in the display substrate described below may be specifically at least one of an OLED, a mini-OLED, or a Micro-OLED or other kinds of light emitting devices, and the OLED is exemplified in the related art and in the various embodiments of the present disclosure.

It should be noted that, in the implementation of the present disclosure, the meaning of "monotonically increasing" means gradually increasing in a specific direction, and no decrease occurs during the increasing process, for example, gradually increasing by a specific value in a specific direction, or increasing in a gradient in a specific direction, etc.

Fig. 1 is a schematic structural view of an exemplary display substrate, as shown in fig. 1, the display substrate having a display area A1 and a non-display area A2 surrounding the display area A1, the non-display area A2 including a bonding area A3, the display substrate including: a substrate (not shown), a plurality of gate lines, a plurality of data lines on the substrate, the plurality of gate lines and the plurality of data lines being disposed to cross each other, and a plurality of pixel units each including a pixel circuit and an OLED light emitting device at the display area A1 being defined at the crossing positions. Fig. 2 is a circuit diagram of an exemplary pixel circuit, and as shown in fig. 2, the pixel driving circuit may include: the driving transistor T3, the data writing transistor T4, the threshold compensating transistor T2, the first light emitting control transistor T5, the second light emitting control transistor T6, the first reset transistor T1, the second reset transistor T7, and the storage capacitor Cst. The drain electrode of the Data writing transistor T4 is electrically connected with the source electrode of the driving transistor T3, the source electrode of the Data writing transistor T4 is configured to be electrically connected with the Data line Data to receive a Data signal, and the grid electrode of the Data writing transistor T4 is configured to be electrically connected with the scanning line Gate to receive a grid electrode driving signal; the first polar plate of the storage capacitor Cst is electrically connected with the first power supply voltage end ELVDD, and the second polar plate of the storage capacitor Cst is electrically connected with the grid electrode of the driving transistor T3; the source of the threshold compensation transistor T2 is electrically connected with the drain of the driving transistor T3, the drain of the threshold compensation transistor T2 is electrically connected with the Gate of the driving transistor T3, and the Gate of the threshold compensation transistor T2 is configured to be electrically connected with the scan line Gate to receive the compensation control signal; the source of the first Reset transistor T1 is configured to be electrically connected to the initialization signal terminal Vinit to receive an initialization signal, the drain of the first Reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the first Reset transistor T1 is configured to be electrically connected to the first Reset control signal line Reset to receive a Reset control signal; the source electrode of the second reset transistor T7 is configured to be electrically connected to the initialization signal terminal Vinit to receive the initialization signal, the drain electrode of the second reset transistor T7 is electrically connected to the first electrode of the OLED light emitting device D, and the Gate electrode of the second reset transistor T7 is configured to be electrically connected to the scan line Gate to receive the scan signal; the source of the first light emitting control transistor T5 is electrically connected to the first power supply voltage terminal ELVDD, the drain of the first light emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light emitting control transistor T5 is configured to be electrically connected to the light emitting control signal line EM to receive the light emitting control signal; the source of the second light emission control transistor T6 is electrically connected to the drain of the driving transistor T3, the drain of the second light emission control transistor T6 is electrically connected to the first electrode of the OLED light emitting device D, and the gate of the second light emission control transistor T6 is configured to be electrically connected to the light emission control signal line EM to receive the light emission control signal; the second electrode of the OLED light emitting device D is electrically connected to the second power voltage terminal ELVSS. The OLED light emitting device may emit light under the voltage driving between the first power voltage terminal ELVDD and the second power voltage terminal ELVSS, thereby realizing a display function. However, it should be noted that the pixel circuit is not limited to the exemplary architecture shown in fig. 2, and more transistors or capacitors may be included in the pixel circuit.

With continued reference to fig. 1, ELVSS power trace 1 is also schematically illustrated in fig. 1, where ELVSS power trace 1 is also referred to as a common power trace, ELVSS power trace 1 is disposed in non-display area A2, and ELVSS power trace 1 extends to bonding area A3 along an outer side of non-display area A2, and is connected to a driving chip (not shown in the figure) in bonding area A3. The ELVSS power trace 1 is also connected to the cathode of the OLED light emitting device in its vicinity for transmitting a second power voltage signal ELVSS to the cathode of the OLED light emitting device. Under this design, the current flowing through all the OLED light emitting devices in the display area A1 will be converged to the ELVSS power trace 1 by the cathode and finally flow back to the bonding area A3, and it can be found that the current of the ELVSS power trace 1 at the corner is most concentrated (see the dotted line circled portion in fig. 1), and the ELVSS power trace 1 has a larger current density at the corner, so that the heating at this location is serious, and the organic film layers above and below the ELVSS power trace 1 are burned, thereby causing poor products.

In order to solve the technical problem that the ELVSS power supply trace 1 in the related art has the most concentrated current at the corner, which causes serious heating at the corner, so that the organic film layers on the ELVSS power supply trace 1 are burned, and the product is bad, the embodiments of the present disclosure provide a display substrate and a display device. The display substrate and the display device provided by the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and detailed description.

The control circuit related to the embodiments of the present disclosure will be described before describing the embodiments of the present disclosure, where the control circuit includes, but is not limited to, one or more of a gate driving circuit, a reset control circuit, and a light emission control circuit, and in the embodiments of the present disclosure, the control circuit includes a plurality of gate driving circuits, a plurality of reset control circuits, and a plurality of light emission control circuits. Each light-emitting control circuit comprises a plurality of cascaded first shift register units, and each first shift register unit is used for providing light-emitting control signals for light-emitting control signal lines; each gate driving circuit comprises a plurality of cascaded second shift register units, and each second shift register unit is used for providing scanning signals for one row of scanning lines; each reset control circuit comprises a plurality of cascaded third shift register units, each third shift register unit is used for providing a reset signal for a reset control signal line, and the third shift register units can be of the same structure as the second shift units, so that the description is not repeated here.

For clarity of description of the specific structure in the embodiments of the present disclosure, a schematic diagram of an exemplary light emission control circuit (fig. 3) and a schematic diagram of an exemplary gate driving circuit (fig. 4) are given below. As shown in fig. 3, the light emission control circuit includes a plurality of cascaded first shift registers E, where the first shift registers E in the light emission control circuit are connected to the light emission control lines in a one-to-one correspondence manner, and are used to provide light emission control signals, and a first signal output end of a first shift register E1 of a present stage is connected to a first signal input end of a first shift register E2 of a next stage; in addition, the first signal INPUT terminal INPUT1 of the first shift register E1 is connected to the first frame start signal STV1. As shown in fig. 4, the gate driving circuit includes a plurality of cascaded second shift registers G. The second shift registers G in the grid driving circuit are connected with the scanning lines in a one-to-one correspondence manner and are used for providing scanning signals, and the second signal output end of the first stage second shift register G1 is connected with the second signal input end of the next stage second shift register G2; in addition, the second signal INPUT terminal INPUT2 of the second shift register G2 is connected to the first frame start signal STV1.

Fig. 5 is a circuit schematic diagram of an exemplary first shift register E, which includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, a seventh transistor M7, an eighth transistor M8, a second capacitor C2, a ninth transistor M9, a tenth transistor M10, and a third capacitor C3, as shown in fig. 5. The gate of the first transistor M1 is connected to the first clock signal terminal CK, the source of the first transistor M1 is connected to the first signal INPUT terminal INPUT1, and the drain of the first transistor M1 is connected to the first node N1. The gate of the second transistor M2 is connected to the first node N1, the source of the second transistor M2 is connected to the first clock signal terminal CK, and the drain of the second transistor M2 is connected to the second node N2. The gate of the third transistor M3 is connected to the first clock signal terminal CK, the source of the third transistor M3 is connected to the first power source terminal VGH, and the drain of the third transistor M3 is connected to the second node N2. The gate of the fourth transistor M4 is connected to the second node N2, the source of the fourth transistor M4 is connected to the second clock signal terminal CKB, and the drain of the fourth transistor M4 is connected to the source of the fifth transistor M5. The gate of the fifth transistor M5 is connected to the second clock signal terminal CLKB, and the drain of the fifth transistor M5 is connected to the third node N3. The gate of the sixth transistor M6 is connected to the first node N1, the source of the sixth transistor M6 is connected to the second power supply terminal VGL, and the drain of the sixth transistor M6 is connected to the third node N3. The first electrode plate of the first capacitor C1 is connected to the second node N2, and the second electrode plate of the first capacitor C1 is connected to the drain electrode of the fourth transistor M4. The gate of the seventh transistor M7 is connected to the third node N3, the source of the seventh transistor M7 is connected to the second power supply terminal VGL, and the drain of the seventh transistor M7 is connected to the first signal output terminal OUT 1. The gate of the eighth transistor M8 is connected to the first node N1, the source of the eighth transistor M8 is connected to the first power source terminal VGH, and the drain of the eighth transistor M8 is connected to the first signal output terminal OUT 1. The first polar plate of the second capacitor C2 is connected with the third node, and the second polar plate of the second capacitor C2 is connected with the first power end VGH.

Fig. 6 is a circuit schematic diagram of an exemplary second shift register G, as shown in fig. 6, which includes: an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, an eighteenth transistor T18, a fourth capacitor C4, a fifth capacitor C5, a sixteenth transistor T16, and a seventeenth transistor T17. The gate of the eleventh transistor T11 is connected to the third clock signal terminal CLK', the source of the eleventh transistor T11 is connected to the second signal input terminal IPUT2, and the drain of the eleventh transistor T11 is connected to the pull-up node PU. The gate of the twelfth transistor T12 is connected to the pull-up node PU, the source of the twelfth transistor T12 is connected to the third clock signal terminal CLK', and the drain of the twelfth transistor T12 is connected to the pull-down node PD. The gate of the thirteenth transistor T13 is connected to the third clock signal terminal CLK', the source of the thirteenth transistor T13 is connected to the second power supply terminal VGL, and the drain of the thirteenth transistor T13 is connected to the pull-down node PD. The gate of the fourteenth transistor T14 is connected to the pull-down node PD, the source of the fourteenth transistor T14 is connected to the first power supply terminal VGH, and the drain of the fourteenth transistor T14 is connected to the second signal output terminal OUT 2. The gate of the fifteenth transistor T15 is connected to the pull-up node PU, the source of the fifteenth transistor T15 is connected to the fourth clock signal terminal CLKB', and the drain of the fifteenth transistor T15 is connected to the second signal output terminal OUT 2. The gate of the sixteenth transistor T16 is connected to the pull-down node PD, the source of the sixteenth transistor T16 is connected to the first power supply terminal VGH, and the drain of the sixteenth transistor T16 is connected to the source of the seventeenth transistor T17. The gate of the seventeenth transistor T17 is connected to the fourth clock signal terminal CLKB', and the drain of the seventeenth transistor T17 is connected to the pull-up node PU. The gate of the eighteenth transistor T18 is connected to the second power supply terminal VGL, the source of the eighteenth transistor T18 is connected to the pull-up node PU, and the drain of the eighteenth transistor T18 is connected to the gate of the fifteenth transistor T15. The first electrode of the fourth capacitor C4 is connected to the gate of the fifteenth transistor T15, and the second electrode of the fourth capacitor C4 is connected to the second signal output terminal OUT 2. A first plate of the fifth capacitor C5 is connected to the pull-down node PD, and a second plate of the fifth capacitor C5 is connected to the source of the fourteenth transistor T14.

In a first aspect, the disclosure provides a display substrate, and fig. 7 is a schematic structural diagram of a display substrate provided in an embodiment of the disclosure, and as shown in fig. 7, the display substrate includes a substrate (not shown in the drawing), an OLED light emitting device (not shown in the drawing), and a first power line 31. The substrate comprises a display area A1 and a non-display area A2 surrounding the display area A1, wherein the non-display area A2 comprises a binding area A3, a first wiring area, a second wiring area and a third wiring area, the binding area A3 is opposite to the first wiring area, and the second wiring area is opposite to the third wiring area. As shown in fig. 7, the second routing area and the third routing area are located at the left and right sides of the display area A1, the first routing area is located at the upper side of the display area A1, the binding area A3 is opposite to the first routing area and is located at the lower side of the display area A1, and it should be noted that the specific routing area may be set according to specific situations, which is not limited herein. The OLED light emitting device is located in the display area A1 and formed on the substrate. The first power line 31 located in the non-display area A2 is configured to supply a first power voltage to the cathode of the OLED light emitting device. The first power line 31 includes a power line segment, and at least one of the second routing area and the third routing area (i.e. the non-display areas on the left and right sides of the display area) is provided with a power line segment, where the line width of the power line segment monotonically increases along the direction of the first routing area pointing to the binding area. In this embodiment, the first power line 31 is located in the second routing area.

In the present embodiment, the first power line 31 is located in the second routing area, and the line widths of the first power line 31 are monotonically increased along the direction of the first routing area pointing to the bonding area, i.e. the first power line 31 gradually widens along the direction of the first routing area pointing to the bonding area. By setting the first power line 31 to monotonically increase in a direction in which the first routing region points to the bonding region, the resistance of the first power line 31 is reduced, thereby reducing the voltage drop (IR drop) generated by the power supply voltage on the first power line 31, reducing the current density of the first power line 31 at the corner, thereby reducing power consumption and improving product quality.

It should be noted that, the first power line 31 may be disposed only in the third wiring area, and the shape of the first power line disposed in the third wiring area may be the same as the shape and the wiring manner of the first power line 31 in the above embodiment, which is not described herein.

In some embodiments, fig. 8 is a schematic structural diagram of another display substrate provided in this disclosure, as shown in fig. 8, a first power line 41 includes a first power line segment 411 and a second power line segment 412, the first power line segment 411 is disposed in a second wiring area, the second power line segment 412 is disposed in a third wiring area, the first power line segment 411 and the second power line segment 412 are electrically connected with a cathode of a light emitting device, and line widths of the first power line segment 411 and the second power line segment 412 are monotonically increased along a direction of the first wiring area pointing to the binding area, i.e., the first power line segment 411 gradually widens along a direction of the first wiring area pointing to the binding area, and the second power line segment 412 gradually widens along a direction of the first wiring area pointing to the binding area. By arranging the power supply line 41 to increase monotonically in the direction of the first routing area towards the binding area, i.e. the resistance of the first power supply line 41 is reduced, thereby reducing the voltage drop (IR drop) generated by the power supply voltage on the first power supply line 41, reducing the current density of the first power supply line 41 at the corners, thereby reducing the power consumption and improving the product quality.

In some embodiments, fig. 9 is a schematic structural diagram of still another display substrate provided in an embodiment of the disclosure, and as shown in fig. 9, the first power line 51 includes a first power line segment 511, a second power line segment 512 and a third power line segment 513. The first power line segment 511 is disposed in the second routing area, the second power line segment 512 is disposed in the third routing area, the third power line segment 513 is disposed in the first routing area, the third power line segment 513 is electrically connected to the first power line segment 511 and the second power line segment 512, and the first power line segment 511, the second power line segment 512 and the third power line segment 513 are all electrically connected to the cathode of the light emitting device.

In the present embodiment, by setting the line widths of the first power line segment 511 and the second power line segment 512 to monotonically increase in the direction in which the first routing region points to the bonding region, the resistance of the first power line 51 is reduced, thereby reducing the voltage drop (IR drop) generated by the power supply voltage on the first power line 51, reducing the current density of the first power line 51 at the corner, thereby reducing the power consumption, and improving the display quality.

It should be noted that, the first power line segment 511, the second power line segment 512 and the second power line segment 513 may be in a split structure or an integrated structure, and preferably, in this embodiment, the first power line segment 511, the second power line segment 512 and the second power line segment 513 are in an integrated structure, and the first power line segment 511, the second power line segment 512 and the second power line segment 513 are designed into an integrated structure, so that in the process of preparing the power line, the process steps are reduced, and the production cost is saved.

With continued reference to fig. 9, the display substrate further includes a control circuit area A4 disposed in the second wiring area and/or the third wiring area, and the control circuit area A4 is located between the first power line and the display area. A plurality of control circuits (for example, a pixel driving circuit, a light-emitting control circuit, a reset control circuit and the like) are arranged in the control circuit area A4, each control circuit provides control signals for a plurality of rows of pixel units, the number of the control circuits in the control circuit group is singly regulated and reduced along the direction of the first wiring area pointing to the binding area, namely, the singly regulated and reduced direction of the number of the control circuits is opposite to the monotonically increasing direction of the first power supply line 51, and the purpose of doing so is to provide space for wiring of the first power supply line 51, so that the width of the first power supply line 51 can be monotonically increased in the second wiring area and the third wiring area. Further, by setting the power supply line 51 to monotonically increase in a direction in which the first routing region points to the bonding region, a voltage drop (IR drop) generated by the power supply voltage on the first power supply line 51 is reduced, a current density of the first power supply line 51 at a corner is reduced, power consumption is reduced, and product quality is improved.

Fig. 10 to 12 show three arrangements of control circuits in a display substrate, and are described below in connection with specific embodiments. It should be understood that the arrangement of the control circuits in the display substrate according to the embodiment of the present disclosure is not limited to the three types shown in fig. 10 to 12, and may be specifically defined according to the size of the non-display area. The following embodiments are described by taking the display substrate having 720 rows of pixel units as an example, and of course, the display substrate may also include a structure not limited to 720 rows of pixel units and a driving circuit structure corresponding to the 720 rows of pixel units, and other display substrates are all within the protection scope of the present disclosure.

In some embodiments, the number of control circuits in at least some adjacently disposed groups of control circuits is the same. For example, fig. 10 is a schematic diagram of a control circuit arrangement manner of the display substrate shown in fig. 9, and as shown in fig. 8, the light emission control circuit E2, the light emission control circuit E6, the reset control circuit R6, and the gate driving circuit G6 form a first control circuit group corresponding to the pixel unit group (601 to 720 rows); the light emission control circuit E1, the light emission control circuit E5, the reset control circuit R5, and the gate drive circuit G5 form a second control circuit group provided corresponding to the pixel cell group (481 to 600 rows); the reset control circuit R2, the light emission control circuit E4, the reset control circuit R4, and the gate drive circuit G4 form a third control circuit group provided corresponding to the pixel cell group (361 to 480 rows); the light emission control circuit E3, the reset control circuit R3, and the gate drive circuit G5 form a fourth control circuit group provided corresponding to the pixel cell group (241 to 360 rows); the reset control circuit R2 and the gate drive circuit G2 form a fifth control circuit group provided corresponding to the pixel cell group (121 to 240 rows); the gate driving circuit G1 forms a sixth control circuit group provided corresponding to the pixel cell group (1 to 120 rows). Wherein the number of control circuits in the first control circuit group, the second control circuit group and the third control circuit group is the same. In this embodiment, through the structural design of the control circuit, a space is provided for the routing of the first power line 51, so that the width of the first power line 51 can be monotonically increased in the first routing area and the second routing area. Further, by setting the power supply line 51 to monotonically increase in a direction in which the first routing region points to the bonding region, a voltage drop (IR drop) generated by the power supply voltage on the first power supply line 51 is reduced, a current density of the first power supply line 51 at a corner is reduced, power consumption is reduced, and display quality is improved.

In some embodiments, the plurality of control circuit groups are divided into a plurality of control circuit units, and the number of control circuits in each control circuit group in the same control circuit unit is the same; wherein the number of control circuits in the control circuit groups of the different control circuit units is different.

For example, fig. 11 is a schematic diagram of another arrangement mode of control circuits of the display substrate shown in fig. 9, and as shown in fig. 9, a light-emitting control circuit E6, a light-emitting control circuit E5, a light-emitting control circuit E4, a reset control circuit R6, a reset control circuit R5, and a gate driving circuit G6 form a first control circuit group corresponding to the pixel unit group (601 to 720 rows); the light emission control circuit E3, the light emission control circuit E2, the light emission control circuit E1, the reset control circuit R4, the reset control circuit R3, and the gate drive circuit G5 form a second control circuit group provided corresponding to the pixel cell group (481 to 600 rows); the reset control circuit R2 and the gate drive circuit G4 form a third control circuit group provided corresponding to the pixel cell group (361 to 480 rows); the reset control circuit R1 and the gate drive circuit G3 form a fourth control circuit group provided corresponding to the pixel cell group (241 to 360 rows); the gate driving circuit G2 forms a fifth control circuit group provided corresponding to the pixel cell group (121 to 240 rows); the gate driving circuit G1 forms a sixth control circuit group provided corresponding to the pixel cell group (1 to 120 rows). The first control circuit group and the second control circuit group are first control circuit units, the third control circuit group and the fourth control circuit group are second control circuit units, and the fifth control circuit group and the sixth control circuit group are third control circuit units. The number of the control circuits in the first control circuit unit is the same as that of the control circuits in the first control circuit unit and the second control circuit unit, the number of the control circuits in the third control circuit unit and the fourth control circuit unit is the same as that of the control circuits in the fifth control circuit unit and the sixth control circuit unit.

In this embodiment, through the structural design of the control circuit, a space is provided for the routing of the first power line 51, so that the width of the first power line 51 can be monotonically increased in the first routing area and the second routing area. Further, by setting the power supply line 51 to monotonically increase in a direction in which the first routing region points to the bonding region, a voltage drop (IR drop) generated by the power supply voltage on the first power supply line 51 is reduced, a current density of the first power supply line 51 at a corner is reduced, power consumption is reduced, and display quality is improved.

In some embodiments, the number of control circuits in at least some adjacently disposed groups of control circuits is the same. Specifically, the plurality of control circuit groups are divided into a plurality of control circuit units, and the number of control circuits in each control circuit group in the same control circuit unit is the same; wherein the number of control circuit groups in different control circuit units is different.

For example, fig. 12 is a schematic diagram of still another arrangement of control circuits of the display substrate shown in fig. 9, and as shown in fig. 12, the reset control circuit R3, the light emission control circuit E2, the light emission control circuit E6, the reset control circuit R6, and the gate driving circuit G6 form a first control circuit group corresponding to the pixel unit group (601 to 720 rows); the light emission control circuit E3, the light emission control circuit E1, the light emission control circuit E5, the reset control circuit R5, and the gate drive circuit G5 form a second control circuit group provided corresponding to the pixel cell group (481 to 600 rows); the reset control circuit R2, the reset control circuit R1, the light emission control circuit E4, the reset control circuit R4, and the gate drive circuit G4 form a third control circuit group provided corresponding to the pixel cell group (361 to 480 rows); the gate driving circuit G3 forms a fourth control circuit group provided corresponding to the pixel cell group (241 to 360 rows); the gate driving circuit G2 forms a fifth control circuit group provided corresponding to the pixel cell group (121 to 240 rows); the gate driving circuit G1 forms a sixth control circuit group provided corresponding to the pixel cell group (1 to 120 rows). The first control circuit unit comprises a first control circuit group, a second control circuit group and a third control circuit group, and the second control unit comprises a fourth control circuit group, a fifth control circuit group and a sixth control circuit group. The number of control circuits in each control circuit group of the first control circuit unit is the same, and the number of control circuits in each control circuit group of the second control circuit unit is the same.

In this embodiment, through the above-mentioned control circuit structural design, a space is provided for the wiring of the first power line 51, so that the width of the first power line 51 can be monotonically increased in the first wiring area and the second wiring area. Further, by setting the power supply line 51 to monotonically increase in a direction in which the first routing region points to the bonding region, a voltage drop (IR drop) generated by the power supply voltage on the first power supply line 51 is reduced, a current density of the first power supply line 51 at a corner is reduced, power consumption is reduced, and product quality is improved.

In a second aspect, an embodiment of the present disclosure provides a display device, where the display device includes the display substrate described in the foregoing product embodiment, and since in the foregoing embodiment, by setting the first power line ELVSS of the display substrate to monotonically increase in a direction pointing to the binding area along the first routing area, that is, reduce the resistance of the first power line, thereby reducing the voltage drop (IR drop) generated by the power supply voltage on the first power line, reducing the current density of the first power line at the corner, achieving the technical effect of reducing the power consumption and improving the display quality, the display device in the embodiment of the present disclosure also has the foregoing beneficial effects, which are not described herein again.

Among them, the display device includes, but is not limited to, a display, a mobile phone, a tablet (Pad), a computer, a Virtual Reality (VR) terminal, an augmented reality (augmented reality, AR) terminal, and the like, which are not limited herein.

It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims

1. A display substrate, comprising:

2. The display substrate of claim 1, further comprising:

3. The display substrate according to claim 2, wherein the number of control circuits in the at least partially adjacently disposed control circuit group is the same.

4. A display substrate according to claim 3, wherein a plurality of the control circuit groups are divided into a plurality of control circuit units, and the number of control circuits in each of the control circuit groups in the same control circuit unit is the same; wherein the number of the control circuit groups in different control circuit units is the same.

5. A display substrate according to claim 3, wherein a plurality of the control circuit groups are divided into a plurality of control circuit units, and the number of control circuits in each of the control circuit groups in the same control circuit unit is the same; wherein the number of the control circuits in the control circuit groups of the different control circuit units is different.

6. The display substrate according to any one of claims 2 to 5, wherein the control circuit comprises at least one or more of a gate driving circuit, a reset control circuit, and a light emission control circuit.

7. The display substrate according to claim 1, wherein the second wiring region and the third wiring region are each provided with the power line segment, and the power line segments are each electrically connected to a cathode of the light emitting device.

8. The display substrate according to claim 7, wherein the first wiring region is also provided with a power line segment, and the power line segment of the first wiring region is electrically connected to the power line segments in the second wiring region and the third wiring region.

9. The display substrate of claim 1, wherein the light emitting device comprises at least one of an OLED, a mini-OLED, or a Micro-OLED.

10. A display device comprising a display substrate according to any one of claims 1-9.