CN216871964U

CN216871964U - Display panel and display device

Info

Publication number: CN216871964U
Application number: CN202123386569.0U
Authority: CN
Inventors: 赖青俊; 朱绎桦; 袁永; 安平; 曹兆铿
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2022-07-01
Anticipated expiration: 2030-12-30
Also published as: CN216871963U; CN215644490U

Abstract

The utility model discloses a display panel and a display device, belonging to the technical field of display, wherein the display panel comprises a first transistor and a second transistor, wherein a first active layer of the first transistor comprises silicon; the second active layer of the second transistor includes an oxide semiconductor; the length of a channel region of the first transistor is L1, the distance between the first gate and the first active layer is D1, and the first area S1 is L1 × D1; the length of a channel region of the second transistor is L2, the distance between the second gate and the second active layer is D2, and the second area S2 is L2 × D2; s1 < S2; the driver circuit includes a second transistor, the pixel circuit includes a first transistor, or the driver circuit includes a first transistor. The display device comprises the display panel. The utility model can save the space of the panel and provide more excellent display effect while ensuring the stability and normal operation of the transistor.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

Display panels are widely used in portable electronic products such as mobile phones and palm computers at present, for example: thin Film Transistor-Liquid Crystal displays (TFT-LCDs), Organic Light Emitting Diode (OLED) displays, Low Temperature Polysilicon (LTPS) displays, Plasma Display Panels (PDPs), and the like.

Displays such as organic light emitting diode displays have an array of display pixels based on light emitting diodes. In this type of display, each display pixel includes a light emitting diode and a thin film transistor for controlling the application of signals to the light emitting diode. Thin film display driver circuitry is typically included in the display. For example, the gate driver circuit and the demultiplexer circuit on the display may be formed of thin film transistors.

With the development of display technology, display devices with better display effect are more and more pursued under the promotion of market competition. The pixel density of the display (pixel Per inc, also called as pixel density, which indicates the number of Pixels in each Inch) has become an important index for measuring the display effect of the display, and the higher the PPI value, i.e. the higher the density of the display screen can display images, the higher the fidelity is.

Therefore, how to further improve the PPI of the display panel, so as to make the display effect more excellent and make the product more advantageous, is a technical problem that needs to be solved urgently by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention provides a display panel and a display device to solve the problems that the pixel density of the display in the prior art cannot be further improved and the display effect needs to be improved.

The utility model discloses a display panel, which comprises a substrate base plate; the first transistor comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, and the first active layer comprises silicon; the second transistor includes a second active layer including an oxide semiconductor, a second gate electrode, a second source electrode, and a second drain electrode; the length of a channel region of the first transistor is L1, the distance between the first gate and the first active layer in the direction perpendicular to the substrate is D1, and the first area S1 is L1 × D1; the length of a channel region of the second transistor is L2, the distance between the second gate and the second active layer in the direction perpendicular to the substrate is D2, and the second area S2 is L2 × D2; wherein S1 < S2; the display panel includes a pixel circuit and a driving circuit which supplies a driving signal to the pixel circuit, wherein the driving circuit includes a second transistor, the pixel circuit includes a first transistor, or the driving circuit includes a first transistor.

Based on the same utility model concept, the utility model also discloses a display device which comprises the display panel.

Compared with the prior art, the display panel and the display device provided by the utility model at least realize the following beneficial effects:

the display panel provided by the utility model is arranged in a direction vertical to the substrate base plate, the distance between the first gate of the first transistor and the first active layer is D1, and the first area S1 is L1 × D1; the distance between the second gate of the second transistor and the second active layer is D2, and the second area S2 is L2 × D2; and S1 is less than S2, because the first transistor of the silicon transistor has better response capability, in order to fully improve the PPI of the display panel, the utility model utilizes the respective advantages of the silicon transistor and the oxide semiconductor transistor, and designs the lengths of the channel regions of the two types of transistors to be as small as possible, thereby being beneficial to saving circuit space and further being beneficial to improving the PPI of the display panel. The display panel is arranged in the direction vertical to a substrate base plate of the display panel, a first area S1 is smaller than a second area S2, wherein the first area S1 is L1 multiplied by D1, the second area S2 is L2 multiplied by D2, the distance between a first grid electrode of a first transistor of a silicon transistor and a first active layer is D1, and the distance between a second grid electrode of a second transistor of an oxide semiconductor transistor and a second active layer is D2, so that the characteristics and advantages of the silicon transistor and the oxide semiconductor transistor can be fully utilized, the stability and the normal operation of the transistors are ensured, the space of the display panel is saved, the PPI of the display panel is improved, the display quality of the display panel is improved, the display effect is more excellent, and the product has competitive advantages.

Of course, it is not necessary for any product in which the present invention is practiced to specifically achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description, serve to explain the principles of the utility model.

Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;

FIG. 2 is a partial film layer cross-sectional view of the area A in FIG. 1;

FIG. 3 is a partial film layer cross-sectional view of the area B in FIG. 1;

fig. 4 is a circuit connection block diagram of the driving circuit provided in the present embodiment;

fig. 5 is a schematic diagram of a top view structure of the first transistor and the second transistor of fig. 2;

fig. 6 is a schematic diagram of a top view structure of the first transistor and the second transistor in fig. 3;

FIG. 7 is a cross-sectional view of another partial film layer in the area A of FIG. 1;

fig. 8 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 9 is an operation timing diagram of the pixel circuit in fig. 8;

FIG. 10 is a cross-sectional view of another partial film layer in area A of FIG. 1;

FIG. 11 is a cross-sectional view of another partial film layer in the area B of FIG. 1;

FIG. 12 is a cross-sectional view of another partial film layer in area A of FIG. 1;

FIG. 13 is a cross-sectional view of another partial film layer in the area B of FIG. 1;

fig. 14 is a schematic plan view of another display panel according to an embodiment of the present invention;

FIG. 15 is a partial film layer sectional view of the region C in FIG. 14;

FIG. 16 is a sectional view of another partial film layer in the area C of FIG. 14;

FIG. 17 is a sectional view of another partial film layer in the area C of FIG. 14;

FIG. 18 is a sectional view of another partial film layer in the area C of FIG. 14;

FIG. 19 is a sectional view of another partial film layer in the area C of FIG. 14;

FIG. 20 is a sectional view of another partial film layer in the area C of FIG. 14;

FIG. 21 is a sectional view of another partial film layer in the area C of FIG. 14;

fig. 22 is a schematic plan view of another display panel according to an embodiment of the present invention;

FIG. 23 is a partial film layer cross-sectional view of region D in FIG. 22;

fig. 24 is a schematic plan view of a display panel according to an embodiment of the present invention;

fig. 25 is a partially enlarged view of the region E in fig. 24;

fig. 26 is another partial enlarged view of the area E in fig. 24;

fig. 27 is a schematic plan view of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the utility model, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as exemplary only and not as limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Referring to fig. 1 to fig. 3, fig. 1 is a schematic plan structure diagram of a display panel according to an embodiment of the present invention, fig. 2 is a partial film sectional structure diagram of an area a in fig. 1, and fig. 3 is a partial film sectional structure diagram of an area B in fig. 1 (it is understood that fig. 2 and fig. 3 only schematically show partial film diagrams of a first transistor and a second transistor, and the first transistor and the second transistor are illustrated together for clearly illustrating technical features of the first transistor and the second transistor, but do not show actual arrangement positions of the first transistor and the second transistor in the display panel, and in a specific implementation, the arrangement positions and connection relationships of the first transistor and the second transistor are determined according to arrangements of a driving circuit and a pixel circuit), and the display panel 000 according to the embodiment includes: a base substrate 10;

a first transistor 20 and a second transistor 30, the first transistor 20 and the second transistor 30 being formed on the substrate 10, the first transistor 20 including a first active layer 201, a first gate 20G, a first source 20S and a first drain 20D, the first active layer 201 including silicon; the second transistor 30 includes a second active layer 301, a second gate electrode 30G, a second source electrode 30S, and a second drain electrode 30D, the second active layer 301 including an oxide semiconductor; optionally, in this embodiment, the first transistor 20 and the second transistor 30 are exemplified by transistors with a top-gate structure, and in specific implementation, the first transistor 20 and the second transistor 30 may also be transistors with other bottom-gate structures, and the like;

the length of the channel region of the first transistor 20 is L1, the distance between the first gate 20G and the first active layer 201 in the direction Z perpendicular to the substrate 10 is D1, and the first area S1 is L1 × D1;

the length of the channel region of the second transistor 30 is L2, the distance between the second gate 30G and the second active layer 301 in the direction Z perpendicular to the substrate 10 is D2, and the second area S2 is L2 × D2; wherein the content of the first and second substances,

S1＜S2；

the display panel 000 includes a pixel circuit 40 and a driving circuit 50 for providing a driving signal to the pixel circuit 40, wherein the first transistor 20 and the second transistor 30 may be transistors in the driving circuit, i.e., the driving circuit 50 includes the first transistor 20 or the second transistor 30; in addition, the first transistor 20 and the second transistor 30 may also be transistors in a pixel circuit, that is, the pixel circuit includes the first transistor 20 or the second transistor 30, for example, the second transistor 30 is located in the pixel circuit, and it may be a driving transistor or a switching transistor;

in some alternative embodiments, the driving circuit 50 includes the second transistor 30, the pixel circuit 40 includes the first transistor 20 or the driving circuit 50 includes the first transistor 20.

Specifically, the display panel 000 of the present embodiment includes a pixel circuit 40 and a driving circuit 50 for providing a driving signal to the pixel circuit 40, and optionally, the driving circuit 50 may be a gate driving circuit for providing a scanning driving signal to the scanning lines G of the display panel 000, and the gate driving circuit may be formed on the substrate 10, for example, disposed at the left edge (it is understood that fig. 1 of the present embodiment only illustrates, as a block diagram, a structure of the driving circuit 50 on the display panel, but is not limited thereto, and the present embodiment does not limit a specific connection structure of the driving circuit 50) and the right edge of the display panel 000, only on a single edge of the display panel 000, or at other positions in the display panel 000. The driving circuit 50 may also be a demultiplexer circuit (not shown in the drawings, the demultiplexer circuit may be located between the bonding area and the display area of the display panel 000) for demultiplexing the data signals from the driving chip or the flexible circuit board in the bonding area to the plurality of corresponding data lines S. The display panel 000 may include a plurality of display pixels 400, each display pixel 400 may include a pixel circuit 40, and the scanning lines G and the data lines S of the display panel 000 cross and are insulated to define a region where the display pixel 400 is located. Fig. 2 of this embodiment illustrates that the driving circuit 50 includes the second transistor 30, and the pixel circuit 40 includes the first transistor 20, and fig. 3 illustrates that the driving circuit 50 includes the second transistor 30 and the first transistor 20, and in a specific implementation, the structures of the pixel circuit 40 and the driving circuit 50 are not limited thereto. The circuit structures of the pixel circuit 40 and the driving circuit 50 for providing the driving signal to the pixel circuit 40 are not particularly limited in this embodiment, and it is only necessary that the driving circuit 50 includes the second transistor 30, the pixel circuit 40 includes the first transistor 20 or the driving circuit 50 includes the first transistor 20, so that at least two types of transistors are disposed on the substrate 10 of the display panel 000.

The first transistor 20 and the second transistor 30 of the present embodiment are formed on the substrate 10, the first transistor 20 includes a first active layer 201, a first gate 20G, a first source 20S and a first drain 20D, the first active layer 201 includes silicon, i.e., the first transistor 20 is a silicon transistor, and the silicon may be polysilicon deposited by using a Low Temperature method, i.e., LTPS (Low Temperature polysilicon) or Low Temperature polysilicon. The length of the channel region of the first transistor 20 is L1, where the channel region of the first transistor 20 is a region where the first active layer 201 of the first transistor 20 overlaps the first gate electrode 20G, and the length of the channel region of the first transistor 20 is the length of the channel region of the first transistor 20 in the current transmission direction between the first source electrode 20S and the first drain electrode 20D. The second transistor 30 includes a second active layer 301, a second gate 30G, a second source 30S and a second drain 30D, the second active layer 301 includes an oxide semiconductor, i.e., the second transistor 30 is an oxide semiconductor transistor, and the oxide semiconductor material is amorphous indium Gallium Zinc oxide (igzo). The length of the channel region of the second transistor 30 is L2, wherein the channel region of the second transistor 30 is a region where the second active layer 301 of the second transistor 30 overlaps the second gate 30G, and the length of the channel region of the second transistor 30 is the length of the channel region of the second transistor 30 in the current transmission direction between the second source 30S and the second drain 30D.

The display panel 000 provided in this embodiment is disposed in the direction Z perpendicular to the substrate base plate 10, the distance between the first gate 20G and the first active layer 201 is D1, and the first area S1 is L1 × D1; the distance between the second gate 30G and the second active layer 301 is D2, and the second area S2 is L2 × D2; and S1 < S2, optionally, the distance D1 between the first gate 20G and the first active layer 201 may be set to be smaller than the distance D2 between the second gate 30G and the second active layer 301, the length L1 of the channel region of the first transistor 20 may also be set to be smaller than the length L2 of the channel region of the second transistor 30, the distance D1 between the first gate 20G and the first active layer 201 may also be set to be smaller than the distance D2 between the second gate 30G and the second active layer 301, and the length L1 of the channel region of the first transistor 20 is smaller than the length L2 of the channel region of the second transistor 30, so that the first area S1 is smaller than the second area S2. Since the first transistor 20 of the present embodiment is a silicon transistor, the second transistor 30 is an oxide semiconductor transistor, and the first transistor 20 of the silicon transistor has a faster carrier migration rate than the second transistor 30 of the oxide semiconductor transistor, and the first active layer 201 of the first transistor 20 includes silicon, and the second active layer 301 of the second transistor 30 includes an oxide semiconductor, the silicon transistor is not sensitive to hydrogen, water oxygen, and the like in the external environment, and therefore, the distance D1 between the first gate electrode 20G of the first transistor 20 and the first active layer 201 may be set to be smaller than the distance D2 between the second gate electrode 30G of the second transistor 30 and the second active layer 301 (as shown in fig. 2 and 3); since the first transistor 20 of the silicon transistor has a better response capability, in order to sufficiently increase the PPI of the display panel 000, the present embodiment utilizes the advantages of the silicon transistor and the oxide semiconductor transistor, and the lengths of the channel regions (L1 and L2) of the two types of transistors are designed to be as small as possible, so as to be beneficial to saving the circuit space and further beneficial to increase the PPI (pixel density, which represents the number of Pixels Per Inch) of the display panel 000. The present embodiment is disposed in a direction Z perpendicular to the substrate 10 of the display panel 000, where a first area S1 is less than a second area S2, where the first area S1 is L1 × D1, the second area S2 is L2 × D2, a distance between the first gate 20G of the first transistor 20 of the silicon transistor and the first active layer 201 is D1, and a distance between the second gate 30G of the second transistor 30 of the oxide semiconductor transistor and the second active layer 301 is D2, so that respective characteristics and advantages of the silicon transistor and the oxide semiconductor transistor can be fully utilized, and while ensuring stability and normal operation of the transistors, the space of the display panel is saved, the PPI of the display panel is enhanced, thereby facilitating enhancement of the display quality of the display panel 000, making the display effect more superior, and making the product more competitive.

It should be noted that, in the foregoing and in the following, the width and the length of the channel region are presented, wherein the length of the channel region refers to the dimension of the channel region in the direction of the carriers moving between the source and the drain, and if this direction is defined as the second direction, the width of the channel region refers to the dimension of the channel region in the third direction, wherein the second direction may be perpendicular to the third direction.

In addition, it should be noted that fig. 1 to fig. 3 of this embodiment only exemplarily show a planar structure and a cross-sectional structure of a partial film layer of the display panel 000, and the structure included in the display panel 000 is not limited thereto, and may also include other film layer structures capable of implementing the related functions of the display panel, such as each insulating layer, a light emitting layer, an electrode layer (organic light emitting display panel), and the like.

In some optional embodiments, please refer to fig. 1-3 and fig. 4 in combination, fig. 4 is a circuit connection block diagram of the driving circuit provided in this embodiment, the driving circuit 50 includes an input module 501, a logic transmission module 502 and an output module 503, the input module 501 is connected between the input end in and the logic transmission module 502, and the output module 503 is connected between the logic transmission module 502 and the output end out; the logic transmission module 502 is connected to the high level signal terminal VGH or the low level signal terminal VGL, and the output terminal out is connected to the pixel circuit 40; wherein the content of the first and second substances,

the logic transmission module 502 comprises the second transistor 30 or the input module 501 comprises the second transistor 30 and the output module 503 comprises the first transistor 20.

This embodiment explains that the driving circuit 50 may be a gate driving circuit for connecting to the pixel circuit 40 through the scanning line G to supply a scanning driving signal to the pixel circuit 40. The driving circuit 50 may include an input module 501, a logic transmission module 502, and an output module 503, where one end of the input module 501 is connected to an input end in of the driving circuit 50, and the other end of the input module 501 is connected to the logic transmission module 502, and the input end in may be connected to a driving chip or a flexible circuit board to provide an input signal for the input module 501; the logic transmission module 502 is connected to the high-level signal terminal VGH or the low-level signal terminal VGL, and generally includes nand gates, nor gate circuits, and the like, which are usually the gate circuits of the high-level signal terminal VGH and the low-level signal terminal VGL; the other end of the logic transmission module 502 is connected to the output module 503, the output module 503 is connected to the output end out of the driving circuit 50, and the output end out is connected to the pixel circuit 40, so as to provide the scanning driving signal to the pixel circuit 40 through the driving circuit 50. In the embodiment, the logic transmission module 502 of the driving circuit 50 includes the second transistor 30, or the input module 501 of the driving circuit 50 includes the second transistor 30, and the output module 503 includes the first transistor 20, because the first area S1 of the first transistor 20 is smaller than the second area S2 of the second transistor 30, the length L1 of the channel region of the first transistor 20 is set to be smaller, or the distance D1 between the first gate 20G and the first active layer 201 is smaller in the direction Z perpendicular to the substrate 10, both of which can make the first area S1 of the first transistor 20 smaller, and further can make the response speed of the first transistor 20 faster. In the driving circuit 50 provided in this embodiment, for the input module 501 and the logic transmission module 502, especially for the nand gate and the nor gate of the logic transmission module 502, the gate circuits of the high-level signal terminal VGH and the low-level signal terminal VGL are usually required to have a low leakage current when the transistors are in an off state, so as to avoid the influence on the high-level signal and the low-level signal after the logic signal transmission due to the transistor leakage current, which affects the normal transmission of the next node signal, therefore, the logic transmission module 502 includes the second transistor 30 of the oxide semiconductor transistor, the input module 501 includes the second transistor 30 of the oxide semiconductor transistor, and the oxide semiconductor transistor has a low leakage current when the oxide semiconductor transistor is in an off state, therefore, the influence on the gating of the high-level signal and the low-level signal after the logic signal transmission of the input module 501 and the logic transmission module 502 due to the arrangement of the relation of other transistor leakage currents can be avoided, and the influence on the normal transmission of the next node signal can be avoided. The output module 503 of the driving circuit 50 generally requires a faster response speed and driving capability, and therefore, the output module 503 of the present embodiment includes the first transistor 20 of a silicon transistor, and the first area S1 of the first transistor 20 is smaller, so that the response speed is faster, thereby ensuring the response and driving capability of the driving circuit 50 and avoiding the problems of signal delay and the like of the display panel 000 caused by the driving circuit 50.

It should be noted that, in this embodiment, a block diagram illustrates a connection structure of each module in the driving circuit 50, and in a specific implementation, the circuit connection structure inside each module of the driving circuit 50 may be designed according to actual requirements, which is not limited in this embodiment.

In some alternative embodiments, please refer to fig. 1-4 in combination with fig. 5 and fig. 6, where fig. 5 is a schematic diagram of a top structure of the first transistor and the second transistor in fig. 2, fig. 6 is a schematic diagram of a top structure of the first transistor and the second transistor in fig. 3, in this embodiment, a width of the channel region of the first transistor 20 is W1, a width of the channel region of the second transistor 30 is W2, a first volume V1 is S1 × W1, and a second volume V2 is S2 × W2; wherein V1 is more than V2. Wherein the channel region of the first transistor 20 is a region where the first active layer 201 of the first transistor 20 overlaps the first gate electrode 20G, the length L1 of the channel region of the first transistor 20 is a length of the channel region of the first transistor 20 in a current transmission direction between the first source electrode 20S and the first drain electrode 20D, and the width W1 of the channel region of the first transistor 20 is a length of the channel region of the first transistor 20 in a direction perpendicular to the length of the channel region of the first transistor 20, that is, the length direction of the channel region of the first transistor 20 and the width direction of the channel region of the first transistor 20 are perpendicular to each other; the channel region of the second transistor 30 is a region where the second active layer 301 of the second transistor 30 overlaps the second gate electrode 30G, the length of the channel region of the second transistor 30 is a length of the channel region of the second transistor 30 in a current transfer direction between the second source electrode 30S and the second drain electrode 30D, and the width W2 of the channel region of the second transistor 30 is a length of the channel region of the second transistor 30, that is, a length direction of the channel region of the second transistor 30 and a width direction of the channel region of the second transistor 30 are perpendicular to each other in a direction perpendicular to the length of the channel region of the second transistor 30.

The present embodiment explains that the width of the channel region of the first transistor 20 of the silicon transistors is W1, the first volume V1 is S1 × W1, the width of the channel region of the second transistor 30 of the oxide semiconductor transistors is W2, the second volume V2 is S2 × W2, although the first area S1 < the second area S2, the present embodiment sets the first volume V1 > the second volume V2, so that by sufficiently increasing the width W1 of the channel region of the first transistor 20 of the silicon transistors, i.e., W1/W2 > S2/S1, the ratio of the width W1 of the channel region of the first transistor 20 to the width W2 of the channel region of the second transistor 30 is greater than the ratio of the second area S2 to the first area S1, so that the first volume V1 > the second volume V2, the output performance of the driving circuit module 503 using the driving circuit 50 of the first transistor 20 can be further ensured, and the output performance of the driving circuit can be further ensured, is beneficial to improving the output effect.

In some alternative embodiments, please refer to fig. 1, fig. 7 and fig. 8 in combination, in which fig. 7 is a sectional structure diagram of another partial film layer in a region a in fig. 1, and fig. 8 is a schematic structural diagram of a pixel circuit 40 according to an embodiment of the present invention, in this embodiment, the pixel circuit 40 includes a first transistor 20, and the first transistor 20 is a driving transistor of the pixel circuit 40, where D1/D2 < L1/L2.

This embodiment explains that the pixel circuit 40 of the display pixel 400 may include the first transistor 20 of a silicon transistor, and the first transistor 20 may be a driving transistor of the pixel circuit 40. In the organic light emitting display panel, the first transistor 20 as a driving transistor may be electrically connected to the light emitting units, and provide an anode voltage signal to the anode of each light emitting unit, so that a certain driving electric field is formed between the anode and the cathode of the light emitting unit, thereby realizing light emission of the light emitting layer and further realizing a display function. Since the driving transistor of the pixel circuit 40 is responsible for the data writing operation of the pixel circuit 40, the requirements on the accuracy of the threshold voltage and the stability of the gate potential of the driving transistor are very high, and therefore, it is necessary to appropriately increase the distance between the gate and the active layer of the transistor or the length of the channel region of the transistor in order to obtain a more accurate threshold voltage and ensure the stability of the gate potential of the driving transistor. Therefore, in the present embodiment, the driving transistor of the pixel circuit 40 is the first transistor 20 which is a silicon transistor, and the carrier mobility rate of the silicon transistor is relatively large, so that when the first area S1 is ensured to be smaller than the second area S2, when the length L1 of the channel region of the first transistor 20 is relatively increased, the response rate of the first transistor 20 is not greatly affected. Therefore, in the present embodiment, the driving transistor of the pixel circuit 40 is the first transistor 20 of a silicon transistor, and the ratio of the distance D1 between the first gate 20G of the first transistor 20 and the first active layer 201 to the distance D2 between the second gate 30G of the second transistor 30 and the second active layer 301 is smaller than the length L1 of the channel region of the first transistor 20 and the length L2 of the channel region of the second transistor 30, that is, the length L1 of the channel region of the first transistor 20 may be greater than or equal to the length L2 of the channel region of the second transistor 30, so that while the threshold voltage of the driving transistor can be obtained more accurately and the stability of the gate potential of the driving transistor is ensured, the response rate of the first transistor 20 can be prevented from being greatly influenced, and the response capability of the pixel circuit 40 can be ensured.

Alternatively, as shown in fig. 8 and 9, fig. 9 is an operation timing diagram of the pixel circuit in fig. 8, and the pixel circuit 40 includes a plurality of switching transistors and driving transistors (M1-M7), a storage capacitor Cst, and a light emitting diode OLED (7T1C), where the transistor M3 is a driving transistor and the rest of the transistors are switching transistors. Taking the structure of the pixel circuit 40 as an example, the working principle of the pixel circuit 40 is as follows: in an initial reset stage T1, the transistor M5 and the transistor M7 are turned on, the other transistors are turned off, the potential of the node N1 is the reference voltage Vref, the potential of the node N4 is the reference voltage Vref, and the anode of the light emitting diode OLED is reset; in the data writing and threshold capturing stage T2, the transistor M2, the transistor M3, and the transistor M4 are turned on, the other transistors are turned off, the potential of the node N2 is the data voltage Vdata, the potentials of the node N1 and the node N3 are Vdata- | Vth |, where Vth is the threshold voltage of the transistor M3; in the light-emitting period T3, the transistors M1, M3 and M6 are turned on, the other transistors are turned off, the signal of the power supply positive voltage PVDD is transmitted to the transistor M3, the transistor M3 generates a driving current to drive the light-emitting diode OLED to emit light, the potential of the node N2 is the power supply positive voltage PVDD, and the potential of the node N1 is the power supply positive voltage PVDDVdata- | Vth |, the potential of the node N3 is PVEE + Voled, PVEE is a power supply negative voltage, Voled is a corresponding voltage on the light emitting diode OLED, and the light emitting current Id ═ k (Vsg- | Vth |)²＝k(PVDD-Vdata-|Vth|)². Optionally, in this embodiment, taking the structure of the pixel circuit 40 as an example, the first transistor 20 of the silicon transistor may be the driving transistor M3 in the pixel circuit 40.

It should be noted that this embodiment merely illustrates one possible circuit structure of the pixel circuit 40, but is not limited thereto, and the structure of the pixel circuit 40 may be other structures, and this embodiment is not limited thereto.

In some alternative embodiments, please refer to fig. 1 and fig. 10 and fig. 11 in combination, in which fig. 10 is a sectional structure diagram of another local film in the area a of fig. 1, and fig. 11 is a sectional structure diagram of another local film in the area B of fig. 1, in this embodiment, the second transistor 30 further includes a fourth gate 30G2, a distance between the fourth gate 30G2 and the second active layer 301 in the direction Z perpendicular to the substrate 10 is D4, and D2 < D4; the channel region of the second transistor 30 defined by the second gate 30G is a second channel region, and the length of the second channel region is L2; the second channel region is a region where the second active layer 301 of the second transistor 30 overlaps the second gate electrode 30G, and the length of the second channel region is a length of the second channel region of the second transistor 30 in a current transmission direction between the second source electrode 30S and the second drain electrode 30D. The channel region of the second transistor 30 defined by the fourth gate 30G2 is a fourth channel region, and the length of the fourth channel region is L4; the fourth channel region is a region where the second active layer 301 of the second transistor 30 overlaps the fourth gate electrode 30G2, and the length of the fourth channel region is the length of the fourth channel region of the second transistor 30 in the current transmission direction between the second source electrode 30S and the second drain electrode 30D; wherein, the fourth area S4 is L4 × D4, and S2 < S4.

The present embodiment explains that the second transistor 30 of the oxide semiconductor transistor may be a double-gate transistor, the second transistor 30 includes a second gate 30G and a fourth gate 30G2, and in the direction Z perpendicular to the substrate 10, the distance D4 between the fourth gate 30G2 and the second active layer 301 is greater than the distance D2 between the second gate 30G and the second active layer 301, that is, the second transistor 30 of the double-gate structure includes two control gates, the second gate 30G is a main gate, the fourth gate 30G2 is an auxiliary gate, and may be considered as a series connection of two single-gate transistors from the structural point of view, and the added fourth gate 30G2 has a certain shielding effect, so that the feedback capacitance between the drain and the second gate 30G can be small, and the display quality of the display panel can be improved. In addition, the present embodiment is disposed in the direction Z perpendicular to the substrate base plate 10, and the distance D4 between the fourth gate 30G2 and the second active layer 301 is greater than the distance D2 between the second gate 30G and the second active layer 301, that is, the insulating layer between the fourth gate 30G2 and the second active layer 301 is set to be thicker, so as to protect the second active layer 301.

In some alternative embodiments, with continued reference to fig. 1, 10 and 11, in this embodiment, the length of the fourth channel region of the second transistor 30 defined by the fourth gate 30G2 of the second transistor 30 is L4 multiplied by the distance D4 between the fourth gate 30G2 and the second active layer 301, which is a fourth area S4, the length L1 of the channel region of the first transistor 20 multiplied by the distance D1 between the first gate 20G and the first active layer 201 is a first area S1, the length L2 of the channel region of the second transistor 30 multiplied by the distance D2 between the second gate 30G and the second active layer 301 is a second area S2, and S4+ S1 > 2S2, that is, the sum of the fourth area S4 and the first area S1 is greater than twice the second area S2.

This embodiment explains that the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 and the second area S2 defined by the second gate 30G of the second transistor 30 of the oxide semiconductor transistor of the double-gate structure is larger than the difference between the second area S2 defined by the second gate 30G of the second transistor 30 and the first area S1 defined by the first gate 20G of the first transistor 20, i.e., S4-S2 > S2-S1, and S4+ S1 > 2S 2. In the present embodiment, the distance D4 between the fourth gate 30G2 and the second active layer 301 is greater than the distance D2 between the second gate 30G and the second active layer 301, that is, the insulating layer between the fourth gate 30G2 and the second active layer 301 is set to be thicker, which can protect the second active layer 301, and the fourth area S4 defined by the fourth gate 30G2 is set to be larger, which can make the fourth area S4 greater than the second area S2, and the first area S1 and the second area S2 are both areas defined by the main gates of the transistors, and when the first transistor 20 and the second transistor 30 are both switching transistors, the difference between the areas is not set to be very large, that is, S4-S2 > S2-S1. The second transistor 30 of this embodiment is an oxide semiconductor transistor with a double-gate structure, the fourth gate 30G2 is an auxiliary gate, the auxiliary gate is located at the bottom of the second active layer 301, and the auxiliary gate can improve the stability of the oxide semiconductor transistor and protect the second active layer 301.

In some alternative embodiments, please refer to fig. 1 and 12 and fig. 13 in combination, in which fig. 12 is a sectional structure diagram of another local film in a region a of fig. 1, and fig. 13 is a sectional structure diagram of another local film in a region B of fig. 1, in this embodiment, the first transistor 20 further includes a third gate 20G2, a distance between the third gate 20G2 and the first active layer 201 is D3 in a direction Z perpendicular to the substrate 10, and D1 < D3; the channel region of the first transistor 20 defined by the first gate 20G is a first channel region having a length L1; the first channel region is a region where the first active layer 201 of the first transistor 20 overlaps the first gate 20G, and the length of the first channel region is a length of the first channel region of the first transistor 20 in a current transmission direction between the first source 20S and the first drain 20D. The channel region of the first transistor 20 defined by the third gate 20G2 is a third channel region, and the length of the third channel region is L3; the third channel region is a region where the first active layer 201 of the first transistor 20 overlaps the third gate electrode 20G2, and the length of the third channel region is the length of the third channel region of the first transistor 20 in the current transmission direction between the first source electrode 20S and the first drain electrode 20D; wherein, the third area S3 is L3 XD 3, and S1 < S3.

The present embodiment explains that the first transistor 20 of the silicon transistor may be a double-gate transistor, the first transistor 20 includes a first gate 20G and a third gate 20G2, and in the direction Z perpendicular to the substrate 10, the distance D3 between the third gate 20G2 and the first active layer 201 is greater than the distance D1 between the first gate 20G and the first active layer 201, that is, the first transistor 20 of the double-gate structure includes two control gates, the first gate 20G is a main gate, the third gate 20G2 is an auxiliary gate, which may be regarded as a series connection of two single-gate transistors from the structural point of view, and the added third gate 20G2 has a certain shielding effect, so that the feedback capacitance between the drain and the first gate 20G can be made small, which is beneficial to improving the display quality of the display panel. In addition, in the embodiment, the third area S3 defined by the third gate 20G2 is set to be larger, the third area S3 is larger than the first area S1, that is, the first area S1 defined by the main gate is smaller than the third area S3 defined by the auxiliary gate, and in the direction Z perpendicular to the substrate 10, the distance D3 between the third gate 20G2 and the first active layer 201 is larger than the distance D1 between the first gate 20G and the first active layer 201, that is, the insulating layer between the third gate 20G2 and the first active layer 201 is set to be thicker, which can play a role of protecting the first active layer 201.

In some alternative embodiments, with continuing reference to fig. 1, 12 and 13, in this embodiment, the third gate 20G2 of the first transistor 20 includes amorphous silicon containing hydrogen.

This embodiment explains that the material of the third gate electrode 20G2 of the first transistor 20 may be hydrogen-containing amorphous silicon (a-Si: H), so that hydrogen elements may be supplied to the first active layer 201 of the first transistor 20 of a silicon transistor to repair defects in the first active layer 201.

In some alternative embodiments, with continued reference to fig. 1, 8, 12 and 13, in the present embodiment, the first transistor 20 is a driving transistor of the pixel circuit 40, where S3-S1 < S4-S2.

This embodiment explains that the pixel circuit 40 of the display pixel 400 may include the first transistor 20 of a silicon transistor, and the first transistor 20 may be a driving transistor of the pixel circuit 40. In the organic light emitting display panel, the first transistor 20 as a driving transistor may be electrically connected to the light emitting units, and provide an anode voltage signal to the anode of each light emitting unit, so that a certain driving electric field is formed between the anode and the cathode of the light emitting unit, thereby realizing light emission of the light emitting layer and further realizing a display function.

In the present embodiment, the difference between the third area S3 and the first area S1 is smaller than the difference between the fourth area S4 and the second area S2, that is, the first transistor 20 and the second transistor 30 are both dual-gate structures, the difference between the third area S3 defined by the bottom gate (the third gate 20G2) of the first transistor 20 and the first area S1 defined by the top gate (the first gate 20G) is S3-S1, the difference between the fourth area S4 defined by the bottom gate (the fourth gate 30G2) of the second transistor 30 and the second area S2 defined by the top gate (the second gate 30G) is S4-S2, the material of the bottom gate (the third gate 20G2) of the first transistor 20 comprises amorphous silicon containing hydrogen, hydrogen can be provided to the first active layer 201 to repair the defect in the first active layer 201, and can also play a role of shielding to prevent the display device of the first transistor 20 from being disturbed by other elements, therefore, the third area S3 defined by the bottom gate (the third gate 20G2) of the first transistor 20 does not need to be set larger relative to the first area S1 defined by the top gate (the first gate 20G), i.e., the difference between S3 and S1 can be smaller. The second active layer 301 of the second transistor 30 is made of an oxide semiconductor material, which is relatively sensitive to a silicon material, and particularly when both the oxide semiconductor transistor and the silicon transistor are disposed in the display panel 000, because the silicon transistor is in an environment with a relatively high hydrogen content, in order to sufficiently protect the oxide semiconductor transistor, after the second transistor 30 is configured with the dual-gate structure, the fourth area S4 defined by the bottom gate (the auxiliary gate — the fourth gate 30G2) thereof may be set to be larger, so that the stability of the second transistor 30 may be improved, and the second active layer 301 of the second transistor 30 may be protected from the hydrogen element by the fourth gate 30G2 with a larger area, so that S3-S1 < S4-S2 is provided in this embodiment.

Moreover, since the third gate 20G2 of the first transistor 20 of the present embodiment is mainly for the purpose of supplementing hydrogen to the first active layer 201 of the first transistor 20 and playing a role of shielding, in the direction Z perpendicular to the substrate 10, the distance D3 between the third gate 20G2 and the first active layer 201 does not need to be set to be large, and for the second transistor 30, in order to fully protect the oxide semiconductor transistor, the distance D2 between the second gate 30G and the second active layer 301 and the distance D4 between the fourth gate 30G2 and the second active layer 301 are generally set to be larger (that is, the thickness of the insulating layer between the second gate 30G and the second active layer 301 and the thickness of the insulating layer between the fourth gate 30G2 and the second active layer 301 are thicker), so that the second transistor 30 can be fully protected, which is beneficial to improving the display quality.

Alternatively, as shown in fig. 8, fig. 8 is a schematic structural diagram of a pixel circuit 40 according to an embodiment of the present invention, where the pixel circuit 40 includes a plurality of switching transistors and driving transistors, a storage capacitor, and a light emitting diode OLED (7T1C), and taking the structure of the pixel circuit 40 as an example, the first transistor 20 of the silicon transistor may be the driving transistor M3 in the pixel circuit 40.

In some alternative embodiments, please refer to fig. 14 and fig. 15 in combination, fig. 14 is another schematic plane structure diagram of the display panel according to the embodiment of the present invention, fig. 15 is a partial film-layer sectional structure diagram of a region C in fig. 14 (it can be understood that fig. 15 only schematically illustrates a partial film-layer diagram of a first transistor, a second transistor, and a third transistor, which is to clearly illustrate the technical solution of the present embodiment, the first transistor, the second transistor, and the third transistor are illustrated together and do not represent actual arrangement positions of the first transistor, the second transistor, and the third transistor in the display panel, in which in a specific implementation, the arrangement positions and connection relationships of the first transistor, the second transistor, and the third transistor are determined according to the arrangement of the driving circuit and the pixel circuit), in this embodiment, the pixel circuit 40 includes a third transistor 60, the third transistor 60 includes a fifth gate electrode 60G, a third active layer 601, a third source electrode 60S, and a third drain electrode 60D, the third active layer 601 including an oxide semiconductor; in the direction Z perpendicular to the substrate base plate 10, the distance between the fifth gate 60G and the third active layer 601 is D5, the channel region of the third transistor 60 defined by the fifth gate 60G is a fifth channel region, the length of the fifth channel region is L5, and the fifth area S5 is L5 × D5; wherein S1 < S5.

This embodiment explains that the pixel circuit 40 of the display panel 000 further includes the third transistor 60, the third transistor 60 includes the fifth gate 60G, the third active layer 601, the third source 60S and the third drain 60D, the third active layer 601 includes an oxide semiconductor, that is, the third transistor 60 is also an oxide semiconductor transistor, the oxide semiconductor material is, for example, amorphous indium Gallium Zinc oxide, that is, igzo (indium Gallium Zinc oxide), the driving circuit 50 includes the second transistor 30 of the oxide semiconductor transistor, and the pixel circuit 40 also includes the third transistor 60 of the oxide semiconductor transistor. The length of the channel region of the third transistor 60 is L5, wherein the channel region of the third transistor 60 is a region where the third active layer 601 of the third transistor 60 overlaps the fifth gate 60G, and the length of the channel region of the third transistor 60 is the length of the channel region of the third transistor 60 in the current transmission direction between the third source 60S and the third drain 60D.

In the display panel 000 provided in the embodiment, the distance between the fifth gate 60G and the third active layer 601 is D5, the length of the fifth channel region of the third transistor 60 defined by the fifth gate 60G is L5, the fifth area S5 is L5 × D5, and S1 < S5, alternatively, the distance D1 between the first gate 20G and the first active layer 201 is smaller than the distance D5 between the fifth gate 60G and the third active layer 601, the length L1 of the channel region of the first transistor 20 is smaller than the length L5 of the channel region of the third transistor 60, the distance D1 between the first gate 20G and the first active layer 201 is smaller than the distance D5 between the fifth gate 60G and the third active layer 601, and the length L1 of the channel region of the first transistor 20 is smaller than the length L5 of the channel region of the third transistor 60, to achieve a first area S1 less than a fifth area S5. Since the first transistor 20 of the present embodiment is a silicon transistor, the third transistor 60 is an oxide semiconductor transistor, the first transistor 20 of the silicon transistor has a faster carrier mobility than the third transistor 60 of the oxide semiconductor transistor, the first active layer 201 of the first transistor 20 includes silicon, and the third active layer 601 of the third transistor 60 includes an oxide semiconductor, the silicon transistor is not sensitive to hydrogen, water oxygen, and the like in the external environment, and therefore, the distance D1 between the first gate electrode 20G of the first transistor 20 and the first active layer 201 may be set to be smaller than the distance D5 between the fifth gate electrode 60G of the third transistor 60 and the third active layer 601 (as shown in fig. 15); since the first transistor 20 of the silicon transistor has a better response capability, in order to sufficiently increase the PPI of the display panel 000, the present embodiment utilizes the advantages of the silicon transistor and the oxide semiconductor transistor, and the lengths of the channel regions (L1 and L5) of the two types of transistors are designed to be as small as possible, so as to be beneficial to saving the circuit space and further beneficial to increase the PPI (pixel density, which represents the number of Pixels Per Inch) of the display panel 000. The present embodiment is disposed in a direction Z perpendicular to the substrate 10 of the display panel 000, and the first area S1 < the fifth area S5, where the first area S1 is L1 × D1, the fifth area S5 is L5 × D5, a distance between the first gate 20G of the first transistor 20 of the silicon transistor and the first active layer 201 is D1, and a distance between the fifth gate 60G of the third transistor 60 of the oxide semiconductor transistor and the third active layer 601 is D5, so that respective characteristics and advantages of the silicon transistor and the oxide semiconductor transistor can be fully utilized, the transistor stability and normal operation are ensured, the space of the display panel is saved, the PPI of the display panel is increased, the display quality of the display panel 000 is further improved, the display effect is further improved, and the product has competitive advantages.

In some alternative embodiments, please refer to fig. 8, fig. 14 and fig. 16 in combination, where fig. 16 is another partial film-layer cross-sectional structure diagram of the region C in fig. 14 (it can be understood that fig. 16 only schematically illustrates a partial film-layer diagram of a first transistor, a second transistor and a third transistor, which is to clearly illustrate the technical solution of this embodiment, the first transistor, the second transistor and the third transistor are illustrated together, and do not represent actual arrangement positions of the first transistor, the second transistor and the third transistor in the display panel, in an embodiment, the arrangement positions and connection relationships of the first transistor, the second transistor and the third transistor are determined according to arrangements of the driving circuit and the pixel circuit), in this embodiment, the third transistor 60 is a switch transistor of the pixel circuit 40, where S2 > S5.

This embodiment explains that the second area S2 defined by the second gate 30G of the second transistor 30 in the driving circuit 50 is larger than the fifth area S5 defined by the fifth gate 60G of the third transistor 60 in the pixel circuit 40. When the third transistor 60 of the oxide semiconductor transistor is a switch transistor of the pixel circuit 40, the third transistor 60 generally only functions as a switch, and therefore the fifth area S5 defined by the fifth gate 60G of the third transistor 60 does not need to be set too large, and can be set smaller than the second area S2 defined by the second gate 30G of the second transistor 30 in the driving circuit 50, so that the space of the panel can be saved, and the PPI of the display panel 000 can be further improved. The driving circuit 50 is generally disposed at the left edge and the right edge of the display panel 000, or only at a single edge of the display panel 000, or at other positions in the display panel 000, and the space that can be disposed is relatively large, and the driving circuit 50 is used to provide signals for the pixel circuit 40, and the length L2 (as shown in fig. 16) of the channel region of the second transistor 30 of the oxide semiconductor transistor is appropriately increased, so that the second area S2 defined by the second gate 30G of the second transistor 30 can be made larger, problems such as delay and distortion of signals of the driving circuit 50 can be avoided as much as possible, and the reliability of the driving circuit 50 is improved.

Optionally, as shown in fig. 8, fig. 8 is a schematic structural diagram of a pixel circuit 40 according to an embodiment of the present invention, where the pixel circuit 40 includes a plurality of switching transistors and driving transistors, a storage capacitor, and a light emitting diode OLED (7T1C), and taking the structure of the pixel circuit 40 as an example, the third transistor 60 of an oxide semiconductor transistor may be any one or more of the switching transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit 40.

In some alternative embodiments, please refer to fig. 8, fig. 14 and fig. 17 in combination, where fig. 17 is another partial film-layer sectional structure diagram of the region C in fig. 14 (it can be understood that fig. 17 only schematically illustrates a partial film-layer diagram of a first transistor, a second transistor and a third transistor, which is to clearly illustrate the technical solution of this embodiment, the first transistor, the second transistor and the third transistor are illustrated together, and do not represent actual arrangement positions of the first transistor, the second transistor and the third transistor in the display panel, in an embodiment, the arrangement positions and connection relationships of the first transistor, the second transistor and the third transistor are determined according to arrangements of a driving circuit and a pixel circuit), in this embodiment, the third transistor 60 is a driving transistor of the pixel circuit 40, where S2 < S5.

This embodiment explains that the second area S2 defined by the second gate 30G of the second transistor 30 in the driving circuit 50 is smaller than the fifth area S5 defined by the fifth gate 60G of the third transistor 60 in the pixel circuit 40. When the third transistor 60 of the oxide semiconductor transistor is a driving transistor of the pixel circuit 40, since the driving transistor is a core element of the pixel circuit 40, the pixel circuit 40 is generally supplied with a driving current, before the driving current is supplied to the display pixel 400 of the pixel circuit 40, it is necessary to store the data voltage signal through the gate of the driving transistor, therefore, the present embodiment provides that the fifth area S5 defined by the fifth gate 60G of the third transistor 60 used as the driving transistor is larger, the length L5 of the channel region of the third transistor 60 of the oxide semiconductor transistor may be lengthened as appropriate (as shown in figure 17), the third transistor 60 used as the driving transistor can have a relatively stable threshold voltage, and the stability of the gate potential can be improved, which is favorable for better realizing the gate storage of the data voltage signal of the driving transistor.

Alternatively, as shown in fig. 8, fig. 8 is a schematic structural diagram of a pixel circuit 40 according to an embodiment of the present invention, where the pixel circuit 40 includes a plurality of switching transistors and driving transistors, a storage capacitor, and a light emitting diode OLED (7T1C), and taking the structure of the pixel circuit 40 as an example, the third transistor 60 of an oxide semiconductor transistor may be the driving transistor M3 in the pixel circuit 40.

In some alternative embodiments, please refer to fig. 14 and 18 in combination, fig. 18 is another partial film cross-sectional structure diagram of the region C in fig. 14, in this embodiment, the third transistor 60 further includes a sixth gate 60G2, in a direction Z perpendicular to the substrate 10, a distance between the fifth gate 60G and the third active layer 601 is D5, a channel region of the third transistor 60 defined by the fifth gate 60G is a fifth channel region, a length of the fifth channel region is L5, and a fifth area S5 is L5 × D5; in the direction Z perpendicular to the substrate base plate 10, the distance between the sixth gate 60G2 and the third active layer 601 is D6, D5 < D6; the channel region of the third transistor 60 defined by the sixth gate 60G2 is a sixth channel region, the length of the sixth channel region is L6, the sixth channel region is a region where the third active layer 601 of the third transistor 60 overlaps the sixth gate 60G2, and the length of the sixth channel region is the length of the sixth channel region of the third transistor 60 in the current transmission direction between the third source 60S and the third drain 60D. The channel region of the third transistor 60 defined by the sixth gate 60G2 is a sixth channel region, and the length of the sixth channel region is L6; a sixth area S6 ═ L6 × D6; wherein S5 < S6.

The present embodiment explains that the third transistor 60 of the oxide semiconductor transistor in the pixel circuit 40 may be a double-gate transistor, the third transistor 60 includes a fifth gate 60G and a sixth gate 60G2, and in the direction Z perpendicular to the substrate 10, the distance D6 between the sixth gate 60G2 and the third active layer 601 is greater than the distance D5 between the fifth gate 60G and the third active layer 601, that is, the double-gate structure of the third transistor 60 includes two control gates, the fifth gate 60G is a main gate, the sixth gate 60G2 is an auxiliary gate, which may be considered as a series connection of two single-gate transistors from the structural point of view, and the added sixth gate 60G2 has a certain shielding effect, so that the feedback capacitance between the drain and the fifth gate 60G can be small, which is beneficial to improve the display quality of the display panel. In addition, the present embodiment is disposed in the direction Z perpendicular to the substrate base plate 10, and the distance D6 between the sixth gate 60G2 and the third active layer 601 is greater than the distance D5 between the fifth gate 60G and the third active layer 601, that is, the insulating layer between the sixth gate 60G2 and the third active layer 601 is set to be thicker, which can protect the third active layer 601.

In some alternative embodiments, with continued reference to fig. 8, 14 and 18, in the present embodiment, the third transistor 60 is a switching transistor of the pixel circuit 40, where S6 < S4.

The present embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a switch transistor, compared with the second transistor 30 in the driving circuit 50, the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 in the dual-gate structure is smaller than the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 in the dual-gate structure, and since the structure of more pixel circuits is more complicated within the display area of the display panel 000, when the third transistor 60 is used as a switch transistor, the present embodiment makes the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 in the pixel circuit 40 smaller, so that the load caused by the parasitic capacitance of the pixel circuit 40 can be reduced, which is beneficial to improving the response speed of the pixel circuit 40 and reducing the problem; the driving circuit 50 is generally disposed at the left edge and the right edge of the display panel 000, or only at a single edge of the display panel 000, or at other positions in the display panel 000, and the space that can be disposed is relatively large, so that the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 is set to be large, that is, S6 < S4, which is beneficial to improving the reliability of the driving circuit 50.

In some alternative embodiments, with continued reference to fig. 8, 14 and 18, in the present embodiment, the third transistor 60 is a switching transistor of the pixel circuit 40, wherein S4-S2 > S6-S5.

The present embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a switching transistor, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 of the oxide semiconductor transistor of the double gate structure is smaller than the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the oxide semiconductor transistor of the double gate structure and the second area S2 defined by the second gate 30G of the second transistor 30 of the oxide semiconductor transistor of the double gate structure than the second transistor 30 of the driving circuit 50 in comparison with the second transistor 30 of the driving circuit 50, and since the structure of the pixel circuit is more complicated within the display area of the display panel 000, the present embodiment makes the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 and the fifth area S5 defined by the fifth gate 60G smaller in the pixel circuit 40 when the third transistor 60 is used as a switching transistor, namely, the difference between S6 and S5 is small, so that the load caused by the parasitic capacitance of the pixel circuit 40 can be reduced, the response speed of the pixel circuit 40 can be improved, and the hysteresis problem can be reduced; the driving circuit 50 is generally disposed at the left edge and the right edge of the display panel 000, or only at a single edge of the display panel 000, or at other positions in the display panel 000, and the layout space is relatively large, so that the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 and the second area S2 defined by the second gate 30G are both large, that is, the difference between S4 and S2 is also large, so that S4-S2 > S6-S5, which is beneficial to improving the reliability of the driving circuit 50.

In some alternative embodiments, please refer to fig. 8, fig. 14 and fig. 19 in combination, fig. 19 is another partial film cross-sectional structure diagram of the region C in fig. 14, in which in the present embodiment, the third transistor 60 is a driving transistor of the pixel circuit 40, where S6 > S4.

This embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor, the fourth area S4 defined by the fourth gate 30G2 (auxiliary gate) of the second transistor 30 in the driving circuit 50 is smaller than the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 in the pixel circuit 40. When the third transistor 60 of the oxide semiconductor transistor is a driving transistor of the pixel circuit 40, since the driving transistor is a core element of the pixel circuit 40, the pixel circuit 40 is generally supplied with a driving current, before the driving current is supplied to the display pixel 400 of the pixel circuit 40, it is necessary to store the data voltage signal through the gate of the driving transistor, therefore, the present embodiment provides that the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 used as the driving transistor is large, the length L6 of the channel region of the third transistor 60 of the oxide semiconductor transistor may be appropriately lengthened (as shown in fig 19), the third transistor 60 used as the driving transistor can have a relatively stable threshold voltage, and the stability of the gate potential of the driving transistor can be improved, which is favorable for better realizing the gate storage of the data voltage signal of the driving transistor.

In some alternative embodiments, referring to fig. 8, fig. 14 and fig. 20 in combination, fig. 20 is another partial film cross-sectional structure diagram of the region C in fig. 14, in this embodiment, the pixel circuit 40 further includes a first capacitor C1, and the first capacitor C1 is used for storing the data voltage transmitted to the gate of the third transistor 60, wherein the sixth gate 60G2 (auxiliary gate) of the third transistor 60 is multiplexed as one plate of the first capacitor C1, optionally, the other plate of the first capacitor C1 may be disposed at the same layer as the other metal conductive film and opposite to the sixth gate 60G2, as shown in fig. 20, the other plate of the first capacitor C1 may be disposed at the same layer as the first gate 20G of the first transistor 20.

The embodiment explains that the pixel circuit 40 may further include a first capacitor C1 serving as a storage capacitor for storing the data voltage transmitted to the gate of the third transistor 60, the sixth gate 60G2 (auxiliary gate) of the third transistor 60 is multiplexed as one plate of the first capacitor C1, and since the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 in the pixel circuit 40 is larger than the fourth area S4 defined by the fourth gate 30G2 (auxiliary gate) of the second transistor 30 in the driving circuit 50, the relative areas of the two plates of the first capacitor C1 may be larger, which is beneficial to improve the storage capability of the first capacitor C1, make the storage capacitor have a better storage capability, and improve the driving effect of the pixel circuit 40.

Optionally, as shown in fig. 8, fig. 8 is a schematic structural diagram of a pixel circuit 40 according to an embodiment of the present invention, where the pixel circuit 40 includes a plurality of switching transistors and driving transistors, a storage capacitor, and a light emitting diode OLED (7T1C), and taking the structure of the pixel circuit 40 as an example, the first capacitor may be the storage capacitor Cst in the pixel circuit 40.

In some optional embodiments, please refer to fig. 14 and 21 in combination, fig. 21 is another partial film cross-sectional structure diagram of the region C in fig. 14, in this embodiment, the driving circuit 50 further includes a second capacitor C2, wherein the fourth gate 30G2 is multiplexed as one plate of the second capacitor C2, optionally, the other plate of the second capacitor C2 may be disposed at the same layer as the other metal conductive film and opposite to the fourth gate 30G2, as shown in fig. 21, the other plate of the second capacitor C2 may be disposed at the same layer as the first gate 20G of the first transistor 20, and the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2.

The embodiment explains that the driving circuit 50 further includes a second capacitor C2, the second transistor 30 in the driving circuit 50 is electrically connected to the second capacitor C2, and the fourth gate 30G2 of the second transistor 30 can be multiplexed as one plate of the second capacitor C2. In the present embodiment, the capacitance value of the first capacitor C1 is set to be greater than that of the second capacitor C2, since the first capacitor C1 is a storage capacitor in the pixel circuit 40, which needs to play a role of storing the data voltage signal, and the capability of storing the data voltage signal directly determines the driving current of the light emitting element in the display pixel 400, a larger capacitance value is needed for the first capacitor C1 used as the storage capacitor in the pixel circuit 40, so that the first capacitor C1 has a higher storage capability, and the second capacitor C2 in the driving circuit 50 is generally set for stabilizing the node potential, and the requirement for the storage capability is lower than that of the first capacitor C1 used as the storage capacitor in the pixel circuit 40, so that the capacitance value of the first capacitor C1 is set to be greater than that of the second capacitor C2, and the first capacitor C1 has a higher storage capability, it is also possible to satisfy the requirement of stabilizing the node potential in the drive circuit 50.

In some alternative embodiments, with continued reference to fig. 8, 14 and 21, the third transistor 60 is a driving transistor of the pixel circuit 40, wherein S4-S2 < S6-S5.

The present embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 of the oxide semiconductor transistor of the double-gate structure and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 is larger than the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the oxide semiconductor transistor of the double-gate structure and the second area S2 defined by the second gate 30G of the second transistor 30, compared to the second transistor 30 in the driving circuit 50, when the third transistor 60 of the oxide semiconductor transistor is a driving transistor of the pixel circuit 40, since the driving transistor is a core element of the pixel circuit 40, the driving current is generally supplied to the pixel circuit 40, and a data writing stage is required before the driving current is supplied to the display pixel 400 of the pixel circuit 40, therefore, in the present embodiment, the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 used as the driving transistor and the fifth area S5 defined by the fifth gate 60G are both large, lengths L5 and L6 (as shown in fig. 21) of the channel region of the third transistor 60 of the oxide semiconductor transistor can be appropriately lengthened, so that S6-S5 > S4-S2, the third transistor 60 used as the driving transistor can have a stable threshold voltage, the stability of the gate potential of the driving transistor can be improved, and the gate of the driving transistor can be better used for storing the data voltage signal.

In some alternative embodiments, please refer to fig. 22 and 23 in combination, fig. 22 is another schematic plan view of a display panel according to an embodiment of the present invention, fig. 23 is a partial film sectional structure diagram of a region D in fig. 22 (it can be understood that fig. 23 only schematically illustrates a partial film diagram of a first transistor, a second transistor, a third transistor, and a fourth transistor, which is to clearly illustrate the technical solution of the present embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor are illustrated together and do not represent actual arrangement positions of the first transistor, the second transistor, the third transistor, and the fourth transistor in the display panel, and in a specific implementation, the arrangement positions and connection relationships of the first transistor, the second transistor, the third transistor, and the fourth transistor are determined according to the arrangement of the driving circuit and the pixel circuit), in the display panel 000 provided in the present embodiment, the pixel circuit 40 further includes a fourth transistor 70;

the fourth transistor 70 includes a seventh gate electrode 70G, a fourth active layer 701, a fourth source electrode 70S, and a fourth drain electrode 70D, the fourth active layer 701 including an oxide semiconductor;

in the direction Z perpendicular to the substrate base plate 10, a distance between the seventh gate 70G and the fourth active layer 701 is D7, a channel region of the fourth transistor 70 defined by the seventh gate 70G is a seventh channel region, a length of the seventh channel region is L7, and a seventh area S7 is L7 × D7;

the fourth transistor 70 further includes an eighth gate 70G2, a distance between the eighth gate 70G2 and the fourth active layer 701 in the direction Z perpendicular to the substrate 10 is D8, a channel region of the fourth transistor 70 defined by the eighth gate 70G2 is an eighth channel region, a length of the eighth channel region is L8, and an eighth area S8 is L8 × D8; wherein D7 < D8, S7 < S8.

This embodiment explains that the pixel circuit 40 further includes a fourth transistor 70, the fourth transistor 70 includes a seventh gate 70G, a fourth active layer 701, a fourth source 70S and a fourth drain 70D, the fourth active layer 701 includes an oxide semiconductor, i.e., the fourth transistor 70 is an oxide semiconductor transistor, and the oxide semiconductor material is, for example, amorphous indium Gallium Zinc oxide (igzo Zinc oxide). The channel region of the fourth transistor 70 defined by the seventh gate 70G of the fourth transistor 70 is a seventh channel region, and the length of the seventh channel region is L7, where the seventh channel region of the fourth transistor 70 is a region where the fourth active layer 701 of the fourth transistor 70 overlaps the seventh gate 70G, and the length of the seventh channel region of the fourth transistor 70 is the length of the seventh channel region of the fourth transistor 70 in the current transmission direction between the fourth source 70S and the fourth drain 70D. The fourth transistor 70 may be a transistor with a double gate structure, the fourth transistor 70 further includes an eighth gate 70G2, a distance between the eighth gate 70G2 and the fourth active layer 701 in a direction Z perpendicular to the substrate 10 is D8, a channel region of the fourth transistor 70 defined by the eighth gate 70G2 is an eighth channel region, and a length of the eighth channel region is L8, where the eighth channel region of the fourth transistor 70 is a region where the fourth active layer 701 of the fourth transistor 70 overlaps the eighth gate 70G2, and the length of the eighth channel region of the fourth transistor 70 is a length of the eighth channel region of the fourth transistor 70 in a current transmission direction between the fourth source 70S and the fourth drain 70D. The pixel circuit 40 of the present embodiment may include the first transistor 20 of the silicon transistor, the third transistor 60 of the oxide semiconductor transistor, and the fourth transistor 70 of the oxide semiconductor transistor in the double-gate structure, that is, the fourth transistor 70 of the double-gate structure includes two control gates, the seventh gate 70G is a main gate, the eighth gate 70G2 is an auxiliary gate, which may be considered as a series connection of two single-gate transistors from the structural point of view, and the added eighth gate 70G2 has a certain shielding effect, so that the feedback capacitance between the drain and the seventh gate 70G may become small, which is beneficial to improving the display quality of the display panel.

In the present embodiment, the distance D7 between the seventh gate 70G (main gate) and the fourth active layer 701 is smaller than the distance D8 between the eighth gate 70G2 (auxiliary gate) and the fourth active layer 701, the seventh area S7 defined by the seventh gate 70G is smaller than the eighth area S8 defined by the eighth gate 70G2, and the insulating layer between the eighth gate 70G2 and the fourth active layer 701 can be made thicker, which can protect the fourth active layer 701.

In some alternative embodiments, please continue to refer to fig. 8, fig. 22 and fig. 23 in combination, in the present embodiment, the third transistor 60 is a driving transistor, and the fourth transistor 70 is a switching transistor, where S6 > S8.

The present embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor and the fourth transistor 70 is used as a switching transistor, the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) of the fourth transistor 70 is smaller than the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60. When the third transistor 60 of the oxide semiconductor transistor is a driving transistor of the pixel circuit 40, since the driving transistor is a core element of the pixel circuit 40, the pixel circuit 40 is generally supplied with a driving current, before the driving current is supplied to the display pixel 400 of the pixel circuit 40, it is necessary to store the data voltage signal through the gate of the driving transistor, therefore, the present embodiment provides that the sixth area S6 defined by the sixth gate 60G2 (sub gate) of the third transistor 60 used as the drive transistor is larger, the length L6 of the channel region of the third transistor 60 of the oxide semiconductor transistor may be lengthened as appropriate (as shown in figure 23), the third transistor 60 used as the driving transistor can have a relatively stable threshold voltage, and the stability of the gate potential of the driving transistor can be improved, which is favorable for better realizing the gate storage of the data voltage signal of the driving transistor. When the fourth transistor 70 of the oxide semiconductor transistor is used as a switching transistor of the pixel circuit 40, the fourth transistor 70 generally only functions as a switch, so that the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) of the fourth transistor 70 does not need to be too large, which can save the space of the panel and is beneficial to further improving the PPI of the display panel 000.

Optionally, as shown in fig. 8, fig. 8 is a schematic structural diagram of a pixel circuit 40 according to an embodiment of the present invention, where the pixel circuit 40 includes a plurality of switching transistors and driving transistors, a storage capacitor, and a light emitting diode OLED (7T1C), and taking the structure of the pixel circuit 40 as an example, the third transistor 60 of the oxide semiconductor transistor may be the driving transistor M3 in the pixel circuit 40, and the fourth transistor 70 of the oxide semiconductor transistor may be any one or more of the switching transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit 40.

In some alternative embodiments, with continuing reference to fig. 8, 22 and 23, in the present embodiment, the third transistor 60 is a driving transistor and the fourth transistor 70 is a switching transistor, wherein S6-S5 > S8-S7.

The present embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor and the fourth transistor 70 is used as a switching transistor, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 of the oxide semiconductor transistor of the double-gate structure is larger than the difference between the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) of the fourth transistor 70 of the oxide semiconductor transistor of the double-gate structure and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70, when the third transistor 60 of the oxide semiconductor transistor is the driving transistor of the pixel circuit 40, since the driving transistor is a core element of the pixel circuit 40, the driving current is generally supplied to the pixel circuit 40, and the data writing stage is required before the driving current is supplied to the display pixel 400 of the pixel circuit 40, therefore, in the present embodiment, the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 used as the driving transistor and the fifth area S5 defined by the fifth gate 60G are both large, lengths L5 and L6 (as shown in fig. 23) of the channel region of the third transistor 60 of the oxide semiconductor transistor can be appropriately lengthened, so that S6-S5 > S8-S7, the third transistor 60 used as the driving transistor can have a stable threshold voltage, the stability of the gate potential of the driving transistor can be improved, and the gate of the driving transistor can be better used for storing the data voltage signal. When the fourth transistor 70 of the oxide semiconductor transistor is used as a switch transistor of the pixel circuit 40, the fourth transistor 70 generally only functions as a switch, and therefore, neither the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 nor the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) needs to be too large, which can save the space of the panel and is beneficial to further increasing the PPI of the display panel 000.

In some alternative embodiments, with continuing reference to fig. 22 and 23, in the pixel circuit 40, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 of the oxide semiconductor transistor with the dual-gate structure and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 is S6-S5; in the driving circuit 50, the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the oxide semiconductor transistor of the double-gate structure and the second area S2 defined by the second gate 30G of the second transistor 30 is S4 to S2; in the pixel circuit 40, the difference between the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) of the fourth transistor 70 of the oxide semiconductor transistor of the double gate structure and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 is S8 to S7, and (S6 to S5) - (S8 to S7) > (S8 to S7) - (S4 to S2), i.e., (S6 to S5) + (S4 to S2) > 2(S8 to S7).

The present embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor, compared with the fourth transistor 70 in the pixel circuit 40 used as a switching transistor, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 of the double-gate structure oxide semiconductor transistor and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 is larger than the difference between the eighth area S8 defined by the eighth gate 70G2 of the fourth transistor 70 of the double-gate structure oxide semiconductor transistor and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70, and therefore, since the display panel 000 has a complicated structure in the display area, the present embodiment makes the eighth area S8 defined by the eighth gate 70G2 of the fourth transistor 70 in the pixel circuit 40 and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 when the fourth transistor 70 is used as a switching transistor The products S7 are all small, i.e., the difference between S8 and S7 is also small, so that the load caused by the parasitic capacitance of the pixel circuit 40 can be reduced, which is beneficial to improving the response speed of the pixel circuit 40 and reducing the hysteresis problem. Since the eighth area S8 defined by the eighth gate 70G2 of the fourth transistor 70 and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 are both smaller, the difference between the eighth area S8 defined by the eighth gate 70G2 of the fourth transistor 70 of the oxide semiconductor transistor of the dual gate structure and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 is larger than the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the oxide semiconductor transistor of the dual gate structure and the second area S2 defined by the second gate 30G of the second transistor 30 of the oxide semiconductor transistor of the dual gate structure, while the difference between (S8-S7) and (S4-S2) is not set to be too large, i.e., the difference between (S6-S5) and (S8-S7) is larger than the difference between (S8-S7) and (S4-S2), which is advantageous for the improvement of the panel, the reliability of the pixel circuit 40 can also be improved.

In some alternative embodiments, please refer to fig. 24 and fig. 25 in combination, where fig. 24 is a schematic plan view of another display panel according to an embodiment of the present invention, and fig. 25 is a partial enlarged view of an area E in fig. 24 (it can be understood that fig. 25 only schematically illustrates a partial top view of one first transistor and one second transistor, and in order to clearly illustrate the technical solution of this embodiment, the first transistor and the second transistor are illustrated together, but not represent actual arrangement positions of the first transistor and the second transistor in the display panel, and in a specific implementation, the arrangement positions and connection relationships of the first transistor and the second transistor are determined according to the arrangement of the driving circuit and the pixel circuit) And the length L1 direction of the channel region of the first transistor 20 is less than 45 degrees to the first direction Y at an angle α 1.

The embodiment explains that the first transistor 20 and the second transistor 30 of the display panel 000 are formed on the substrate 10, the first transistor 20 includes a first active layer 201, a first gate 20G, a first source 20S and a first drain 20D, the first active layer 201 includes silicon, i.e., the first transistor 20 is a silicon transistor, and the silicon may be polysilicon deposited by using a Low Temperature method, i.e., LTPS (Low Temperature polysilicon) or Low Temperature polysilicon. The length of the channel region of the first transistor 20 is L1, wherein the channel region of the first transistor 20 is a region where the first active layer 201 of the first transistor 20 overlaps the first gate electrode 20G, and the length L1 of the channel region of the first transistor 20 is the length of the channel region of the first transistor 20 in the current transmission direction (e.g., the direction X1 in fig. 25) between the first source electrode 20S and the first drain electrode 20D. The second transistor 30 includes a second active layer 301, a second gate 30G, a second source 30S and a second drain 30D, the second active layer 301 includes an oxide semiconductor, i.e., the second transistor 30 is an oxide semiconductor transistor, and the oxide semiconductor material is amorphous indium Gallium Zinc oxide (igzo). The length of the channel region of the second transistor 30 is L2, wherein the channel region of the second transistor 30 is a region where the second active layer 301 of the second transistor 30 overlaps the second gate electrode 30G, and the length of the channel region of the second transistor 30 is the length of the channel region of the second transistor 30 in the current transmission direction (e.g., the direction X2 in fig. 25) between the second source electrode 30S and the second drain electrode 30D. The display panel 000 of the embodiment may be a foldable display panel, the foldable display panel includes a bending axis 80 extending along a first direction Y, and an angle α 2 between a length direction X2 of a channel region of the second transistor 30 and the first direction Y is greater than 45 degrees, an angle α 1 between a length direction X1 of a channel region of the first transistor 20 and the first direction Y is less than 45 degrees, and the second transistor 30 of the oxide semiconductor transistor has better bending performance, so that the embodiment sets an angle α 2 between a length direction X2 of a channel region of the second transistor 30 and the first direction Y to be greater than 45 degrees, that is, the angle α 2 is more inclined to 90 degrees, and an angle α 1 between a length direction X1 of a channel region of the first transistor 20 and the first direction Y to be less than 45 degrees, that is, the angle α 1 is more inclined to 0 degrees, so that the second transistor 30 with better bending performance can pass through a region where the bending axis 80 is located as much as possible, bear larger bending pressure, and the first transistor 20 with poorer bending performance is prevented from penetrating through the area where the bending shaft 80 is located as much as possible, so that the failure of the first transistor 20 due to bending can be avoided, and the product yield is improved.

In some alternative embodiments, please refer to fig. 24 and fig. 26 in combination, where fig. 26 is another partial enlarged view of the region E in fig. 24 (it is understood that fig. 26 only schematically illustrates a partial top view of a first transistor and a second transistor, and the first transistor and the second transistor are illustrated together for clarity of illustrating the technical solution of this embodiment, and do not represent actual arrangement positions of the first transistor and the second transistor in the display panel, in a specific implementation, the arrangement positions and connection relationships of the first transistor and the second transistor are determined according to the arrangement of the driving circuit and the pixel circuit), in this embodiment, the length direction X2 of the channel region of the second transistor 30 is perpendicular to the first direction Y; the length direction X1 of the channel region of the first transistor 20 is parallel to the first direction Y.

The embodiment explains that the first transistor 20 and the second transistor 30 of the display panel 000 are formed on the substrate 10, the first transistor 20 includes a first active layer 201, a first gate 20G, a first source 20S and a first drain 20D, the first active layer 201 includes silicon, i.e., the first transistor 20 is a silicon transistor, and the silicon may be polysilicon deposited by using a Low Temperature method, i.e., LTPS (Low Temperature polysilicon) or Low Temperature polysilicon. The length of the channel region of the first transistor 20 is L1, wherein the channel region of the first transistor 20 is a region where the first active layer 201 of the first transistor 20 overlaps the first gate electrode 20G, and the length L1 of the channel region of the first transistor 20 is the length of the channel region of the first transistor 20 in the current transmission direction (e.g., the direction X1 in fig. 26) between the first source electrode 20S and the first drain electrode 20D. The second transistor 30 includes a second active layer 301, a second gate 30G, a second source 30S and a second drain 30D, the second active layer 301 includes an oxide semiconductor, i.e., the second transistor 30 is an oxide semiconductor transistor, and the oxide semiconductor material is amorphous indium Gallium Zinc oxide (igzo). The length of the channel region of the second transistor 30 is L2, wherein the channel region of the second transistor 30 is a region where the second active layer 301 of the second transistor 30 overlaps the second gate electrode 30G, and the length of the channel region of the second transistor 30 is the length of the channel region of the second transistor 30 in the current transmission direction (e.g., the direction X2 in fig. 26) between the second source electrode 30S and the second drain electrode 30D. The display panel 000 of the embodiment may be a foldable display panel, the foldable display panel includes a bending axis 80 extending along a first direction Y, and a length direction X2 of a channel region of the second transistor 30 is perpendicular to the first direction, a length direction X1 of a channel region of the first transistor 20 is parallel to the first direction Y, and the second transistor 30 of the oxide semiconductor transistor has better bending performance, so that the included angle between the length direction X2 of the channel region of the second transistor 30 and the first direction Y is 90 degrees, and the included angle between the length direction X1 of the channel region of the first transistor 20 and the first direction Y is 0 degree, which may further enable the second transistor 30 with better bending performance to pass through a region where the bending axis 80 is located as much as possible to bear a larger bending pressure, and the first transistor 20 with poorer bending performance avoids passing through a region where the bending axis 80 is located as much as possible, the failure of the first transistor 20 due to bending can be better avoided, and the product yield can be ensured.

In some alternative embodiments, please refer to fig. 27, where fig. 27 is a schematic plane structure diagram of a display device according to an embodiment of the present invention, and the display device 111 according to this embodiment includes the display panel 000 according to the above embodiment of the present invention. The embodiment of fig. 27 is only an example of a mobile phone, and the display device 111 is described, it is understood that the display device 111 provided in the embodiment of the present invention may be another display device 111 having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel 000 in the above embodiments, which is not described herein again.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the utility model. The scope of the utility model is defined by the appended claims.

Claims

1. A display panel, comprising:

a substrate base plate;

a third transistor and a fourth transistor formed on the substrate, the third transistor including a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode, the third transistor being an oxide semiconductor transistor; the fourth transistor comprises an eighth grid electrode, a fourth active layer, a fourth source electrode and a fourth drain electrode, and the fourth transistor is an oxide semiconductor transistor;

in a direction perpendicular to the substrate, a distance between the sixth gate and the third active layer is D6, a channel region of the third transistor defined by the sixth gate is a sixth channel region, a length of the sixth channel region is L6, and a sixth area S6 is L6 × D6;

in a direction perpendicular to the substrate, a distance between the eighth gate and the fourth active layer is D8, a channel region of the fourth transistor defined by the eighth gate is an eighth channel region, a length of the eighth channel region is L8, and an eighth area S8 is L8 × D8;

the display panel comprises a pixel circuit and a driving circuit for providing a driving signal for the pixel circuit, wherein the third transistor is a driving transistor of the pixel circuit, and the fourth transistor is a switching transistor of the pixel circuit; wherein the content of the first and second substances,

S6＞S8。

2. the display panel according to claim 1,

the third transistor further comprises a fifth gate, a distance between the fifth gate and the third active layer in a direction perpendicular to the substrate is D5, a channel region of the third transistor defined by the fifth gate is a fifth channel region, the length of the fifth channel region is L5, and a fifth area S5 is L5 × D5;

the fourth transistor further comprises a seventh gate, a distance between the seventh gate and the fourth active layer in a direction perpendicular to the substrate is D7, a channel region of the fourth transistor defined by the seventh gate is a seventh channel region, a length of the seventh channel region is L7, and a seventh area S7 is L7 × D7; wherein, the first and the second end of the pipe are connected with each other,

D5＜D6，S5＜S6；

D7＜D8，S7＜S8。

3. the display panel according to claim 2,

S6-S5＞S8-S7。

4. the display panel according to claim 3,

the driving circuit comprises a second transistor, wherein the second transistor comprises a second active layer, a second grid electrode, a second source electrode and a second drain electrode, and the second transistor is an oxide semiconductor transistor;

the length of a channel region of the second transistor is L2, the distance between the second gate and the second active layer in the direction perpendicular to the substrate is D2, and S2 is L2 × D2; wherein the content of the first and second substances,

S2＜S5。

5. the display panel according to claim 4,

the second transistor further comprises a fourth gate, and the distance between the fourth gate and the second active layer in the direction perpendicular to the substrate base plate is D4, D2 < D4;

the channel region of the second transistor defined by the second gate is a second channel region, and the length of the second channel region is L2;

the channel region of the second transistor defined by the fourth gate is a fourth channel region, and the length of the fourth channel region is L4; wherein the content of the first and second substances,

the fourth area S4 ═ L4 × D4, S2 < S4.

6. The display panel according to claim 5,

S6＞S4。

7. the display panel according to claim 5,

S4-S2＜S6-S5。

8. the display panel according to claim 5,

(S6-S5)+(S4-S2)＞2(S8-S7)。

9. the display panel according to claim 2,

the display panel further includes a first transistor, the pixel circuit includes the first transistor or the driving circuit includes the first transistor;

the first transistor comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, and the first transistor is a silicon transistor; the length of a channel region of the first transistor is L1, the distance between the first gate and the first active layer in the direction perpendicular to the substrate is D1, and a first area S1 is L1 × D1; wherein, the first and the second end of the pipe are connected with each other,

S1＜S5。

10. a display device characterized by comprising the display panel according to any one of claims 1 to 9.