CN117727764A - Display panel and display device - Google Patents

Abstract

The display panel and the display device provided by the present disclosure include: a substrate, a first shift register and a second shift register on the substrate; the first shift register and the second shift register comprise a first output transistor, a second output transistor and a plurality of switching holes; the transfer hole is used for bridging the active region of the first output transistor and the active region of the second output transistor through the conductive layer; the number of the switching holes in the second shift register is larger than that in the first shift register; and/or the size of the transfer hole in the second shift register is larger than that of the transfer hole in the first shift register; the threshold voltage of the first output transistor in the second shift register is negatively biased compared with the threshold voltage of the first output transistor in the first shift register; the threshold voltage of the second output transistor in the second shift register is negatively biased compared to the threshold voltage of the second output transistor in the first shift register.

Description

Display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a display device.

Background

With the rapid development of display technology, display panels have shown a trend of high integration and low cost. The gate driving (Gate Driver On Array, GOA) technology of the array substrate has been widely used in various display panels, and the performance of the existing gate driving circuit is unstable due to the influence of factors such as threshold voltage drift of the thin film transistor, so as to influence the display quality of the display panel. For example, in the process of electrifying the gate driving circuit in an electrostatic field or at a high temperature, the threshold voltage of the thin film transistor in the gate driving circuit is easy to generate forward bias, so that electric leakage is caused, signal abnormality is caused, and the display effect is further affected.

Disclosure of Invention

Some embodiments of the present disclosure provide a display panel, including: a substrate, a first shift register and a second shift register on the substrate; the first shift register and the second shift register comprise a first output transistor, a second output transistor and a plurality of transfer holes; the transfer hole is used for bridging the active region of the first output transistor and the active region of the second output transistor through the conducting layer; the number of the switching holes in the second shift register is larger than that of the switching holes in the first shift register; and/or the size of the transfer hole in the second shift register is larger than that of the transfer hole in the first shift register;

the threshold voltage of the first output transistor in the second shift register is negatively biased compared to the threshold voltage of the first output transistor in the first shift register; the threshold voltage of the second output transistor in the second shift register is negatively biased compared to the threshold voltage of the second output transistor in the first shift register.

In some possible embodiments of the disclosure, a front projection of a portion of the via hole on the substrate overlaps with a front projection of an active region of the first output transistor and an active region of the second output transistor on the substrate.

In some possible embodiments of the present disclosure, the size of the transfer aperture in the first shift register is between 2.3 microns and 3.5 microns; the size of the transfer hole in the second shift register is between 2.5 micrometers and 4 micrometers.

In some possible embodiments of the present disclosure, the second shift register further includes a plurality of virtual switch holes; the orthographic projection of the virtual transfer hole on the substrate is adjacent to the orthographic projection of the active layer of the first output transistor and the active layer of the second output transistor on the substrate.

In some possible embodiments of the present disclosure, the gate of the first output transistor is coupled to a first node, the first pole of the first output transistor is coupled to a first level signal line, and the second pole of the first output transistor is coupled to a cascade output signal line;

the gate of the second output transistor is coupled to a second node, the first pole of the second output transistor is coupled to a second level signal line, and the second pole of the second output transistor is coupled to the cascade output signal line.

In some possible embodiments of the present disclosure, further comprising: the semiconductor layer is located on the substrate, the gate insulating layer is located the semiconductor layer deviates from substrate one side, the gate conducting layer is located the gate insulating layer deviates from substrate one side, the first insulating layer is located the gate conducting layer deviates from substrate one side, the first conducting layer is located the first insulating layer deviates from substrate one side, the second insulating layer is located the first conducting layer deviates from substrate one side, the second conducting layer is located the second insulating layer deviates from substrate one side.

In some possible embodiments of the present disclosure, the gate conductive layer includes: a gate of the first output transistor, a gate of the second output transistor; the semiconductor layer includes: an active region of the first output transistor and an active region of the second output transistor; the active region of the first output transistor includes: a first pole and a second pole of the first output transistor; the active region of the second output transistor includes: a first pole and a second pole of the second output transistor;

the conductive layer includes: the first conductive layer and the second conductive layer;

the first level signal line and the second level signal line are positioned on the second conductive layer; the cascade output signal line is located at the first conductive layer or the second conductive layer.

In some possible embodiments of the present disclosure, when the cascade output signal line is located on the first conductive layer, a front projection of a portion of the transfer hole on the substrate overlaps with a front projection of the cascade output signal line on the substrate.

In some possible embodiments of the present disclosure, when the cascade output signal line is located on the second conductive layer, a front projection of a portion of the transfer hole on the substrate overlaps with a front projection of the gate conductive layer on the substrate.

Some embodiments of the present disclosure provide a display device including the above display panel.

Drawings

Fig. 1 is a schematic diagram of some structures of a display device according to an embodiment of the disclosure;

fig. 2 is a schematic diagram of other structures of a display device according to an embodiment of the disclosure;

fig. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the disclosure;

fig. 4 is a schematic diagram of other structures of a thin film transistor according to an embodiment of the disclosure;

fig. 5 is a schematic view of still other structures of a thin film transistor according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a thin film transistor according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram illustrating some configurations of a first shift register according to an embodiment of the disclosure;

FIG. 8 is a schematic diagram illustrating a second shift register according to an embodiment of the disclosure;

FIG. 9 is a schematic diagram illustrating other structures of a second shift register according to an embodiment of the disclosure;

FIG. 10 is a schematic diagram of a second shift register according to an embodiment of the present disclosure;

fig. 11 is an equivalent circuit diagram provided by an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. And embodiments of the invention and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.

Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the dimensions and shapes of the figures in the drawings do not reflect true proportions, and are intended to illustrate the present invention only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

For example, as shown in fig. 1, the display device may include a display panel 100, a source driving circuit 120. The display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (e.g., GA1, GA2, GA3, GA 4), a plurality of data lines DA (e.g., DA1, DA2, DA 3), and a gate driving circuit 110. The gate driving circuit 110 is coupled to the gate lines GA1, GA2, GA3, GA4, respectively, and the source driving circuit 120 is coupled to the data lines DA1, DA2, DA3, respectively. Illustratively, each pixel cell includes a plurality of sub-pixels SPX. For example, the pixel unit may include red, green, and blue sub-pixels, so that color mixing can be performed by red, green, and blue to realize color display. Alternatively, the pixel unit may include red, green, blue and white sub-pixels, so that color mixing can be performed by red, green, blue and white to realize color display. Of course, in practical application, the emission color of the sub-pixels in the pixel unit may be designed and determined according to the practical application environment, which is not limited herein.

For example, the source driving circuits 120 may be provided in 2, wherein one source driving circuit 120 is connected to half of the number of data lines, and the other source driving circuit 120 is connected to the other half of the number of data lines. Of course, 3, 4, or more source driving circuits 120 may be provided, which may be determined by design according to the requirements of practical applications, and is not limited herein.

Illustratively, as shown in fig. 1, a driving transistor 01 and a pixel electrode 02 are included in each sub-pixel SPX. One row of sub-pixels SPX corresponds to one gate line, and one column of sub-pixels SPX corresponds to one data line. The gate electrode of the driving transistor 01 is electrically connected with the corresponding gate line, the source electrode of the driving transistor 01 is electrically connected with the corresponding data line, the drain electrode of the driving transistor 01 is electrically connected with the pixel electrode 02, it should be noted that the pixel array structure of the disclosure may also be a double-gate structure, that is, two gate lines are arranged between two adjacent rows of sub-pixels, the arrangement mode can reduce half of the data lines, that is, some adjacent two columns of sub-pixels contain data lines, some adjacent two columns of sub-pixels do not contain data lines, the specific sub-pixel arrangement structure and the data lines, and the arrangement mode of the scanning lines is not limited.

Illustratively, as shown in fig. 2, the display panel 100 may further include a plurality of clock signal lines, and the plurality of clock signal lines are coupled with the gate driving circuit 110. Thus, a corresponding clock signal may be input to the gate driving circuit 110 through the clock signal line, thereby loading a signal to the gate line. For example, the display panel 100 may include clock signal lines CK1 to CK12, and the clock signal lines CK1 to CK12 are coupled with the gate driving circuit 110. For example, if the display panel 100 is designed with a single gate driving circuit 110, the gate driving circuit 110 may be coupled to 12 clock signal lines CK1 to CK12. If the display panel 100 is designed with the dual gate driving circuits 110, each gate driving circuit 110 can be coupled to 12 clock signal lines CK 1-CK 12. In fig. 2, only 12 clock signal lines are taken as an example for illustration, and in practical application, the specific number of clock signal lines may be determined according to the requirements of practical application, and the present invention is not limited thereto, and for example, the number of clock signal lines may be 2, 4, 6, 8, 10, or the like, which is an integer multiple of 2. The grid driving circuit comprises a plurality of shift registers, and each shift register corresponds to at least one clock signal line.

Illustratively, the gate driving circuit generally includes a plurality of thin film transistors. The test shows that the threshold voltage of the thin film transistor has a correlation with the via hole, and the test values are shown in table 1 below. Since the polysilicon semiconductor in the thin film transistor (Thin film transistor, TFT) contains a small amount of hydrogen bonds, the small amount of hydrogen bonds may pass through the transition Kong Waiyi during the heat treatment, thereby affecting the threshold voltage of the thin film transistor. Therefore, the design difference of the via hole can affect the threshold voltage of the thin film transistor, thereby affecting the gate driving circuit and further the display quality of the display panel. How to adjust the threshold voltage of the thin film transistor, so as to improve the display effect of the display panel is a problem to be solved by those skilled in the art.

As illustrated in fig. 3 to 6, the active region 10 of the thin film transistor (e.g., TFT1, TFT2, TFT3, TFT 4) includes a source region, a drain region, and a channel region G10 between the source region and the drain region. Wherein the channel region G10 is located at the overlap of the gate conductive layer 20 and the active region 10. The thin film transistors TFT1, TFT2, TFT3 and TFT4 comprise transfer holes K1-1, K1-2 and K1-3; the distance between the center of the via hole K1-1 and the channel region G10 is a, the distance between the center of the via hole K1-2 and the channel region G10 is b, the distance between the center of the via hole K1-3 and the channel region G10 is c, and the sizes of the via holes K1-1, K1-2 and K1-3 are e. The thin film transistor TFT1 further includes 2 dummy via holes K2, and the size of the dummy via holes K2 is d. The thin film transistors TFT1, TFT2, TFT3, and TFT4 have the same channel width to length ratio W/L. The values of a, b, c, d, e in the thin film transistors TFT1, TFT2, TFT3, TFT4 are shown in table 1 below.

Units: um (um)	TFT1	TFT2	TFT3	TFT4
					a	8.5	8.5	13.2	8.5
b	5.2	5.2	7.6	5.2
					c	4.8	4.8	8.1	4.8
d	3.0*3.0	-	-	-
					e	3.0*3.0	3.0*3.0	3.0*3.0	4.0*4.0
Vth	-2.06V	-1.73V	-1.61V	-1.79V

TABLE 1

As is clear from table 1, the threshold voltages Vth of the thin film transistors TFT1, TFT2, TFT3, and TFT4 are different from each other. The thin film transistor TFT2 lacks 2 dummy transfer holes K2 compared to the thin film transistor TFT1, and the threshold voltage Vth of the thin film transistor TFT1 is negatively biased compared to the threshold voltage Vth of the thin film transistor TFT 1. The distances a, b, c between the center of the via hole and the channel region in the thin film transistor TFT2 are smaller than the distances a, b, c between the center of the via hole and the channel region in the thin film transistor TFT3, and the threshold voltage Vth of the thin film transistor TFT2 is negatively biased than the threshold voltage Vth of the thin film transistor TFT 3. The size e of the via hole in the thin film transistor TFT2 is smaller than the size e of the via hole in the thin film transistor TFT4, and the threshold voltage Vth of the thin film transistor TFT4 is negatively biased than the threshold voltage Vth of the thin film transistor TFT 2. As can be seen from the values in table 1, the larger the number of the via holes and the virtual via holes, the smaller the distances a, b, c between the centers of the via holes and the channel region, the larger the size of the via holes, and the more negative the threshold voltage Vth. Therefore, the threshold voltage of the thin film transistor is adjusted by adjusting the design of the transfer hole.

For example, if the threshold voltage of the thin film transistor is positively biased, the threshold voltage of the thin film transistor is biased as negatively as possible by increasing the number of the via holes and the virtual via holes, reducing the distance between the center of the via hole and the channel region, and increasing the size of the via hole, so that the bias voltage is neutralized by the bias voltage and the bias voltage, thereby improving the drift of the threshold voltage of the thin film transistor.

For example, if the threshold voltage of the thin film transistor is negatively biased, the threshold voltage of the thin film transistor is biased as much as possible, and then is neutralized by positive bias and negative bias, so as to improve the drift of the threshold voltage of the thin film transistor by reducing the number of the via holes and the virtual via holes, increasing the distance between the center of the via hole and the channel region, and reducing the size of the via hole.

The display panel provided in the embodiment of the disclosure, as shown in fig. 7 and 8, includes: a substrate, a first shift register 111 and a second shift register 112 on the substrate; the first shift register 111 and the second shift register 112 each include a first output transistor M1, a second output transistor M2, and a plurality of switching holes K1; the transfer hole K1 is used for bridging the active region of the first output transistor M1 and the active region of the second output transistor M2 through the conductive layer; wherein, the number of the transfer holes K1 in the second shift register 112 is greater than the number of the transfer holes K1 in the first shift register 112;

the threshold voltage of the first output transistor M1 in the second shift register 112 is negatively biased compared to the threshold voltage of the first output transistor M1 in the first shift register 111; the threshold voltage of the second output transistor M2 in the second shift register 112 is negatively biased compared to the threshold voltage of the second output transistor M2 in the first shift register 111.

According to the embodiment of the disclosure, the number of the switching holes in the second shift register is larger than that of the switching holes in the first shift register, so that the threshold voltage of the first output transistor in the second shift register is negatively biased compared with that of the first output transistor in the first shift register; the threshold voltage of the second output transistor in the second shift register is negatively biased compared with the threshold voltage of the second output transistor of the first shift register; the threshold voltage of the first output transistor and the threshold voltage of the second output transistor can be biased relatively negatively, so that influences of positive bias of the threshold voltage in the electrostatic field or high-temperature power-on process, namely neutralization of negative bias and positive bias, are avoided, electric leakage is avoided, signal abnormality is avoided, and display effect is improved.

As shown in fig. 7 and 8, the number of the transfer holes K1 on the right side of the first output transistor M1 in the first shift register 111 is 6, and the number of the transfer holes K1 on the right side of the second output transistor M2 in the first shift register 111 is 4; the number of the transfer holes K1 on the right side of the first output transistor M1 in the second shift register 112 is 5, and the number of the transfer holes K1 on the right side of the second output transistor M2 in the second shift register 112 is 10; i.e. the number of transfer holes K1 in the second shift register 112 is larger than the number of transfer holes K1 in the first shift register 111. Of course, the number of the transfer holes K1 in the first shift register 111 and the number of the transfer holes K1 in the second shift register 112 may be other values, which are not limited herein.

In some embodiments of the present disclosure, as shown in fig. 7 and 9, the size of the transfer hole K1-1 in the second shift register 112 is larger than the size of the transfer hole K1 in the first shift register 111.

Illustratively, as shown in FIGS. 7 and 9, the size of the transfer hole K1-1 in the second shift register 112 is larger than the size of the transfer hole K1-2 in the second shift register 112. The size of the transfer hole K1-2 in the second shift register 112 may be the same as the size of the transfer hole K1 in the first shift register 111, however, the size of the transfer hole K1-2 in the second shift register 112 may also be different from the size of the transfer hole K1 in the first shift register 111, which is not limited herein.

In some embodiments of the present disclosure, as shown in fig. 7 and 9, the size K1 of the transfer hole in the first shift register 111 is between 2.3 micrometers and 3.5 micrometers; the size of the transfer hole K1-1 in the second shift register 112 is between 2.5 micrometers and 4 micrometers.

Illustratively, the size of the transfer hole K1-2 in the second shift register 112 is between 2.3 microns and 3.5 microns.

In some embodiments of the present disclosure, as shown in fig. 7 to 10, the orthographic projection of the partial via K1, K1-1 on the substrate overlaps with the orthographic projection of the active region of the first output transistor M1 and the active region of the second output transistor M2 on the substrate.

In some embodiments of the present disclosure, as shown in fig. 10, the second shift register 112 further includes a plurality of virtual switch holes K2; the orthographic projection of the virtual transfer hole K2 on the substrate is adjacent to the orthographic projection of the active layer of the first output transistor M1 and the active layer of the second output transistor M2 on the substrate.

As illustrated in fig. 10, the active layer of the first output transistor M1 and the active layer of the second output transistor M2 are provided with a row of dummy via holes K2.

In some embodiments of the present disclosure, as shown in fig. 7 to 11, the gate of the first output transistor M1 is coupled to the first node N1, the first pole of the first output transistor M1 is coupled to the first level signal line VGH, and the second pole of the first output transistor M1 is coupled to the cascade output signal line Out; the gate of the second output transistor M2 is coupled to the second node N2, the first pole of the second output transistor M2 is coupled to the second level signal line VGL, and the second pole of the second output transistor M2 is coupled to the cascade output signal line Out. Fig. 11 is an equivalent circuit diagram of fig. 7 to 10.

As illustrated in fig. 7 to 11, the display panel further includes: a first clock signal line CK, a second clock signal line CB, a frame start signal line STV, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3; wherein, the gate of the first transistor T1 is coupled to the first clock signal line CK, the first pole of the first transistor T1 is coupled to the frame start signal line STV, and the second pole of the first transistor T1 is coupled to the gate of the second transistor T2; a first pole of the second transistor T2 is coupled to a second pole of the third transistor T3, and a second pole of the second transistor T2 is coupled to the first clock signal line CK; a gate of the third transistor T3 is coupled to the first clock signal line CK, and a first pole of the third transistor T3 is coupled to the second level signal line VGL; the gate of the fourth transistor T4 is coupled to the second node N2, the first pole of the fourth transistor T4 is coupled to the second pole of the fifth transistor T5, and the second pole of the fourth transistor T4 is coupled to the second clock signal line CB; the gate of the fifth transistor T5 is coupled to the second pole of the third transistor T3, and the first pole of the fifth transistor T5 is coupled to the first level signal line VGH; the first electrode of the second capacitor C2 is coupled to the second pole of the fifth transistor T5, and the second electrode of the second capacitor C2 is coupled to the second node N2; the gate of the sixth transistor T6 is coupled to the first electrode of the first capacitor C1, the first pole of the sixth transistor T6 is coupled to the second clock signal line CB, and the second pole of the sixth transistor T6 is coupled to the second electrode of the first capacitor C1; the gate of the seventh transistor T7 is coupled to the second clock signal line CB, the first pole of the seventh transistor T7 is coupled to the second pole of the sixth transistor T6, and the second pole of the seventh transistor T7 is coupled to the first node N1; the first electrode of the third capacitor C3 is coupled to the first level signal line VGH, and the second electrode of the third capacitor C3 is coupled to the first node N1; the gate of the eighth transistor T8 is coupled to the second pole of the first transistor T1, the first pole of the eighth transistor T8 is coupled to the first node N1, and the second pole of the eighth transistor T8 is coupled to the first level signal line VGH; the gate of the ninth transistor T9 is coupled to the second level signal line VGL, the first pole of the ninth transistor T9 is coupled to the gate of the fifth transistor T5, and the second pole of the ninth transistor T9 is coupled to the gate of the sixth transistor T6; the gate of the tenth transistor T10 is coupled to the second level signal line VGL, the first pole of the tenth transistor T10 is coupled to the gate of the eighth transistor T8, and the second pole of the tenth transistor T10 is coupled to the second node N2.

Illustratively, the first pole of the transistor may be its source and the second pole may be its drain. Alternatively, the first pole is its drain and the second pole is its source. And are not limited thereto.

The transistor generally adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) material as the active layer, has high mobility, can be made thinner and smaller, has lower power consumption, and the like, and can be made into low temperature polysilicon material when in implementation. This makes it possible to set the above-described transistor as an LTPS-type transistor so that the pixel circuit can realize high mobility and can be made thinner and smaller, power consumption lower, and the like.

Since the leakage current of the transistor using the metal oxide semiconductor material as the active layer is generally small, in order to reduce the leakage current, in some embodiments of the present disclosure, the material of the active layer of the at least one transistor may also include a metal oxide semiconductor material, for example, IGZO (Indium Gallium Zinc Oxide ), or may be other metal oxide semiconductor materials, which is not limited herein. This makes it possible to set the above transistor as an oxide type transistor (Oxide Thin Film Transistor) so that the leak current of the pixel circuit can be reduced.

By way of example, all transistors may be provided as LTPS type transistors.

Alternatively, all the transistors may be set as oxide type transistors. Because the metal oxide has lower cost, the crystallization process is not needed by using laser equipment.

Alternatively, part of the transistors may be oxide transistors, and the remaining transistors may be LTPS transistors.

In some embodiments of the present disclosure, further comprising: the semiconductor layer is arranged on the substrate, the gate insulating layer is arranged on one side of the semiconductor layer, which is away from the substrate, the gate conducting layer is arranged on one side of the gate insulating layer, which is away from the substrate, the first insulating layer is arranged on one side of the gate conducting layer, which is away from the substrate, the first conducting layer is arranged on one side of the first insulating layer, which is away from the substrate, the second insulating layer is arranged on one side of the first conducting layer, which is away from the substrate, and the second conducting layer is arranged on one side of the second insulating layer, which is away from the substrate.

In some embodiments of the present disclosure, the gate conductive layer includes: a gate of the first output transistor M1, a gate of the second output transistor M2; the semiconductor layer includes: an active region of the first output transistor M1 and an active region of the second output transistor M2; the active region of the first output transistor M1 includes: a first pole and a second pole of the first output transistor M1; the active region of the second output transistor M2 includes: a first pole and a second pole of the second output transistor M2; the conductive layer includes: a first conductive layer and a second conductive layer; the first level signal line VGH and the second level signal line VGL are positioned on the second conductive layer; the cascade output signal line Out is located in the first conductive layer or the second conductive layer.

Illustratively, as shown in fig. 7-9, the cascade output signal line Out is located at the first conductive layer.

Illustratively, as shown in fig. 10, the cascade output signal line Out is located in the second conductive layer.

Illustratively, the gate conductive layer further comprises: a gate of the first transistor T1, a gate of the second transistor T2, a gate of the third transistor T3, a gate of the fourth transistor T4, a gate of the fifth transistor T5, a gate of the sixth transistor T6, a gate of the seventh transistor T7, a gate of the eighth transistor T8, a gate of the ninth transistor T9, a gate of the tenth transistor T10;

illustratively, the semiconductor layer further comprises: an active region of the first transistor T1, an active region of the second transistor T2, an active region of the third transistor T3, an active region of the fourth transistor T4, an active region of the fifth transistor T5, an active region of the sixth transistor T6, an active region of the seventh transistor T7, an active region of the eighth transistor T8, an active region of the ninth transistor T9, an active region of the tenth transistor T10.

Illustratively, the active region of the transistor includes a source region, a drain region, and a channel region between the source region and the drain region. The source region may be a first pole of the transistor, and the drain region may be a second pole of the transistor; or the source region may be the second pole of the transistor and the drain region may be the first pole of the transistor; and are not limited herein.

For example, if the first electrode of the first capacitor C1 is located on the gate conductive layer, the second electrode of the first capacitor C1 is located on the first conductive layer, and if the second electrode of the first capacitor C1 is located on the gate conductive layer, the first electrode of the first capacitor C1 is located on the first conductive layer; if the first electrode of the second capacitor C2 is located in the gate conductive layer, the second electrode of the second capacitor C2 is located in the first conductive layer, and if the second electrode of the second capacitor C2 is located in the gate conductive layer, the first electrode of the second capacitor C2 is located in the first conductive layer; if the first electrode of the third capacitor C3 is located on the gate conductive layer, the second electrode of the third capacitor C3 is located on the first conductive layer, and if the second electrode of the third capacitor C3 is located on the gate conductive layer, the first electrode of the third capacitor C3 is located on the first conductive layer.

Illustratively, the first clock signal line CK, the second clock signal line CB, and the start-of-frame signal line STV are all located in the second conductive layer.

Illustratively, the semiconductor layer may be patterned using a semiconductor material. The semiconductor layer may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor material, or the like, and is not limited herein. The source region and the drain region may be a conductive region doped with an n-type impurity or a p-type impurity.

Illustratively, the materials of the first and second conductive layers may be conductive materials. For example, the conductive material may include a metal material such as aluminum, molybdenum, titanium, or an alloy material, or may include a metal oxide such as Indium Tin Oxide (ITO), or the like, and the material of each functional layer is not limited in the embodiments of the present disclosure.

The gate insulating layer, the first insulating layer, and the second insulating layer are each formed of an insulating material, and an organic insulating material, such as polyimide, a resin material, or the like, or an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, may be selected as needed.

In some embodiments of the present disclosure, as shown in fig. 7 to 9, when the cascade output signal line Out is located on the first conductive layer, the orthographic projection of the partial via K1, K1-1 on the substrate overlaps with the orthographic projection of the cascade output signal line Out on the substrate.

In some embodiments of the present disclosure, as shown in fig. 10, when the cascade output signal line Out is located on the second conductive layer, the orthographic projection of the portion of the via K1 on the substrate overlaps with the orthographic projection of the gate conductive layer on the substrate.

Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the display panel provided by the embodiment of the invention. The principle of the display device for solving the problems is similar to that of the display panel, so that the implementation of the display device can be referred to the implementation of the display panel, and the repetition is omitted herein.

In a specific implementation, in an embodiment of the present invention, the display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the invention.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims and the equivalents thereof, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A display panel, comprising: a substrate, a first shift register and a second shift register on the substrate; the first shift register and the second shift register comprise a first output transistor, a second output transistor and a plurality of transfer holes; the transfer hole is used for bridging the active region of the first output transistor and the active region of the second output transistor through the conducting layer; the number of the switching holes in the second shift register is larger than that of the switching holes in the first shift register; and/or the size of the transfer hole in the second shift register is larger than that of the transfer hole in the first shift register;

the threshold voltage of the first output transistor in the second shift register is negatively biased compared to the threshold voltage of the first output transistor in the first shift register; the threshold voltage of the second output transistor in the second shift register is negatively biased compared to the threshold voltage of the second output transistor in the first shift register.

2. The display panel of claim 1, wherein a front projection of a portion of the transfer hole at the substrate overlaps with a front projection of an active region of the first output transistor and an active region of the second output transistor at the substrate.

3. The display panel of claim 2, wherein the size of the transfer aperture in the first shift register is between 2.3 microns and 3.5 microns; the size of the transfer hole in the second shift register is between 2.5 micrometers and 4 micrometers.

4. The display panel of any one of claims 1-3, wherein the second shift register further comprises a plurality of virtual switch holes; the orthographic projection of the virtual transfer hole on the substrate is adjacent to the orthographic projection of the active layer of the first output transistor and the active layer of the second output transistor on the substrate.

5. The display panel of claim 4, wherein a gate of the first output transistor is coupled to a first node, a first pole of the first output transistor is coupled to a first level signal line, and a second pole of the first output transistor is coupled to a cascade output signal line;

the gate of the second output transistor is coupled to a second node, the first pole of the second output transistor is coupled to a second level signal line, and the second pole of the second output transistor is coupled to the cascade output signal line.

6. The display panel of claim 5, further comprising: the semiconductor layer is located on the substrate, the gate insulating layer is located the semiconductor layer deviates from substrate one side, the gate conducting layer is located the gate insulating layer deviates from substrate one side, the first insulating layer is located the gate conducting layer deviates from substrate one side, the first conducting layer is located the first insulating layer deviates from substrate one side, the second insulating layer is located the first conducting layer deviates from substrate one side, the second conducting layer is located the second insulating layer deviates from substrate one side.

7. The display panel of claim 6, wherein the gate conductive layer comprises: a gate of the first output transistor, a gate of the second output transistor; the semiconductor layer includes: an active region of the first output transistor and an active region of the second output transistor; the active region of the first output transistor includes: a first pole and a second pole of the first output transistor; the active region of the second output transistor includes: a first pole and a second pole of the second output transistor;

the conductive layer includes: the first conductive layer and the second conductive layer;

the first level signal line and the second level signal line are positioned on the second conductive layer; the cascade output signal line is located at the first conductive layer or the second conductive layer.

8. The display panel of claim 7, wherein when the cascade output signal line is located in the first conductive layer, a front projection of a portion of the via on the substrate overlaps with a front projection of the cascade output signal line on the substrate.

9. The display panel of claim 7, wherein when the cascade output signal line is located in the second conductive layer, a front projection of a portion of the via hole on the substrate overlaps with a front projection of the gate conductive layer on the substrate.

10. A display device comprising a display panel according to any one of claims 1-9.