KR20190010059A - Organic light emitting display device - Google Patents

Abstract

The present specification relates to an organic light emitting display device capable of accurately sensing a threshold voltage of a driving transistor. According to one embodiment of the present specification, the organic light emitting display device comprises: a driving transistor driving an organic light emitting diode; a switching circuit unit controlling a driving timing of the driving transistor; and a capacitor unit storing voltages of first and second nodes in the switching circuit unit. The switching circuit unit of the present specification maintains a sensing section for sensing the threshold voltage of the driving transistor for two horizontal sections after input of a data voltage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

The present invention relates to an organic light emitting display.

Description of the Related Art [0002] A display device technology for displaying visual information as an image or an image in an information society has been developed. Among display devices, an organic light emitting display uses an organic light emitting diode that generates light by recombination of electrons and holes to display an image. The organic light emitting display device has a fast response speed and is capable of expressing low gradation according to the self light emission, and thus, it is attracting attention as a next generation display.

The organic light emitting display includes a display region provided with pixels for displaying an image and a display panel disposed outside the display region and having a non-display region that does not display an image. Each of the pixels is driven by a scan signal and emits light at a brightness corresponding to the magnitude of the data voltage.

The horizontal time (H) is the time when the data voltage is supplied to one pixel. One horizontal period has a value obtained by dividing one frame, which is a length obtained by dividing one second by a frame frequency which is a unit for driving the display, by the number of scan lines supplying scan signals. For example, when a display device having a frame frequency of 60 Hz has 1000 scan lines, one horizontal interval is 1/60 ms.

In the case of an OLED display device having the same size of display panel, as the resolution increases, the number of pixels increases in the direction of the scan line for supplying the scan signals and the direction of the data line for supplying the data voltages, The number of the pixel columns is also increased. A scan line is provided for each pixel column. Therefore, as the number of pixel columns increases, the number of scan lines arranged in the display panel increases. Accordingly, as the resolution increases in a display device having a frame interval of the same length, the length of one horizontal interval becomes shorter. For example, when a display device having a frame frequency of 60 Hz has 2000 scan lines, one horizontal interval is 1/120 ms.

Meanwhile, the organic light emitting display device must compensate the threshold voltage by sensing the threshold voltage of the driving transistor during driving. In order to sense the accurate threshold voltage of the driving transistor, the sensing period must be maintained for a time length necessary for the voltage of the source electrode of the driving transistor to rise to the sum of the data voltage and the threshold voltage. According to the conventional driving method, the threshold voltage of the organic light emitting display is sensed for one horizontal period. Accordingly, when the length of one horizontal section is short in a high-resolution display device, there is a problem that an accurate threshold voltage can not be sensed.

The present application aims to provide an organic light emitting display device capable of accurately sensing a threshold voltage of a driving transistor.

The OLED display includes a driving transistor for driving the organic light emitting diode, a switching circuit for controlling the driving timing of the driving transistor, and a capacitor for storing the voltages of the first and second nodes in the switching circuit. do. The switching circuit portion of the present application maintains the sensing period for sensing the threshold voltage of the driving transistor for two horizontal intervals after the input of the data voltage.

The organic light emitting display according to the present application can accurately sense the threshold voltage of the driving transistor.

1 is a conceptual block diagram of an organic light emitting diode display according to the present application.
2 is an internal circuit diagram of a pixel according to the first embodiment of the present application.
3 is an internal circuit diagram of a pixel according to a second embodiment of the present application.
4 is a waveform diagram of input / output signals and voltages according to a second embodiment of the present application.
5 is a pixel drive simulation graph according to the second embodiment of the present application.
6 is a waveform diagram showing a first node voltage when the sensing period is maintained for one horizontal period according to the first embodiment of the present application.
FIG. 7 is a waveform diagram showing a first node voltage when a sensing period is maintained for two horizontal periods according to a second embodiment of the present application. FIG.

Brief Description of the Drawings The advantages and features of the present application, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that this application is not limited to the examples disclosed herein, but may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein, To fully disclose the scope of the invention to those skilled in the art, and this application is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like described in the drawings for describing an example of the present application are illustrative, and thus the present application is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the description of the present application, a detailed description of known related arts will be omitted if it is determined that the gist of the present application may be unnecessarily obscured.

Where the terms "comprises", "having", "done", and the like are used herein, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the scope of the present application.

The terms "first horizontal axis direction "," second horizontal axis direction ", and "vertical axis direction" should not be interpreted solely by the geometric relationship in which the relationship between them is vertical, It may mean having a wider directionality in the inside.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

Each of the features of the various embodiments of the present application may be combined or combined with each other partially or entirely, technically various interlocking and driving are possible, and the examples may be independently performed with respect to each other, .

Hereinafter, preferred embodiments of the organic light emitting display according to the present application will be described in detail with reference to the accompanying drawings.

1 is a conceptual block diagram of an organic light emitting diode display according to the present application. 2 is an internal circuit diagram of a pixel P according to the first embodiment of the present application.

1 and 2, an OLED display according to the present invention includes a display panel 100, a gate driver 110, a data driver 120, and a timing controller (T-CON) .

The display panel 100 includes a display area and a non-display area provided around the display area. The display area is an area where pixels P are provided to display an image. The non-display area is an area outside the display panel 100 and protects the display area from external impact. The display panel 100 is provided with gate lines GL1 to GLp, p is a positive integer of 2 or more, data lines DL1 to DLq, q is a positive integer of 2 or more, and sensing lines SL1 to SLq do. The data lines DL1 to DLq and the sensing lines SL1 to SLq may intersect the gate lines GL1 to GLp. The data lines DL1 to DLq and the sensing lines SL1 to SLq may be parallel to each other. The display panel 100 may include a lower substrate on which pixels P are provided and an upper substrate that performs an encapsulation function to protect pixels P from foreign substances.

Each of the pixels P may be connected to any one of the gate lines GL1 to GLp and one of the data lines DL1 to DLq and the sensing lines SL1 to SLq. 2, the pixel P according to an exemplary embodiment of the present invention includes a driving transistor DT, a light emitting element EL, a storage capacitor Cst, and first to sixth transistors T1 to T6. . In the following description, the driving transistor DT and the first to sixth transistors T1 to T6 according to an example of the present application have a gate electrode, a source electrode, and a drain electrode It is assumed that the MOSFET is implemented as a P-type MOSFET.

A gate electrode of the driving transistor DT is connected to a first node N1 to which one electrode of the storage capacitor Cst, a drain electrode of the first transistor T1, and a drain electrode of the fifth transistor T5 are connected, Respectively. The source electrode of the driving transistor DT is connected to the drain electrode of the third transistor T3 which receives the pixel driving power ELVDD as a source electrode. The drain electrode of the driving transistor DT is connected to the source electrode of the fourth transistor T4.

And is turned on when a voltage higher than the threshold voltage is supplied to the gate electrode of the driving transistor DT. The turned-on driving transistor DT passes a driving current from the source electrode to the drain electrode.

The light emitting element EL includes an anode electrode and a cathode electrode. The light emitting element EL flows a driving current from the anode electrode to the cathode electrode. The anode electrode of the light emitting device EL is connected to the second node N2 to which the drain electrode of the fourth transistor T4 is connected. The cathode electrode of the light emitting device EL is connected to the cathode electrode of the ground line where the low potential supply voltage ELVSS is formed. The light emitting element EL emits light with brightness corresponding to the driving current flowing from the driving transistor DT.

The storage capacitor Cst has both electrodes. One electrode of the storage capacitor Cst is connected to the first node N1. The other electrode of the storage capacitor Cst is connected to the pixel drive power supply ELVDD line.

The storage capacitor Cst stores the difference voltage between the pixel drive power source ELVDD and the first node N1 when the fifth transistor T5 connected to the first node N1 is turned on. The storage capacitor Cst maintains the difference voltage stored in the first node N1 when the fifth transistor T5 is turned off. Further, the storage capacitor Cst can control driving of the driving transistor DT by using the stored and held voltage.

The gate electrode of the first transistor T1 receives the second scan signal Scan2. The source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor DT. The drain electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 is turned on by the second scan signal Scan2 so that the voltage of the first node N1 is set to Vdata which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. + Vtp.

The gate electrode of the second transistor T2 receives the second scan signal Scan2. The source electrode of the second transistor T2 is connected to the data line DL to receive the data voltage Vdata. The drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor DT. The second transistor T1 is turned on by the second scan signal Scan2 and supplies the data voltage Vdata to the source electrode of the driving transistor DT.

The gate electrode of the third transistor T3 is supplied with the emission control signal EM. The source electrode of the third transistor T3 is supplied with the pixel driving power ELVDD. The drain electrode of the third transistor T3 is connected to the source electrode of the driving transistor DT. The third transistor T3 is turned on by the emission control signal EM and supplies the pixel driving power ELVDD to the driving transistor DT so that the driving transistor DT allows the driving current to flow.

The gate electrode of the fourth transistor T4 is supplied with the emission control signal EM. The source electrode of the fourth transistor T4 is connected to the drain electrode of the driving transistor DT. The drain electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 is turned on by the emission control signal EM so that a drive current flows through the light emitting element EL to emit the light emitting element EL.

The gate electrode of the fifth transistor T5 receives the first scan signal Scan1. The source electrode of the fifth transistor T5 is supplied with the initializing voltage Vinit. The drain electrode of the fifth transistor T5 is connected to the first node N1. The fifth transistor T5 is turned on by the first scan signal Scan1 to initialize the voltage of the first node N1 to the initialization voltage Vinit.

The gate electrode of the sixth transistor T6 receives the first scan signal Scan1. The source electrode of the sixth transistor T6 is supplied with the initializing voltage Vinit. The drain electrode of the sixth transistor T6 is connected to the second node N2. The sixth transistor T6 is turned on by the first scan signal Scan1 to initialize the voltage of the second node N2 to the initializing voltage Vinit.

The pixel P according to the first embodiment of the present invention includes seven thin film transistors (TFT) and one capacitor and is collectively referred to as a 7T1C compensation circuit. In addition, the pixel P according to the first embodiment of the present invention operates with two types of scan signals (Scan) and one type of emission control signal (EM).

The difference voltage Vgs between the gate voltage of the driving transistor DT and the source voltage maintains the gate-low voltage (VGL) state at the start of an arbitrary frame. Further, the emission control signal EM is also in a gate low voltage (VGL) state. Thus, the third and fourth transistors T3 and T4 are turned on. Accordingly, a predetermined amount of driving current flows through the driving transistor DT to cause the light emitting element EL to emit light.

Thereafter, the emission control signal EM has the gate high voltage VGH, and the source electrode and the drain electrode of the driving transistor DT are in the floating state.

Thereafter, the pixel P has an initialization step. In the initialization step, when the first scan signal Scan1 becomes the gate-low voltage VGL, the fifth transistor T5 is turned on and the initialization voltage Vinit is applied to the first node N1. When the first scan signal Scan1 again becomes the gate high voltage VGH after the initialization step, the fifth transistor T5 is turned off and the first node N1 becomes a floating state.

Thereafter, the pixel P has a Programming step. In the programming step, the first, second and sixth transistors T1, T2 and T6 are turned on when the second scan signal Scan2 becomes the gate-low voltage VGL. The light emitting element EL is reset by the sixth transistor T6. Further, the second transistor T2 is turned on, and the data voltage Vdata is supplied to the source electrode of the driving transistor DT.

The initialization voltage Vinit of the pixel P according to an example of the present application is lower than the data voltage Vdata. The data voltage Vdata is supplied to the source electrode of the driving transistor DT and the initializing voltage is supplied to the gate electrode of the driving transistor DT. Accordingly, the difference voltage Vgs between the gate voltage of the driving transistor DT and the source voltage has a negative (-) voltage value.

When the difference voltage Vgs between the gate voltage and the source voltage has a negative voltage value, the driving transistor DT operates in a linear region. As a result, the voltage of the drain electrode of the driving transistor DT rises. Since the first transistor T1 is in a turned-on state, the drain electrode and the gate electrode of the driving transistor can be regarded as electrically identical nodes. As a result, the voltage of the first node N1 rises to Vdata + Vth, which is the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT. Here, the threshold voltage Vth has a negative voltage value.

Thereafter, the pixel P has a step of sensing a threshold voltage Vth. Since the voltage of the first node N1 is raised to the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT in the threshold voltage Vth sensing step, So that only the subthreshold current flows.

At this time, the threshold voltage Vth can be sensed by sensing Vdata + Vth, which is the voltage of the gate electrode of the driving transistor DT, based on the data voltage Vdata.

Thereafter, the pixel driving voltage ELVDD is supplied to the drain electrode of the driving transistor when the emission control signal EM becomes the gate-low voltage VGL again. As a result, the next frame starts, and the light emitting element EL emits light.

The gate driving unit 120 receives the gate driving unit control signal GCS from the timing controller 130 and generates gate signals according to the gate driving unit control signal GCS and supplies the gate signals to the gate lines GL1 to GLp.

The data driver 120 receives the data driver control signal DCS from the timing controller 130 and generates data voltages according to the data driver control signal DCS to supply the data voltages to the data lines DL1 to DLq. The data driver 120 senses voltage and current characteristics of each of the pixels P to generate sensing data SEN and supplies the sensing data SEN to the timing controller 130.

The timing controller 130 is supplied with digital video data DATA including a timing signal TS for controlling the display timing of an image from outside and color-specific information for implementing an image. A timing signal TS and digital video data DATA are input to the input terminal of the timing controller 130 according to a protocol set. The timing controller 130 receives the sensing data SEN according to the voltage and current characteristics of the pixels P from the data driver 120.

The timing signal TS includes a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE and a dot clock DCLK. . The timing controller 130 compensates the digital video data (DATA) based on the sensing data SEN.

The timing controller 130 generates driving unit control signals for controlling the operation timings of the gate driving unit 110, the data driving unit 120, the scan driving unit, and the sensing driving unit. The driving unit control signals include a gate driving unit control signal GCS for controlling the operation timing of the gate driving unit 110, a data driving unit control signal DCS for controlling the operation timing of the data driving unit 120, And a sensing driver control signal for controlling the operation timing of the sensing driver.

The timing controller 130 operates the data driver 120, the scan driver, and the sensing driver in one of a display mode and a sensing mode according to a mode signal. The display mode is a mode in which the pixels P of the display panel 100 display an image and the sensing mode is a mode of sensing the current of the drive transistor DT of each of the pixels P of the display panel 100. [ When the waveform of the scan signal and the waveform of the sensing signal supplied to each of the pixels P in the display mode and the sensing mode are changed, the data driver control signal DCS, the scan driver control signal, The sensing driver control signal can also be changed. Accordingly, the timing controller 130 generates the data driver control signal DCS, the scan driver control signal, and the sensing driver control signal according to the mode, depending on whether the display mode or the sensing mode.

The timing controller 130 outputs the gate driver control signal GCS to the gate driver 110. [ The timing controller 130 outputs the compensated digital video data and the data driver control signal DCS to the data driver 120. The timing controller 130 outputs a scan driver control signal to the scan driver. The timing controller 130 outputs a sensing driver control signal to the sensing driver.

The timing controller 130 generates a mode signal for driving the data driving unit 120, the scan driving unit, and the sensing driving unit depending on which of the display mode and the sensing mode is driven. The timing controller 130 operates the data driver 120, the scan driver, and the sensing driver in one of a display mode and a sensing mode according to a mode signal.

3 is an internal circuit diagram of a pixel according to a second embodiment of the present application. A pixel according to an example of the present application includes a driving transistor DT, a switching circuit portion SWC, and a capacitor portion CS. Here, the switching circuit portion SWC includes the first to sixth switching transistors T1 to T6. In addition, the capacitor portion CS includes first and second capacitors C1 and C2.

The driving transistor DT drives the organic light emitting diode OLED. And is turned on when a voltage higher than the threshold voltage is supplied to the gate electrode of the driving transistor DT. The turned-on driving transistor DT passes a driving current from the source electrode to the drain electrode. Accordingly, the driving transistor DT causes a driving current to flow to the organic light emitting diode OLED.

The driving transistor DT has a gate electrode, a source electrode, and a drain electrode. The gate electrode of the driving transistor DT is connected to the first node N1 to which one electrode of the first capacitor C1, the drain electrode of the first switching transistor ST1, and the drain electrode of the third switching transistor DT3 are connected, Respectively. The source electrode of the driving transistor DT is connected to the second node N2 connected to the drain electrode of the fourth switching transistor ST4. The drain electrode of the driving transistor DT is connected to the source electrode of the fifth switching transistor ST5.

The switching circuit portion SWC controls the driving timing of the driving transistor DT. The switching circuit SWC is supplied with the first to third scan signals Scan1 to Scan3, the emission control signal EM, the pixel driving voltage ELVDD, the data voltage Vdata, and the initialization voltage Vinit. The switching circuit SWC supplies the initializing voltage Vinit to the gate electrode of the driving transistor DT in accordance with the first scan signal Scan1. The switching circuit SWC supplies the data voltage Vdata to the source electrode of the driving transistor DT in accordance with the second scan signal Scan2. The switching circuit SWC senses the threshold voltage of the driving transistor DT in accordance with the third scan signal Scan3. The switching circuit portion SWC supplies the pixel driving voltage ELVDD to the source electrode of the driving transistor DT in accordance with the emission control signal EM.

The capacitor portion CS stores the voltages of the first and second nodes N1 and N2 in the switching circuit portion SWC. The capacitor portion CS is provided between the pixel drive voltage ELVDD line and the first node N1. Further, the capacitor portion CS is provided between the pixel drive voltage ELVDD line and the second node N2. The capacitor unit CS stores the difference voltage between the pixel drive voltage ELVDD and the voltage of the first node N1. Also, the capacitor unit CS separately stores the difference voltage between the pixel drive voltage ELVDD and the voltage of the second node N2.

The switching circuit SWC according to the second embodiment of the present application maintains the sensing period for sensing the threshold voltage of the driving transistor DT for two horizontal periods H after the input of the data voltage Vdata . Accordingly, the switching circuit SWC according to an exemplary embodiment of the present invention applies the third scan signal Scan3 to the first logic level L1 lower than the first logic level L1 during two horizontal periods H after the input of the data voltage Vdata 2 logic level (L2).

Since the horizontal period H is the time at which the data voltage Vdata is supplied to one pixel, the data voltage Vdata is supplied for one horizontal period. One horizontal period has a value obtained by dividing one frame, which is a length obtained by dividing one second by a frame frequency which is a unit for driving the display, by the number of scan lines supplying scan signals. At this time, the number of scan lines is equal to the number of pixel columns arranged in the column direction parallel to the scan lines. In addition, the number of pixel columns increases as the resolution increases.

Therefore, in the case of a display device having a low resolution, the number of scan lines is relatively small and one horizontal section is relatively long. The voltage of the first node N1 in the sensing period is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT even if the sensing period is maintained for only one horizontal period Vdata + Vtp, so that the sensing of the threshold voltage Vtp is accurately performed.

However, in the case of a display device having a high resolution, the number of scan lines is relatively large, so that one horizontal section is relatively short. If the sensing period is maintained for one horizontal period only when the horizontal interval is short, the voltage of the first node N1 is maintained at the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT until the end of the sensing period It does not rise to the combined voltage Vdata + Vtp but rises to a voltage lower than the sum. Accordingly, a voltage smaller than the sum of the data voltage (Vdata) and the threshold voltage (Vtp) of the driving transistor (DT) is sensed at the end of the sensing period, and the sensing of the threshold voltage (Vtp) can not be accurately performed.

The switching circuit SWC according to the second embodiment of the present application maintains the sensing period for sensing the threshold voltage Vtp of the driving transistor DT for two horizontal periods H after the input of the data voltage Vdata . Accordingly, in the organic light emitting diode display according to an embodiment of the present invention, the voltage of the first node N1 is equal to the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT before the end of the sensing period Vtata + Vtp, which is a voltage. As a result, the organic light emitting display according to the second embodiment of the present invention senses the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT at the end of the sensing period, (Vtp) can be accurately sensed.

The switching circuit portion SWC according to the second embodiment of the present application comprises the first to sixth switching transistors SW1 to SW6. Each of the first to sixth switching transistors SW1 to SW6 has a gate electrode, a source electrode, and a drain electrode. In addition, the capacitor unit CS according to the second embodiment of the present application comprises first and second capacitors C1 and C2.

The gate electrode of the first switching transistor SW1 receives the first scan signal Scan1. The source electrode of the first switching transistor SW1 is supplied with the initializing voltage Vinit. The drain electrode of the first switching transistor SW1 is connected to the first node N1. One electrode of the first capacitor C1, a drain electrode of the first switching transistor ST1, and a drain electrode of the third switching transistor ST5 are connected to the first node N1. The first switching transistor SW1 supplies the initialization voltage Vinit to the first node N1 according to the first scan signal Scan1. The initialization voltage Vinit is a voltage for removing the data voltage Vdata of the previous frame stored in the first node N1 and has a potential lower than the data voltage Vdata. The first switching transistor SW1 initializes the voltage of the first node N1 according to the first scan signal Scan1.

The gate electrode of the second switching transistor SW2 receives the second scan signal Scan2. The source electrode of the second switching transistor SW2 is supplied with the data voltage Vdata. The drain electrode of the second switching transistor SW2 is connected to the second node N2. A source electrode of the driving transistor DT, a drain electrode of the fourth switching transistor ST4, and one electrode of the second capacitor C2 are connected to the second node N2. The second switching transistor SW2 supplies the data voltage Vdata to the second node N2 in accordance with the second scan signal Scan2.

The gate electrode of the third switching transistor SW3 receives the third scan signal Scan3. And the source electrode of the third switching transistor SW3 is connected to the third node N3. A drain electrode of the driving transistor DT and a source electrode of the fifth switching transistor SW5 are connected to the third node N3. The drain electrode of the third switching transistor SW3 is connected to the first node N1. The third switching transistor SW3 senses the voltage of the third node N3 according to the third scan signal Scan3. The third switching transistor SW3 transfers the voltage of the sensed third node N3 to the first node N1. The voltage transferred to the first node N1 is stored in the first capacitor C1.

The third scan signal Scan3 of the present application is supplied for two horizontal periods H after completion of initialization of the voltage of the first node N1. While the third scan signal Scan3 is supplied, the third switching transistor SW3 may sense the voltage of the third node N3. The voltage of the third node N3 at the time when the supply of the third scan signal Scan3 is terminated is stored in the first node N1.

The voltage of the third node N3 is applied to the gate of the driving transistor DT and the data voltage Vdata when the third scan signal Scan3 is supplied for two horizontal periods H which are twice the conventional supply time. And has a sufficient time to rise to Vdata + Vtp which is the sum of the voltages Vtp. Accordingly, a voltage smaller than the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT is sensed at the third node N3 at the end of the sensing period, Vtata + Vtp which is a sum of the threshold voltage Vtp of the driving transistor DT and the threshold voltage Vtp of the driving transistor DT. Accordingly, the accurate voltage Vdata + Vtp can be stored in the first node N1, so that the sensing of the threshold voltage Vtp can be accurately performed.

The gate electrode of the fourth switching transistor SW4 is supplied with the emission control signal EM. The source electrode of the fourth switching transistor SW4 is supplied with the pixel driving voltage ELVDD. The drain electrode of the fourth switching transistor SW4 is connected to the second node N2. The fourth switching transistor SW4 supplies the pixel driving power to the driving transistor DT in accordance with the emission control signal EM.

The gate electrode of the fifth switching transistor SW5 is supplied with the emission control signal EM. And the source electrode of the fifth switching transistor SW5 is connected to the third node N3. The drain electrode of the fifth switching transistor SW5 is connected to the anode electrode of the organic light emitting diode OLED. The fifth switching transistor SW5 connects the driving transistor DT to the organic light emitting diode OLED according to the emission control signal EM. The fifth switching transistor SW5 allows the driving current generated by the driving transistor DT to flow to the organic light emitting diode OLED.

The gate electrode of the sixth switching transistor SW6 receives the third scan signal Scan3. The source electrode of the sixth switching transistor SW6 is supplied with the initializing voltage Vinit. The drain electrode of the sixth switching transistor SW6 is connected to the anode electrode of the organic light emitting diode OLED. The sixth switching transistor SW5 supplies the initialization voltage Vinit to the anode electrode of the organic light emitting diode OLED according to the third scan signal Scan3. The sixth switching transistor SW6 initializes the potential difference between the two electrodes of the organic light emitting diode OLED according to the third scan signal Scan3.

The switching circuit unit SWC according to the second embodiment of the present invention controls the driving timing and the potential difference of the driving transistor DT and the organic light emitting diode OLED using the fourth to sixth switching transistors SW4 to SW6 . Accordingly, the organic light emitting display according to the second embodiment of the present invention can further stabilize the driving timing, and can set the potential difference of the organic light emitting diode OLED to the initialization voltage Vinit at the start of each frame .

One electrode of the first capacitor C1 is connected to the first node N1. The other electrode of the first capacitor C1 is supplied with the pixel drive voltage ELVDD. The other electrode of the first capacitor C1 is held constant by the pixel drive voltage ELVDD. Accordingly, the first capacitor C1 stores the voltage of the first node N1.

One electrode of the second capacitor C2 is connected to the second node N2. And the other electrode of the second capacitor C2 is supplied with the pixel drive voltage ELVDD. And the other electrode of the second capacitor C2 is held constant by the pixel drive voltage ELVDD. Thus, the second capacitor C2 stores the voltage of the second node N2.

The second capacitor C2 senses the voltage of the third node N3 by the third switching transistor SW3 and supplies the voltage stored during the sensing period stored in the first node N1 to the second node N2 do. The second capacitor C2 maintains the voltage of the second node N2 constant during the sensing period. The second capacitor C2 maintains the voltage of the second node N2 at a constant level in two horizontal intervals H extending from the first horizontal interval H of the sensing period during which the third scan signal Scan3 is supplied Respectively.

When the second capacitor C2 does not keep the voltage of the second node N2 connected to the source electrode of the driving transistor DT constant, the potential of the third node N3 to which the drain electrode of the driving transistor DT is connected The voltage of the source electrode of the driving transistor DT changes when the voltage is sensed. Sensing the voltage of the drain electrode of the driving transistor DT in order to sense the threshold voltage Vtp of the driving transistor DT does not sense the absolute value of the voltage of the drain electrode, And the potential difference of the drain electrode should be sensed. When the voltage of the source electrode of the driving transistor DT changes, the threshold voltage Vtp of the driving transistor DT can not be accurately sensed.

The second capacitor C2 of the present invention supplies the voltage stored in the second node N2 during the sensing period to keep the voltage of the second node N2 constant during the two horizontal periods during the sensing period. According to the present application, the voltage of the source electrode of the driving transistor DT can be kept constant in the sensing period. Accordingly, the present application can accurately sense the potential difference between the source electrode and the drain electrode of the driving transistor DT, and accurately sense the threshold voltage Vtp of the driving transistor DT.

To this end, the second capacitor C2 stores the data voltage Vdata supplied while the second scan signal Scan2 is supplied, and supplies the data voltage Vdata to the second node N2 (Vdata).

The second capacitor C2 may store the data voltage Vdata supplied to the source electrode of the driving transistor DT to maintain the voltage of the second node N2 constant during the sensing period. Accordingly, the voltage of the second node N2 can be kept constant without supplying an external voltage.

The switching circuit portion SWC and the capacitor portion CS according to the present application sense the threshold voltage Vtp of the driving transistor DT even if the threshold voltage Vtp changes and maintain the driving current flowing through the organic light emitting diode OLED constant, Is a constant compensation method. However, as the length of one horizontal section H becomes short and the sensing period compensating for the threshold voltage Vtp becomes short, the compensation rate decreases, which causes a change in luminance. The switching circuit unit SWC and the capacitor unit CS according to the present invention maintains the sensing period for sensing the threshold voltage Vtp during the two horizontal periods H to set the compensation ratio of the threshold voltage Vtp to 100% Is minimized.

The 7T1C compensation circuit using seven transistors and one capacitor according to the first embodiment of the present application is configured to sense the threshold voltage (Vtp) while supplying the data voltage (Vdata). Therefore, one horizontal period (H) for inputting the data voltage (Vdata) is the maximum sensing period length. When the length of one horizontal section H is shortened, the gate voltage of the driving transistor DT to be sensed is lowered, and as a result, the driving transistor DT is turned on during a period in which the organic light emitting diode OLED emits light by the emission control signal EM. The value of Vgs, which is the difference voltage between the voltage of the gate electrode and the voltage of the source electrode, increases. Accordingly, even if the same data voltage Vdata is supplied, the contrast luminance in a normal case becomes brighter.

The compensation circuit composed of the switching circuit portion SWC and the capacitor portion CS according to the second embodiment of the present application maintains the sensing period for two horizontal periods H to maximize the compensation rate of the threshold voltage Vtp, Minimize change.

In order to maintain the sensing period for two horizontal periods (H), the third scan signal (Scan3) must be supplied for two horizontal periods (H). In addition, the second scan signal (Scan2) and the third scan signal (Scan3) must overlap each other for at least a part of the period. The data voltage Vdata is supplied to the driving transistor DT only when the second scan signal Scan2 is supplied and the voltage of the third node N3 is Vdata + Vtp, which is the sum of the data voltage Vdata and the threshold voltage Vtp . Therefore, the threshold voltage (Vtp) of the driving transistor DT can be sensed by performing the overlap driving in which the third scan signal (Scan3) is supplied while the second scan signal (Scan2) is supplied.

A clock supplied from the gate driver 120 implemented as a gate in panel (GIP) for overlap driving of the first and second scan signals Scan2 and Scan3 is divided into two horizontal periods H . In this case, the first scan signal, the second scan signal, and the third scan signals Scan1 to Scan3 may all be supplied during the second horizontal period H.

In order to generate scan signals having different lengths, a separate circuit must be mounted in the gate driver 120. Accordingly, when the lengths of the scan signals are different from each other, the size of the gate driver 120 increases and the area of the bezel surrounding the display region of the organic light emitting display device also increases.

The gate driver 120 according to the present invention sets the lengths of the first to third scan signals Scan1 to Scna3 to be equal to two horizontal intervals H, Accordingly, the size of the GIP circuit implementing the gate driver 120 of the present application can be minimized. In addition, by minimizing the size of the GIP circuit, the area of the bezel can be minimized, and an organic light emitting display having a narrow bezel can be easily designed.

The compensation circuit according to the second embodiment of the present invention initializes the voltage of the first node N1 by the first scan signal Scan1 and the data voltage by the second scan signal Scan2 to the second node N2 . The voltage of the third node N3 is sensed by the third scan signal and is stored in the first node N1. At this time, when the initialization period and the sensing period are overlapped, the sensing starts from the point in time when the initialization of the first node N1 is not completed, and the correct sensing voltage is not stored in the first node N1.

Accordingly, the first scan signal (Scan1) and the third scan signal (Scan3) of the present application do not overlap. If the second scan signal Scan2 is partially overlapped with the third scan signal Scan3, there is no problem in driving the compensation circuit, and the second scan signal Scan1 may overlap or not overlap with the first scan signal Scan1. The first scan signal Scan1 and the third scan signal Scan3 are supplied without being overlapped so that the data voltage supply period can be easily arranged while preventing the initialization period and the sensing period from being overlapped by using the three scan signals .

The second switching transistor SW2 is turned on as the second and third scan signals Scan2 and Scan3 are driven to overlap with each other and the data voltage Vdata is input to the switching circuit SWC according to the second embodiment of the present application. At the same time, the third switching transistor SW3 is turned on and the first node N1 starts to be charged. At this time, the first node N1 is charged to the voltage Vdata + Vtp which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. The supply of the second scan signal Scan2 is stopped earlier than the third scan signal Scan3 and the second switching transistor SW2 is turned off so that the supply of the data voltage Vdata stops in the middle of the sensing period.

The sensing period is maintained even while the supply of the second scan signal Scan2 is stopped and only the third scan signal Scan3 is supplied. The organic light emitting display according to the second embodiment of the present application further arranges a second capacitor C2 between the second node N2 and the pixel driving voltage ELVDD in order to maintain the sensing period. And the data voltage Vdata is held while the data voltage Vdata is supplied using the second capacitor C2. Even if the supply of the second scan signal Scan2 is stopped and the second switching transistor SW2 is turned off, the third scan signal Scan3 is still turned on. Accordingly, the voltage of the source electrode of the driving transistor DT can be kept constant by using the data voltage Vdata held in the second capacitor C2. Accordingly, the sensing period of the driving transistor DT can be maintained for two horizontal periods (H).

4 is a waveform diagram of input / output signals and voltages according to a second embodiment of the present application. In FIG. 4, the first to third scan signals Scan1 to Scan3, the emission control signal EM, the digital video data DATA, the first node voltage VN1, and the second node voltage VN2 are shown. In addition, FIG. 4 illustrates a case where a total of eight horizontal intervals H including the initial horizontal interval H0 and the first to seventh horizontal intervals H1 to H7 are included in one frame period. The present application exemplifies the case of using a P-type MOS transistor. Thus, the transistors are turned off when a high logic level signal or a high voltage is applied, and the transistors are turned on when a low logic level signal or a low voltage is applied.

In the initial horizontal period H0 according to the present application, the emission control signal EM has a second logic level L2 which is a low logic level. The initial horizontal interval H0 corresponds to a display period in which the organic light emitting display displays an image. Accordingly, the first to seventh horizontal sections H1 to H7 according to the present application also belong to the display section since they are driven during the display section for displaying the image. The first to seventh horizontal sections H1 to H7 according to the present application are distinguished from the sensing driving in which only the initial characteristics of the respective pixels of the organic light emitting display device are sensed and no image is displayed.

In the initial horizontal interval H0, the first to third scan signals Scan1 to Scan3 all have a first logic level L1 having a high logic level. Accordingly, the digital video data DATA is not supplied and the data voltage becomes 0V, and the first node voltage VN1 and the second node voltage VN2 are also 0V. The emission control signal EM also has a second logic level L2 which is a low logic level. The driving transistor DT supplies a driving current having a magnitude corresponding to the data voltage Vdata of the previous frame stored in the first capacitor C1 to emit the organic light emitting diode OLED.

In the first horizontal period H1, the emission control signal EM changes to the first logic level L1 to turn off the organic light emitting diode OLED.

In the second horizontal interval H2, the first scan signal Scan1 changes to the second logic level L2 to initialize the first node voltage VN1 to the initialization voltage Vinit.

In the third horizontal period H3, the second scan signal Scan2 changes to the second logic level L2. This is to unify the length of the second scan signal Scan2 into the same two horizontal intervals H2 as the third scan signal Scan3. Since the second scan signal Scan2 is a signal required in the fourth horizontal interval H4, the second scan signal Scan2 may be supplied only in the fourth horizontal interval H4.

In the fourth horizontal interval H4, the first scan signal Scan1 changes to the first logic level L1 and the third scan signal Scan3 changes to the second logic level L2. As a result, the initialization of the first node voltage VN1 is completed and the first node voltage VN1 sensing the voltage of the third node N3 also starts to rise as the voltage of the third node N3 rises do.

In addition, a data voltage (Vdata) according to the digital video data (DATA) is supplied in the fourth horizontal period (H4). As a result, the second node voltage VN2 rises to the data voltage Vdata. The second capacitor C2 holds or stores the data voltage Vdata.

In the fifth horizontal period H5, the second scan signal Scan2 changes to the first logic level L1. In the fifth horizontal period H5, the supply of the digital video data DATA is stopped and the data voltage Vdata becomes 0V. Thus, the second node voltage VN2 instantaneously changes. However, when the data voltage Vdata is held or stored during the fourth horizontal period H4 in the second capacitor C2 and the data voltage Vdata is supplied to the second node N2 in the fifth horizontal period H5 And holds the second node voltage VN2 at the data voltage Vdata.

Accordingly, the sensing period can be maintained in the fifth horizontal interval H5. In addition, the voltage of the first node VN1 may rise to Vdata + Vtp which is the sum of the data voltage Vdata and the driving voltage Vtp of the driving transistor DT.

In the sixth horizontal period H6, the third scan signal Scan3 changes to the first logic level L1. And the remaining input / output signals and voltages remain the same as the fifth horizontal interval H5.

In the seventh horizontal period H7, the emission control signal EM changes to the second logic level L2. The first and second node voltages VN1 and VN2 change as the emission control signal EM changes to the second logic level L2. By the emission control signal EM, the driving transistor DT passes a driving current to the organic light emitting diode OLED.

5 is a pixel drive simulation graph according to the second embodiment of the present application.

The first to third scan signals Scan1 to Scan3 of the present application have first to third sustain lengths D1 to D3, respectively. The first to third sustain lengths D1 to D3 may be 4 mu s or more and 8 mu s or less. During the first sustain period D1, the initialization period INI initializes the first node N1. During the third sustain period D3, the sensing period SENSE senses the voltage of the third node N3 and stores the sensed voltage at the first node N1.

It can be seen that the first node voltage VN1 continuously increases during the third sustain period D3. Also, it can be seen that the second node voltage VN2 maintains a constant voltage level despite the change of the interval.

6 is a waveform diagram showing a first node voltage VN1 when a sensing period is maintained for one horizontal period H according to the first embodiment of the present application.

When the sensing period is maintained for one horizontal period (H), the first sensing voltage (Vsen1) is sensed at the end of the sensing period. The first sensing voltage Vsen1 is smaller than Vdata + Vtp which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. That is, the threshold voltage Vtp of the driving transistor DT can not be accurately sensed. In addition, the first gate source voltage difference Vgs1, which is the difference between the voltage at the gate electrode of the driving transistor DT and the voltage at the source electrode, also increases.

7 is a waveform diagram showing a first node voltage VN1 when a sensing period is maintained for two horizontal periods H according to a second embodiment of the present application.

The voltage value of the second sensing voltage Vsen2 sensing the first node voltage VN1 is higher than the voltage sensing value of the second sensing voltage Vse1 when the sensing period is maintained for one horizontal period, (Vsen1). The second sensing voltage Vsen2 is equal to Vdata + Vtp, which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. Thus, the second gate source voltage difference Vgs2, which is the difference between the voltage of the gate electrode and the voltage of the source electrode when the driving transistor DT is driven by the emission control signal EM, decreases. Thus, the gate-source voltage difference can be accurately controlled, and the luminance change is minimized.

The OLED display according to the present invention senses a threshold voltage during two horizontal intervals. Accordingly, an accurate threshold voltage can be sensed even in a high resolution organic light emitting display device having a short horizontal length and an organic light emitting display device having a high frame frequency. Accordingly, the present invention can be applied to a UHD high-resolution display device and a display device having a high frame frequency of 120 Hz.

In addition, the organic light emitting display according to the present application has a structure in which ion mobility is reduced in an area bent in a foldable or foldable display device of a display panel 100, The threshold voltage can be compensated precisely even if it is decreased in the corresponding region.

The organic light emitting display according to the present application can accurately sense the threshold voltage of the driving transistor.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: gate driver
120: Data driver 130: Timing controller
P: pixel DT: driving transistor
EL: light emitting element Cst: storage capacitor
T1 to T6: first to sixth transistors OLED: organic light emitting diode
SWC: switching circuit part CS: capacitor part
ST1 to ST6: First to sixth switching transistors
C1, C2: first and second capacitors

Claims (8)

A driving transistor for driving the organic light emitting diode;
A switching circuit for controlling the driving timing of the driving transistor; And
And a capacitor portion for storing voltages at first and second nodes in the switching circuit portion,
The switching circuit unit includes:
Wherein a sensing period for sensing a threshold voltage of the driving transistor is maintained for two horizontal periods after a rising time of a data voltage. The method according to claim 1,
The switching circuit unit includes:
A first switching transistor for initializing a voltage of the first node according to a first scan signal;
A second switching transistor for supplying a data voltage to the second node according to a second scan signal; And
And a third switching transistor for sensing a voltage of a third node according to a third scan signal,
Wherein the third scan signal is supplied during two horizontal spaces after the initialization of the voltage of the first node. 3. The method of claim 2,
The switching circuit unit includes:
A fourth switching transistor for supplying a pixel driving power to the driving transistor according to a light emission control signal;
A fifth switching transistor for connecting a driving transistor to the organic light emitting diode according to the emission control signal; And
And a sixth switching transistor for initializing a potential difference between the two electrodes of the organic light emitting diode according to the third scan signal. The method according to claim 1,
The capacitor unit includes:
A first capacitor for storing a voltage of the first node; And
And a second capacitor for keeping the voltage of the second node constant during the sensing period. 5. The method of claim 4,
Wherein the second capacitor comprises:
Wherein the data voltage supplied during the supply of the second scan signal is stored and the stored data voltage is supplied to the second node after the supply of the data voltage is completed. The method according to claim 1,
Wherein the sensing voltage sensed in the sensing period is a sum of a data voltage and a threshold voltage of the driving transistor. 3. The method of claim 2,
The second scan signal and the third scan signal are overlapped for a certain period,
Wherein the first scan signal, the second scan signal, and the third scan signal are all supplied during a second horizontal interval. 8. The method of claim 7,
Wherein the first scan signal and the third scan signal do not overlap with each other.

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