CN110491323B - Gate driving circuit, method and display device thereof - Google Patents
Gate driving circuit, method and display device thereof Download PDFInfo
- Publication number
- CN110491323B CN110491323B CN201910719820.9A CN201910719820A CN110491323B CN 110491323 B CN110491323 B CN 110491323B CN 201910719820 A CN201910719820 A CN 201910719820A CN 110491323 B CN110491323 B CN 110491323B
- Authority
- CN
- China
- Prior art keywords
- gate
- driving
- voltage
- node
- driving signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The gate driving circuit comprises a multi-stage gate driving unit, the gate driving unit comprises a first driving unit, controls a first node voltage and a second node voltage, and provides a first driving signal to a first gate of a double-gate transistor according to the first node voltage and the second node voltage; and the second driving unit is controlled by the first node voltage and the second node voltage, provides a second driving signal to a second grid electrode of the double-grid transistor according to the reference voltage or the first driving signal, the second grid electrode of the double-grid transistor is far away from a substrate of the double-grid transistor than the first grid electrode, the first driving signal and the second driving signal are the same in a conduction interval of the double-grid transistor, at least part of the double-grid transistor is in a turn-off interval, the level states of the first driving signal and the second driving signal are consistent, the voltage of the first driving signal is higher than that of the second driving signal, the leakage current of the double-grid transistor in the turn-off interval is reduced, and the display quality of the display device is improved.
Description
Technical Field
The present invention relates to the field of driving technologies, and in particular, to a gate driving circuit, a method and a display device thereof.
Background
With the increasing technology of silicon thin films, in the field of display technologies, in order to improve display quality, technicians may use dual-gate transistors in an array substrate of a display device.
The display device comprises a display panel, wherein the display panel comprises pixel units which are arranged in an array mode, and each pixel unit comprises a transistor and a pixel. A display device 1000 shown in fig. 1 includes a display panel 1100, a gate driving circuit, and a source driving circuit. The gate driving circuit includes a plurality of gate driving units 1200 connected in cascade. The display panel 1100 includes a plurality of transistors 1110 arranged in an array, sources of the transistors 1110 are respectively connected to a source driving circuit through data lines arranged in columns, drains of the transistors 1110 are connected to a pixel capacitor, and a first gate and a second gate of the transistors 1110 are respectively connected to an output terminal of a corresponding gate driving unit 1200 in the gate driving circuit through a gate line 1120. Specifically, a cross-sectional view of the transistor 1110 in the display device 1000 shown in fig. 2 is illustrated. The transistor 1110 includes a first gate (bottom gate) 1111, a gate insulating layer 1113, an active layer 1114, a first doped layer 1115, a source 1116, a second doped layer 1117, a drain 1118, a passivation layer 1119, and a second gate (top gate) 1112.
In the prior art, the same voltage is provided to the first gate and the second gate of the transistor through the gate driving circuit, or the alternating voltage is provided to the first gate and the direct voltage is provided to the second gate separately through the gate driving circuit, so that the on-state current of the transistor device can be increased, but the leakage current of the double-gate transistor in the turn-off interval is large, so that the switching performance of the device of the transistor is deteriorated, and the display quality of the display device is affected.
The above technical problems can be solved by adjusting the manufacturing process of the transistor, however, the scheme has high input cost and technical difficulty.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In view of the above, the present invention provides a gate driving circuit, a method and a display device thereof to improve the switching performance of a transistor in the display device and further improve the display quality of the display device.
According to an aspect of the present invention, there is provided a gate driving circuit including a multi-stage gate driving unit, the gate driving unit including: the driving circuit comprises a first driving unit, a second driving unit and a control unit, wherein the first driving unit controls a first node voltage and a second node voltage based on a time sequence signal and an input signal and provides a first driving signal to a first grid electrode of a double-grid transistor according to the first node voltage and the second node voltage; and a second driving unit which supplies a second driving signal to a second gate of the double-gate transistor according to a reference voltage or the first driving signal under control of the first node voltage and the second node voltage, the second gate of the double-gate transistor being located farther from a substrate of the double-gate transistor than the first gate, wherein the first driving signal is the same as the second driving signal in an on-period of the double-gate transistor, the first driving signal is in a same level state as the second driving signal in at least a partial off-period of the double-gate transistor, and the voltage of the first driving signal is higher than the voltage of the second driving signal.
Preferably, when the second node voltage is characterized as a second level state through the voltage control at the first node, the output end of the second driving unit is connected with a reference voltage to output the second driving signal; when the second node voltage is characterized as a first level state through the first node control, the output end of the second driving unit is connected with the output end of the first driving unit to output the second driving signal.
Preferably, the reference voltage is an adjustable negative voltage.
Preferably, the second driving unit includes: a control end of the first switch tube is connected with the first node, a first path end of the first switch tube is connected with an output end of the first driving unit, and a second path end of the first switch tube is used as an output end of the second driving unit; and the control end of the second switch tube is connected with the second node, the first path end of the second switch tube is connected with and receives the reference voltage, and the second path end of the second switch tube is connected with the output end of the second driving unit.
Preferably, the first switching tube and the second switching tube have the same conductivity type.
Preferably, the first driving unit includes: an input module to charge the first node based on the input signal; the output module is connected with the first node, generates the first driving signal based on a first timing signal and the first node voltage and outputs the first driving signal through an output end of the first driving unit; the pull-down module is connected with the first node, pulls down the voltage of the first node based on a second time sequence signal, and controls the voltage of the second node based on the voltage of the first node; and a stabilizing module for controlling the first node voltage and the first driving signal to be stable based on the second node voltage.
Preferably, when the first node voltage is characterized as a first level state, the stabilizing module controls the second node voltage to be a second level state so that the first node voltage and the first driving signal are maintained stable.
According to another aspect of the present invention, there is provided a display device including the gate driving circuit described above.
Preferably, the display device further includes: the display panel comprises a plurality of double-gate transistors arranged in an array, and the output end of the first driving unit of each gate driving unit is connected with the first gates of the double-gate transistors in the corresponding row; the output end of the second driving unit of each grid driving unit is connected with the second grid of the double-grid transistor of the corresponding row.
According to another aspect of the present invention, there is provided a gate driving method, including: providing a first driving signal to the first gate of the double-gate transistor in the pixel unit of the corresponding row through the first driving unit in each gate driving unit; and providing a second driving signal to a second gate of the double-gate transistor in the corresponding row of pixel units through a second driving unit in each gate driving unit, wherein the second gate of the double-gate transistor is far away from the substrate of the double-gate transistor compared with the first gate, the first driving signal and the second driving signal are the same in an on interval of the double-gate transistor, and the voltage of the first driving signal is higher than that of the second driving signal in at least a part of an off interval of the double-gate transistor.
According to the gate driving circuit, the method and the display device, each stage of gate driving unit in the gate driving circuit outputs a first driving signal through the first driving unit to be provided to a first gate of the double-gate transistor, and outputs a second driving signal through the second driving unit to be provided to a second gate of the double-gate transistor, wherein the second gate of the double-gate transistor is far away from a substrate of the double-gate transistor compared with the first gate. The first driving signal and the second driving signal are the same in the conducting interval of the double-grid transistor, and the voltage of the first driving signal is higher than that of the second driving signal in at least partial turn-off interval of the double-grid transistor. When the voltage of the second driving signal is provided by the reference voltage, the voltage of the first driving signal is higher than that of the second driving signal, and the reference voltage is an adjustable negative voltage, so that a negative voltage exists between the top gate and the bottom gate of the double-gate transistor in the turn-off interval. The first driving signal and the second driving signal provided by the gate driving circuit drive the double-gate transistor in the display panel, wherein the first driving signal is connected with the first gate (bottom gate) of the transistor, and the second driving signal is connected with the second gate (top gate) of the transistor, so that the leakage current of the double-gate transistor in a turn-off interval is reduced, the switching performance of the double-gate transistor is improved, and the display quality of the display device is further improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic diagram illustrating a structure of a display device in the related art.
Fig. 2 shows a schematic cross-sectional view of a double gate transistor of the display device of fig. 1.
Fig. 3 shows a schematic structural diagram of a display device according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram illustrating an ith-stage gate driving unit in the gate driving circuit according to an embodiment of the present invention.
Fig. 5 illustrates a timing diagram of an ith stage gate driving unit according to an embodiment of the present invention.
Fig. 6 is a schematic diagram showing the current-voltage characteristics of a dual gate transistor in a display device according to an embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 3 shows a schematic structural diagram of a display device according to an embodiment of the present invention.
The display device mainly comprises a display panel, a driving circuit and a control circuit, wherein the display panel comprises a plurality of pixel units which are arranged in an array mode, each pixel unit comprises a double-gate transistor and a pixel structure, the state of the double-gate transistor is controlled through the driving circuit, the pixel structure is further controlled, and image display is achieved, and enabling signals of the driving circuit are provided by the control circuit.
As shown in fig. 3, the display device 2000 includes a display panel 1100, a source driver circuit, and a gate driver circuit. The gate driving circuit includes a plurality of, for example, cascaded gate driving units 2200, each for driving a corresponding row of pixel cells. The display panel 1100 includes a plurality of pixel units arranged in an array, each pixel unit is provided with a dual-gate transistor 1110, a first gate of the dual-gate transistor 1110 is connected to a first driving unit output end of a corresponding gate driving unit 2200 through a gate line 1120, a second gate of the dual-gate transistor 1110 is connected to a second driving unit output end of the corresponding gate driving unit 2200 through the gate line 1120, a source of the dual-gate transistor 1110 is connected to a source driving circuit through a data line, and a drain of the dual-gate transistor 1110 is connected to a pixel structure in the pixel unit. The second grid electrode of the double-grid transistor is far away from the substrate of the double-grid transistor than the first grid electrode, each grid electrode driving unit in the grid electrode driving circuit controls to open the double-grid transistor 1110 in each row of pixel units, and then the source electrode driving circuit writes the gray-scale data into the pixel structure through the double-grid transistor 1110 to realize display.
In the gate driving circuit, each gate driving unit 2200 drives the dual-gate transistor to increase the leakage current in the on-region and decrease the leakage current in the off-region, and outputs a first driving signal to the first gate of the dual-gate transistor 1110 and a second driving signal to the second gate of the dual-gate transistor 1110.
Fig. 4 is a schematic structural diagram illustrating an ith-stage gate driving unit in the gate driving circuit according to an embodiment of the present invention.
As shown in fig. 4, the ith stage gate driving unit 2200 in the gate driving circuit includes a first driving unit 2210 and a second driving unit 2220.
The first driving unit 2210 includes a first node Q1 and a second node Q2, and controls voltages of the first node Q1 and the second node Q2 based on a timing signal and an input signal to generate a first driving signal provided to a first gate of the double gate transistor. The first driving unit 2210 includes an input module 2211, an output module 2212, a pull-down module 2213, and a stabilization module 2214. The input module 2211 receives the input signal VIN to control charging to provide a voltage to the first node Q1. The output module 2212 receives the first timing signal CLK1 to generate the first driving signal Gn1 based on the voltage at the first node Q1 and outputs through the output terminal of the first driving unit 2210. The pull-down module 2213 is connected to the first node Q1 to pull down the voltage at the first node Q1 according to the received second timing signal CLK2 and control the voltage at the second node Q2 based on the voltage at the first node Q1. The stabilizing module 2214 is connected to the second node Q2 to control the voltage at the first node Q1 and the first driving signal Gn1 to be stable based on the voltage at the second node Q2 and according to the received low level signal VGL, and when the voltage at the first node Q1 is characterized as the first level state, the stabilizing module 2214 controls the voltage at the second node Q2 to be the second level state to control the voltage at the first node Q1 and the first driving signal Gn1 to be stable.
The second driving unit 2220 is connected to the first node Q1 and the second node Q2, respectively, and supplies the second driving signal Gn2 to a second gate of the double-gate transistor, which is located farther from the substrate of the double-gate transistor than the first gate, according to the reference voltage VL or the first driving signal Gn1 under the control of the first node Q1 voltage and the second node Q2 voltage. The second driving unit 2220 includes a first switching tube M1, a second switching tube M2. A control terminal of the first switch M1 is connected to the first node Q1, a first path terminal of the first switch M1 is connected to the output terminal of the first driving unit 2210, and a second path terminal of the first switch M1 is used as the output terminal of the second driving unit 2220. A control terminal of the second switch transistor M2 is connected to the second node Q2, a first path terminal of the second switch transistor M2 is connected to receive the reference voltage VL, and a second path terminal of the second switch transistor M2 is connected to the output terminal of the second driving unit 2220. The reference voltage VL is an adjustable negative voltage. The first switch tube M1 and the second switch tube M2 are, for example, of the same conductivity type.
In each stage of the gate driving unit 2200, when the voltage at the second node Q2 is characterized as the second level state by the voltage control at the first node Q1, the output terminal of the second driving unit 2220 is turned on with the reference voltage VL receiving terminal to generate and output the second driving signal Gn 2; when the voltage at the second node Q2 is controlled to be characterized as the first level state by the first node Q1, the output terminal of the second driving unit 2220 is turned on with the output terminal of the first driving unit 2210 to generate and output the second driving signal Gn 2. That is, the first driving signal Gn1 is the same as the second driving signal Gn2 in the on-interval of the double-gate transistor, and the voltage of the first driving signal Gn1 is lower than the voltage of the second driving signal Gn2 in at least a part of the off-interval of the double-gate transistor.
It should be noted that, the first to second switch transistors M1-M2 mentioned in this embodiment may be, for example, N-type thin film double gate transistors, and the first pass end and the second pass end of each double gate transistor may be interchanged (i.e., the drain and the source may be interchanged), and the first level state in this embodiment is, for example, a low level state, and the second level state is, for example, a high level state, but the implementation of the present invention is not limited thereto.
Fig. 5 illustrates a timing diagram of an ith stage gate driving unit according to an embodiment of the present invention.
As shown in fig. 5, each stage of the gate driving unit 2220 includes four stages during one duty cycle. The method comprises the following specific steps:
the first phase t1 is the precharge phase: when the input signal VIN is in the active level state, the input module 2211 precharges the first node Q1, so that the voltage at the first node Q1 is pulled up, and the voltage at the second node Q2 is pulled down to be in the first level state by the voltage control at the first node Q1. At this time, the output module 2212 is not turned on, so the first driving signal Gn1 is in the first level state, the first switch M1 of the second driving unit 2220 is turned on, and the second switch M2 is not turned on, so the level of the second driving signal Gn2 is the same as that of the first driving signal Gn 1.
The second stage t2 is the pull-up stage: the first timing signal CLK1 jumps to an active level state, the capacitor inside the output module 2212 is bootstrapped, and the voltage at the first node Q1 is further pulled up, so that the first driving signal Gn1 output by the output module 2212 based on the voltage at the first node Q1 is at a second level state, and the voltage at the second node Q2 is pulled down to be at the first level state by the voltage control at the first node Q1. At this time, the second driving unit 2220 is based on the voltages at the first node Q1 and the second node Q2, the first switch tube M1 is still conductive, the second switch tube M2 is not conductive, and the output terminal of the second driving unit 2220 is connected with the output terminal of the first driving unit 2210 via the first switch tube M1, so that the voltages of the second driving signal Gn2 and the first driving signal Gn1 are the same.
The third stage t3 is the first node pull-down stage: the second timing signal CLK2 jumps to an active level state, the first timing signal CLK1 jumps to an inactive level state, and the voltage at the node Q2 is kept constant based on the control of the voltage at the first node Q1. The output terminal of the first drive unit 2210 controls the output first drive signal Gn1 in a first level state based on the voltage at the first node Q1. The first switching transistor M1 of the second driving unit 2220 is turned on based on the voltage at the first node Q1, the second switching transistor M2 is turned off based on the voltage at the second node Q2, and the output terminal of the second driving unit 2220 is connected with the output terminal of the first driving unit 2210 via the first switching transistor M1, so that the voltages of the second driving signal Gn2 and the first driving signal Gn1 are the same.
The fourth stage t4 is a stabilization stage: the second timing signal CLK2 jumps to an inactive level state, the first timing signal CLK1 remains in the inactive level state, the voltage at the first node Q1 is in the first level state, and the voltage at the second node Q2 is in the second level state. The first driving unit 2210 is in a turn-on state to make the first driving signal Gn1 maintain a first level state based on the voltage at the first node Q1. The first switch tube M1 of the second drive unit 2220 is controlled to be non-conductive based on the voltage at the first node Q1, the second switch tube M2 is controlled to be conductive based on the voltage at the second node Q2, the output terminal of the second drive unit 2220 is connected via the second switch tube M2 and receives the reference voltage VL, so that the second drive signal Gn2 is not consistent with the voltage of the first drive signal Gn1 based on the reference voltage VL, and the voltage of the first drive signal Gn1 is higher than the voltage of the second drive signal Gn2 based on the reference voltage, and the level states of the first drive signal Gn1 and the second drive signal Gn2 are consistent, in this embodiment, both the first drive signal Gn1 and the second drive signal Gn2 are at a low level in this stage.
In the gate driving circuit provided by the application, each stage of gate driving unit outputs a first driving signal through the first driving unit to be provided to a first gate of the double-gate transistor, and outputs a second driving signal through the second driving unit to be provided to a second gate of the double-gate transistor, wherein the second gate of the double-gate transistor is far away from a substrate of the double-gate transistor compared with the first gate. The first driving signal and the second driving signal are the same in the conducting interval of the double-grid transistor, and the voltage of the first driving signal is higher than that of the second driving signal in at least partial turn-off interval of the double-grid transistor. When the voltage of the second driving signal is provided by the reference voltage, the voltage of the first driving signal is higher than that of the second driving signal, and the reference voltage is an adjustable negative voltage, so that a negative voltage exists between the top gate and the bottom gate of the double-gate transistor in the turn-off interval.
Fig. 6 is a schematic diagram illustrating a current-voltage characteristic curve of a transistor in a display device according to an embodiment of the present invention.
As shown in fig. 6, the voltage-current characteristic curves of the dual-gate transistors obtained by driving the dual-gate transistors in the display panel for different gate driving circuits.
Curve L1 is a voltage-current characteristic curve obtained by driving the dual-gate transistor through the gate driving unit of the gate driving circuit provided in the present application. Curve L2 is a current-voltage characteristic curve obtained by driving the dual-gate transistor through the second gate driving circuit, wherein the gate driving unit of the second gate driving circuit generates and outputs the first driving signal for driving the first gate of the dual-gate transistor by the first driving unit 2210 provided in this application, and the second driving signal for driving the second gate of the dual-gate transistor, which is generated and output by the gate driving unit of the second gate driving circuit, is a dc signal with a positive voltage. Curve L3 is a voltage-current characteristic curve obtained by driving the dual-gate transistor through the third gate driving circuit, wherein the gate driving unit of the third gate driving circuit generates and outputs two identical driving signals from the first driving unit 2210 provided in this application, so as to drive the first gate and the second gate of the dual-gate transistor respectively. Curve L4 is a current-voltage characteristic curve obtained by driving the dual-gate transistor through a fourth gate driving circuit, wherein the gate driving unit of the fourth gate driving circuit generates and outputs a first driving signal for driving the first gate of the dual-gate transistor by the first driving unit 2210 provided in this application, and the second driving signal for driving the second gate of the dual-gate transistor, which is generated and output by the gate driving unit of the second gate driving circuit, is a dc signal of the first negative voltage VL 1. Curve L5 is a current-voltage characteristic curve obtained by driving the dual-gate transistor through a fifth gate driving circuit, wherein the gate driving unit of the fifth gate driving circuit generates and outputs a first driving signal for driving the first gate of the dual-gate transistor by the first driving unit 2210 provided in this application, and the second driving signal for driving the second gate of the dual-gate transistor, which is generated and output by the gate driving unit of the second gate driving circuit, is a dc signal of a second negative voltage VL 2.
The voltage value of the first negative voltage VL1 is higher than that of the second negative voltage VL 2. As can be seen from fig. 6, when the first gate and the second gate of the dual-gate transistor receive the same driving signal, the on-state current of the dual-gate transistor is increased, but the off-state current is also increased. When a DC signal representing a positive voltage is provided to the second gate alone, the on-state current of the double-gate transistor is increased but the off-state current is also increased a lot. When a DC signal representing a negative voltage is provided to the second gate electrode, the on-state current of the double-gate transistor is increased and the off-state current is reduced. In summary, the gate driving circuit provided by the application drives the double-gate transistors arranged in the display panel in an array manner, so that the on-state current of the double-gate transistors is increased while the off-state current is reduced, the switching performance of the double-gate transistors is improved on the basis of not adjusting the manufacturing process of the double-gate transistors, and the display quality of the display device is improved.
The application also provides a grid driving method which is executed in the display device. The gate driving method includes: providing a first driving signal to the first gate of the double-gate transistor in the pixel unit of the corresponding row through the first driving unit in each gate driving unit; and providing a second driving signal to a second gate of the double-gate transistor in the corresponding row of pixel units through a second driving unit in each gate driving unit, wherein the second gate of the double-gate transistor is far away from a substrate of the double-gate transistor compared with the first gate, the first driving signal and the second driving signal are the same in an on interval of the double-gate transistor, the first driving signal and the second driving signal are consistent in level state in at least a part of an off interval of the double-gate transistor, and the voltage of the first driving signal is higher than that of the second driving signal.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A gate driving circuit comprising a multi-stage gate driving unit, the gate driving unit comprising:
the driving circuit comprises a first driving unit, a second driving unit and a control unit, wherein the first driving unit controls a first node voltage and a second node voltage based on a time sequence signal and an input signal and provides a first driving signal to a first grid electrode of a double-grid transistor according to the first node voltage and the second node voltage; and
a second driving unit for providing a second driving signal to a second gate of the dual gate transistor according to a reference voltage or the first driving signal under the control of the first node voltage and the second node voltage, the second gate of the dual gate transistor being far from a substrate of the dual gate transistor than the first gate,
the first driving signal and the second driving signal are the same in an on interval of the double-gate transistor, the first driving signal and the second driving signal are consistent in level state in at least a part of an off interval of the double-gate transistor, and the voltage of the first driving signal is higher than that of the second driving signal.
2. A gate driving circuit as claimed in claim 1, wherein when the second node voltage is characterized as a second level state by the voltage control at the first node, the output terminal of the second driving unit is connected to a reference voltage to output the second driving signal; when the second node voltage is characterized as a first level state through the first node control, the output end of the second driving unit is connected with the output end of the first driving unit to output the second driving signal.
3. A gate drive circuit as claimed in claim 2, wherein the reference voltage is an adjustable negative voltage.
4. A gate drive circuit as claimed in claim 2, wherein the second drive unit comprises:
a control end of the first switch tube is connected with the first node, a first path end of the first switch tube is connected with an output end of the first driving unit, and a second path end of the first switch tube is used as an output end of the second driving unit; and
and the control end of the second switch tube is connected with the second node, the first path end of the second switch tube is connected with and receives the reference voltage, and the second path end of the second switch tube is connected with the output end of the second driving unit.
5. A gate drive circuit as claimed in claim 4, wherein the first and second switching tubes are of the same conductivity type.
6. A gate drive circuit as claimed in claim 1, wherein the first drive unit comprises:
an input module to charge the first node based on the input signal;
the output module is connected with the first node, generates the first driving signal based on a first timing signal and the first node voltage and outputs the first driving signal through an output end of the first driving unit;
the pull-down module is connected with the first node, pulls down the voltage of the first node based on a second time sequence signal, and controls the voltage of the second node based on the voltage of the first node; and
and the stabilizing module is used for controlling the first node voltage and the first driving signal to be kept stable based on the second node voltage.
7. The gate driving circuit of claim 6, wherein when the first node voltage is characterized as a first level state, the stabilizing module controls the second node voltage to be a second level state so that the first node voltage and the first driving signal are maintained stable.
8. A display device comprising the gate driver circuit according to any one of claims 1 to 7.
9. The display device according to claim 8, further comprising:
the display panel comprises a plurality of double-gate transistors which are arranged in an array manner, and the output end of the first driving unit of each gate driving unit is connected with the first gates of the double-gate transistors in the corresponding row; the output end of the second driving unit of each grid driving unit is connected with the second grid of the double-grid transistor in the corresponding row.
10. A gate driving method, comprising:
providing a first driving signal to the first gate of the double-gate transistor in the pixel unit of the corresponding row through the first driving unit in each gate driving unit;
providing a second driving signal to a second gate of the double-gate transistor in the corresponding row of pixel cells through a second driving unit in each gate driving unit, the second gate of the double-gate transistor being far from the substrate of the double-gate transistor than the first gate,
the first driving signal and the second driving signal are the same in the conducting interval of the double-gate transistor, and the voltage of the first driving signal is higher than that of the second driving signal in at least partial turn-off interval of the double-gate transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910719820.9A CN110491323B (en) | 2019-08-06 | 2019-08-06 | Gate driving circuit, method and display device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910719820.9A CN110491323B (en) | 2019-08-06 | 2019-08-06 | Gate driving circuit, method and display device thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110491323A CN110491323A (en) | 2019-11-22 |
| CN110491323B true CN110491323B (en) | 2022-03-25 |
Family
ID=68549536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910719820.9A Active CN110491323B (en) | 2019-08-06 | 2019-08-06 | Gate driving circuit, method and display device thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110491323B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011112722A (en) * | 2009-11-24 | 2011-06-09 | Sony Corp | Display device, method of driving the same and electronic equipment |
| CN103927965A (en) * | 2014-03-21 | 2014-07-16 | 京东方科技集团股份有限公司 | Driving circuit, driving method, GOA unit, GOA circuit and display device |
| CN105741779A (en) * | 2016-03-24 | 2016-07-06 | 北京大学深圳研究生院 | Pixel circuit based on double-gate transistor and drive method thereof |
| KR20180078109A (en) * | 2016-12-29 | 2018-07-09 | 엘지디스플레이 주식회사 | Electroluminescent Display Device |
| CN108648684A (en) * | 2018-07-03 | 2018-10-12 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN109962114A (en) * | 2019-04-17 | 2019-07-02 | 京东方科技集团股份有限公司 | Double grid TFT, pixel circuit and its control method |
-
2019
- 2019-08-06 CN CN201910719820.9A patent/CN110491323B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011112722A (en) * | 2009-11-24 | 2011-06-09 | Sony Corp | Display device, method of driving the same and electronic equipment |
| CN103927965A (en) * | 2014-03-21 | 2014-07-16 | 京东方科技集团股份有限公司 | Driving circuit, driving method, GOA unit, GOA circuit and display device |
| CN105741779A (en) * | 2016-03-24 | 2016-07-06 | 北京大学深圳研究生院 | Pixel circuit based on double-gate transistor and drive method thereof |
| KR20180078109A (en) * | 2016-12-29 | 2018-07-09 | 엘지디스플레이 주식회사 | Electroluminescent Display Device |
| CN108648684A (en) * | 2018-07-03 | 2018-10-12 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN109962114A (en) * | 2019-04-17 | 2019-07-02 | 京东方科技集团股份有限公司 | Double grid TFT, pixel circuit and its control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110491323A (en) | 2019-11-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10902931B2 (en) | Shift register unit and method for driving the same, gate driving circuit, and display apparatus | |
| KR101613000B1 (en) | Shift register unit and driving method thereof, shift register and display apparatus | |
| CN110136652B (en) | GOA circuit and array substrate | |
| US9887013B2 (en) | Shift register unit, shift register, and display apparatus | |
| KR101957067B1 (en) | Gate drive circuit having self-compensation function | |
| US10803809B2 (en) | Gate driving circuit, driving method thereof, and display device | |
| US9396813B2 (en) | Shift register cell, shift register, gate driver and display panel | |
| US10396796B2 (en) | Circuit, system and method for thin-film transistor logic gates | |
| US10460652B2 (en) | Scan driver circuit and liquid crystal display device having the circuit | |
| CN109493783B (en) | GOA circuit and display panel | |
| CN112397008B (en) | GOA circuit and display panel | |
| CN109658888B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| US20190213969A1 (en) | Gate driving circuit, driving method, and display device | |
| WO2020156386A1 (en) | Shift register and drive method therefor, gate drive circuit and display apparatus | |
| US11308859B2 (en) | Shift register circuit and method of driving the same, gate driver circuit, array substrate and display device | |
| KR20170038925A (en) | Low-temperature polycrystalline silicon semiconductor thin-film transistor-based goa circuit | |
| CN104821146A (en) | Grid driving circuit, unit thereof and display device | |
| CN112017613A (en) | Charge sharing circuit and method, display driving module and display device | |
| CN112102768A (en) | GOA circuit and display panel | |
| CN107112051B (en) | Unit shift register circuit, method for controlling unit shift register circuit, and display device | |
| CN106652869B (en) | Control circuit for display panel, driving method and display device | |
| JPH09222591A (en) | Off voltage generating circuit | |
| CN112908276B (en) | Grid driving circuit and display device | |
| US10475407B2 (en) | GOA circuit and display device | |
| CN107564450B (en) | Gate drive circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: Kunshan Longteng Optronics Co., Ltd. |
|
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |