KR102316567B1 - Electroluminescent Display Device And Driving Method Of The Same - Google Patents

Abstract

The electroluminescent display device of the present invention includes a first pixel, a second pixel and a control switch. The first pixel includes a first light emitting device having an anode electrode connected to a first node and a cathode electrode connected to an input terminal of a low potential pixel driving voltage, and a first driving device connected between a high potential power supply line and the first node. has The second pixel includes a second light emitting device having an anode electrode connected to a second node and a cathode electrode connected to an input terminal of the low potential pixel driving voltage, and a second light emitting device connected between the high potential power supply line and the second node. It has a driving element. The control switch is connected between the first node and the second node, is turned on in a first driving mode for displaying a low grayscale image, and is turned off in a second driving mode for displaying a high grayscale image do.

Description

Electroluminescent Display Device And Driving Method Of The Same

The present invention relates to an electroluminescent display device and a driving method thereof.

The electroluminescent display device is roughly divided into an inorganic light emitting display device and an electroluminescent display device according to the material of the light emitting layer. Among them, the active matrix type electroluminescent display device includes an organic light emitting diode (hereinafter referred to as "OLED"), which is a representative electroluminescent diode that emits light by itself, and has a response speed It has the advantages of fast speed, luminous efficiency, luminance and viewing angle.

OLED, which is a self-luminous device, includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween. An electroluminescent display device arranges pixels each including an OLED and a driving TFT (Thin Film Transistor) in a matrix form, and adjusts the luminance of an image implemented in the pixels according to the gradation of image data. The driving TFT controls the pixel current input to the OLED according to the voltage applied between its gate electrode and the source electrode (hereinafter referred to as “gate-source voltage”).

In general, when the driving TFT operates in the saturation region, the pixel current Ids flowing between the drain-source of the driving TFT is expressed as follows.

Ids = 1/2*(μ*C*W/L)*(Vgs-Vth) ²

Here, μ denotes electron mobility, C denotes the capacitance of the gate insulating film, W denotes the channel width of the driving TFT, and L denotes the channel length of the driving TFT, respectively. And, Vgs represents the gate-source voltage of the driving TFT, and Vth represents the threshold voltage (or threshold voltage) of the driving TFT.

The amount of light emitted and the luminance of the OLED are determined according to the pixel current. In other words, the gradation is expressed by the pixel current flowing through the driving TFT. Since the pixel current is proportional to the square of the gate-source voltage, it is difficult to express grayscale in a low grayscale region.

In the case of a high-resolution, large-area panel, the pixel size is small and the current driving ability of the driving TFT is high. The higher the current driving capability, the lower the current resolution of the driving TFT in the low gray scale region, and thus the low gray scale expression power decreases. In order to increase the expressive power of low gradation, the prior art uses a data processing algorithm such as a dithering technique or a frame rate control technique, but more circuit logic is required for this, and due to the data processing algorithm, There is a side effect such as a gradation step in the low gradation region.

Accordingly, the present invention has been devised to solve the above-described problems, and provides an electroluminescent display device capable of minimizing side effects and increasing low grayscale expression power and a driving method thereof.

The electroluminescent display device of the present invention includes a first pixel, a second pixel and a control switch. The first pixel includes a first light emitting device having an anode electrode connected to a first node and a cathode electrode connected to an input terminal of a low potential pixel driving voltage, and a first driving device connected between a high potential power supply line and the first node. has The second pixel includes a second light emitting device having an anode electrode connected to a second node and a cathode electrode connected to an input terminal of the low potential pixel driving voltage, and a second light emitting device connected between the high potential power supply line and the second node. It has a driving element. The control switch is connected between the first node and the second node, is turned on in a first driving mode for displaying a low grayscale image, and is turned off in a second driving mode for displaying a high grayscale image do.

The method of driving an electroluminescent display device according to the present invention includes a first light emitting device having an anode electrode connected to a first node and a cathode electrode connected to an input terminal of a low potential pixel driving voltage, and between a high potential power supply line and the first node. a first pixel having a connected first driving element; and a second light emitting device having an anode electrode connected to a second node and a cathode electrode connected to an input terminal of the low potential pixel driving voltage, and a second driving device connected between the high potential power supply line and the second node. A method of driving an electroluminescent display device having a second pixel, wherein input image data to be written in the first pixel and the second pixel is analyzed to display a first driving mode for displaying a low grayscale image and a high grayscale image separating the second driving mode for turning on a control switch connected between the first node and the second node in the first driving mode; and turning off the control switch in the second driving mode.

According to the present invention, when a low grayscale image is displayed, a control switch connected between two pixels is turned on, and all of the light emitting devices of the two pixels are driven with a pixel current generated in any one of the two pixels. Since the pixel current generated in the one pixel is large enough to drive all the light emitting devices of the two pixels, the current resolution and low grayscale expression power of the driving device included in the one pixel can be greatly improved.

The present invention can greatly improve the current resolution and low grayscale expression power of the driving device while minimizing grayscale distortion when displaying a low grayscale image.

In the present invention, since a data processing algorithm such as a dithering technique or a frame rate control technique is not used to increase the expressive power of the low gray scale, the circuit logic can be simplified as much as possible, and the low gray level due to the data processing algorithm It is possible to prevent a side effect such as a gradation step occurring in the gradation region in advance.

1 is a view showing an electroluminescent display device according to an embodiment of the present invention.
FIG. 2 is a view showing a pixel array formed on the display panel of FIG. 1 .
3 is a diagram illustrating a method of driving an electroluminescent display device according to an embodiment of the present invention.
4 is a view showing an example of a connection of a control switch according to the first embodiment of the present invention.
5 is a circuit diagram illustrating a detailed configuration of a first pixel, a second pixel, and a control switch according to the first embodiment of the present invention.
6 is a waveform diagram of driving signals applied to the circuit diagram of FIG. 5 in a second driving mode.
FIG. 7 is a view showing the operation of the circuit diagram of FIG. 5 according to the driving signals of FIG. 6 .
8 is a waveform diagram of driving signals applied to the circuit diagram of FIG. 5 in a first driving mode.
9A and 9B are diagrams illustrating the operation of the circuit diagram of FIG. 5 according to the driving signals of FIG. 8 .
10 is another waveform diagram of driving signals applied to the circuit diagram of FIG. 5 in a first driving mode.
11A and 11B are diagrams illustrating the operation of the circuit diagram of FIG. 5 according to the driving signals of FIG. 10 .
12 is a view showing a connection example of a control switch according to a second embodiment of the present invention.
13 is a circuit diagram illustrating a detailed configuration of a first pixel, a second pixel, and a control switch according to a second embodiment of the present invention.
14 is a waveform diagram of driving signals applied to the circuit diagram of FIG. 13 in a second driving mode.
15 is a diagram illustrating an operation of the circuit diagram of FIG. 13 according to the driving signals of FIG. 14 .
16 is a waveform diagram of driving signals applied to the circuit diagram of FIG. 13 in a first driving mode.
17 is a diagram illustrating an operation of the circuit diagram of FIG. 13 according to the driving signals of FIG. 16 .
18 is a diagram illustrating another operation of the circuit diagram of FIG. 13 according to the driving signals of FIG. 16 .
19 is a waveform diagram illustrating a change in pixel current in a low grayscale section and a high grayscale section.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

The first, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to substantially like elements throughout.

Features of various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship. have.

In the present invention, the pixel circuit formed on the substrate of the display panel may be implemented as a TFT having an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type TFT, since electrons flow from the source to the drain, the direction of the current flows from the drain to the source. In the case of a p-type TFT (PMOS), since a carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET may be changed according to an applied voltage.

Hereinafter, the gate-on voltage is the voltage of the gate signal at which the TFT can be turned on. The gate off voltage is a voltage at which the TFT can be turned off. In NMOS, the gate-on voltage is the gate-high voltage, and the gate-off voltage is the gate-low voltage. In a PMOS, a gate-on voltage is a gate-low voltage, and a gate-off voltage is a gate-high voltage.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the electroluminescent display device will be mainly described with respect to the organic light emitting display device including the organic light emitting material. However, it should be noted that the technical spirit of the present invention is not limited to the electroluminescent display device, and may be applied to an inorganic light emitting display device including an inorganic light emitting material.

FIG. 1 shows an electroluminescent display device according to an embodiment of the present invention, and FIG. 2 shows a pixel array formed on the display panel of FIG. 1 . 3 shows a method of driving an electroluminescent display device according to an embodiment of the present invention.

1 and 2 , an electroluminescent display device according to an embodiment of the present invention may include a display panel 10 , a timing controller 11 , a data driving circuit 12 , and a gate driving circuit 13 . can

In the display panel 10 , a plurality of data lines 14 and a plurality of gate lines 15 cross each other, and pixels PIX are arranged in a matrix form in each crossed area. Each of the pixels PIX includes a light emitting element (hereinafter, OLED) and a driving element (hereinafter, a driving TFT), respectively.

Each pixel PIX may further include a switch TFT for controlling a gate-source voltage of the driving TFT. The switching TFT of each pixel PIX is switched by the gate signal applied from the gate line 15 . Each pixel PIX may be connected to at least one gate line 15 according to a circuit configuration thereof. Each pixel PIX may receive a high potential pixel driving voltage EVDD and a low potential pixel driving voltage EVSS generated by a power generator (not shown).

In the display panel 10 , a pixel array as shown in FIG. 2 is formed by pixels PIX arranged in a matrix form. The pixel array may include a plurality of pixel lines L#1 to L#n. Here, each pixel line refers to a set of pixels PIX arranged adjacent to each other along a gate line extension direction (eg, a horizontal direction) to receive input image data DATA at the same time. The pixel array may be connected to the data lines 14 and the gate lines 15 , and may be further connected to a high potential power line to which the high potential pixel driving voltage EVDD is supplied.

The pixels PXL may include a red pixel, a green pixel, a blue pixel, and a white pixel to implement various colors. A red pixel, a green pixel, a blue pixel, and a white pixel may constitute one unit pixel. A color implemented in a unit pixel may be determined according to emission ratios of a red pixel, a green pixel, a blue pixel, and a white pixel. One data line 14 , one gate line 15a , a high potential power line, etc. may be connected to each of the pixels PXL.

The display panel 10 may further include a plurality of control switches connecting two pixels PIX implementing the same color to each other. A gate electrode of each control switch may be connected to a control line to which a control signal is applied.

The timing controller 11 analyzes the input image data DATA in units of 1 pixel line or 2 pixel lines as shown in FIG. 3, and performs a first driving mode for displaying a low grayscale image based on the analysis result. A second driving mode for displaying a high grayscale image is separated (S1, S2, S3, and S6). Here, the low grayscale image indicates an image in which the average grayscale value of the image data written in the first and second pixels connected to each other through the control switch is equal to or lower than a preset threshold grayscale value (TH in FIG. 19). . The high grayscale image indicates an image in which the average grayscale value of the image data written in the first pixel and the second pixel is higher than the threshold grayscale value (TH of FIG. 19 ).

The timing controller 11 controls the gate driving circuit 13 to turn on the control switch in the first driving mode for displaying the low grayscale image, and turns on the control switch in the second driving mode for displaying the high grayscale image. It can be turned off (S4, S7).

The timing controller 11 controls the data driving circuit 12 and the gate driving circuit 13 in the first driving mode to generate a pixel current of any one of the first pixel and the second pixel. All OLEDs can be driven (S5). The timing controller 11 controls the data driving circuit 12 and the gate driving circuit 13 in the second driving mode to drive the OLED of the first pixel with the pixel current of the first pixel, and The OLED of the second pixel may be driven by the pixel current (S8).

The timing controller 11 replaces the image data to be written in the first pixel and the second pixel with data for driving black and data for driving low grayscale in the first driving mode, and transmits the replaced data to the data driving circuit 12 . can supply On the other hand, the timing controller 11 may supply image data to be written in the first pixel and the second pixel to the data driving circuit 12 in the second driving mode.

The timing controller 11 receives digital data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The host system may be any one of a television (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The timing controller 11 multiplies the input frame frequency by i to control the operation timing of the display panel driving circuits 12 and 13 with the frame frequency of the input frame frequency * i (i is a positive integer greater than 0) Hz. have. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme.

The timing controller 11 includes a data timing control signal DDC for controlling the operation timing of the data driving circuit 12 based on the timing signals Vsync, Hsync, DE, and DCLK received from the host system, and a gate driving circuit A gate timing control signal GDC for controlling the operation timing of the furnace 13 is generated.

The data timing control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the sampling start timing of the data driving circuit 12 . The source sampling clock is a clock for shifting the data sampling timing. If the signal transmission interface between the timing controller 11 and the data driving circuit 12 is a mini LVDS (Low Voltage Differential Signaling) interface, the source start pulse and the source sampling clock may be omitted.

The gate timing control signal GDC includes a gate start pulse, a gate shift clock, and the like. The gate start pulse is generated at the beginning of each frame period and is input to each shift register of the gate driving circuit 13 . The gate start pulse controls the start timing at which the gate signal is output in every frame period. The gate shift clock is input to the shift register of the gate driving circuit 13 to control shift timing of the gate signal.

The data driving circuit 12 converts the input image data DATA received from the timing controller 11 into a data voltage in the first driving mode, and then converts the data voltage to the data lines connected to all the pixels PIX. 14) can be supplied. The data driving circuit 12 converts the black driving data received from the timing controller 11 into a black driving data voltage in the second driving mode and also converts the low grayscale driving data received from the timing controller 11 . The low grayscale driving data voltage may be converted and supplied to the data lines 14 connected to some pixels PIX. The data driving circuit 12 converts the input image data DATA received from the timing controller 11 into a data voltage in the second driving mode, and then converts the data voltage to the remaining pixels except for the some pixels PIX. It can be supplied to the data lines 14 connected to (PIX).

The data driving circuit 12 may include a digital-to-analog converter that converts digital data into an analog voltage.

A multiplexer (not shown) may be further disposed between the data driving circuit 12 and the data lines 14 of the display panel 10 . The multiplexer divides the data voltage output from the data driving circuit 12 through one output channel into a plurality of data lines, thereby reducing the number of output channels of the data driving circuit 12 compared to the number of data lines. The multiplexer may be omitted depending on the resolution and use of the display device.

The data driving circuit 12 may further include a power generator (not shown). Meanwhile, the power generator may be electrically connected to the data driving circuit through a conductive film or the like after being mounted on the outside of the data driving circuit 12 .

The gate driving circuit 13 may generate a gate signal in the first and second driving modes and supply it to the gate lines 15 connected to all the pixels PIX in a line sequential manner. The gate driving circuit 13 may generate a control signal at an off level in the first driving mode and supply it to the control lines connected to the control switches. The gate driving circuit 13 generates a control signal at an on level in the second driving mode and supplies it to control lines connected to some control switches, and generates a control signal at an OFF level to control lines connected to the remaining control switches. can be supplied to The gate driving circuit 13 may be built in a non-display area outside the screen area of the display panel 10 . Meanwhile, the gate driving circuit 13 may be manufactured as an IC (Integrated Circuit) type and then bonded to the display panel 10 through a conductive film.

4 shows a connection example of the control switch according to the first embodiment of the present invention.

Referring to FIG. 4 , the first pixel PB1 and the second pixel PB2 connected to each other through the control switch CT implement the same color. The control switch CT is switched according to the control signal CON applied from the control line 17 to electrically connect or block the first pixel PB1 and the second pixel PB2. The first pixel PB1 and the second pixel PB2 may be a red pixel, a green pixel, a blue pixel, or a white pixel.

4 , the first pixel PB1 and the second pixel PB2 are disposed adjacent to each other in the Y direction (the data line extension direction), and may be connected to the same data line and to different gate lines. . In general, since two pixels that implement the same color and are disposed adjacent to each other exhibit similar luminance except in exceptional cases, turn on the control switch CT in the first driving mode to distribute one pixel current to Even if it is supplied to light emitting elements, there is no problem in image display.

In FIG. 4 , a pixel PA1 , a pixel PB1 , a pixel PC1 , and a pixel PD1 implementing different colors (red/white/green/blue) may constitute a unit pixel UPXL1. In addition, the pixel PA2, the pixel PB2, the pixel PC2, and the pixel PD2 implementing different colors (red/white/green/blue) may constitute a unit pixel UPXL2.

The current driving capability of the driving TFT is relatively high in the case of the white pixel compared to the red, green, and blue pixels. Accordingly, the problem that the current resolution of the driving TFT is low in the low gray scale region and the low gray scale expression power is lowered is more serious in the white pixel. Considering this, the first pixel PB1 and the second pixel PB2 may be white pixels. However, the technical spirit of the present invention is not limited thereto. The first pixel PB1 and the second pixel PB2 may be any one of red, green, and blue pixels.

Meanwhile, although the control switch is connected only between pixels of a specific color in FIG. 4 , the control switch may be further connected between pixels of other colors.

5 shows a detailed configuration of the first pixel PB1, the second pixel PB2, and the control switch CT according to the first embodiment of the present invention.

Referring to FIG. 5 , the first pixel PB1 includes a first light emitting device OL1 having an anode electrode connected to the first node N1 and a cathode electrode connected to an input terminal of the low potential pixel driving voltage EVSS; It has a first driving element DT1 connected between the high potential power wiring 18 and the first node N1. The first pixel PB1 may further include a first switch element ST1 and a first storage capacitor Cst1. The gate electrode of the first driving element DT1 is connected to the node Nx, and the source electrode is connected to the first node N1. The first storage capacitor Cst1 is connected to the node Nx and the first node N1 to store the gate-source voltage of the first driving device DT1 for one frame. The first switch element ST1 is connected between the data line 14 and the node Nx, and is switched according to the j-th gate signal SCAN applied from the j-th gate line 15a (j is a natural number).

Referring to FIG. 5 , the second pixel PB2 includes a second light emitting device OL2 having an anode electrode connected to the second node N2 and a cathode electrode connected to an input terminal of the low potential pixel driving voltage EVSS; It has a second driving element DT2 connected between the high potential power wiring 18 and the second node N2. The second pixel PB2 may further include a second switch element ST2 and a second storage capacitor Cst2. The gate electrode of the second driving element DT2 is connected to the node Ny, and the source electrode is connected to the second node N2. The second storage capacitor Cst2 is connected to the node Ny and the second node N2 to store the gate-source voltage of the second driving device DT2 for one frame. The second switch element ST2 is connected between the data line 14 and the node Ny, and is switched according to the j+1th gate signal SCAN applied from the j+1th gate line 15b.

Referring to FIG. 5 , the control switch CT is connected between the first node N1 and the second node N2 , and is switched according to the control signal CON applied from the control line 17 . The control switch CT is turned on in the first driving mode for displaying a low grayscale image, and is turned off in the second driving mode for displaying a high grayscale image. Here, the low grayscale image indicates an image in which an average grayscale value of image data written in the first pixel PB1 and the second pixel PB2 is equal to or lower than a preset threshold grayscale value (TH in FIG. 19 ). The high grayscale image indicates an image in which the average grayscale value of the image data written in the first pixel PB1 and the second pixel PB2 is higher than the threshold grayscale value (TH of FIG. 19 ).

6 is a waveform diagram of driving signals applied to the circuit diagram of FIG. 5 in a second driving mode. And, FIG. 7 is a view showing the operation of the circuit diagram of FIG. 5 according to the driving signals of FIG. 6 .

6 and 7 , in the second driving mode, the data driving circuit 12 supplies the data voltage DH1 to the data line 14 during section A, and applies the data voltage DH2 to the data line during section B following section A. (14) is supplied. The average grayscale value of the data voltages DH1 and DH2 is higher than a preset threshold grayscale value (TH in FIG. 19). In the second driving mode, the gate driving circuit 13 supplies the j-th gate signal SCAN of the on level to the j-th gate line 15a during the period A, and the j+1th gate signal (SCAN) of the on level during the period B. SCAN) is supplied to the j+1th gate line 15b. And, in the second driving mode, the gate driving circuit 13 supplies the control signal CON of the off level to the control line 17 during sections A and B.

6 and 7 , the first pixel PB1 programs the gate-source voltage of the first driving device DT1 during the period A, and maintains the programmed voltage until the start time of the next frame. During section A, the first switch element ST1 is turned on according to the on-level j-th gate signal SCAN, and the data voltage DH1 charged in the data line 14 is applied to the gate electrode of the first driving element DT1. do. In this case, a reference voltage may be applied to the source electrode of the first driving element DT1 through a reference power line (not shown). Here, the reference voltage is a DC voltage lower than the lowest data voltage (the data voltage for driving black). Accordingly, the gate-source voltage of the first driving device DT1 is programmed as the “data voltage DH1-reference voltage” and is stored in the first storage capacitor Cst1. Since the programmed voltage is higher than the threshold voltage of the first driving element DT1, the first driving element DT1 is turned on, and the first pixel current ( Ids1) flows. The first light emitting device OL1 emits light by the first pixel current Ids1 applied from the first driving device DT1 , and maintains this light emitting state for approximately one frame.

6 and 7 , the second pixel PB2 programs the gate-source voltage of the second driving device DT2 during period B, and maintains the programmed voltage until the start time of the next frame. During section B, the second switch element ST2 is turned on according to the on-level j+1th gate signal SCAN to apply the data voltage DH2 charged in the data line 14 to the gate electrode of the second driving element DT2. accredit to In this case, the reference voltage may be applied to the source electrode of the second driving element DT2 through a reference power line. Accordingly, the gate-source voltage of the second driving device DT2 is programmed as the “data voltage DH2-reference voltage” and is stored in the second storage capacitor Cst2. Since the programmed voltage is higher than the threshold voltage of the second driving element DT2, the second driving element DT2 is turned on, and the second pixel current ( Ids2) flows. The second light emitting device OL2 emits light by the second pixel current Ids2 applied from the second driving device DT2 and maintains this light emitting state for approximately one frame.

6 and 7 , in the second driving mode, the control switch CT is turned off according to the off-level control signal CON to electrically cut off the first node N1 and the second node N2. do. Accordingly, the first light emitting device OL1 is driven by the first pixel current Ids1 , and the second light emitting device OL2 is driven by the second pixel current Ids2 . The first pixel current Ids1 and the second pixel current Ids2 belong to the high grayscale section GR2 in the grayscale vs. pixel current graph of FIG. 19 . Since the current resolution of the driving element in the high grayscale section GR2 is higher than that of the low grayscale section GR1 , the control switch CT is turned off and the first pixel PB1 and the second pixel PB2 transmit the respective pixel currents. can be individually driven.

8 is a waveform diagram of driving signals applied to the circuit diagram of FIG. 5 in a first driving mode. And, FIGS. 9A and 9B show the operation of the circuit diagram of FIG. 5 according to the driving signals of FIG. 8 .

Referring to FIGS. 8, 9A and 9B , in the first driving mode, the data driving circuit 12 supplies the low grayscale driving data voltage DL1 to the data line 14 during the A' period, followed by the A' period. The data voltage DL2 for the black gradation is supplied to the data line 14 during the period B'. The low grayscale driving data voltage DL1 is higher than the black grayscale data voltage DL2. The low gray level driving data voltage DL1 is set higher than the average data voltage corresponding to the average gray level value of the low gray level image to improve the current resolution of the driving device. In this case, the average voltage of the low gray level driving data voltage DL1 and the black driving data voltage DL2 may be set to be the same as the average data voltage so that the gray level reversal phenomenon does not occur in the low gray level section.

In the first driving mode, the gate driving circuit 13 supplies the j-th gate signal SCAN of the on level to the j-th gate line 15a during the period A', and the j+1-th gate of the on level during the period B'. The signal SCAN is supplied to the j+1th gate line 15b. And, in the first driving mode, the gate driving circuit 13 supplies the control signal CON of the on level to the control line 17 for approximately one frame from the section A'. That is, in the first driving mode, the gate driving circuit 13 supplies the on-level control signal CON to the corresponding control line 17 for approximately one frame from the time when the low grayscale driving data voltage DL1 is applied.

Referring to FIGS. 8 and 9A , the first pixel PB1 programs the gate-source voltage of the first driving device DT1 during the period A′, and maintains the programmed voltage until the start time of the next frame. . During the A' period, the first switch element ST1 is turned on according to the on-level j-th gate signal SCAN to apply the low gray level driving data voltage DL1 charged in the data line 14 to the first driving element DT1 . applied to the gate electrode of In this case, a reference voltage may be applied to the source electrode of the first driving element DT1 through a reference power line (not shown). Here, the reference voltage is a DC voltage lower than the lowest data voltage (the data voltage for driving black). Accordingly, the gate-source voltage of the first driving device DT1 is programmed as the “low grayscale driving data voltage DL1-reference voltage” and is stored in the first storage capacitor Cst1 . Since the programmed voltage is higher than the threshold voltage of the first driving element DT1, the first driving element DT1 is turned on, and the first pixel current ( Ids1) flows.

8 and 9A , the control switch CT is turned on according to the on-level control signal CON in the section A' to electrically connect the first node N1 and the second node N2. . In this case, the first pixel current Ids1 is divided into the current IA and the current IB at the first node N1 . The first light emitting device OL1 is driven by the current IA, and the second light emitting device OL2 is driven by the current IB. In other words, the first light emitting device OL1 and the second light emitting device OL2 are driven by the divided currents IA and IB of the first pixel current Ids1 . 19 , since the first pixel current Ids1 is sufficiently large by the low gray level driving data voltage DL1, the current resolution and low gray level expression power of the first driving element DT1 are improved. A graph indicated by a dashed-dotted line in the low grayscale section GR1 of FIG. 19 represents the first pixel current Ids1 , and a graph indicated by a solid line in the low grayscale section GR1 represents distribution currents IA and IB. As can be clearly seen from FIG. 19 , the present invention can greatly improve the current resolution and low grayscale expression power of the driving device while minimizing grayscale distortion when displaying a low grayscale image.

Referring to FIGS. 8 and 9B , the second pixel PB2 programs the gate-source voltage of the second driving device DT2 during the period B′, and maintains the programmed voltage until the start time of the next frame. . During section B′, the second switch element ST2 is turned on according to the on-level j+1th gate signal SCAN to apply the black driving data voltage DL2 charged in the data line 14 to the second driving element DT2 . ) to the gate electrode. In this case, the reference voltage may be applied to the source electrode of the second driving element DT2 through a reference power line. Accordingly, the gate-source voltage of the second driving device DT2 is programmed as the “black driving data voltage DL2-reference voltage” and is stored in the second storage capacitor Cst2 . Since the programmed voltage is lower than the threshold voltage of the second driving device DT2 , the second driving device DT2 is turned off, and a pixel current does not flow through the second driving device DT2 .

Referring to FIGS. 8 and 9B , the control switch CT electrically connects the first node N1 and the second node N2 by maintaining an on state according to the on-level control signal CON in the section B′. Connect. At this time, no pixel current flows in the second driving device DT2 , and the first and second light emitting devices OL1 and OL2 are continuously driven by the distribution currents IA and IB of the first pixel current Ids1 . do. A graph indicated by a dotted line in the low grayscale section GR1 of FIG. 19 indicates that the pixel current does not flow in the second driving element DT2 . In the first driving mode, the control switch CT maintains an on state for approximately one frame, and accordingly, the first light emitting element OL1 and the second light emitting element OL1 and the second The light emitting element OL2 is driven.

10 is another waveform diagram of driving signals applied to the circuit diagram of FIG. 5 in a first driving mode. 11A and 11B show the operation of the circuit diagram of FIG. 5 according to the driving signals of FIG. 10 .

10 to 11B show the distribution currents IA of the second pixel current Ids2 because the application order of the low grayscale driving data voltage DL1 and the black driving data voltage DL2 is reversed compared to the aforementioned FIGS. 8 to 9B. There is a difference in that the first light emitting element OL1 and the second light emitting element OL2 are driven by , IB.

10, 11A, and 11B , in the first driving mode, the data driving circuit 12 supplies the data voltage DL2 for the black gradation to the data line 14 during section A”, followed by the data voltage DL2 for section A”. During the ” section, the data voltage DL1 for driving the low gradation is supplied to the data line 14 .

In the first driving mode, the gate driving circuit 13 supplies the j-th gate signal SCAN of the on level to the j-th gate line 15a during the period A” and the j+1th gate of the on level during the period B”. The signal SCAN is supplied to the j+1th gate line 15b. And, in the first driving mode, the gate driving circuit 13 supplies the control signal CON of the on level to the control line 17 for approximately one frame from section B”. That is, in the first driving mode, the gate driving circuit 13 supplies the on-level control signal CON to the corresponding control line 17 for approximately one frame from the time when the low grayscale driving data voltage DL1 is applied.

Referring to FIGS. 10 and 11A , the first pixel PB1 programs the gate-source voltage of the first driving device DT1 during the A” period, and maintains the programmed voltage until the start time of the next frame. . During the A” period, the first switch element ST1 is turned on according to the on-level j-th gate signal SCAN to apply the black driving data voltage DL2 charged in the data line 14 to that of the first driving element DT1. applied to the gate electrode. In this case, the reference voltage may be applied to the source electrode of the first driving element DT1 through a reference power line. Accordingly, the gate-source voltage of the first driving device DT1 is programmed as the “black driving data voltage DL2-reference voltage” and is stored in the first storage capacitor Cst1 . Since the programmed voltage is lower than the threshold voltage of the first driving device DT1 , the first driving device DT1 is turned off, and a pixel current does not flow through the first driving device DT1 .

Referring to FIGS. 10 and 11B , the second pixel PB2 programs the gate-source voltage of the second driving device DT2 during the period B” and maintains the programmed voltage until the start time of the next frame. . During the period B”, the second switch element ST2 is turned on according to the on-level j+1th gate signal SCAN to apply the low grayscale driving data voltage DL1 charged in the data line 14 to the second driving element ( DT2) is applied to the gate electrode. In this case, a reference voltage may be applied to the source electrode of the second driving element DT2 through a reference power line (not shown). Accordingly, the gate-source voltage of the second driving device DT2 is programmed as the “low grayscale driving data voltage DL1-reference voltage” and is stored in the second storage capacitor Cst2 . Since the programmed voltage is higher than the threshold voltage of the second driving element DT2, the second driving element DT2 is turned on, and the second pixel current ( Ids2) flows. A graph indicated by a dotted line in the low grayscale section GR1 of FIG. 19 indicates that the pixel current does not flow in the first driving element DT1 .

10 and 11B , the control switch CT is turned on according to the on-level control signal CON in the section B” to electrically connect the first node N1 and the second node N2. . In this case, the second pixel current Ids2 is divided into the current IA and the current IB at the second node N2 . The first light emitting device OL1 is driven by the current IA, and the second light emitting device OL2 is driven by the current IB. In other words, the first light emitting device OL1 and the second light emitting device OL2 are driven by the divided currents IA and IB of the second pixel current Ids2. 19 , since the second pixel current Ids2 is sufficiently large by the low gray level driving data voltage DL1, the current resolution and low gray level expression power of the second driving element DT2 are improved. A graph indicated by a dashed line in the low gray scale section GR1 of FIG. 19 represents the second pixel current Ids2, and a graph indicated by a solid line in the low gray scale section GR1 represents distribution currents IA and IB. As can be clearly seen from FIG. 19 , the present invention can greatly improve the current resolution and low grayscale expression power of the driving element while minimizing grayscale distortion when displaying a low grayscale image. In the first driving mode, the control switch CT maintains an on state for approximately one frame, and accordingly, the first light emitting element OL1 and the second The light emitting element OL2 is driven.

12 shows an example of a connection of a control switch according to a second embodiment of the present invention.

Referring to FIG. 12 , the first pixel PB1 and the second pixel PB2 connected to each other through the control switch CT implement the same color. The control switch CT is switched according to the control signal CON applied from the control line 17 to electrically connect or block the first pixel PB1 and the second pixel PB2. The first pixel PB1 and the second pixel PB2 may be a red pixel, a green pixel, a blue pixel, or a white pixel.

12 , the first pixel PB1 and the second pixel PB2 are respectively disposed in unit pixels adjacent to each other along the X direction (the gate line extension direction), are connected to the same gate line, and have different data lines can be connected to In general, since pixels implementing the same color within two unit pixels disposed adjacent to each other exhibit similar luminance except in exceptional cases, one pixel current is reduced by turning on the control switch CT in the first driving mode. Even if it is distributed and supplied to the light emitting elements of two pixels, there is no problem in image display.

12 , a pixel PA1, a pixel PB1, a pixel PC1, and a pixel PD1 implementing different colors (red/white/green/blue) may constitute a unit pixel UPXL1. In addition, the pixel PA2, the pixel PB2, the pixel PC2, and the pixel PD2 implementing different colors (red/white/green/blue) may constitute a unit pixel UPXL2.

The current driving capability of the driving TFT is relatively high in the case of the white pixel compared to the red, green, and blue pixels. Accordingly, the problem that the current resolution of the driving TFT is low in the low gray scale region and the low gray scale expression power is lowered is more serious in the white pixel. Considering this, the first pixel PB1 and the second pixel PB2 may be white pixels. However, the technical spirit of the present invention is not limited thereto. The first pixel PB1 and the second pixel PB2 may be any one of red, green, and blue pixels.

Meanwhile, although the control switch is connected only between pixels of a specific color in FIG. 4 , the control switch may be further connected between pixels of other colors.

13 shows a detailed configuration of the first pixel PB1, the second pixel PB2, and the control switch CT according to the second embodiment of the present invention.

Referring to FIG. 13 , the first pixel PB1 includes a first light emitting device OL1 having an anode electrode connected to the first node N1 and a cathode electrode connected to an input terminal of the low potential pixel driving voltage EVSS; It has a first driving element DT1 connected between the high potential power wiring 18 and the first node N1. The first pixel PB1 may further include a first switch element ST1 and a first storage capacitor Cst1. The gate electrode of the first driving element DT1 is connected to the node Nx, and the source electrode is connected to the first node N1. The first storage capacitor Cst1 is connected to the node Nx and the first node N1 to store the gate-source voltage of the first driving device DT1 for one frame. The first switch element ST1 is connected between the first data line 14a and the node Nx, and is switched according to the j-th gate signal SCAN applied from the j-th (j is a natural number) gate line 15 .

13 , the second pixel PB2 includes a second light emitting device OL2 having an anode electrode connected to the second node N2 and a cathode electrode connected to an input terminal of the low potential pixel driving voltage EVSS; It has a second driving element DT2 connected between the high potential power wiring 18 and the second node N2. The second pixel PB2 may further include a second switch element ST2 and a second storage capacitor Cst2. The gate electrode of the second driving element DT2 is connected to the node Ny, and the source electrode is connected to the second node N2. The second storage capacitor Cst2 is connected to the node Ny and the second node N2 to store the gate-source voltage of the second driving device DT2 for one frame. The second switch element ST2 is connected between the second data line 14b and the node Ny, and is switched according to the j-th gate signal SCAN applied from the j-th gate line 15 .

Referring to FIG. 13 , the control switch CT is connected between the first node N1 and the second node N2 , and is switched according to the control signal CON applied from the control line 17 . The control switch CT is turned on in the first driving mode for displaying a low grayscale image, and is turned off in the second driving mode for displaying a high grayscale image. Here, the low grayscale image indicates an image in which an average grayscale value of image data written in the first pixel PB1 and the second pixel PB2 is equal to or lower than a preset threshold grayscale value (TH in FIG. 19 ). The high grayscale image indicates an image in which the average grayscale value of the image data written in the first pixel PB1 and the second pixel PB2 is higher than the threshold grayscale value (TH of FIG. 19 ).

14 is a waveform diagram of driving signals applied to the circuit diagram of FIG. 13 in a second driving mode. And, FIG. 15 shows the operation of the circuit diagram of FIG. 13 according to the driving signals of FIG. 14 .

14 and 15 , in the second driving mode, the data driving circuit 12 supplies the data voltage DH1 to the first data line 14a and simultaneously applies the data voltage DH2 to the second data line 14b during the scan-on period. ) is supplied to The average grayscale value of the data voltages DH1 and DH2 is higher than a preset threshold grayscale value (TH in FIG. 19). In the second driving mode, the gate driving circuit 13 supplies the j-th gate signal SCAN of the on level to the j-th gate line 15 during the scan-on period. And, in the second driving mode, the gate driving circuit 13 supplies the control signal CON of the off level to the control line 17 during the scan-on period.

14 and 15 , the first pixel PB1 programs the gate-source voltage of the first driving device DT1 during the scan-on period, and maintains the programmed voltage until the start time of the next frame. . During the scan-on period, the first switch element ST1 is turned on according to the on-level j-th gate signal SCAN to apply the data voltage DH1 charged in the first data line 14a to the gate of the first driving element DT1 . applied to the electrode. In this case, a reference voltage may be applied to the source electrode of the first driving element DT1 through a reference power line (not shown). Here, the reference voltage is a DC voltage lower than the lowest data voltage (the data voltage for driving black). Accordingly, the gate-source voltage of the first driving device DT1 is programmed as the “data voltage DH1-reference voltage” and is stored in the first storage capacitor Cst1. Since the programmed voltage is higher than the threshold voltage of the first driving element DT1, the first driving element DT1 is turned on, and the first pixel current ( Ids1) flows. The first light emitting device OL1 emits light by the first pixel current Ids1 applied from the first driving device DT1 , and maintains this light emitting state for approximately one frame.

14 and 15 , the second pixel PB2 programs the gate-source voltage of the second driving device DT2 during the scan-on period, and maintains the programmed voltage until the start time of the next frame. . During the scan-on period, the second switch element ST2 is turned on according to the on-level j-th gate signal SCAN to apply the data voltage DH2 charged in the second data line 14b to the gate of the second driving element DT2. applied to the electrode. In this case, the reference voltage may be applied to the source electrode of the second driving element DT2 through a reference power line. Accordingly, the gate-source voltage of the second driving device DT2 is programmed as the “data voltage DH2-reference voltage” and is stored in the second storage capacitor Cst2. Since the programmed voltage is higher than the threshold voltage of the second driving element DT2, the second driving element DT2 is turned on, and the second pixel current ( Ids2) flows. The second light emitting device OL2 emits light by the second pixel current Ids2 applied from the second driving device DT2 and maintains this light emitting state for approximately one frame.

14 and 15 , in the second driving mode, the control switch CT is turned off according to the off-level control signal CON to electrically cut off the first node N1 and the second node N2. do. Accordingly, the first light emitting device OL1 is driven by the first pixel current Ids1 , and the second light emitting device OL2 is driven by the second pixel current Ids2 . The first pixel current Ids1 and the second pixel current Ids2 belong to the high grayscale section GR2 in the grayscale vs. pixel current graph of FIG. 19 . Since the current resolution of the driving element in the high grayscale section GR2 is higher than that of the low grayscale section GR1 , the control switch CT is turned off and the first pixel PB1 and the second pixel PB2 transmit the respective pixel currents. can be individually driven.

16 is a waveform diagram of driving signals applied to the circuit diagram of FIG. 13 in a first driving mode. FIG. 17 shows an operation of the circuit diagram of FIG. 13 according to the driving signals of FIG. 16 . And, FIG. 18 shows another operation of the circuit diagram of FIG. 13 according to the driving signals of FIG. 16 .

16 to 18 , in the first driving mode, the data driving circuit 12 supplies the low gray level driving data voltage DL1 to the first data line 14a and the black gray level data voltage DL2 during the scan-on period. is supplied to the second data line 14b. The low grayscale driving data voltage DL1 is higher than the black grayscale data voltage DL2. The low gray level driving data voltage DL1 is set higher than the average data voltage corresponding to the average gray level value of the low gray level image to improve the current resolution of the driving device. In this case, the average voltage of the low gray level driving data voltage DL1 and the black driving data voltage DL2 may be set to be the same as the average data voltage so that the gray level reversal phenomenon does not occur in the low gray level section.

In the first driving mode, the gate driving circuit 13 supplies an on-level j-th gate signal SCAN to the j-th gate line 15 during the scan-on period. And, in the first driving mode, the gate driving circuit 13 supplies the control signal CON of the on level to the control line 17 for about one frame from the scan-on period. That is, in the first driving mode, the gate driving circuit 13 supplies the on-level control signal CON to the corresponding control line 17 for approximately one frame from the time when the low grayscale driving data voltage DL1 is applied.

16 and 17 , the first pixel PB1 programs the gate-source voltage of the first driving device DT1 during the scan-on period, and maintains the programmed voltage until the start time of the next frame. . During the scan-on period, the first switch element ST1 is turned on according to the on-level j-th gate signal SCAN to apply the low grayscale driving data voltage DL1 charged in the first data line 14a to the first driving element ( It is applied to the gate electrode of DT1). In this case, a reference voltage may be applied to the source electrode of the first driving element DT1 through a reference power line (not shown). Here, the reference voltage is a DC voltage lower than the lowest data voltage (the data voltage for driving black). Accordingly, the gate-source voltage of the first driving device DT1 is programmed as the “low grayscale driving data voltage DL1-reference voltage” and is stored in the first storage capacitor Cst1 . Since the programmed voltage is higher than the threshold voltage of the first driving element DT1, the first driving element DT1 is turned on, and the first pixel current ( Ids1) flows.

16 and 17 , the second pixel PB2 programs the gate-source voltage of the second driving device DT2 during the scan-on period, and maintains the programmed voltage until the start time of the next frame. . During the scan-on period, the second switch element ST2 is turned on according to the on-level j+1th gate signal SCAN to apply the black driving data voltage DL2 charged in the second data line 14b to the second driving element. It is applied to the gate electrode of (DT2). In this case, the reference voltage may be applied to the source electrode of the second driving element DT2 through a reference power line. Accordingly, the gate-source voltage of the second driving device DT2 is programmed as the “black driving data voltage DL2-reference voltage” and is stored in the second storage capacitor Cst2 . Since the programmed voltage is lower than the threshold voltage of the second driving device DT2 , the second driving device DT2 is turned off, and a pixel current does not flow through the second driving device DT2 .

16 and 17 , the control switch CT is turned on according to the on-level control signal CON in the scan-on period to electrically connect the first node N1 and the second node N2. . In this case, the first pixel current Ids1 is divided into the current IA and the current IB at the first node N1 . The first light emitting device OL1 is driven by the current IA, and the second light emitting device OL2 is driven by the current IB. In other words, the first light emitting device OL1 and the second light emitting device OL2 are driven by the divided currents IA and IB of the first pixel current Ids1 . 19 , since the first pixel current Ids1 is sufficiently large by the low gray level driving data voltage DL1, the current resolution and low gray level expression power of the first driving element DT1 are improved. A graph indicated by a dashed-dotted line in the low grayscale section GR1 of FIG. 19 represents the first pixel current Ids1 , and a graph indicated by a solid line in the low grayscale section GR1 represents distribution currents IA and IB. In addition, a graph indicated by a dotted line in the low grayscale section GR1 of FIG. 19 indicates that the pixel current does not flow in the second driving element DT2 . As can be clearly seen from FIG. 19 , the present invention can greatly improve the current resolution and low grayscale expression power of the driving element while minimizing grayscale distortion when displaying a low grayscale image.

Meanwhile, referring to FIGS. 16 and 18 , the first pixel PB1 programs the gate-source voltage of the first driving device DT1 during the scan-on period, and applies the programmed voltage to the start time of the next frame. keep it During the scan-on period, the first switch element ST1 is turned on according to the on-level j-th gate signal SCAN to apply the black driving data voltage DL2 charged in the first data line 14a to the first driving element DT1 . ) to the gate electrode. In this case, a reference voltage may be applied to the source electrode of the first driving element DT1 through a reference power line (not shown). Accordingly, the gate-source voltage of the first driving element DT1 is programmed as the “black driving data voltage DL2-reference voltage” and is stored in the first storage capacitor Cst1 . Since the programmed voltage is lower than the threshold voltage of the first driving device DT1 , the first driving device DT1 is turned off, and a pixel current does not flow through the first driving device DT1 .

16 and 18 , the second pixel PB2 programs the gate-source voltage of the second driving device DT2 during the scan-on period, and maintains the programmed voltage until the start time of the next frame. . During the scan-on period, the second switch element ST2 is turned on according to the on-level j+1th gate signal SCAN to second drive the low grayscale driving data voltage DL1 charged in the second data line 14b. It is applied to the gate electrode of the device DT2. In this case, the reference voltage may be applied to the source electrode of the second driving element DT2 through a reference power line. Accordingly, the gate-source voltage of the second driving device DT2 is programmed as the “low grayscale driving data voltage DL1-reference voltage” and is stored in the second storage capacitor Cst2 . Since the programmed voltage is higher than the threshold voltage of the second driving device DT2 , the second driving device DT2 is turned on, and the second pixel current Ids2 flows through the second driving device DT2 .

16 and 18 , the control switch CT is turned on according to the on-level control signal CON in the scan-on period to electrically connect the first node N1 and the second node N2. . In this case, the second pixel current Ids2 is divided into the current IA and the current IB at the second node N2 . The first light emitting device OL1 is driven by the current IA, and the second light emitting device OL2 is driven by the current IB. In other words, the first light emitting device OL1 and the second light emitting device OL2 are driven by the divided currents IA and IB of the second pixel current Ids2. 19 , since the second pixel current Ids2 is sufficiently large by the low gray level driving data voltage DL1, the current resolution and low gray level expression power of the second driving element DT2 are improved. A graph indicated by a dashed line in the low gray scale section GR1 of FIG. 19 represents the second pixel current Ids2, and a graph indicated by a solid line in the low gray scale section GR1 represents distribution currents IA and IB. Also, a graph indicated by a dotted line in the low grayscale section GR1 of FIG. 19 indicates that the pixel current does not flow in the first driving element DT1 . As can be clearly seen from FIG. 19 , the present invention can greatly improve the current resolution and low grayscale expression power of the driving element while minimizing grayscale distortion when displaying a low grayscale image.

As described above, the present invention turns on a control switch connected between two pixels when displaying a low grayscale image, and drives all of the light emitting devices of the two pixels with the pixel current generated in any one of the two pixels. . Since the pixel current generated in the one pixel is large enough to drive all the light emitting devices of the two pixels, the current resolution and low grayscale expression power of the driving device included in the one pixel can be greatly improved.

The present invention can greatly improve the current resolution and low grayscale expression power of the driving device while minimizing grayscale distortion when displaying a low grayscale image.

In the present invention, since a data processing algorithm such as a dithering technique or a frame rate control technique is not used to increase the expressive power of the low gray scale, the circuit logic can be simplified as much as possible, and the low gray level due to the data processing algorithm It is possible to prevent a side effect such as a gradation step occurring in the gradation region in advance.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit

Claims (17)

A first pixel having a first light emitting device having an anode electrode connected to a first node and a cathode electrode connected to an input terminal of a low potential pixel driving voltage, and a first driving device connected between a high potential power supply line and the first node ;
A second light emitting device having an anode electrode connected to a second node and a cathode electrode connected to an input terminal of the low potential pixel driving voltage, and a second driving device connected between the high potential power supply line and the second node 2 pixels; and
A control switch connected between the first node and the second node,
The control switch is turned on in a first driving mode for displaying a low grayscale image and turned off in a second driving mode for displaying a high grayscale image. The method of claim 1,
The low grayscale image indicates an image in which an average grayscale value of image data written in the first pixel and the second pixel is equal to or lower than a preset threshold grayscale value;
The high grayscale image indicates an image in which an average grayscale value of image data written in the first pixel and the second pixel is higher than the threshold grayscale value. 3. The method of claim 2,
In the first driving mode,
any one of the first driving element and the second driving element is turned off according to a data voltage for black driving applied to its gate electrode;
The other one of the first driving element and the second driving element is turned on according to a data voltage for low grayscale driving applied to its gate electrode,
The low grayscale driving data voltage is higher than the black driving data voltage. 4. The method of claim 3,
The low grayscale driving data voltage is higher than an average data voltage corresponding to the average grayscale value of the low grayscale image. 5. The method of claim 4,
An average voltage of the low grayscale driving data voltage and the black driving data voltage is the same as the average data voltage. 4. The method of claim 3,
In the first driving mode,
A pixel current corresponding to the low grayscale driving data voltage flows through the other one of the first driving element and the second driving element;
The pixel current is distributed to the first light emitting device and the second light emitting device. 7. The method of claim 6,
In the first driving mode,
The control switch is turned on for one frame from the time of application of the low grayscale driving data voltage. The method of claim 1,
and the first pixel and the second pixel realize the same color. 9. The method of claim 8,
The first pixel and the second pixel are connected to the same data line and to different gate lines. 9. The method of claim 8,
The first pixel and the second pixel are connected to the same gate line and connected to different data lines. A first pixel having a first light emitting device having an anode electrode connected to a first node and a cathode electrode connected to an input terminal of a low potential pixel driving voltage, and a first driving device connected between a high potential power supply line and the first node ; and a second light emitting device having an anode electrode connected to a second node and a cathode electrode connected to an input terminal of the low potential pixel driving voltage, and a second driving device connected between the high potential power supply line and the second node. A method of driving an electroluminescent display having a second pixel, the method comprising:
separating the first driving mode for displaying the low grayscale image and the second driving mode for displaying the high grayscale image by analyzing input image data to be written in the first pixel and the second pixel;
turning on a control switch connected between the first node and the second node in the first driving mode; and
and turning off the control switch in the second driving mode. 12. The method of claim 11,
The low grayscale image indicates an image in which an average grayscale value of image data written in the first pixel and the second pixel is equal to or lower than a preset threshold grayscale value;
The high grayscale image indicates an image in which an average grayscale value of image data written in the first pixel and the second pixel is higher than the threshold grayscale value. 13. The method of claim 12,
In the first driving mode,
any one of the first driving element and the second driving element is turned off according to a data voltage for black driving applied to its gate electrode;
The other one of the first driving element and the second driving element is turned on according to a data voltage for low grayscale driving applied to its own gate electrode,
The low grayscale driving data voltage is higher than the black driving data voltage. 14. The method of claim 13,
The low grayscale driving data voltage is higher than an average data voltage corresponding to the average grayscale value of the low grayscale image. 15. The method of claim 14,
An average voltage of the low grayscale driving data voltage and the black driving data voltage is the same as the average data voltage. 14. The method of claim 13,
In the first driving mode,
A pixel current corresponding to the low grayscale driving data voltage flows through the other one of the first driving element and the second driving element;
The pixel current is distributed to the first light emitting element and the second light emitting element. 17. The method of claim 16,
In the first driving mode,
The control switch is turned on for one frame from the time of application of the low grayscale driving data voltage.

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