KR20130030879A - Organic light emitting diode display device - Google Patents

Abstract

PURPOSE: An organic light emitting diode display is provided to increase a response speed of a pixel by reducing an initialization path of a driving TFT. CONSTITUTION: An organic light emitting diode emits light by a driving current. The driving current flows between an input terminal of a high potential driving voltage and an input terminal of a low potential driving voltage. A driving TFT(DT) is connected between the input terminal of the high potential driving voltage and the organic light emitting diode. The driving TFT controls the amount of driving currents applied to the organic light emitting diode according to a gate voltage applied to a first node. An initialization TFT applies an initialization voltage to the first node and initializes a gate voltage of the driving TFT. The initialization TFT is directly connected to the first node.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display device, and more particularly, to an organic light emitting diode display device for improving image quality.

Recently, development of various flat panel displays (FPDs) has been accelerated. Among them, the organic light emitting diode display device has advantages in that the response speed is high and the luminous efficiency, luminance, and viewing angle are large by using the self-luminous element emitting light by itself.

The organic light emitting diode display device has an organic light emitting diode as shown in FIG. The organic light emitting diode has organic compound layers (HIL, HTL, EML, ETL, EIL) formed between the anode electrode and the cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The organic light emitting diode display arranges the pixels including the organic light emitting diodes in a matrix form and controls the brightness of the pixels according to the gray level of the video data. In particular, an active matrix organic light emitting diode display using a thin film transistor (TFT) as a switching element selects a pixel by selectively turning on the active TFT, and selects a pixel and maintains it in a storage capacitor. The light emission of the pixel is maintained at the voltage.

2 is a circuit diagram showing one pixel equivalently in an active matrix type organic light emitting diode display.

Referring to FIG. 2, the pixel includes an organic light emitting diode OLED, a switch TFT ST, a driving TFT DT, a storage capacitor Cst, and the like.

The switch TFT ST is turned on in response to a scan pulse from the gate line GL to conduct a current path between its source electrode and the drain electrode. The switch TFT ST applies the data voltage from the data line DL to the gate electrode and the storage capacitor Cst of the driving TFT DT during the turn-on period. The driving TFT DT controls the current flowing through the organic light emitting diode OLED according to its gate-source voltage Vgs. The storage capacitor Cst keeps the gate potential of the driving TFT DT constant for a predetermined period. The organic light emitting diode OLED is implemented in the structure as shown in FIG. 1 and is connected between the drain electrode of the driving TFT DT and the ground voltage source GND.

The brightness of the pixel as shown in FIG. 2 is proportional to the driving current flowing through the organic light emitting diode OLED, and the driving current depends on the gate-source voltage of the driving TFT DT, the threshold voltage of the driving TFT DT, and the like.

The threshold voltage of the driving TFTs varies from pixel to pixel due to various reasons such as process variation and deterioration variation over time. Therefore, recently, a technique of changing a pixel structure differently to compensate for a threshold voltage variation of a driving TFT between pixels, and performing an initialization operation and a sampling operation prior to light emission of pixels every frame has been used. In the initialization operation, the gate voltage of the driving TFT is initialized to a predetermined value. In the sampling operation following this initialization operation, the threshold voltage of the driving TFT is reflected in the gate voltage of the driving TFT.

In order to effectively compensate for the threshold voltage deviation of the driving TFT between the pixels, the gate voltage of the driving TFT should be sufficiently initialized to a desired predetermined value within the initialization period. However, in the conventional pixel structure, the initialization path to the gate electrode of the driving TFT is long, and thus is affected by the parasitic capacitor. The greater the influence of the parasitic capacitor on the initialization path, the lower the response characteristic of the pixel. That is, if the parasitic capacitance on the initialization path is large when the display image is changed from black gray to white gray (or white gray to black), the previous frame data held at the gate electrode of the driving TFT is not sufficiently initialized and is currently This will affect the frame data. As a result, if the gate voltage of the driving TFT is not sufficiently initialized due to the influence of parasitic capacitance, there is a problem that the response speed is lowered and the image quality of the display image is lowered.

Accordingly, an object of the present invention is to provide an organic light emitting diode display device capable of improving the image quality of a display image by reducing the initialization path of the driving TFT to increase the response speed of the pixel.

In order to achieve the above object, an organic light emitting diode display according to an embodiment of the present invention is an organic light emitting diode that emits light by a driving current flowing between the input terminal of the high potential driving voltage and the input terminal of the low potential driving voltage; A driving TFT connected between the input terminal of the high potential driving voltage and the organic light emitting diode and controlling an amount of driving current applied to the organic light emitting diode according to a gate voltage applied to the first node; And an initialization TFT for initializing a gate voltage of the driving TFT by applying an initialization voltage to the first node according to a previous stage scan signal. The initialization TFT is directly connected to the first node.

The initialization voltage is selected from one of a reference voltage and the low potential driving voltage.

The initialization TFT may include a gate electrode connected to a previous scan line to which the previous scan signal is applied; A source electrode connected to the input terminal of the reference voltage; And a drain electrode directly connected to the first node.

The initialization TFT may include a gate electrode connected to a previous scan line to which the previous scan signal is applied; A source electrode connected to the input terminal of the low potential driving voltage; And a drain electrode directly connected to the first node.

A first switch TFT for switching a current path between the data line and the second node according to the current stage scan signal; A second switch TFT switching a current path between a third node connected to the drain electrode of the driving TFT and the first node according to the current stage scan signal; A third switch TFT for applying the reference voltage to the second node according to a current emission signal; A fourth switch TFT for switching a current path between the third node and the anode electrode of the organic light emitting diode according to the current stage emission signal; A fifth switch TFT for switching a current path between an input terminal of the reference voltage and an anode electrode of the organic light emitting diode according to the current stage scan signal; And a storage capacitor connected between the first node and the second node.

According to the previous stage scan signal, the current stage scan signal, and the current stage emission signal, each frame includes a first initialization period, a second initialization period following the first initialization period, and the second initialization period. This is divided into a sampling period and a light emission period following the sampling period.

The previous stage scan signal is generated at an activation level in the first and second initialization periods and is generated at an inactivation level in the sampling period and the emission period; The current stage scan signal is generated at an activation level in the sampling period and is generated at an inactivation level in the first and second initialization periods and the emission period; The current stage emission signal is generated at an activation level in the first initialization period and the light emission period, and is generated at an inactivation level in the second initialization period and the sampling period.

The organic light emitting diode display according to the present invention includes an initialization TFT directly connected to the gate electrode of the driving TFT for each pixel to reduce the initialization path of the driving TFT, thereby increasing the response speed of the pixel and improving the image quality of the display image. .

1 is a diagram illustrating a light emission principle of a general organic light emitting diode display.
2 is an equivalent circuit diagram of a pixel in a conventional organic light emitting diode display.
3 is a block diagram illustrating an organic light emitting diode display device according to an exemplary embodiment of the present invention.
4 is an equivalent circuit diagram illustrating an example of a pixel disposed in an nth horizontal pixel line;
5 is a diagram illustrating waveforms of scan signals and emission signals applied to the pixel of FIG. 4;
6A through 6D are diagrams illustrating equivalent circuits of pixels for each operation period divided through FIG. 5;
7 is a waveform diagram showing a change in potential of a first node for each operation period;
FIG. 8 is a diagram illustrating a simulation result of a change in current applied to an organic light emitting diode when the display image is changed from black to white gradations, compared with a conventional example. FIG.
FIG. 9 is a diagram illustrating a response speed between black and white gray levels in comparison with the related art based on FIG. 8; FIG.
Fig. 10 is an equivalent circuit diagram showing another example of pixels arranged on an nth horizontal pixel line.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 10.

3 is a block diagram illustrating an organic light emitting diode display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 10 in which pixels P are arranged in a matrix, and a data driver for driving data lines 14. 12, the scan driver 13A for driving the scan lines 15, the emission driver 13B for driving the emission lines 16, and the drivers 12, 13A, 13B. A timing controller 11 for controlling the operation is provided.

The display panel 10 includes a plurality of data lines 14, scan lines 15 and emission lines 16 intersecting the data lines 14, and signal lines 14, 15, and 16. Pixels P are formed at every intersection of the regions. Each of the pixels P is supplied with a high potential driving voltage Vdd, a low potential driving voltage Vss, and a reference voltage Vref. Each of the pixels P may be connected to one data line 14, two adjacent scan lines 15, and one emission line 16 as shown in FIGS. 4 and 10. The high potential drive voltage Vdd is generated at a constant DC level by the high potential drive voltage source. The low potential driving voltage Vss is generated at a constant DC level by the low potential driving voltage source. The reference voltage Vref is generated at a constant DC level by the reference voltage source. The reference voltage Vref may be generated at a voltage level higher than the black gray voltage and lower than the white gray voltage. Each of the pixels P includes an initialization TFT directly connected to the gate electrode of the driving TFT, which reduces the initialization path as compared with the conventional method, and sets the gate voltage of the driving TFT within the desired time period to the reference voltage Vref or the low potential driving voltage. Quickly reset to (Vss).

The timing controller 11 aligns digital video data RGB input from the outside to the data driver 12 in alignment with the resolution of the display panel 10. In addition, the timing controller 11 may determine the timing of the data driver 12 based on timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE. Data control signal DDC for controlling the operation timing, scan control signal SDC for controlling the operation timing of the scan driver 13A, and emission control for controlling the operation timing of the emission driver 13B. Generate signal EDC.

The data driver 12 converts the digital video data RGB into an analog data voltage (hereinafter, referred to as a data voltage) according to the data control signal DDC and supplies the same to the data lines 14.

The scan driver 13A generates a scan signal according to the scan control signal SDC and supplies the scan signal to the scan lines 15. The scan driver 13A includes a shift register for shifting the scan signal. The shift register may be directly formed on the display panel 10 according to a GIP (Gate Driver IC In Pane) method.

The emission driver 13B generates an emission signal according to the emission control signal EDC and supplies the emission signal to the emission lines 16. The emission driver 13B includes a shift register for shifting the emission signal. The shift register may be directly formed on the display panel 10 according to a gate in panel (GIP) method.

4 illustrates an example of a pixel P disposed in an nth horizontal pixel line (n is a positive integer).

Referring to FIG. 4, a pixel P according to an exemplary embodiment of the present invention may include an organic light emitting diode OLED, a driving TFT DT, an initialization TFT directly connected to a gate electrode of the driving TFT DT, A plurality of switch TFTs ST1 to ST5 and a storage capacitor Cst are provided. Here, the TFTs DT, Tint, and ST1 to ST5 may be all implemented as P-type MOSFETs (metal-oxide semiconductor field effect transistors).

The organic light emitting diode OLED emits light by a driving current flowing between the input terminal of the high potential driving voltage Vdd and the input terminal of the low potential driving voltage Vss. The cathode of the organic light emitting diode OLED is connected to the input terminal of the low potential driving voltage Vss. The organic light emitting diode OLED has a structure as shown in FIG. 1.

The driving TFT DT is connected between the input terminal of the high potential driving voltage Vdd and the organic light emitting diode OLED, and is applied to the anode electrode of the organic light emitting diode OLED according to the potential of the first node N1. Control the amount of current. The gate electrode of the driving TFT DT is connected to the first node N1, the source electrode is connected to the input terminal of the high potential driving voltage Vdd, and the drain electrode is connected to the third node N3.

The initialization TFT Tint applies the reference voltage Vref to the first node N1 according to the previous stage scan signal SCAN [n-1] to convert the gate voltage of the driving TFT DT into the reference voltage Vref. Initialize The gate electrode of the initialization TFT (Tint) is connected to the previous scan line 15n-1, the source electrode is connected to the input terminal of the reference voltage Vref, and the drain electrode is connected to the first node N1. The initialization TFT Tint is directly connected to the first node N1 to which the gate electrode of the driving TFT DT is connected, thereby reducing the initialization path. When the initialization path is shortened, the influence of parasitic capacitance on the initialization path is reduced, so that the gate voltage of the driving TFT DT can be quickly initialized to the reference voltage Vref within a desired time. This leads to an improvement in pixel response speed and image quality.

The first switch TFT ST1 switches the current path between the data line 14 and the second node N2 according to the current stage scan signal SCAN [n]. The gate electrode of the first switch TFT ST1 is connected to the current scan line 15n, the source electrode is connected to the data line 14, and the drain electrode is connected to the second node N2.

The second switch TFT ST2 switches the current path between the first node N1 and the third node N3 according to the present stage scan signal SCAN [n]. The gate electrode of the second switch TFT ST2 is connected to the current scan line 15n, the source electrode is connected to the third node N3, and the drain electrode is connected to the first node N1.

The third switch TFT ST3 applies the reference voltage Vref to the second node N2 according to the current emission signal EM [n]. The gate electrode of the third switch TFT ST3 is connected to the current emission line 16n, the source electrode is connected to the input terminal of the reference voltage Vref, and the drain electrode is connected to the second node N2.

The fourth switch TFT ST4 switches the current path between the third node N3 and the anode electrode of the organic light emitting diode OLED according to the current emission signal EM [n]. The gate electrode of the fourth switch TFT ST4 is connected to the emission line 16n at the present stage, the source electrode is connected to the third node N3, and the drain electrode is connected to the anode electrode of the organic light emitting diode OLED. do.

The fifth switch TFT ST5 switches the current path between the input terminal of the reference voltage Vref and the anode electrode of the organic light emitting diode OLED according to the current stage scan signal SCAN [n]. The gate electrode of the fifth switch TFT ST5 is connected to the current scan line 15n, the source electrode is connected to the input terminal of the reference voltage Vref, and the drain electrode is connected to the anode electrode of the organic light emitting diode OLED. do.

The storage capacitor Cst is connected between the first node N1 and the second node N2. The storage capacitor Cst stabilizes the gate voltage of the driving TFT DT.

FIG. 5 shows waveforms of scan signals SCAN [n-1] and SCAN [n] and emission signal EM [n] applied to the pixel of FIG. 4.

Referring to FIG. 5, the operation of the pixel P according to an exemplary embodiment of the present invention may be performed on the waveforms of the scan signals SCAN [n-1] and SCAN [n] and the emission signal EM [n]. Accordingly, the description may be divided into the initialization period T1, the sampling period T2, and the light emission period T3. The initialization period T1 may be divided into a first initialization period T1A and a second initialization period T1B. In FIG. 5, 'Td1' and 'Td2' indicate a transient period. In FIG. 5, 'H' indicates an inactivation level capable of turning off the TFT of the pixel, and 'L' indicates an activation level in which the TFT of the pixel is turned on.

The previous stage scan signal SCAN [n-1] is generated at the activation level L in the first and second initialization periods T1A and T1B, and is deactivated in the sampling period T2 and the emission period T3. Can be generated at level H. The current stage scan signal SCAN [n] is generated at the activation level L in the sampling period T2, and is deactivated in the first and second initialization periods T1A and T1B and the emission period T3. H). The current emission signal EM [n] is generated at the activation level L in the first initialization period T1A and the light emission period T3, and the second initialization period T1B and the sampling period T2 are generated. ) May be generated at an inactivation level (H).

6A to 6D show an equivalent circuit of pixels for each operation period divided through FIG. 5. 7 is a waveform diagram illustrating a change in potential of the first node for each operation period. 5 to 7, the detailed operation of the pixel in each operation period is as follows.

Referring to FIG. 6A, during the first initialization period T1A, the initialization TFT Tint is turned on in response to the scan signal SCAN [n-1] preceding the activation level L, and the inactivation level ( In response to the current stage scan signal SCAN [n] of H), the first, second and fifth switch TFTs ST1, ST2, and ST5 are turned off, and the current stage emission signal of the activation level L In response to EM [n]), the third and fourth switch TFTs ST3 and ST4 are turned on.

As a result, during the first initialization period T1A, the potential VN1 of the first node N1 is changed to the reference voltage Vref. At this time, since the reference voltage Vref is also applied to the second node N2 connected to the first node N1 through the capacitor Cst, the potential VN1 of the first node N1 becomes faster than the reference voltage. Is changed to (Vref).

Referring to FIG. 6B, during the second initialization period T1B, the initialization TFT Tint is turned on in response to the previous scan signal SCAN [n-1] of the activation level L, and the inactivation level ( The first to fifth switch TFTs ST1 to ST5 are all turned off in response to the current stage scan signal SCAN [n] and the current stage emission signal EM [n].

As a result, during the second initialization period T1B, the second node N2 is floated and the potential VN1 of the first node N1 maintains the reference voltage Vref at the initialization level.

Referring to FIG. 6C, during the sampling period T2, the initialization TFT Tint is turned off in response to the previous scan signal SCAN [n−1] of the inactivation level H, and the activation level L is turned on. The first, second and fifth switch TFTs ST1, ST2, and ST5 are turned on in response to the current stage scan signal SCAN [n] of the current stage, and the current emission signal EM of the deactivation level H is turned on. In response to [n]), the third and fourth switch TFTs ST3 and ST4 are turned off.

As a result, during the sample, the potential VN1 of the first node N1 is shorted by the diode connection of the driving TFT DT (the gate electrode and the drain electrode of the driving TFT DT are shorted, or the first node N1 and the first node N1). The sample is sampled by the first operation value Vdd-Vth minus the threshold voltage Vth of the driving TFT DT by the high potential driving voltage Vdd by the short of the three nodes N3). At the same time, the potential of the second node N2 is programmed to the data voltage Vdata.

In the sampling period T2, the sampled first operation value Vdd-Vth is maintained at the first node N1 by the storage capacitor Cst, and the programmed data voltage Vdata is stored in the storage capacitor Cst. By the second node N2.

Referring to FIG. 6D, during the light emission period T3, the initialization TFT Tint is turned off in response to the previous scan signal SCAN [n−1] of the inactivation level H, and the inactivation level H The first, second, and fifth switch TFTs ST1, ST2, and ST5 are turned off in response to the current stage scan signal SCAN [n] and the current stage emission signal EM of the activation level L is turned off. In response to [n]), the third and fourth switch TFTs ST3 and ST4 are turned on.

As a result, the potential of the second node N2 is changed from the data voltage Vdata held just before to the reference voltage Vref. The second operation value Vdata-Vref corresponding to this variation, that is, the value obtained by subtracting the reference voltage Vref from the data voltage Vdata, is reflected in the potential VN1 of the first node N1. Accordingly, the potential VN1 of the first node N1 is a compensation value {(Vdd-Vth)-(Vdata-Vref) obtained by subtracting the second calculation value Vdata-Vref from the first calculation value Vdd-Vth. Is set to}.

Since the potential VN1 of the first node N1 is set to the compensation value {(Vdd-Vth)-(Vdata-Vref)} and the fourth switch TFT ST4 is turned on, the organic light emitting diode OLED As shown in Equation (1) below, a driving current Ioled flows that is not affected by the threshold voltage Vth of the driving TFT DT.

Where 'μ' is the mobility of the driving TFT DT, 'Cox' is the parasitic capacitance of the driving TFT DT, 'W' is the channel width of the driving TFT DT, and 'L' is the driving TFT. The channel length of (DT), 'Vgs' is the gate-source voltage difference of the driving TFT (DT), 'Vth' is the threshold voltage of the driving TFT (DT), 'Vdd' is the high potential driving voltage, 'Vdata' represents a data voltage and 'Vref' represents a reference voltage.

FIG. 8 shows a simulation result of a change in current applied to an organic light emitting diode when the display image is changed from black gray to white gray as compared with the related art. In Fig. 8, the horizontal axis represents time and the vertical axis represents driving current, respectively. FIG. 9 shows the response speed between black and white gray levels in comparison with the related art based on FIG. 8.

According to the prior art, since the initialization path is long, the gate voltage of the driving TFT is not sufficiently initialized due to the influence of parasitic capacitance, so that the response speed of gray to gray is reduced. According to the related art, when the display image is changed from black gray to white gray as shown in FIG. 8, the time (response time) to reach 90% of the white gray is very long as about 1.45 frames as shown in FIG. 9.

On the other hand, the present invention reduces the initialization path compared to the conventional method by directly connecting the initialization TFT to the gate electrode of the driving TFT, and quickly removes the influence of parasitic capacitance on the initialization path, so that the gate voltage of the driving TFT is rapidly increased to the reference voltage within a desired time. Initialize According to the present invention, the response speed of gray to gray is improved to increase the display quality. According to the present invention, when the display image is changed from black gradation to white gradation as shown in FIG. 8, the time (response time) to reach 90% of white gradation is very short as about 0.75 frames as shown in FIG.

10 shows another example of the pixel P disposed in the nth horizontal pixel line (n is a positive integer). As compared with the pixel P of FIG. 4, the pixel P of FIG. 10 differs only in the connection configuration of the initialization TFT Tint, and the rest (connection configuration, operation, etc.) is substantially the same.

Referring to FIG. 10, a pixel P according to another embodiment of the present invention may include an organic light emitting diode OLED, a driving TFT DT, an initialization TFT directly connected to a gate electrode of the driving TFT DT, A plurality of switch TFTs ST1 to ST5 and a storage capacitor Cst are provided.

The initialization TFT Tint applies the low potential driving voltage Vss to the first node N1 according to the previous stage scan signal SCAN [n-1] to convert the gate voltage of the driving TFT DT into the low potential driving voltage. Initialize to (Vss). The gate electrode of the initialization TFT (Tint) is connected to the previous scan line 15n-1, the source electrode is connected to the input terminal of the low potential driving voltage Vss, and the drain electrode is connected to the first node N1. . The initialization TFT Tint is directly connected to the first node N1 to which the gate electrode of the driving TFT DT is connected, thereby reducing the initialization path. When the initialization path is shortened, the influence of parasitic capacitance on the initialization path is reduced, so that the gate voltage of the driving TFT DT can be quickly initialized to the low potential driving voltage Vss within a desired time. This leads to an improvement in pixel response speed and image quality.

The connection configuration and operation of the organic light emitting diode OLED, the driving TFT DT, the plurality of switch TFTs ST1 to ST5, and the storage capacitor Cst are substantially the same as in FIG. 4.

As described above, the organic light emitting diode display according to the present invention includes an initialization TFT directly connected to the gate electrode of the driving TFT for each pixel, thereby reducing the initialization path of the driving TFT, thereby increasing the response speed of the pixel and improving the display image quality. Can improve.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, in the embodiment of the present invention, only the case where the TFT is implemented as a P-type MOSFET has been described, but the technical idea of the present invention is not limited thereto, and it can be applied to the N-type MOSFET. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driver 13A: scan driver
13B: Emission Driver 14: Data Line
15 gate line 16 emission line

Claims (7)

An organic light emitting diode emitting light by a driving current flowing between an input terminal of a high potential driving voltage and an input terminal of a low potential driving voltage;
A driving TFT connected between the input terminal of the high potential driving voltage and the organic light emitting diode and controlling an amount of driving current applied to the organic light emitting diode according to a gate voltage applied to the first node; And
An initialization TFT for initializing a gate voltage of the driving TFT by applying an initialization voltage to the first node according to a previous scan signal;
And the initialization TFT is directly connected to the first node. The method of claim 1,
And the initialization voltage is selected from one of a reference voltage and the low potential driving voltage. The method of claim 2,
The initialization TFT,
A gate electrode connected to a previous scan line to which the previous scan signal is applied;
A source electrode connected to the input terminal of the reference voltage; And
And a drain electrode directly connected to the first node. The method of claim 2,
The initialization TFT,
A gate electrode connected to a previous scan line to which the previous scan signal is applied;
A source electrode connected to the input terminal of the low potential driving voltage; And
And a drain electrode directly connected to the first node. The method of claim 2,
A first switch TFT for switching a current path between the data line and the second node according to the current stage scan signal;
A second switch TFT switching a current path between a third node connected to the drain electrode of the driving TFT and the first node according to the current stage scan signal;
A third switch TFT for applying the reference voltage to the second node according to a current emission signal;
A fourth switch TFT for switching a current path between the third node and the anode electrode of the organic light emitting diode according to the current stage emission signal;
A fifth switch TFT for switching a current path between an input terminal of the reference voltage and an anode electrode of the organic light emitting diode according to the current stage scan signal; And
And a storage capacitor connected between the first node and the second node. The method of claim 5, wherein
According to the previous stage scan signal, the current stage scan signal, and the current stage emission signal, each frame includes a first initialization period, a second initialization period following the first initialization period, and the second initialization period. And a sampling period and a light emission period subsequent to the sampling period. The method according to claim 6,
The previous stage scan signal is generated at an activation level in the first and second initialization periods and is generated at an inactivation level in the sampling period and the emission period;
The current stage scan signal is generated at an activation level in the sampling period and is generated at an inactivation level in the first and second initialization periods and the emission period;
And the current emission signal is generated at an activation level in the first initialization period and the light emission period, and is generated at an inactivation level in the second initialization period and the sampling period.

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