KR20190078794A - Register for oled emission control and oled display device using the same - Google Patents

Abstract

Disclosed are a register for OLED emission control and an OLED display device using the same. According to an embodiment of the present invention, the register for OLED emission control includes a plurality of stages connected dependently connected to each other. The stages sequentially outputs a plurality of emission control signals, whose phases are delayed with a voltage level of a control voltage source in response to a plurality of clock pulses. The control voltage source supplied to the stages varied with a high potential or low potential voltage level in units of an image display period and emission control period unit in each frame period. A turn on/off period of the OLED emission control signal may be adjusted without additionally having a separate circuit or transformer. Accordingly, the brightness or luminance of a display image may be more easily controlled.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an OLED light emission control register and an OLED display using the OLED light emission control register.

The present invention relates to an OLED emission control register capable of controlling the brightness and brightness of a display image in at least one frame unit by adjusting an emission period of an OLED (Organic Light Emitting Diode) and an OLED display using the same.

The organic light emitting diode display uses an organic light emitting diode (OLED), which is a self-luminous element, and thus has a high response speed and a large luminous efficiency, luminance, and viewing angle.

The OLED includes an organic compound layer formed between the anode electrode and the cathode electrode. The OLED display device arranges the pixels including the OLED in a matrix form, and controls the brightness of the pixels according to the gradation of the video data. The OLED display selectively turns on a TFT (Thin Film Transistor), which is an active element, to select a pixel, and maintains the emission of a pixel at a voltage stored in a storage capacitor.

The OLED pixel includes an OLED emitting light by a driving current flowing between a high potential voltage (VDD) and a low potential voltage (VSS), a driving TFT (DT) controlling the amount of driving current applied to the OLED, A switch circuit SWC for adjusting the gate voltage of the driving TFT DT using the data voltage Vdata applied from the data line DL and the scan pulse SCAN applied from the gate line GL, And an emission TFT (ET) for turning on / off the current flow between the driver TFT (DT) and the OLED in response to a light emission control signal (EM) applied from the OLED. Here, the TFTs formed in the pixel may be selected as the P-type.

The OLED display includes a scan driver for driving the gate lines GL formed on the display panel and a light emission control driver for driving the emission lines EL.

The scan driver supplies a scan pulse (SCAN) for determining the addressing time of the data voltage (Vdata) to the scan lines (GL).

The light emission control driver supplies emission control signals EM to the emission lines EL for determining the light emission time of the pixels. The scan pulse SCAN is generated at the turn-on level and the emission control signal EM is generated at the turn-off level in the period in which the data voltage Vdata is addressed. Is generated at the turn-off level, and the light emission control signal EM is generated at the turn-on level.

The emission control driver is composed of a plurality of stages STG1 to STG4 which are connected in a dependent manner as shown in Fig. 2 and sequentially output the emission control signals EM1 to EM4.

Each of the stages STG1 to STG4 sequentially receives the start signal VST and the light emission control signal output from the previous stage and the plurality of clock pulses CLK1 and CLK2 and sequentially outputs the light emission control signals EM1 to EM4 Output.

According to this configuration, the OLED display device displays the data voltages (Vdata) addressed to the respective pixels in accordance with the turn-on emission control signals EM1 to EM4 sequentially applied to the respective pixel lines, .

In recent years, in order to reduce the power consumption of the OLED display device, functions capable of adjusting the brightness and brightness of the display image according to the change of the usage environment and the display mode conversion have been proposed.

However, the OLED display device may be difficult and complicated to lower the brightness or brightness of the display image as needed. For example, control signal modulation circuits for adjusting the video display period or a voltage conversion circuit for lowering the OLED driving voltage should be additionally provided in order to lower the brightness and brightness of the display image. Therefore, it is difficult to apply the function for adjusting the brightness and brightness of the display image due to the design, arrangement, cost, and the like of the additional components.

The inventors of the present invention invented an OLED display device capable of controlling the brightness and brightness of a display image without reducing the brightness of the display device.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an OLED emission control register that can control the brightness and brightness of a display image more easily by controlling the turn-on / off period of the OLED emission control signal without any additional circuit configuration. And to provide an OLED display using the same.

Another object of the present invention is to provide an OLED emission control register capable of reducing power consumption according to a change in usage environment and a display mode conversion option by allowing the OLED emission period of all pixels to be adjusted in a blank period of every frame period, And an OLED display device using the same.

The OLED light emission control register of the present invention includes a plurality of stages connected to each other in a dependent manner, the plurality of stages successively outputting a plurality of emission control signals phase-delayed by the voltage level of the control voltage source in response to a plurality of clock pulses, The voltage of the control voltage supplied to the stage of the emission control period is changed to the high or low potential voltage level in each of the video display period and the emission control period of each frame period.

The OLED display device of the present invention includes a plurality of OLED pixels and is driven by an image display panel for displaying an image, a gate and data lines of the image display panel, and outputs a plurality of emission control signals to the emission lines of the image display panel And a power supply unit for applying a power supply signal to the power supply lines of the image display panel, wherein the driving IC includes a control voltage source, which is variable in a high or low potential voltage level, A plurality of emission control signals are generated and supplied to the emission lines.

The ON / OFF period of the OLED emission control signal can be adjusted without further construction of a circuit or a transformer in the OLED emission control register of the present invention and the OLED display using the OLED emission control register. Thus, it is possible to more easily control the brightness and brightness of the display image.

In addition, the OLED emission control register of the present invention and the OLED display using the OLED emission control register enable the OLED emission period of all the pixels to be adjusted for each blank period of each frame period. Therefore, the power consumption of the OLED display device can be reduced according to the change of the usage environment and the display mode conversion option.

1 is a diagram schematically showing an equivalent circuit of an OLED pixel.
2 is a configuration diagram showing a light emission control driver structure.
3 is a configuration diagram illustrating an OLED emission control register according to an embodiment of the present invention.
FIG. 4 is a configuration diagram specifically showing the first through fourth stage configurations of FIG. 3. FIG.
5 is an equivalent circuit diagram specifically showing the first stage structure shown in FIG.
6 is a timing diagram illustrating a control signal and an output OLED emission control signal input to the OLED emission control register of the present invention.
FIG. 7 is a configuration diagram illustrating an OLED display according to an exemplary embodiment of the present invention. Referring to FIG.
8 is a view schematically showing an equivalent circuit of the OLED pixel shown in Fig.
Fig. 9 is a block diagram specifically showing the structure of the driving integrated circuit of Fig. 7; Fig.

The terms and words used in the present specification and claims should not be construed as limited to ordinary or preliminary meaning and the inventor shall properly define the concept of the term in order to describe its invention in the best possible way It should be construed in accordance with the meaning and concept consistent with the technical idea of the present invention.

It should be noted that the embodiments described in the present specification and the configurations shown in the drawings are only the most preferred embodiments of the present invention and do not represent all the technical ideas of the present invention, It should be understood that various equivalents and modifications are possible.

Hereinafter, an OLED emission control register according to the present invention and an OLED display using the same will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram illustrating an OLED emission control register according to an embodiment of the present invention.

The OLED emission control register shown in Fig. 3 includes a plurality of stages ST1 to ST4 which are connected to each other in dependence.

The plurality of stages ST1 to ST4 successively output the plurality of emission control signals EM1 to EM4 which are delayed in phase with the voltage level of the control voltage source Vcon in response to the plurality of clock pulses CLK1 and CLK2.

Although only the first to fourth stages ST1 to ST4 are illustrated in FIG. 3, the stages of the OLED emission control register may be configured to have a number equal to or greater than the number of horizontal lines or gate lines of the image display panel. The OLED emission control register sequentially transmits a plurality of emission control signals EM1 to EM4 to the emission control lines connected to the horizontal lines of the image display panel.

The plurality of emission control signals EM1 to EM4 may be output at a voltage level of low potential or high potential to control the OLED emission of each pixel. Hereinafter, assuming that the TFTs of the driving TFT and the switching circuit of each pixel are of the PMOS type, it is assumed that a plurality of emission control signals EM1 to EM4 for causing the OLED of each pixel to emit light at a low potential level Will be described. To this end, the control voltage source Vcon supplied to the plurality of stages ST1 to ST4 is maintained and supplied at a low potential voltage level for a period during which the plurality of emission control signals EM1 to EM4 are outputted to display an image.

The plurality of stages ST1 to ST4 receive the two-phase clock pulses CLK1 and CLK2 whose phases are alternately inverted in at least one clock unit. Sequentially responds to one of the two clock pulses CLK1 and CLK2 and successively outputs the respective emission control signals EM1 to EM4 during a period corresponding to one of the clock pulses CLK1 and CLK2. Hereinafter, a configuration using a two-phase clock pulse will be described as an example, but the present invention is not limited thereto.

For example, the first stage ST1 is responsive to at least one clock pulse of the start pulse VST and the first and second clock pulses CLK1 and CLK2 applied from the outside, And outputs the first emission control signal EM1 at the potential level. The first emission control signal EM1 can be maintained at a low potential level during the video display period of each frame period and output.

The second stage ST2 receives the first emission control signal EM1 output from the first stage ST1 as a carry signal. In response to a clock pulse of at least one of the first emission control signal EM1 and the first and second clock pulses CLK1 and CLK2, the second emission control signal EM2 Can be output and maintained.

The third stage ST3 receives the second emission control signal EM2 output from the second stage ST2 as a carry signal. In response to at least one of the clock pulses of the second emission control signal EM2 and the first and second clock pulses CLK1 and CLK2, the third emission control signal < RTI ID = 0.0 > EM3).

The fourth stage ST4 is responsive to a clock pulse of at least one of the third emission control signal EM3 output from the third stage ST3 and the first and second clock pulses CLK1 and CLK2, It is possible to output and maintain the fourth emission control signal EM4 at a low potential level of Vcon. In this manner, all stages connected to each other in a dependent manner sequentially output and maintain emission control signals to each other within an image display period.

The control voltage source Vcon supplied collectively to the plurality of stages ST1 to ST4 is maintained at a low potential or a high potential level in a predetermined video display period in each frame period. Hereinafter, an example in which the voltage level of the control voltage source Vcon is maintained at the low potential voltage level during the video display period will be described.

On the other hand, the control voltage source Vcon is varied and supplied to the high or low potential voltage level opposite to the potential held during the video display period in the preset emission control period in each frame period. An example in which the voltage level of the control voltage source Vcon is maintained at the low potential voltage level during the video display period has been described. On the contrary, in the preset emission control period, the voltage level of the control voltage source Vcon is set to the high potential voltage level And are supplied to the stages ST1 to ST4.

Each frame period includes an image display period in which the data voltages Vdata are supplied to the image display pixels and the pixels emit light in accordance with the data voltage Vdata and a blank period in which the data voltages Vdata are not supplied to the image display pixels Time period. The emission control period in which the potential of the control voltage source (Vcon) is varied in reverse to the video display period is a preset period so as to be included in the blank period of each frame period.

When the control voltage source Vcon is maintained at a preset low potential voltage level (for example, ground or ground voltage or VSS voltage level) during the video display period, the plurality of stages ST1 to ST4 are set to the low potential voltage level, And sequentially outputs the plurality of emission control signals EM1 to EM4.

Thereafter, when the control voltage source Vcon is changed to a preset high potential voltage level (for example, VDD voltage level) during the light emission control period, the plurality of stages ST1 to ST4 are turned on during the light emission control period And simultaneously outputs the control signals EM1 to EM4. This can be applied when the OLED driving TFT of the video display pixel is composed of the PMOS TFT.

If the OLED driving TFT of the video display pixel is composed of the NMOS TFT, the potential of the control voltage source (Vcon) can be applied and supplied as opposed to the case of the PMOS TFT. In the case where the OLED driving TFT is composed of the NMOS TFT, the control voltage source Vcon is maintained at the preset high potential voltage level during the video display period, and the plurality of stages ST1 to ST4 are the plurality of light emission And sequentially outputs and holds the control signals EM1 to EM4. During the light emission control period, the control voltage source Vcon is changed to a preset low potential voltage level, and the plurality of stages ST1 to ST4 simultaneously output the light emission control signals EM1 to EM4 having low potential voltage levels during the light emission control period .

As described above, the potential of the control voltage source Vcon that varies in the video display period or the emission control period can be set differently according to the characteristics of the OLED pixel structure of the video display panel and the driving TFTs formed in the OLED pixels.

FIG. 4 is a configuration diagram specifically showing the first through fourth stage configurations of FIG. 3. FIG. And Fig. 5 is an equivalent circuit diagram showing the first stage structure shown in Fig.

First, referring to Fig. 4, each of the plurality of stages ST1 to ST4 includes control circuit portions SR1 to SR4, a pull-up TFT Tu, and a pull-down TFT Td.

The control circuit units SR1 to SR4 receive the start pulse VST from the outside or the light emission control signal of the previous single stage as a carry signal and receive the carry signal and any one of the clock pulses CLK1 and CLK2 And controls the potentials of the Q node and the QB node, which are self-configured, to be opposite to each other according to the pulse. In other words, the control circuit units SR1 to SR4 control the self-configured Q node in an enable state according to the start pulse VST, the carry signal from the previous stage, and either one of the clock pulses CLK1 and CLK2 do. When the Q node is enabled, the control circuit units SR1 to SR4 control the QB node to a state of disabling the potential opposite to that of the Q node. Thereafter, when the Q node is controlled to be in a disabled state, the QB node is controlled to be in an enabled state.

The pull-up TFT Tu outputs each emission control signal at the voltage level of the control voltage source Vcon in accordance with the enable control state of the Q node configured in the control circuit units SR1 to SR4. In other words, the pull-up TFT Tu is turned on when the Q node of the control circuit portion connected thereto is enabled to the low potential, and outputs the light emission control signal at the low potential voltage level of the control voltage source (Vcon).

The pull-down TFT (Td) switches the emission control signal to the high or low potential voltage level in accordance with the enable control state of the QB node configured in the control circuit portions SR1 to SR4. That is, the pull-down TFT (Td) is turned on when the QB node of the control circuit portion connected to the pull-down TFT (Td) is enabled at the low potential to switch the potential of the emission control signal to the voltage level of the high- do.

5, the first control circuit SR2 of the plurality of control circuit units SR1 to SR4 includes a first switching TFT T1, a plurality of Q-node control TFTs T4, T5, and T8, and a plurality of QBs And a node control TFT (T2, T6, T7). The first switching TFT T1, the plurality of Q-node control TFTs T4, T5, and T8, and the plurality of QB node control TFTs T2, T6, and T7 may be PMOS TFTs.

The first switching TFT (T1) is turned on in response to a start pulse (VST) from the outside and any one of the clock pulses to control the Q node to an enabled state at a low potential.

The first switching TFT Tl included in the second control circuit portion SR2 is turned on according to the emission control signal from the first stage ST1 of the previous stage and any one of the clock pulses, And controls it in an enabled state.

Likewise, the first switching TFT (T1) included in the other control circuit portions, which are respectively connected to the second control circuit portion SR2, is also turned on according to the emission control signal from the previous stage and any one of the clock pulses The Q node is controlled to be in a low-potential enable state.

The plurality of Q-node control TFTs (T4, T5, T8) formed in each of the control circuit sections SR1 to SR4 are turned on in response to any one of the clock pulses in the state in which the Q node is enabled by the first switching TFT And maintains the enable state of the Q node.

On the other hand, the plurality of QB node control TFTs (T2, T6, T7) control the QB node in the disable state in contrast to the Q node according to the other clock pulse of the plurality of clock pulses CLK1, CLK2.

Thus, the pull-up TFT Tu is turned on in accordance with the enable control state of the Q node, and outputs the respective emission control signals at the voltage level of the control voltage source (Vcon). For example, the pull-up TFT Tu is turned on when the Q node is enabled to the low potential, and outputs the emission control signal at the low potential voltage level of the control voltage source (Vcon).

When the QB node is enabled by the plurality of QB node control TFTs (T2, T6, T7), the pull-down TFT (Td) switches the light emission control signal to the voltage level of the high potential or the low potential connected thereto. For example, the pull-down TFT (Td) may be turned on when the QB node is enabled to the low potential to switch the potential of the emission control signal to the high or low potential level.

6 is a timing diagram illustrating a control signal and an output OLED emission control signal input to the OLED emission control register of the present invention.

Referring to FIG. 6, in each frame period, a data voltage (Vdata) is supplied to the video display pixels and a video display period in which the OLED of each pixel emits light according to the data voltage (Vdata) And a blank period P_blank during which no data Vdata is supplied. The emission control period P_con (off) in which the potential of the control voltage source Vcon is varied can be set in advance to be included in the blank period P_blank of each frame period.

During the video display period during each frame period, the video data Data to be displayed in each OLED pixel is sequentially enabled in accordance with the data enable signal DE, and the video data Data is supplied to the data voltage (Vdata) and supplied to each OLED pixel.

When the OLED driving TFT of the video display pixel is composed of the PMOS TFT, the control voltage source Vcon supplied to the plurality of stages ST1 to ST4 is maintained at the low potential voltage level during the video display period during each frame period. And the two-phase clock pulses CLK1 and CLK2 are generated so that the phases are alternately inverted in at least one clock unit.

As shown in FIG. 6, during the video display period, the control voltage source Vcon is maintained at a low potential voltage level of the ground, ground voltage, or VSS voltage level. Thus, the plurality of stages ST1 to ST4 sequentially emit the plurality of emission control signals EM1 to EMn, which are delayed in phase with a low potential voltage level according to the control voltage source Vcon of the low potential voltage level supplied during the video display period Output, and maintain. In this manner, when the OLED driving TFT and the emission control TFT of the video display pixel are constituted by the PMOS TFT, the OLED of the video display pixel is caused to emit in response to the plurality of emission control signals EM1 to EMn which are delayed in phase by the low potential voltage level Display the image.

Thereafter, the control voltage source Vcon is controlled to a high or low potential voltage level opposite to the potential held during the image display period during the blank period P_blank of each frame period, in particular, in the predetermined emission control period P_con (off) Respectively. 6, since the control voltage source Vcon is maintained at the low potential level during the video display period, the control voltage source Vcon is switched to the high potential level level in the emission control period P_con (off) And supplied to the stages ST1 to ST4.

When the control voltage source Vcon is changed to a preset high potential voltage level (for example, VDD voltage level) in the light emission control period P_con (off), the plurality of stages ST1 to ST4 are turned on during the light emission control period P_con off) during the sustain period of the emission control signals EM1 to EM4. Thus, during the emission control period P_con (off), the OLEDs of all the pixels turn on during the emission control period P_con (off), as the emission control signals EM1 to EM4 of the high potential level are supplied to all the OLED pixels - Off.

As described above, in the present invention, the emission control period P_con (off) is controlled and the potential of the control voltage source Vcon can be varied in the emission control period P_con (off) the OLED of all OLED pixels is turned off for each frame period so that the brightness and brightness of the display image can be adjusted for each frame period.

On the other hand, when the OLED driving TFT of the video display pixel and the emission control TFT are composed of the NMOS TFT, the potential of the control voltage source (Vcon) can be applied and supplied in the opposite manner. As described above, the potential of the control voltage source Vcon, which is variable in the video display period or the emission control period, can be set differently depending on the OLED pixel structure of the image display panel and the characteristics of the switching device configured in the OLED pixel.

FIG. 7 is a configuration diagram illustrating an OLED display according to an exemplary embodiment of the present invention. Referring to FIG. And FIG. 8 is a view schematically showing an equivalent circuit of the OLED pixel shown in FIG.

7, the OLED display includes an image display panel 100, a driving integrated circuit 200, and a power supply 300. [

The image display panel 100 displays an image through a plurality of OLED pixels P arranged in a matrix form in each pixel region. Specifically, each OLED pixel P arranged in the pixel regions of the image display panel 100 includes an OLED and an OLED driving circuit that independently drives the OLED. The form in which the plurality of OLED pixels P are arranged in the respective pixel regions is not limited to the matrix form, but may be variously arranged in a stripe shape, a pixel sharing shape, a diamond shape, or the like.

8, each OLED pixel P includes an OLED that emits light due to a driving current flowing between a high potential (VDD) and a low potential (VSS), a driving TFT that controls the amount of driving current applied to the OLED A switch circuit SWC for adjusting the gate voltage of the driver TFT DT using a data voltage Vdata applied from the data line DL and a scan pulse SCAN applied from the gate line GL, And an emission TFT (ET) for turning on / off the current flow between the driving TFT (DT) and the OLED in response to the emission control signal (EM) applied from the emission line (EL). Here, an example in which the TFTs formed in the pixel are PMOS TFTs will be described.

The switch circuits SWC supply the analog data voltage Vdata from the data line DL connected thereto to the OLED so that the data voltage Vdata is charged to maintain the light emitting state.

The driving integrated circuit 200 itself generates gate control signals for driving the gate lines GL1 to GLn using at least one synchronization signal DCLK, Hsync, Vsync, DE, (For example, the gate voltage of the low or high logic). And sequentially supplies the gate-on signals to the gate lines GL1 to GLn. Here, the gate-off voltage is supplied during a period in which the gate-on voltage is not supplied to the gate lines GL1 to GLn. Accordingly, the driving integrated circuit 200 causes the switch circuits SWC connected to the gate lines GL1 to GLn to be sequentially driven in units of the gate lines GL.

The driving integrated circuit 200 applies emission control signals EL1 to ELn to the emission lines EL1 to ELn using at least one synchronization signal DCLK, Hsync, Vsync, DE and a control voltage source Vcon from the power supply unit 300. [ (EM1 to EMn) sequentially. Specifically, the driving integrated circuit 200 includes a plurality of emission control signals EM1 to EMn that are phase delayed by a low potential voltage level during a video display period of every frame period when the control voltage source Vcon is supplied at a low potential voltage level To the emission lines EL1 to ELn. The driving integrated circuit 200 outputs the emission control signals EM1 to EMn of high potential level during the emission control period P_con (off) during the blank period P_blank during which the control voltage source Vcon is supplied at the high potential level. To the emission lines EL1 to ELn at the same time.

The driving integrated circuit 200 converts the digital image data RGB input from the outside or stored in the memory device into the analog data voltage Vdata by using at least one synchronization signal DCLK, Hsync, Vsync, DE. Specifically, the driving integrated circuit 200 generates a gamma voltage set by subdividing the reference gamma voltages of a plurality of levels so as to correspond to the gradation values (for example, 0 gradation value to 255 gradation value) of the digital image data RGB And then converts the compensated digital image data to an analog data voltage (Vdata) using a gamma voltage set. The converted analog data voltages Vdata are successively supplied to the respective data lines DL1 to DLm and displayed as images.

The power supply unit 300 applies the high potential voltage VDD and the low potential voltage VSS to the power supply lines PL1 to PLn of the image display panel 100. [ The power supply unit 300 supplies a control voltage source Vcon having a low potential level to the driving IC 200 during a video display period of each frame period under the control of the driving IC 200. The power supply unit 300 supplies a control voltage source Vcon having a high potential level to the driving IC 200 in the emission control period P_con (off) of each frame period.

Fig. 9 is a block diagram specifically showing the structure of the driving integrated circuit of Fig. 7; Fig.

9 includes a timing control unit 201, a brightness / brightness control unit 210, a gate driving unit 220, a shift register 230, a latch unit 240, a gamma voltage generating unit 260 A digital-to-analog converter (DAC) 250, an output buffer 270, and an OLED emission control register 280.

The timing control unit 201 generates a start signal VST, a gate control signal GCS, a source shift clock SSC, a source start pulse SSP, a source output enable (SOE) (EL1 to ELn) and the gate and data lines (GL1 to GLn, DL1 to DLm). And outputs a gamma selection signal VGB to select high and low potential reference gamma voltages. When the digital image data RGB is input from the outside, the timing controller 201 sequentially supplies the digital image data RGB to the brightness / brightness controller 210.

The brightness / brightness controller 210 controls the brightness of the display image based on the brightness control information M_Data for adjusting the display brightness of the display image and the brightness control information P_Data for adjusting brightness, And resets the period (P_con (off)). The brightness / brightness controller 210 outputs the control voltage source Vcon as the low potential voltage level during the video display period and the control voltage source Vcon as the high potential voltage Vcon during the reset emission control period P_con (off) Level. The control voltage source (Vcon), which is varied to a low potential or a high potential level, is supplied to the OLED emission control register 280.

The luminance control information (M_Data) and the brightness control information (P_Data) are signal information set on the system board according to the brightness and brightness control of the user. When the user increases or decreases the brightness or brightness, the brightness control information (M_Data) or the brightness control information (P_Data) is increased or decreased. Accordingly, the emission control period P_con (off) also becomes longer or shorter, and the control voltage source Vcon having the low potential voltage level is output in the emission control period P_con (off).

The gate driver 220 sequentially generates and outputs gate-on signals for driving the gate lines GL1 to GLn in accordance with the gate control signal GCS from the timing controller 201. [

The shift register 230 sequentially outputs a sampling signal SAM in response to a source start pulse SSP and a source shift clock SSC from the timing controller 201 .

The latch unit 240 sequentially samples the modulated data IData compensated and modulated by the data compensator 210 in response to the sampling signal SAM. A source output signal (SOE) and video data (Data Output) are supplied from the timing controller 201 and simultaneously sampled data for one line (RData) is output.

The gamma voltage generator 260 divides the reference gamma voltages of a plurality of levels into the gamma voltages V0 of the digital image data RGB according to the gamma selection signal VGB from the timing controller 201, To V255).

The DAC 250 converts one line of data RData from the latch unit 240 into an analog video signal AData using the gamma voltage sets V0 to V255 supplied from the gamma voltage generator 260 And outputs it.

The output buffer 270 amplifies the analog video signal AData from the DAC 250 and supplies the amplified analog video signal AData to each of the data lines DL1 to DLm so that an image is displayed in each of the sub pixel regions on a horizontal line basis .

The OLED emission control register 280 is connected to the OLED emission control register 280 in accordance with the start signal VST input from the timing control unit 201, the plurality of clock pulses CLK1 and CLK2, and the control voltage source Vcon from the brightness / And emits light emission control signals EM1 to EM4.

As described with reference to Figs. 3 to 6, the OLED emission control register 280 includes a plurality of stages ST1 to ST4 that are connected to each other in dependence. The plurality of stages ST1 to ST4 successively output the plurality of emission control signals EM1 to EM4 which are delayed in phase with the voltage level of the control voltage source Vcon in response to the plurality of clock pulses CLK1 and CLK2.

Since the control voltage source Vcon, which is transmitted from the brightness / luminance controller 210 to the OLED emission control register 280 during the video display period, is supplied at a low potential level, the OLED emission control register 280 can supply To the emission lines EL1 to ELn, a plurality of emission control signals EM1 to EMn which are delayed in phase with a low potential voltage level according to the control voltage source Vcon of the low potential level.

The control voltage source Vcon from the brightness / brightness control unit 210 is varied and supplied to the high potential level during the emission control period P_con (off) during the blank period P_blank of each frame period. Thus, the OLED emission control register 280 simultaneously outputs the emission control signals EM1 to EMn of the high potential level during the emission control period P_con (off) to all the emission lines EL1 to ELn at the same time. During the emission control period P_con (off), as the emission control signals EM1 to EMn of the high potential level during the emission control period P_con (off) are supplied to all the OLED pixels P, (P) is turned off.

As described above, in the present invention, by controlling the emission control period (P_con (off)) and varying the potential of the control voltage source (Vcon) in the controlled emission control period (P_con The brightness and the brightness of the display image can be adjusted for each frame period by turning off the OLED of the display unit P. [

In other words, the turn-on / off periods of the OLED emission control signals EM1 to EM4 may be set to be different from the OLED emission control register 280 of the present invention and the OLED display device using the OLED emission control register 280, To be adjusted. Thus, it is possible to more easily control the brightness and brightness of the display image.

In addition, the OLED emission control register 280 of the present invention and the OLED display using the OLED emission control register 280 can control the OLED emission period of the entire OLED pixels P in each blank period P_blank of each frame period. Therefore, the power consumption of the OLED display device can be reduced according to the change of the usage environment and the display mode conversion option.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. I will understand. Accordingly, the true scope of protection of the present invention should be defined by the following claims.

ST1 to ST4: First to fourth stages
SR1 to SR4: First to fourth control circuits
100: display panel
200: drive integrated circuit
201:
210: luminance analysis controller
280: OLED emission control register
300: Power supply

Claims (11)

1. An OLED emission control register comprising a plurality of stages connected to each other in a dependent fashion,
Wherein the plurality of stages successively outputs a plurality of emission control signals phase-delayed in response to a plurality of clock pulses at a voltage level of a control voltage source,
Wherein the control voltage source supplied to the plurality of stages is varied to a high or low potential voltage level in a video display period and a light emission control period unit of each frame period,
OLED emission control register. The method according to claim 1,
The control voltage source
Wherein the plurality of stages are supplied with a voltage level of high or low potential during a video display period of each frame period,
Wherein the plurality of stages are supplied with a voltage level of a high potential or a low potential opposite to a voltage level of the control voltage source supplied during the image display period during the emission control period of each frame period,
OLED emission control register. 3. The method of claim 2,
The plurality of stages
And sequentially outputs the plurality of emission control signals during the video display period with a control voltage source of a high potential or a low potential voltage level supplied during a video display period of each frame period,
Wherein the plurality of emission control signals are varied during the emission control period with a voltage level of a high potential or a low potential opposite to a voltage level of the control voltage source supplied during the video display period in the emission control period of each frame period,
OLED emission control register. 3. The method of claim 2,
Each of the frame periods
An image display period in which a data voltage is supplied to the image display pixels and the OLED of the image display pixels emits light, and a blank period in which no data voltage is supplied to the image display pixels,
The light emission control period
Wherein the frame period is a preset period to be included in the blank period in each frame period,
OLED emission control register. 3. The method of claim 2,
Each of the plurality of stages
A QB node and a QB node are connected in parallel to each other. The QB node receives a start pulse from the outside and a light emission control signal of the previous single stage as a carry signal. The carry signal and the clock pulse of at least one of the plurality of clock pulses A control circuit unit for controlling the control circuit unit to be controlled;
A pull-up TFT for outputting the respective emission control signals at a voltage level of the control voltage source according to an enable control state of the Q node; And
And a pull-down TFT for switching the light emission control signal to a voltage level of high or low potential according to an enable control state of the QB node.
OLED emission control register. An image display panel having an OLED pixel and displaying an image;
A driving integrated circuit driving the gate and data lines of the image display panel and outputting a plurality of emission control signals to the emission lines of the image display panel to display an image through the OLED pixels; And
And a power supply unit for applying a power supply signal to the power supply lines of the image display panel,
The drive integrated circuit
Generating a plurality of emission control signals with a control voltage source varying to a high potential or a low potential voltage level and supplying the plurality of emission control signals to the emission lines,
OLED display. The method according to claim 6,
The drive integrated circuit
A timing controller for controlling driving timings of the emission lines and the gate and data lines;
The emission control period of each frame period is set according to the luminance control information for adjusting the display luminance of the display image and the brightness control information for adjusting the brightness and the voltage level of the control voltage source is set to the high potential or low potential voltage level A brightness / luminance controller for outputting a variable value;
And an OLED emission control register for outputting the plurality of emission control signals to the emission lines in accordance with a start signal from the timing control unit, a plurality of clock pulses, and the control voltage source from the brightness /
OLED display. 8. The method of claim 7,
The OLED emission control register
And includes a plurality of stages connected to each other in a dependent manner
The plurality of stages successively outputting the plurality of emission control signals which are delayed in phase with the voltage level of the control voltage source in response to the plurality of clock pulses,
Wherein the control voltage source supplied to the plurality of stages in the brightness / brightness controller is varied to a high or low potential voltage level in a video display period and a light emission control period unit of each frame period,
OLED display. 9. The method of claim 8,
The control voltage source
Wherein the plurality of stages are supplied with a voltage level of high or low potential during a video display period of each frame period,
Wherein the plurality of stages are supplied with a voltage level of a high potential or a low potential opposite to a voltage level of the control voltage source supplied during the image display period during the emission control period of each frame period,
OLED display. 9. The method of claim 8,
The plurality of stages
And sequentially outputs the plurality of emission control signals during the video display period with a control voltage source of a high potential or a low potential voltage level supplied during a video display period of each frame period,
Wherein the plurality of emission control signals are varied during the emission control period with a voltage level of a high potential or a low potential opposite to a voltage level of the control voltage source supplied during the video display period in the emission control period of each frame period,
OLED display. 9. The method of claim 8,
Each of the frame periods
An image display period in which a data voltage is supplied to the image display pixels and the OLED of the image display pixels emits light, and a blank period in which no data voltage is supplied to the image display pixels,
The light emission control period
Wherein the frame period is a preset period to be included in the blank period in each frame period,
OLED display.

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