KR20180066629A - Gate Driver and Display Device using the same - Google Patents

Abstract

The present invention provides a display device including a display panel, a data driving circuit, and a gate driving circuit. The display panel includes a light emitting diode, a driving TFT for controlling a driving current flowing in the light emitting diode in accordance with a voltage between a gate node and a source node, and a plurality of pixels connected to a data line, a reference line, and a gate line. The data driving circuit supplies a data voltage to the data line and supplies a reference voltage to the reference line. The gate driving circuit generates a scan signal synchronized with the data voltage and a sensing signal synchronized with the reference voltage, and supplies the same to the gate line. The gate driving circuit outputs a scan signal including a first scan pulse synchronized with a first data voltage applied during a light emitting period for one frame and a second scan pulse synchronized with a second data voltage applied during a non-light emitting period.

Description

[0001] The present invention relates to a gate driver circuit and a display device using the same,

The present invention relates to a gate driving circuit and a display using the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as an electroluminescence display (ELD), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Among the display devices described above, the electroluminescent display device includes a display panel including a plurality of sub-pixels and a driver for driving the display panel. The driving unit includes a scan driver for supplying a scan signal (or a scan signal) to the display panel, and a data driver for supplying a data signal to the display panel.

The display panel has a plurality of subpixels implemented based on a driving transistor (TFT) for controlling a driving current and a diode for emitting light. The plurality of sub-pixels emit light in proportion to the driving current generated from the driving transistor.

In the case of an electroluminescent display device, a duty control technique has been proposed that adjusts the emission duty (the ratio of the emission time to the frame time) during one frame in order to improve the moving image response characteristic and the low gradation display quality. However, the duty control technique proposed in the related art has a problem that luminance distortion occurs due to a problem of an increase in consumed power and heat generation or a voltage drop due to a series transistor.

According to an aspect of the present invention, there is provided a gate driving circuit for outputting a signal capable of adjusting emission duty of a light emitting diode without writing black data or providing a light emitting control TFT in a pixel, and a display device using the same. .

According to the present invention, there is provided a display device including a display panel, a data driving circuit, and a gate driving circuit. The display panel has a light emitting diode and a driving TFT controlling a driving current flowing in the light emitting diode according to the voltage between the gate node and the source node, and has a plurality of pixels connected to the data line, the reference line and the gate line, respectively. The data driving circuit supplies the data voltage to the data line and the reference voltage to the reference line. The gate drive circuit generates a scan signal synchronized with the data voltage and a sensing signal synchronized with the reference voltage and supplies the generated signal to the gate line. The gate driving circuit outputs a scan signal including a first scan pulse synchronized with a first data voltage applied during a light emission period and a second scan pulse synchronized with a second data voltage applied during a non-emission period for one frame.

The gate driving circuit may output a scan signal including a first scan pulse and a second scan pulse based on a start signal generated at least two logic highs during one frame.

The period during which the first scan pulse and the second scan pulse are generated may vary.

The second scan pulse may be output with a time difference after the first scan pulse is applied.

The gate driver circuit includes a scan signal generator having M clock signal lines for generating a scan signal and M clock signal lines for generating a sensing signal, wherein N is an integer or a fraction of 2 or more, * M (where M is an integer of 4 or more).

The clock signals applied through the clock signal lines may each have a region where some sections overlap.

The gate driving circuit may output a sensing signal including a first sensing pulse synchronized with the first scan pulse.

In another aspect, the present invention provides a gate driving circuit including stage circuits for outputting a scan signal including a first scan pulse and a second scan pulse for one frame. The scan signal output from the gate driver circuit is generated based on a start signal that occurs at least twice high for one frame.

The period during which the first scan pulse and the second scan pulse are generated may vary.

A clock signal line for generating a sensing signal is divided into N (where N is an integer or a fraction of 2 or more) * M (M is an integer or a fraction) And a sensing signal generator having 4 or more constants.

The present invention has an effect that it is possible to easily adjust a non-emission period in which light emission is stopped for one frame by appropriately controlling a scan signal or a scan signal or a sensing signal without having to program black data capable of turning off the driving TFT. Further, the present invention eliminates the need to write black data for duty driving, thereby preventing an increase in power consumption due to black data writing. Further, the present invention eliminates the necessity of further providing a light emission control TFT for duty driving, and it is advantageous in that the configuration of the pixel is simplified, and the luminance distortion due to the operation of the light emission control TFT is also prevented .

1 shows a conventional duty control technique for writing black data or turning off a light emission control TFT in a pixel to control the light emission duty.
2 is a view showing a conventional pixel structure including a light emission control TFT to implement a conventional duty control technique.
3 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
4 is a diagram illustrating an example of a pixel structure for implementing a duty control technique according to the present invention.
5 is a diagram showing an example in which an interval between pulses of a gate signal is controlled in accordance with a light emission duty.
6 is a diagram showing a change in the frame average OLED driving current according to the emission duty.
FIG. 7 and FIG. 8 are diagrams illustrating driving waveforms for implementing a duty control technique according to an embodiment of the present invention. FIG.
9A to 9C are equivalent circuit diagrams of pixels corresponding to the programming period, the light emission period and the non-light emission period, respectively.
10 is a diagram showing potentials of a gate node and a source node in a programming period, a light emission period, and a non-light emission period (corresponding to a black display period) in Fig. 8;
11 is a block diagram schematically showing a gate drive circuit according to an embodiment of the present invention.
12 shows a configuration of a clock signal according to the first experimental example;
13 shows a Q node potential and an output waveform of a gate driving circuit according to the first experimental example of Fig.
14 is a diagram showing a configuration of a clock signal according to a second experimental example;
FIG. 15 is a diagram showing a Q node potential and an output waveform of a gate driving circuit according to a second experimental example of FIG. 14; FIG.
16 is a diagram specifically illustrating a driving waveform for implementing a duty control technique according to an embodiment of the present invention;
17 is a diagram showing a configuration of a clock signal according to the first embodiment;
FIG. 18 is a diagram showing a Q node potential and an output waveform of the gate driving circuit according to the first embodiment of FIG. 17; FIG.
19 shows a configuration of a clock signal according to the second embodiment;
FIG. 20 is a diagram showing a Q node potential and an output waveform of a gate driving circuit according to the second embodiment of FIG. 19; FIG.
21 is a view for explaining a connection method of a clock signal line according to the first experimental example;
22 is a view for explaining a connection method of a clock signal line according to the first embodiment;
23 is a view for explaining a connection method of a clock signal line according to a second experimental example;
24 is a view for explaining a connection method of a clock signal line according to the second embodiment;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The display device according to the present invention can be implemented by a television, a video player, a personal computer (PC), a home theater, a smart phone, or the like, but is not limited thereto. The display device described below is an example of an organic light emitting display device implemented based on an organic light emitting diode. However, the display device described below can be implemented based on organic light emitting diodes or inorganic light emitting diodes. The present invention is not limited to an electroluminescent display device but may be applied to a display device of a similar type.

In particular, the present invention relates to a duty control technique for adjusting an emission duty (a ratio of emission time to a frame time) for one frame in order to improve motion picture response characteristics and low gradation display quality.

FIG. 1 is a view showing a conventional duty control technique of writing black data or controlling a light emission duty by turning off a light emission control TFT in a pixel, and FIG. 2 is a diagram showing a conventional duty control technique, FIG.

1, the conventional duty control technique 1 divides one frame (Fn + 1 or Fn + 2) into a light emission period Ta and a black display period Tb, The black data is written at a predetermined timing in accordance with the line sequential method. The black data has a data level capable of turning off the driving TFT. When the black data is applied, the driving current applied to the organic light emitting diode (hereinafter abbreviated as OLED) is cut off, and the OLED is not emitted. The emission period Ta is reduced and the black display period Tb is increased as the timing for writing black data during one frame is advanced. According to such a conventional duty control technique 1, since the output channel potential of the data driving circuit for black data writing must be continuously swung from the image data level to the black data level or vice versa, power and heat dissipated in the data driving circuit Is increased.

As shown in FIG. 2, the conventional duty control technique 2 further includes a separate emission control TFT ET in a pixel, and a frame Fn + 1 or Fn + 2 is divided into a light emission period Ta and a black display period Tb. Then, the emission control TFT ET is turned off in accordance with the line sequential method at a predetermined timing to implement the black display period Tb. The light emission control TFT ET can be connected to an arbitrary position between the input terminal of the high potential drive voltage EVDD and the input terminal of the low potential drive voltage EVSS in the pixel. In Fig. 2, DT indicates a drive TFT, and SWC indicates a switch circuit connected to the drive TFT DT and the emission control TFT ET. When the emission control TFT (ET) is turned off, the driving current applied to the OLED is cut off, so that the OLED is not emitted. This conventional duty control technique 2 has a problem that the pixel array structure becomes complicated due to the light emission control TFT ET, and luminance distortion occurs due to the resistance of the light emission control TFT ET.

As described above, the conventionally proposed duty control technique has a problem in that brightness distortion occurs due to a problem of an increase in consumed power and heat generation or a resistance of an added transistor. Hereinafter, an embodiment of the present invention for improving the conventional duty control technique will be described.

3 is a view illustrating an organic light emitting display according to an exemplary embodiment of the present invention.

3, the organic light emitting display device includes a display panel 10, a timing controller 11, a data driving circuit 12, and a gate driving circuit 13, as shown in FIG.

The display panel 10 is formed with a plurality of data lines 15 and reference lines 16 and a plurality of gate lines 17 and 18. Pixels are formed at intersections of the data lines 15, the reference lines 16, and the gate lines 17 and 18. The pixels may be divided line by line based on the horizontal direction. For example, the pixels may be divided into first through Nth horizontal pixel lines HL1 through HLn. The pixels arranged in the same horizontal direction are supplied with the same scan signal.

The gate lines 17 and 18 may include first gate lines 17 to which a scan signal is applied and second gate lines 18 to which a sensing signal is applied. Each pixel is connected to one of the data lines 15, to one of the reference lines 16, to one of the first gate lines 17, and to one of the second gate lines 18 Lt; / RTI > Each pixel includes an OLED and a driving TFT, and duty driving for controlling the emission duty of the OLED in one frame is possible.

These pixels are supplied with the high potential driving voltage (EVDD) and the low potential driving voltage (EVSS) from the power supply block. The TFTs constituting the pixel can be realized as p-type, n-type, or hybrid type combining p-type and n-type. The semiconductor layer of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or an oxide.

The data driving circuit 12 converts the input image data RGB into data voltages under the control of the timing controller 11 and supplies the data voltages to the data lines 15. [ In addition, the data driving circuit 12 generates a reference voltage under the control of the timing controller 11 and supplies the reference voltage to the reference lines 16.

The gate drive circuit 13 generates a scan signal synchronized with the data voltage and supplies the scan signal to the first gate lines 17 under the control of the timing controller 11 to generate a sensing signal synchronized with the reference voltage, To the lines (18). The gate drive circuit 13 may be embedded in the non-display area of the display panel 10 or may be bonded to the display panel 10 in the form of an IC.

The gate driving circuit 13 includes a first scan pulse and a second scan pulse for duty driving for one frame and supplies the first scan pulse and the second scan pulse separately to the same pixel for one frame . The first scan pulse and the second scan pulse are supplied with a time difference.

The gate driving circuit 13 may configure a sensing signal for duty driving for only one frame with only the first sensing pulse and supply the first sensing pulse to the pixel in synchronization with the first scanning pulse. The gate driving circuit 13 constitutes a sensing signal for duty driving for one frame with a first sensing pulse and a second sensing pulse and supplies the first sensing pulse to the pixel in synchronization with the first scanning pulse, The second sensing pulse may be supplied to the pixel in succession to the second scanning pulse.

The timing controller 11 receives input image data RGB from the host system 14 via an interface circuit (not shown) and outputs the image data RGB to a data driving circuit (not shown) through various interface methods such as mini-LVDS (12).

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the host system 14, And generates control signals for controlling the operation timings of the drive circuit 12 and the gate drive circuit 13. [ The control signals include a gate timing control signal GDC for controlling the operation timing of the gate drive circuit 13, a source timing control signal DDC for controlling the operation timing of the data drive circuit 12, And a duty control signal DCON for controlling duty.

The duty control signal DCON is a signal for controlling the interval between the first and second scan pulses of the scan signal. The duty control signal DCON may be a signal for controlling the interval between the first and second scan pulses of the scan signal and the interval between the first and second sensing pulses of the sensing signal. The duty control signal DCON is a signal that is completely independent of writing black data or turning on / off the light emission control TFT in the pixel as in the conventional art. The present invention adjusts the non-emission period in which the emission of the OLED stops for one frame by appropriately controlling the scan signal or the scan signal or the sensing signal without programming the black data capable of turning off the driving TFT.

The timing controller 11 can minimize the power consumption due to the duty drive by controlling the operation of the gate drive circuit 13 so that the duty drive is performed only when the inter-frame image change value is large. The duty controller 11 generates a duty control signal DCON when the average image level of the image data RGB is the same as a preset reference value and outputs the duty control signal DCON to the first and second scan The interval between pulses can be maintained at a default value.

The timing controller 11 generates a duty control signal DCON to set the interval between the first and second scan pulses of the scan signal applied to the same pixel as the default Value can be increased. The timing controller 11 generates the duty control signal DCON and outputs the interval between the first and second scan pulses of the scan signal applied to the same pixel if the average picture level of the image data RGB is smaller than a preset reference value The default value can be reduced.

4 is a diagram illustrating an example of a pixel structure for implementing the duty control technique according to the present invention. In Fig. 4, the DAC denotes a digital-analog converter in the data driving circuit that outputs the data voltage.

4, the pixel according to the present invention includes an OLED, a driving TFT (Thin Film Transistor) DT, a storage capacitor Cst, a first switch TFT ST1, and a second switch TFT ST2 .

The OLED includes an anode electrode connected to the source node Ns, a cathode electrode connected to the input terminal of the low potential driving voltage EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode.

The driving TFT DT controls the driving current flowing in the OLED according to the voltage difference between the gate node Ng and the source node Ns. The driving TFT DT has a gate electrode connected to the gate node Ng, a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the source node Ns. The storage capacitor Cst is connected between the gate node Ng and the source node Ns.

The first switch TFT ST1 switches the data voltage on the data line 15 to the gate node Ng by switching the current flow between the data line 15 and the gate node Ng in response to the scan signal SCAN. . The first switch TFT ST1 has a gate electrode connected to the first gate line 17, a drain electrode connected to the data line 15, and a source electrode connected to the gate node Ng.

The second switch TFT ST2 switches the reference voltage Vref on the reference line 16 to the source node Ns by switching the current flow between the reference line 16 and the source node Ns in response to the sensing signal SEN Ns. The second switch TFT ST2 has a gate electrode connected to the second gate line 18, a drain electrode connected to the reference line 16, and a source electrode connected to the source node Ns.

FIG. 5 shows an example in which the interval between the pulses of the gate signal is controlled according to the emission duty, and FIG. 6 shows a change in the frame average OLED driving current according to the emission duty. The frame average current is a value obtained by multiplying the current flowing in the bite period by the duty. The brightness perceived by the eye is proportional to the frame average current.

As shown in FIGS. 5 and 6, the present invention supplies a scan signal SCAN including first and second scan pulses P1 and P2 for one frame for duty driving, By controlling the interval between the scan pulses P1 and P2, the emission duty of the OLED is controlled.

The present invention can maintain the emission duty of the OLED at 100% when the frame-to-frame (Fn, Fn + 1) image variation value is small. In this case, the duty drive is not performed, and the scan signal SCAN of the first scan pulse P1 is applied to each pixel during one frame.

The present invention performs duty driving only when the frame-to-frame (Fn, Fn + 1) image variation value is large, and adjusts the emission duty of the OLED to 25%, 50%, 96%, etc. in proportion to the average image level of the input image data. can do. In order to realize duty driving, the present invention applies scan signals (SCAN) of a first scan pulse (P1) and a second scan pulse (P2) to each pixel for one frame.

The interval between the first and second scan pulses P1 and P2 of the scan signal SCAN is inversely proportional to the emission duty of the OLED. As the interval between the first and second scan pulses P1 and P2 of the scan signal SCAN increases, the emission duty of the OLED decreases, but the improvement of the video response characteristics and the low gradation display quality becomes greater. Meanwhile, the present invention is not limited to the high speed driving at a frequency of 120 Hz for duty driving, for example.

FIGS. 7 and 8 are diagrams showing driving waveforms for implementing a duty control technique according to an embodiment of the present invention. FIGS. 9A to 9C show equivalent circuit diagrams of pixels corresponding to a programming period, a light emitting period, And Fig. 10 is a diagram showing the potentials of the gate node and the source node in the programming period, the light emission period, and the non-light emission period (corresponding to the black display period) in Fig.

In the first embodiment of the present invention, a scan signal SCAN is generated with a double pulse waveform including first and second scan pulses Pa1 and Pa2, and a single pulse waveform including a first sensing pulse Pb1, (SEN).

7 shows driving waveforms of pixels sharing the same data line and sharing the same reference line. In particular, FIG. 7 shows a case where the first pixel is arranged in the first horizontal pixel line HL1, the second pixel is arranged in the second horizontal pixel line HL2, and the jth pixel is arranged in the jth horizontal pixel line HLj And the j + 1-th pixel is arranged in the (j + 1) -th horizontal pixel line (HLj + 1).

7, a first data voltage D1 corresponding to the first input image data RGB is applied to the first pixel and a second input image data RGB is applied to the second pixel during the same frame, A j th data voltage Dj corresponding to the j th input image data RGB is applied to the j th pixel and a j th data voltage D j corresponding to the j th The (j + 1) th data voltage Dj + 1 corresponding to the input image data RGB is applied.

The first scan pulse Pa1 of the scan signal SCAN is applied to the first gate lines HL1 to HLn of the horizontal pixel lines HL1 to HLn in synchronization with the respective data voltages D1, D2, Dj, and Dj + (17) in a line-sequential manner. In synchronization with the first scan pulse Pa1 of the scan signal SCAN, the first sensing pulse Pb1 of the sensing signal SEN is applied to the second gate line 18 of each of the horizontal pixel lines HL1 to HLn Line-sequential manner. During the same frame, a second scan pulse Pa2 of the scan signal SCAN is applied to the first gate line (first scan line) of each of the horizontal pixel lines HL1 to HLn in synchronism with the respective data voltages Dj, Dj + 17 in a line-sequential manner.

8 shows driving waveforms of the scan signal SCAN, the sensing signal SEN, and the data voltages D1 and Dj applied to the first pixel arranged in the first horizontal pixel line HL1. 8, one frame for duty driving is divided into a programming period Tp for setting the voltage between the gate node Ng and the source node Ns to match the driving current, And a non-emission period Tb during which the emission of the OLED is stopped.

9A, in the programming period Tp, the first switch TFT ST1 of the first pixel is turned on according to the first scan pulse Pa1 of the scan signal SCAN to be supplied to the gate node Ng The first data voltage D1 is applied. The second switch TFT ST2 of the first pixel in the programming period Tp is turned on according to the first sensing pulse Pb1 of the sensing signal SEN to apply the reference voltage Vref to the source node Ns . The voltage between the gate node Ng and the source node Ns of the first pixel is set to the driving current in the programming period Tp.

The first switch TFT ST1 of the first pixel is turned off according to the scan signal SCAN in the light emission period Te and the second switch TFT ST2 of the first pixel is turned off And is turned off according to the signal SEN. The voltage Vgs between the gate node Ng and the source node Ns set in the first pixel in the programming period Tp is maintained in the light emission period Te. Since the voltage Vgs between the gate node Ng and the source node Ns is greater than the threshold voltage Vth of the driving TFT DT of the first pixel as shown in FIG. 10, A driving current flows in the driving TFT of the pixel circuit. The potential of the gate node Ng and the potential of the source node Ns are respectively boosted while maintaining the voltage Vgs between the gate node Ng and the source node Ns in the light emission period Te by this drive current . When the potential of the source node Ns is boosted to the operating point level of the OLED, the OLED of the first pixel emits light.

The first switch TFT ST1 of the first pixel is turned on according to the second scan pulse Pa2 of the scan signal SCAN in the non-emission period Tb to turn on the gate node Ng, (J) < / RTI > The second switch TFT (ST2) of the first pixel maintains the turn-off state according to the sensing signal SEN. Here, the jth data voltage Dj corresponds to the input image data to be applied to the jth pixel. Since the first pixel and the j-th pixel share one data line and the non-emission period Tb of the first pixel overlaps the programming period Tp of the j-th pixel, the j-th data voltage Dj not only the gate node of the j pixel but also the gate node Ng of the first pixel.

When the jth data voltage Dj is applied in the non-emission period Tb, the potential of the gate node Ng of the first pixel is leveled down to the jth data voltage Dj at the boosting level, The potential of the node Ns is maintained at the operating point level of the OLED. In the present invention, the operating point level of the OLED is set to be higher than the maximum data voltage corresponding to the brightest gradation.

Therefore, when the jth data voltage Dj is applied in the non-emission period Tb, the voltage Vgs between the gate node Ng and the source node Ns becomes equal to the threshold voltage Vth of the driving TFT DT, And as a result, the driving current flowing through the driving TFT DT is cut off. When the supply of the second scan pulse Pa2 of the scan signal SCAN is stopped in the non-emission period Tb (i.e., when the second scan pulse Pa2 of the scan signal SCAN is polled) The potential of the gate node Ng and the potential of the source node Ns are respectively leveled down while the voltage Vgs between the gate node Ng and the source node Ns is kept smaller than the threshold voltage Vth of the drive TFT DT do. When the potential of the source node Ns becomes lower than the operating point level of the OLED, the emission of the OLED is stopped.

As described above, according to the present invention, the scan signal or the scan signal and the sensing signal are appropriately controlled without separately programming the black data capable of turning off the driving TFT, thereby adjusting the non-emission period in which the emission of the OLED stops for one frame . For example, a scan signal SCAN divided into a first scan pulse P1 and a second scan pulse P2 is applied to each pixel during one frame. As a result, the present invention eliminates the necessity of providing a light emitting control TFT (ET) in order to implement a duty control technique as in the prior art, so that the pixel structure is simplified, and the luminance distortion due to the operation of the light emitting control TFT It is prevented in advance.

Hereinafter, an embodiment of a gate driving circuit for applying a scan signal SCAN divided into a first scan pulse P1 and a second scan pulse P2 will be described.

11 is a block diagram schematically showing a gate driving circuit according to an embodiment of the present invention.

As shown in Fig. 11, the gate drive circuit according to the embodiment of the present invention includes a plurality of stage circuits STG [D] to STG [j + 1]. The plurality of stage circuits STG [D] to STG [j + 1] operate based on an externally supplied start signal VST and a clock signal CLK. The stage circuits STG [D] to STG [j + 1] include a scan signal generator for generating and outputting scan signals SCAN and SCANd, a sensing signal generator for generating and outputting sensing signals SEN and SENd, And a carry signal generation unit for generating and outputting the carry signal CAR.

The stage circuits STG [D] to STG [j + 1] include at least one dummy stage circuit STG [D] and a plurality of stage circuits STG [ . The scan signal SCANd and the sensing signal SENd output from the dummy stage circuit STG [D] are not supplied to the display panel 10. [ On the other hand, the carry signal CAR output from the dummy stage circuit STG [D] is supplied to the plurality of stage circuits STG [1] to STG [[j + 1]).

The scan signal SCAN and the sensing signal SEN output from the plurality of stage circuits STG [1] to STG [j + 1] are supplied to the display panel 10. [ For example, the first stage circuit STG [1] supplies the scan signal SCAN and the sensing signal SEN to the first horizontal pixel line HL1 of the display panel 10, STG [j + 1] supplies a scan signal SCAN and a sensing signal SEN to the (j + 1) th horizontal pixel line HLj + 1 of the display panel 10. The carry signal CAR output from the plurality of stage circuits STG [1] to STG [[j + 1]) is supplied to the plurality of stage circuits STG [1] to STG [[j + 1] . For example, the carry signal CAR is supplied to the stage circuit arranged at least one step and / or below the self.

The characteristics of the output signals outputted from the plurality of stage circuits STG [D] to STG [j + 1] are determined corresponding to the input signals inputted to drive them. Therefore, in order to generate the scan signal SCAN divided into the first scan pulse and the second scan pulse by using the plurality of stage circuits STG [D] to STG [j + 1], the input signal is appropriately set Should be. Hereinafter, embodiments for generating a scan signal SCAN divided into a first scan pulse and a second scan pulse will be described with reference to experimental examples.

12 is a diagram showing a configuration of a clock signal according to the first experimental example, FIG. 13 is a diagram showing a Q node potential and an output waveform of a gate driving circuit according to the first experimental example of FIG. 12, FIG. 15 is a diagram showing a configuration of a clock signal according to an experimental example, and FIG. 15 is a diagram showing a Q node potential and an output waveform of a gate driving circuit according to a second experimental example of FIG.

The stage circuits STG [D] to STG [j + 1] of Fig. 11 are replaced with the first to fourth clock signals CLK1 to CLK4 of the four- CLK4). As a result, the output as shown in FIG. 13 was obtained.

According to the first experimental example, the stage circuits STG [D] to STG [j + 1] of FIG. 11 are provided with the scan signals CLK1 to CLK4 on the basis of the first to fourth clock signals CLK1 to CLK4 of four phases, (SCAN), a sensing signal (SEN), and a carry signal (CAR) are generated. Accordingly, the stage circuits STG [D] to STG [j + 1] of Fig. 11 are turned off during the charging period in which the Q node maintains the logic high, the scan signals SCAN, the sensing signal SEN, ). However, the scan signal SCAN divided into the first scan pulse and the second scan pulse can not be output by only the first to fourth clock signals CLK1 to CLK4 of the four commonly used phases.

On the other hand, in the first experimental example, the stage circuits STG [D] to STG [j + 1] are arranged in such a manner that the outputs of the stage circuits arranged two stages below (n + 2) As input. As shown in FIG. 12, the first to fourth clock signals CLK1 to CLK4 of the four phases each have a region in which some sections are sequentially superimposed. 1, 2, 3, 4, ... in the first to fourth clock signals CLK1 to CLK4 denote the order in which logic high occurs in the clock signal. VST means the start signal and RESET means the reset signal. In the third and fourth clock signals CLK3 and CLK4, DMY means that a logic high has occurred as a dummy.

The stage circuits STG [D] to STG [j + 1] of FIG. 11 are replaced with the first to sixth clock signals CLK1 to CLK of FIG. 14, CLK6). As a result, the output as shown in FIG. 15 was obtained.

According to the second experimental example, the stage circuits STG [D] to STG [j + 1] of FIG. 11 are provided with the scan signals CLK1 to CLK6 based on the first to sixth clock signals CLK1 to CLK6 of six phases, (SCAN), a sensing signal (SEN), and a carry signal (CAR) are generated. Accordingly, the stage circuits STG [D] to STG [j + 1] of Fig. 11 are turned off during the charging period in which the Q node maintains the logic high, the scan signals SCAN, the sensing signal SEN, ). However, the scan signal SCAN divided into the first scan pulse and the second scan pulse can not be outputted only by the first to sixth clock signals CLK1 to CLK6 of the 6th phase generally used conventionally.

On the other hand, in the second experimental example, the stage circuits STG [D] to STG [j + 1] are arranged in such a manner that the output of the stage circuit arranged three stages below (n + 3) As input. As shown in FIG. 14, the first to sixth clock signals CLK1 to CLK6 of the six phases each have an area in which some sections are sequentially superimposed. 1, 2, 3, 4, 5, 6, ... in the first through sixth clock signals CLK1 through CLK6 denote the order in which logic high occurs in the clock signal. VST means the start signal and RESET means the reset signal. In the fourth to sixth clock signals CLK4 to CLK6, DMY means that a logic high has occurred as a dummy.

As can be seen from the above first and second experimental examples, the stage circuits STG [D] to STG [j + 1] of Fig. 11 generate an output when the Q node maintains a logic high state. The output of the stage circuits STG [D] to STG [j + 1] depends on the phase of the clock signal related to the charge and discharge of the Q node (generally, phase) The k phase can be interpreted as k lines where the Q node is a logic high. In order to select a line to which the scan signal SCAN and the sensing signal SEN are to be output, k clock signals are required.

According to the first and second experimental examples, the scan signal SCAN of the frame is outputted twice and the sensing signal SEN is not output once, by using the clock signal conventionally used in the related art.

As a result of studying the reason, in order to output the scan signal SCAN twice out of the frame, there must be two line regions whose Q node is logic high. Therefore, to output the scan signal (SCAN) twice in the frame, if the Q node is a logic high region, it should have 4 lines × 2 in 4 phase and 6 lines × 2 in 6 phase do. That is, if there are two regions where the Q node is logic high in the k phase, then there are 2k lines where the Q node is logic high. The stage circuits STG [D] to STG [j + 1] of FIG. 11 output the scan signal SCAN twice for one frame only if the scan signal SCAN is controlled to be k clock signals .

17 is a diagram showing the configuration of a clock signal according to the first embodiment, and FIG. 18 is a timing chart of the duty control operation according to the embodiment of FIG. 17, FIG. 19 is a diagram showing a configuration of a clock signal according to the second embodiment, and FIG. 20 is a diagram showing a configuration of a gate driving circuit according to a second embodiment of FIG. 19 And a Q-node potential and an output waveform of the gate driving circuit according to FIG.

According to the embodiment of the present invention, the scan signal SCAN and the carry signal CAR are controlled by k clock signals and the clock signal SEN is controlled by 2k clock signals, as in the experimental examples . In other words, the clock signal line for outputting the sensing signal SEN is increased at least twice as compared with the experimental example, the scan signal SCAN is output twice in one frame, and the sensing signal SEN is output only once. .

To this end, as shown in FIG. 16, the embodiment of the present invention is configured so that the stage circuits STG [D] of FIG. 11 are formed based on the start signals VST1 and VST2 occurring at least twice during one frame, To STG [j + 1]. The first and second start signals VST1 and VST2 have at least two logic highs during one frame. A data programming period for normally applying a data voltage and a black data insertion period for applying black data make a timing difference by (2x + 1) k. Here, since (2x + 1) k is a multiple of k, the scan signal SCAN and the carry signal CAR operate in the same manner, but the sensing signal SEN is not a multiple of 2k, so only one of the two regions is outputted. As described above, the emission duty (light emission time) for one frame is adjusted by the time difference of the start signal VST.

According to the first embodiment, the stage circuits STG [D] to STG [j + 1] of Fig. 11 are switched on the basis of the first to eighth clock signals CLK1 to CLK8 of the eighth phase in Fig. As a result of the operation, the result as shown in FIG. 18 was obtained.

According to the first embodiment, the stage circuits STG [D] to STG [j + 1] of FIG. 11 are provided with the scan signals CLK1 to CLK4 on the basis of the first to fourth clock signals CLK1 to CLK4 of four phases, The scan signal SCAN and the carry signal CAR are generated and the sensing signal SEN is generated based on the first to eighth clock signals CLK1 to CLK8 of eight phases. Accordingly, the stage circuits STG [D] to STG [j + 1] of Fig. 11 are turned on during the charge period in which the Q node Q keeps the logic high, the scan signals SCAN, And outputs a signal CAR. At this time, the first scan pulse Pa1 and the second scan pulse Pa2 are outputted with the start signals VST1 and VST2 inputted only twice as the scan signal SCAN as shown in FIG.

On the other hand, in the first embodiment, the stage circuits STG [D] to STG [j + 1] are arranged in such a manner that the outputs of the stage circuits arranged two stages below (n + 2) As input. As shown in FIG. 17, each of the first to eighth clock signals CLK1 to CLK8 of the eight phases has an area in which some sections are sequentially superimposed. 1, 2, 3, 4, 5, 6, 7, 8, ... in the first through eighth clock signals CLK1 through CLK8 denote the order in which logic high occurs in the clock signal. VST means the start signal. In the seventh and eighth clock signals CLK7 and CLK8, DMY means that a logic high is generated as a dummy. On the other hand, although only one VST is shown, it is generated twice in one frame. And although not shown, a reset signal such as RESET occurs at a logic high at the point where the last dummy logic high falls to the falling edge.

According to the second embodiment, the stage circuits STG [D] to STG [j + 1] of FIG. 11 are switched on the basis of the first to twelfth clock signals CLK1 to CLK12 of the twelfth phase of FIG. As a result of the operation, the output result as shown in FIG. 20 was obtained.

The stage circuits STG [D] to STG [j + 1] of FIG. 11 are provided with the scan signals CLK1 to CLK6 based on the first to sixth clock signals CLK1 to CLK6 of six phases, The scan signal SCAN and the carry signal CAR are generated and the sensing signal SEN is generated based on the first to twelfth clock signals CLK1 to CLK12 of 12 phases. Accordingly, the stage circuits STG [D] to STG [j + 1] of Fig. 11 are turned on during the charge period in which the Q node Q keeps the logic high, the scan signals SCAN, And outputs a signal CAR. At this time, the first scan pulse Pa1 and the second scan pulse Pa2 are outputted with the start signals VST1 and VST2 inputted only twice as the scan signal SCAN as shown in FIG.

On the other hand, in the second embodiment, the stage circuits STG [D] to STG [j + 1] are arranged in such a manner that the output of the stage circuit arranged three stages below (n + 3) As input. As shown in FIG. 20, the first to twelfth clock signals CLK1 to CLK12 of the 12 phases each have an area in which some sections are sequentially superimposed. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 ... in the first to twelfth clock signals CLK1 to CLK12, . VST means the start signal. In the tenth to twelfth clock signals CLK10 to CLK12, DMY means that a logic high has occurred as a dummy. On the other hand, although only one VST is shown, it is generated twice in one frame. And although not shown, a reset signal such as RESET occurs at a logic high at the point where the last dummy logic high falls to the falling edge.

Hereinafter, the connection method of the clock signal lines according to the embodiments will be described.

FIG. 21 is a view for explaining a connection method of a clock signal line according to the first experimental example, FIG. 22 is a view for explaining a connection method of a clock signal line according to the first embodiment, FIG. 23 is a cross- FIG. 24 is a view for explaining a connection method of a clock signal line according to an example. FIG. 24 illustrates a connection method of a clock signal line according to the second embodiment. 21 to 24, Line denotes one stage circuit for driving one horizontal pixel line. For example, Line 1 becomes the first stage circuit for driving the first horizontal pixel line, and Line 1100 becomes the 1100th stage circuit for driving the 1100th horizontal pixel line.

21, the scan signal generation unit Scan, the sensing signal generation unit Sense, and the carry signal generation unit (Carry) included in the stage circuits of the first experimental example are all four phase 1 to the fourth clock signals CLK1 to CLK4. That is, the stage circuits of the first experimental example are all connected to the clock signal lines of the same four phases. Since all of the first experimental examples operate on the basis of the four clock signals CLK1 to CLK4, there is a period in which the Q node can not be made logic high. Therefore, the first experimental example can not output the scan signal in the same manner as the present invention.

As shown in FIG. 22, the scan signal generating unit Scan and the carry signal generating unit Carry included in the stage circuits of the first embodiment generate first to fourth clock signals CLK1 to CLK4 of four phases, And the sensing signal generator Sense operates based on the first to eighth clock signals CLK1 to CLK8 of eight phases. That is, the stage circuits of the first embodiment are connected to clock signal lines of four phases and clock signal lines of eight phases. Since the first embodiment operates based on the clock signals CLK1 to CLK4 of four phases and the clock signals CLK1 to CLK8 of eight phases, there is no period in which the Q node can not be made logic high Do not. Therefore, the first embodiment can output a scan signal in the same manner as the present invention.

23, the scan signal generation unit Scan, the sensing signal generation unit Sense, and the carry signal generation unit (Carry) included in the stage circuits of the second experimental example are all formed in six phases 1 to the sixth clock signals CLK1 to CLK6. That is, the stage circuits of the second experimental example are all connected to the clock signal lines of the same six phases. The second experimental example operates on the basis of the six clock signals CLK1 to CLK6, so that there is a period in which the Q node can not be made logic high. Therefore, the second experimental example can not output the scan signal in the same manner as the present invention.

As shown in FIG. 24, the scan signal generating unit Scan and the carry signal generating unit included in the stage circuits of the second embodiment include first through sixth clock signals CLK1- And the sensing signal generator Sense operates based on the first to twelfth clock signals CLK1 to CLK12 of 12 phases. That is, the stage circuits of the second embodiment are connected to the clock signal lines of six phases and the clock signal lines of twelve phases. The first embodiment operates based on the six clock signals CLK1 to CLK6 and the twelve phase clock signals CLK1 to CLK12 so that there is no period in which the Q node can not be made logic high Do not. Therefore, the second embodiment can output a scan signal in the same manner as the present invention.

On the other hand, in the first and second embodiments, the start signal and the clock signal for generating the first and second scan pulses in one scan signal SCAN based on the first and second experimental examples The present invention is not limited to this. That is, according to the present invention, black data can be written by generating two scan pulses in one scan signal (SCAN) for one frame without adding a separate circuit. For this purpose, the start signal and the clock signal To be set. For example, the present invention can be achieved only by changing the start signal without necessarily setting the clock signals as in the embodiments. Therefore, it should be understood that the present invention is most widely started from the configuration of the start signal for writing black data in the implementation of the gate driving circuit.

As shown in the first and second embodiments, the scan signal generating unit for generating scan signals has M (M is an integer of 4 or more) clock signal lines, and generates a sensing signal for generating a sensing signal The part has N clock signal lines (N is an integer of 2 or more or a fraction) * M (M is an integer of 4 or more). Two or more fractions of the value of N are fractions whose numerator is greater than two times the denominator. And N * M must be an integer.

The present invention has the effect of easily controlling the scan signal or the non-emission period in which the emission of light is stopped for one frame by appropriately controlling the scan signal or the scan signal and the sensing signal without having to program the black data capable of turning off the drive TFT . Further, the present invention eliminates the need to write black data for duty driving, thereby preventing an increase in power consumption due to black data writing. Further, the present invention eliminates the necessity of further providing a light emission control TFT for duty driving, and can change the gate drive circuit, so that the structure of the pixel is simplified, and luminance distortion due to the operation of the light emission control TFT is also prevented .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the appended claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
15: Data line 16: Reference line
17: first gate line 18: second gate line
VST: Start signal SCAN: Scan signal
SEN: sensing signal CAR: carry signal
Pa1: first scan pulse Pa2: second scan pulse

Claims (10)

A display panel having a light emitting diode and a plurality of pixels each having a drive TFT for controlling a drive current flowing in the light emitting diode according to a voltage between the gate node and the source node and connected to the data line, the reference line and the gate line;
A data driving circuit for supplying a data voltage to the data line and supplying a reference voltage to the reference line; And
And a gate driving circuit for generating a scan signal synchronized with the data voltage and a sensing signal synchronized with the reference voltage and supplying the generated sensing signal to the gate line,
The gate drive circuit
And a scan signal including a first scan pulse synchronized with a first data voltage applied during a light emission period for one frame and a second scan pulse synchronized with a second data voltage applied during a non-light emission period. The method according to claim 1,
The gate drive circuit
And outputs the scan signal including the first scan pulse and the second scan pulse based on a start signal generated at least two logic highs during one frame. 3. The method of claim 2,
Wherein a period during which the first scan pulse and the second scan pulse are generated is variable. The method according to claim 1,
The second scan pulse
Wherein the first scan pulse is applied with a time difference after the first scan pulse is applied. The method according to claim 1,
The gate drive circuit
A scan signal generating unit having M clock signal lines for generating the scan signal; M (N is an integer or a fraction of 2 or more) * M (N is an integer or a fraction of 2) clock signal lines for generating the sensing signal; (M is an integer of 4 or more). 6. The method of claim 5,
And clock signals applied through the clock signal lines each have an area in which some sections overlap. The method according to claim 1,
The gate drive circuit
And outputs a sensing signal including a first sensing pulse synchronized with the first scan pulse. Stage circuits for outputting a scan signal including a first scan pulse and a second scan pulse for one frame,
The scan signal
A gate drive circuit that is generated based on a start signal that occurs at least two logic highs during a frame. 9. The method of claim 8,
Wherein a period during which the first scan pulse and the second scan pulse are generated is variable. 9. The method of claim 8,
A scan signal generating unit having M clock signal lines for generating the scan signal; M (N is an integer or a fraction of 2 or more) * M (N is an integer or a fraction of 2) clock signal lines for generating the sensing signal; (M is an integer of 4 or more).

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