KR102601780B1 - Light emitting display apparatus - Google Patents

Abstract

A light emitting display device according to the present specification includes a light emitting display panel including a plurality of data lines and pixels disposed in pixel areas defined by first to mth gate line groups, and a light emitting display panel disposed in the light emitting display panel and including first to mth gate line groups. It includes a gate driving circuit that drives the gate line group in a normal driving mode or a low-speed driving mode, wherein the gate driving circuit drives the first to m-th gates during the N (N is a natural number) unit of a plurality of unit times in the low-speed driving mode. Some of the gate line groups among the line groups may be driven, and the remaining gate line groups among the first to mth gate line groups may be driven for an (N+1)th unit time.

Description

Light emitting display device {LIGHT EMITTING DISPLAY APPARATUS}

This specification relates to a light emitting display device.

In addition to display devices for televisions and monitors, light emitting display devices are widely used as display screens for laptop computers, tablet computers, smart phones, smart watches, portable display devices, and portable information devices. Light-emitting display devices are attracting attention as next-generation display devices because they display images using self-luminous elements, have high-speed response speeds, low power consumption, and do not have problems with viewing angles.

Recently, light emitting display devices have been applied with a variable refresh rate driving method (or low-speed driving method) that can reduce power consumption when displaying images with little change in gradation between frames, such as still images. Research and development is in progress.

A variable refresh rate driven light emitting display device is driven by a refresh period (or refresh frame) that updates the image within a plurality of frames and a hold period (or hold frame) that continuously displays the updated image. As a result, the image is updated at a low speed, which can reduce power consumption. For example, when the driving frequency of the light emitting display device is 60Hz, the image is updated during the first frame among the first to 60 frames constituting 1 second, and the same image updated during the remaining 2nd to 60th frames is updated. Images can be displayed continuously.

However, in a light emitting display device driven by a variable refresh rate method, viewing characteristics may deteriorate due to a flicker phenomenon occurring due to a luminance difference between the refresh period and the hold period.

The content of the background technology described above is technical information that the inventor of this specification possessed to derive examples of this specification or acquired in the process of deriving examples of this specification, and must be disclosed to the general public prior to filing an application for this specification. It cannot be said to be publicly known technology.

The object of this specification is to provide a light emitting display device that can minimize the flicker phenomenon that occurs when driving at low speeds.

In addition to the tasks of the present specification mentioned above, other features and advantages of the present specification are described below, or can be clearly understood by those skilled in the art from such descriptions and descriptions. will be.

A light emitting display device according to the present specification includes a light emitting display panel including a plurality of data lines and pixels disposed in pixel areas defined by first to mth gate line groups, and a light emitting display panel disposed in the light emitting display panel and including first to mth gate line groups. It includes a gate driving circuit that drives the gate line group in a normal driving mode or a low-speed driving mode, wherein the gate driving circuit drives the first to m-th gates during the N (N is a natural number) unit of a plurality of unit times in the low-speed driving mode. Some of the gate line groups among the line groups may be driven, and the remaining gate line groups among the first to mth gate line groups may be driven for an (N+1)th unit time.

The light emitting display device according to the present specification can minimize the flicker phenomenon that occurs when driven at low speeds.

In addition to the effects of the present specification mentioned above, other features and advantages of the present specification are described below, or can be clearly understood by those skilled in the art from such descriptions and descriptions.

1 is a diagram showing a light emitting display device according to an example of the present specification.
Figure 2 is a diagram showing a method of driving a gate line group in the normal driving mode of the gate driving circuit according to the present specification.
3A and 3B are diagrams showing a method of driving a gate line group in a low-speed driving mode of the gate driving circuit according to the present specification.
FIGS. 4A and 4B are diagrams showing images updated on a light emitting display panel according to a low-speed driving mode in a light emitting display device according to the present specification.
FIG. 5 is an equivalent circuit diagram according to an example of the pixel shown in FIG. 1.
FIG. 6 is a waveform diagram showing a signal according to a first example supplied to the pixel shown in FIG. 5.
FIG. 7 is a waveform diagram showing a signal according to a second example supplied to the pixel shown in FIG. 5.
FIG. 8 is a waveform diagram showing a signal according to a third example supplied to the pixel shown in FIG. 5.
FIG. 9 is a waveform diagram showing a signal according to a fourth example supplied to the pixel shown in FIG. 5.
FIG. 10 is a waveform diagram showing a signal according to a fifth example supplied to the pixel shown in FIG. 5.
FIG. 11 is a waveform diagram showing a modified example of the signal according to the fifth example shown in FIG. 10.
FIG. 12 is a waveform diagram showing another modified example of the signal according to the fifth example shown in FIG. 10.
13 is a diagram showing a gate driving circuit according to the present specification.
FIG. 14 is a diagram showing the first stage block, first transistor unit, and first switching unit shown in FIG. 13.
FIG. 15 is a diagram illustrating a comparison between the luminance drop width of a light-emitting display device driven in a low-speed drive mode of the interlace driving method according to an example of the present specification and the luminance drop width of a light-emitting display device driven in a low-speed drive mode according to a comparative example. am.
FIG. 16 is a diagram showing a comparison between the pixel charging time of a light-emitting display device driven in a low-speed drive mode according to an example of the present specification and the pixel charging time of a light-emitting display device driven in a low-speed drive mode according to a comparative example.

The advantages and features of the present specification and methods for achieving them will become clear by referring to examples described in detail below along with the accompanying drawings. However, the present specification is not limited to the examples disclosed below and will be implemented in various different forms, and only the examples of the present specification ensure that the disclosure of the present specification is complete and will be used in the technical field to which the technical idea of the present specification pertains. It is provided to fully inform those skilled in the art of the scope of the technical idea of the present specification, and examples of the present specification are only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining an example of the present specification are illustrative and are not limited to the matters shown in the drawings of the present specification. Like reference numerals refer to like elements throughout the specification. Additionally, when describing examples of the present specification, if it is determined that detailed descriptions of related known technologies may unnecessarily obscure the gist of the present specification, the detailed descriptions will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical idea of the present specification.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, “at least one of the first, second, and third items” means each of the first, second, or third items, as well as two of the first, second, and third items. It can mean a combination of all items that can be presented from more than one.

Each feature of the various examples of the present specification can be partially or entirely combined or combined with each other, and various technological interconnections and operations are possible, and each example can be implemented independently of each other or together in a related relationship. .

Hereinafter, a preferred example of a light emitting display device according to the present specification will be described in detail with reference to the attached drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, the scale of the components shown in the attached drawings has a different scale from the actual scale for convenience of explanation, and is therefore not limited to the scale shown in the drawings.

1 is a diagram showing a light emitting display device according to an example of the present specification.

Referring to FIG. 1 , a light emitting display device according to an example of the present specification may include a light emitting display panel 100, a timing control unit 300, a data driving circuit 500, and a gate driving circuit 700.

The light emitting display panel 100 may include a display area (AA) (or active area) defined on a substrate, and a non-display area (IA) (or inactive area) surrounding the display area (AA).

The display area AA may include a plurality of pixels P disposed in a pixel area defined by the intersection of the first to m gate line groups GLG1 to GLGm and the plurality of data lines DL1 to DLn. there is.

Each of the first to m gate line groups (GLG1 to GLGm) may include a plurality of gate lines arranged to be spaced apart from each other on the substrate. For example, each of the first to m gate line groups (GLG1 to GLGm) may include first to fourth gate lines.

Each of the plurality of data lines DL1 to DLn may be arranged on the substrate to be spaced apart from each other and intersect the first to mth gate line groups GLG1 to GLGm.

According to one example, each of the plurality of pixels P may be a red pixel, a green pixel, or a blue pixel. In this case, adjacent red pixels, green pixels, and blue pixels may implement one unit pixel.

According to one example, each of the plurality of pixels P may be a red pixel, a green pixel, a blue pixel, or a white pixel. In this case, adjacent red pixels, green pixels, blue pixels, and white pixels may implement one unit pixel for displaying one color image.

The plurality of pixels P may be implemented in a stripe structure or a pentile structure on the display area AA.

One unit pixel implemented in a pentile structure may include at least one red pixel, at least one green pixel, and at least one blue pixel arranged two-dimensionally in a polygonal shape. For example, a unit pixel with a pentile structure may have one red pixel, two green pixels, and one blue pixel arranged in an octagonal shape, in which case the blue pixel has the largest size. and the green pixel can have the smallest size.

Each of the plurality of pixels P emits light based on a light emitting device and a plurality of gate signals supplied from adjacent gate line groups (GLG1 to GLGm) and data voltages supplied from adjacent data lines (DL1 to DLn). May include pixel circuitry.

The non-display area (IA) may be provided along the edge of the substrate to surround the display area (AA). One non-display area of the non-display area (IA) may include a pad portion provided on the substrate and connected to a plurality of data lines DL1 to DLn.

The timing control unit 300 aligns the input image data (Idata) to suit the operation of the light emitting display panel 100 to generate digital data (Pdata) for each pixel, and data based on the input timing synchronization signal (TSS). A control signal (DCS) can be generated and provided to the data driving circuit 500.

The timing control unit 300 may generate a gate control signal (GCS) including a start signal and a plurality of shift clock signals based on the timing synchronization signal (TSS) and provide the gate control signal (GCS) to the gate driving circuit 700.

The timing control unit 300 may generate a mode control signal (MCS) for driving the gate driving circuit 700 in a normal driving mode or a low-speed driving mode and provide the mode control signal (MCS) to the gate driving circuit 700. For example, normal mode may be a progressive driving mode (or sequential driving mode). The low-speed driving mode may be a variable refresh rate driving mode. Additionally, the low-speed driving mode may be a variable refresh rate driving mode using an interlace driving method.

The timing control unit 300 according to an example analyzes image data (Idata) of one frame image to determine whether the input image is a video or a still image, and when the input image is a video, a mode control signal (MCS) for the normal driving mode is used. ) and can generate a mode control signal (MCS) for low-speed driving mode when the input image is a still image. For example, when the input image does not change for a plurality of frames, the timing controller 300 may determine the input image to be a still image and generate a mode control signal (MCS) for the low-speed driving mode.

The data driving circuit 500 may be connected to a plurality of data lines DL1 to DLn provided in the light emitting display panel 100. The data driving circuit 500 according to an example uses pixel-specific digital data (Pdata) and data control signal (DCS) provided from the timing control unit 300 and a plurality of reference gamma voltages provided from the power supply to provide pixel-specific digital data (Pdata). The data Pdata may be converted into an analog data voltage for each pixel, and the converted data voltage for each pixel may be supplied to the corresponding data lines DL1 to DLn.

Optionally, the data driving circuit 500 according to an example may generate a dummy data voltage for each pixel immediately before supplying the original data voltage for each pixel and supply it to the corresponding data lines DL1 to DLn. For example, the data driving circuit 500 may supply dummy data voltages for each pixel to the corresponding data lines DL1 to DLn during the blank period between horizontal periods according to the interlace driving method in the low-speed driving mode of the interlace driving method. You can. In this case, the timing control unit 300 may generate dummy digital data for each pixel based on the original digital data for each pixel. For example, dummy digital data for each pixel may have a higher grayscale value than the corresponding original digital data for each pixel.

The gate driving circuit 700 may be disposed in the non-display area (IA) of the light emitting display panel 100 and electrically connected to the first to mth gate line groups (GLG1 to GLGm). For example, the gate driving circuit 700 may be integrated on one edge or both edges of the substrate depending on the manufacturing process of the thin film transistor and connected one-to-one with the first to mth gate line groups (GLG1 to GLGm). Alternatively, the gate driving circuit 700 may be configured as an integrated circuit and mounted on a substrate or on a flexible circuit film and connected one-to-one with the first to mth gate line groups (GLG1 to GLGm).

The gate driving circuit 700 operates the first to m gate line groups (GLG1 to GLGm) in normal driving mode or low speed based on the gate control signal (GCS) and mode control signal (MCS) supplied from the timing controller 300. It can be driven in drive mode.

The gate driving circuit 700 according to an example may sequentially drive the first to mth gate line groups GLG1 to GLGm in a normal driving mode according to the mode control signal MCS. For example, the gate driving circuit 700 according to the normal driving mode operates the first to mth gate line groups (GLG1 to GLGm) for each of 60 frames of 1/60 second based on a driving frequency of 60Hz. can be driven sequentially. In other words, the gate driving circuit 700 according to the normal driving mode sequentially operates the 1st to mth gate line groups (GLG1 to GLGm) in each of the 1st to 60th frames included within a unit time of 1 second. It can be driven with .

The gate driving circuit 700 according to an example may drive the first to mth gate line groups GLG1 to GLGm according to an interlace driving method in a low-speed driving mode according to the mode control signal MCS. For example, the gate driving circuit 700 according to the low-speed driving mode operates the first to mth gate line groups (GLG1 to GLGm) for each refresh period of 1/60 second based on a driving frequency of 1 Hz. can be driven sequentially according to the interlace driving method.

In an interlace driving low-speed driving mode, the gate driving circuit 700 according to an example operates the first to mth refresh frames of the Nth unit time (N is a natural number) among a plurality of unit times having a refresh frame and a hold frame. Some of the gate line groups (GLG1 to GLGm) can be driven, and the remaining gate line groups among the first to m gate line groups (GLG1 to GLGm) can be driven during the refresh frame of the N+1th unit time. there is. The unit time may be 1 second, and within the unit time, the refresh frame time may be shorter than the hold frame time. As an example, when the gate driving circuit 700 according to the low-speed driving mode is driven based on a driving frequency of 1 Hz, the time of the refresh frame may be set to 0 second to 1/60 second. , the time of the hold frame can be set to 1/60 second to 1 second following the refresh frame. As another example, taking the driving frequency of 60Hz as an example, the refresh frame may correspond to the first frame among the first to 60th frames consisting of 1/60 second, and the hold frame may correspond to the 2nd to 60th frames. can be responded to.

The gate driving circuit 700 according to the low-speed driving mode may sequentially drive only a portion of the first to mth gate line groups (GLG1 to GLGm) for each refresh frame according to the interlace driving method. For example, the gate driving circuit 700 according to the low-speed driving mode of the interlace driving method operates the odd gate line group (GLG1, GLG3, ... GLGm-1) are sequentially driven, and even-numbered gate line groups (GLG2, GLG4, ... GLGm) among the first to m gate line groups (GLG1 to GLGm) during the refresh frame of the N+1th unit time. can be driven sequentially.

Additionally, the light emitting display device according to the present specification may further include a power circuit 900.

Based on the input power (Vin), the power circuit 900 generates a pixel driving voltage (EVdd), a pixel common voltage (EVss), an initialization voltage (EVini), a stage driving voltage (GVdd), and a stage common voltage (GVss), respectively. can be generated and provided to the light emitting display panel 100. For example, the power circuit 900 may supply each of the pixel driving voltage (EVdd), the pixel common voltage (EVss), and the initialization voltage (EVini) to the pixels (P). Additionally, the power circuit 900 may supply each of the stage driving voltage (GVdd) and the stage common voltage (GVss) to the gate driving circuit 700.

As such, the light emitting display device according to the present specification can be driven in a normal driving mode or a low-speed driving mode depending on the input image, and power consumption can be reduced by the low-speed driving mode. In addition, the light emitting display device according to the present specification updates the image displayed on the light emitting display panel 100 through refresh frames at each N-th and N+1-th unit time according to the interlace driving method in the low-speed driving mode, thereby refreshing the image in the refresh frame. As the luminance drop rate is reduced, the flicker phenomenon that occurs in low-speed driving mode can be minimized.

Figure 2 is a diagram showing a method of driving a gate line group in the normal driving mode of the gate driving circuit according to the present specification.

Referring to Figures 1 and 2, the gate driving circuit 700 according to the present specification operates within a unit time of 1 second (1 second) in the normal driving mode according to the mode control signal (MCS) supplied from the timing control unit 300. A gate group driving signal is generated based on the gate control signal (GCS) supplied from the timing control unit 300 for each of the included frames (F1 to Fn) to the first to m gate line groups (GLG1 to GLGm). Can be supplied sequentially. For example, when a light emitting display device is driven according to a driving frequency of 60 Hz, the gate driving circuit 700 according to the normal driving mode performs timing in each of the 1st to 60th frames included within a unit time of 1 second. Based on the gate control signal (GCS) supplied from the control unit 300, a gate group driving signal of the on voltage level (Von) may be generated and sequentially supplied to the first to mth gate line groups (GLG1 to GLGm). As such, when the gate driving circuit 700 is driven in the normal driving mode, the image displayed on the light emitting display panel 100 is updated for each of the plurality of frames (F1 to Fn) included within a unit time (1 second). You can.

3A and 3B are diagrams showing a method of driving a gate line group in a low-speed driving mode of the gate driving circuit according to the present specification.

Referring to FIGS. 1, 3A, and 3B, the gate driving circuit 700 according to the present specification operates in a low-speed driving mode according to the mode control signal (MCS) supplied from the timing control unit 300. A gate group driving signal with an on voltage level (Von) can be generated based on the gate control signal (GCS) supplied from and sequentially supplied to some of the first to mth gate line groups (GLG1 to GLGm). For example, the gate driving circuit 700 according to the low-speed driving mode generates a gate group driving signal of the on voltage level (Von) according to an interlace driving method based on a unit time of 1 second to drive the first to mth gate lines. It can be supplied to groups (GLG1 to GLGm).

According to one example, the gate driving circuit 700 according to the low-speed driving mode of the interlace driving method, as shown in FIG. 3A, the timing controller 300 in the refresh frame (Fr) of the Nth unit time (N second) A gate group driving signal of the on voltage level (Von) is generated based on the gate control signal (GCS) supplied from the odd gate line group (GLG1, GLG3, …can be supplied sequentially to GLGm-1). As such, when the gate driving circuit 700 is driven in the low-speed driving mode of the interlace driving method, the image displayed on the odd-numbered horizontal line among the images displayed on the light-emitting display panel 100 lasts for the Nth unit time (N second). It may be updated in the refresh frame (Fr) and maintained during the hold frame (Fh). For example, the image displayed on the odd-numbered horizontal line of the light emitting display panel 100 may be updated every 2 seconds.

In addition, the gate driving circuit 700 according to the low-speed driving mode of the interlace driving method, as shown in FIG. 3B, operates the timing control unit 300 in the refresh frame (Fr) of the N+1th unit time (N+1 second). ) generates a gate group driving signal with an on-voltage level (Von) based on the gate control signal (GCS) supplied from , … can be supplied sequentially to GLGm). As such, when the gate driving circuit 700 is driven in the interlace driving low-speed driving mode, the image displayed on the even-numbered horizontal line among the images displayed on the light-emitting display panel 100 is the N+1th unit time (N +1 second) and can be updated in the refresh frame (Fr) and maintained during the hold frame (Fh). For example, the image displayed on the even-numbered horizontal line of the light emitting display panel 100 may be updated every 2 seconds. Accordingly, when the gate driving circuit 700 is driven in the low-speed driving mode of the interlace driving method, the image displayed on the light-emitting display panel 100 is a refresh frame (Fr) for each of the Nth unit time and the N+1th unit time. ) can be updated over time.

FIGS. 4A and 4B are diagrams showing images updated on a light emitting display panel according to a low-speed driving mode in a light emitting display device according to the present specification.

Referring to FIGS. 1, 3A, and 4A, in the light emitting display device according to the present specification, the gate driving circuit 700 performs the first refresh frame (Fr) of the N-th unit time (N second) according to the low-speed driving mode. A gate group driving signal is sequentially supplied to the odd-numbered gate line groups (GLG1, GLG3, ... GLGm-1) among the 1st to m-th gate line groups (GLG1 to GLGm), and the data driving circuit 500 supplies the odd-numbered gate line groups (GLG1 to GLGm-1). It is possible to supply a data voltage for each pixel that is synchronized with the gate group driving signal sequentially supplied to the groups (GLG1, GLG3, ... GLGm-1). Accordingly, among the images displayed on the light emitting display panel 100, the images displayed on the odd-numbered horizontal lines (A1, A3, ... Am-1) are updated in the refresh frame (Fr) of the Nth unit time (N second). It can be maintained during the hold frame (Fh). Here, the image displayed on the odd-numbered horizontal lines (A1, A3, ... Am-1) can be maintained until updated by the refresh frame (Fr) of the N+2th unit time.

Referring to FIGS. 1, 3B, and 4B, in the light emitting display device according to the present specification, the gate driving circuit 700 operates a refresh frame (N+1 second) of the N+1th unit time according to the low-speed driving mode. During Fr), the gate group driving signal is sequentially supplied to the even-numbered gate line groups (GLG2, GLG4, ... GLGm) among the first to m-th gate line groups (GLG1 to GLGm), and the data driving circuit 500 is connected to the even-numbered gate line groups (GLG1 to GLGm). It is possible to supply a data voltage for each pixel that is synchronized with the gate group driving signal sequentially supplied to the gate line groups (GLG2, GLG4, ... GLGm). Accordingly, among the images displayed on the light emitting display panel 100, the images displayed on the even-numbered horizontal lines (A2, A4, ... Am) are displayed in the refresh frame (Fr) of the N+1th unit time (N+1 second). It can be updated and maintained for a hold frame (Fh). Here, the image displayed on the even-numbered horizontal lines (A2, A4, ... Am) can be maintained until updated by the refresh frame (Fr) of the N+3th unit time.

FIG. 5 is an equivalent circuit diagram according to an example of the pixel shown in FIG. 1, which shows one pixel disposed on the ith horizontal line of the light emitting display panel.

Referring to FIGS. 1 and 5 , the pixel P according to the present specification may include a light emitting device (ELD) and a pixel circuit (PC).

The light emitting device (ELD) may emit white light or colored light with a predetermined brightness by emitting light in proportion to the size of the data current (idata) supplied from the pixel circuit (PC).

The light emitting device (ELD) according to one example includes a first electrode (or anode electrode) connected to the pixel circuit (PC) and a second electrode (or cathode electrode) connected to the pixel common power line (Lvss) (or low-potential power line). It may include a light emitting layer interposed therebetween. The light-emitting layer may include an organic light-emitting layer, a quantum dot light-emitting layer, an inorganic light-emitting layer, or a micro light-emitting diode.

The pixel circuit (PC) emits data current (idata) based on the data voltage (Vdata) supplied to the data line (DL) in response to the gate group driving signal applied to the gate line group (GLGi) from the gate driving circuit. By supplying light to the device (LED), the light emission of the light emitting device (LED) can be controlled.

The gate line group GLGi may include first to fourth gate lines GL1, GL2, GL3, and GL4. The gate group driving signal is supplied to the first gate driving signal GS1 (or initialization control signal) supplied to the first gate line GL1 (or initialization control line) and the second gate line GL2 (or scan control line). A second gate driving signal GS2 (or scan control signal) supplied, a third gate driving signal GS3 (or anode reset control signal) supplied to the third gate line GL3 (or anode reset control line), and a fourth gate driving signal GS4 (or light emission control signal) supplied to the fourth gate line GL4 (or light emission control line).

The pixel circuit (PC) according to one example may include a driving thin film transistor (Tdr), first to sixth transistors (T1, T2, T3, T4, T5, T6), and a storage capacitor (Cst).

According to one example, the thin film transistors (Tdr, T1, T2, T3, T4, T5, and T6) may be implemented as low-temperature poly-Si (LTPS) thin film transistors with excellent response characteristics. For example, the thin film transistors (Tdr, T1, T2, T3, T4, T5, T6) may be PMOS type LTPS thin film transistors.

According to another example, the thin film transistors (Tdr, T1, T2, T3, T4, T5, and T6) may be implemented as oxide thin film transistors with excellent off current characteristics. For example, the thin film transistors (Tdr, T1, T2, T3, T4, T5, T6) may be NMOS type oxide thin film transistors.

According to another example, at least one of the thin film transistors (Tdr, T1, T2, T3, T4, T5, T6) is implemented as an NMOS type oxide thin film transistor, and the remaining thin film transistors are implemented as PMOS type LTPS thin film transistors. It can be implemented. For example, the driving thin film transistor (Tdr) and the third, fourth, and sixth thin film transistors (T3, T4, and T6) are implemented as PMOS-type LTPS thin film transistors, and the first, second, and fifth thin film transistors are implemented as PMOS-type LTPS thin film transistors. (T1, T2, T5) can be implemented with an NMOS-type oxide thin film transistor.

The driving thin film transistor (Tdr) can control the data current (idata) flowing through the light emitting device (ELD). The driving thin film transistor Tdr according to an example includes a gate electrode connected to the first node N1, a first source/drain electrode connected to the second node N2, and a second source/drain electrode connected to the third node N3. It may include a drain electrode. This driving thin film transistor (Tdr) is turned on according to the voltage between the first node (N1) and the second node (N2) during the light emission period of the pixel (P), thereby generating the data current (idata) flowing in the light emitting device (ELD). can be controlled.

The first thin film transistor T1 may selectively connect the data line DL and the second node N2 in response to the second gate driving signal GS2 supplied to the second gate line GL2. The first thin film transistor T1 according to an example includes a gate electrode connected to the second gate line GL2, a first source/drain electrode connected to the data line DL, and a second source connected to the second node N2. /May include a drain electrode. This first thin film transistor T1 is turned on by the second gate driving signal GS2 at the transistor-on voltage level supplied to the second gate line GL2 during the sampling period of the pixel P, thereby driving the data line DL. ) can be supplied to the second node (N2).

The second thin film transistor T2 may selectively connect the first node N1 and the third node N3 in response to the second gate driving signal GS2 supplied to the second gate line GL2. The second thin film transistor T2 according to an example includes a gate electrode connected to the second gate line GL2, a first source/drain electrode connected to the first node N1, and a second electrode connected to the third node N3. It may include source/drain electrodes. This second thin film transistor T2 is turned on by the second gate driving signal GS2 at the transistor-on voltage level supplied to the second gate line GL2 during the sampling period of the pixel P, thereby driving the first node ( N1) and the third node (N3) are electrically connected, and through this, the driving thin film transistor (Tdr) is connected in the form of a diode.

The third thin film transistor T3 is connected to the pixel driving power line Lvdd (or high potential power line) and the second node N2 in response to the fourth gate driving signal GS4 supplied to the fourth gate line GL4. can be selectively connected. The third thin film transistor T3 according to an example includes a gate electrode connected to the fourth gate line GL4, a first source/drain electrode connected to the second node N2, and a first electrode connected to the pixel driving power line Lvdd. It may include 2 source/drain electrodes. This third thin film transistor T3 is turned on by the fourth gate driving signal GS4 at the transistor-on voltage level supplied to the fourth gate line GL4 during the emission period of the pixel P, thereby driving the pixel driving power line. The pixel driving voltage (EVdd) supplied from (Lvdd) may be supplied to the first source/drain electrodes of the driving thin film transistor (Tdr) through the second node (N2).

The fourth thin film transistor T4 may selectively connect the third node N3 and the fourth node N4 in response to the fourth gate driving signal GS4 supplied to the fourth gate line GL4. The fourth thin film transistor T4 according to an example includes a gate electrode connected to the fourth gate line GL4, a first source/drain electrode connected to the third node N3, and a second electrode connected to the fourth node N4. It may include source/drain electrodes. This fourth thin film transistor T4 is turned on by the fourth gate driving signal GS4 at the transistor-on voltage level supplied to the fourth gate line GL4 during the emission period of the pixel P, thereby forming the third node ( The data current Idata supplied from the driving thin film transistor Tdr through N3) may be supplied to the first electrode of the light emitting device ELD through the fourth node N4.

The fifth thin film transistor T5 may selectively connect the initialization power line Lvini and the first node N1 in response to the first gate driving signal GS1 supplied to the first gate line GL1. The fifth thin film transistor T5 according to an example includes a gate electrode connected to the first gate line GL1, a first source/drain electrode connected to the first node N1, and a second electrode connected to the initialization power line Lvini. It may include source/drain electrodes. This fifth thin film transistor T5 is turned on by the first gate driving signal GS1 at the transistor-on voltage level supplied to the first gate line GL1 during the initialization period of the pixel P, thereby generating the initialization power line ( The initialization power (Vini) supplied from Lvini may be supplied to the first node (N1).

The sixth thin film transistor T6 may selectively connect the initialization power line Lvini and the fourth node N4 in response to the third gate driving signal GS3 supplied to the third gate line GL3. The sixth thin film transistor T6 according to one example includes a gate electrode connected to the third gate line GL3, a first source/drain electrode connected to the fourth node N4, and a second electrode connected to the initialization power line Lvini. It may include source/drain electrodes. This sixth thin film transistor T6 is turned on by the third gate driving signal GS3 at the transistor-on voltage level supplied to the third gate line GL3 during the anode reset period of the pixel P, thereby initializing the power line. The initialization power (Vini) supplied from (Lvini) is supplied to the fourth node (N4), and through this, the voltage of the fourth node (N4) is discharged to the initialization power line (Lvini), thereby discharging the first voltage of the light emitting device (ELD). The voltage of the electrode can be reset.

The storage capacitor Cst may be connected between the pixel driving power line Lvdd and the first node N1.

Alternatively, each of the second and fifth thin film transistors T2 and T5 connected to the first node N1 may include a dual channel structure. That is, each of the second and fifth thin film transistors (T2, T5) is electrically connected to the gate electrode of the driving thin film transistor (Tdr), and therefore has a dual-channel structure to maintain the gate voltage of the driving thin film transistor (Tdr) constant. It can be implemented. According to the dual-channel structure, since the channel length is longer than that of the single-gate structure, the off-resistance increases and the off-state current decreases, thereby ensuring operational stability. For example, each of the second and fifth thin film transistors T2 and T5 may be implemented as at least two thin film transistors connected in series to be turned on simultaneously according to the corresponding gate driving signals GS1 and GS2.

FIG. 6 is a waveform diagram showing a signal according to a first example supplied to the pixel shown in FIG. 5.

Referring to FIGS. 5 and 6, the pixel P according to the first example of the present specification operates during the first to fourth periods (t1) in each frame according to the normal driving mode of the gate driving circuit or the refresh frame according to the low-speed driving mode. , t2, t3, t4).

The first period t1 may be an initialization period for initializing the first node N1. For example, the first period t1 may be set as a time corresponding to one horizontal period.

In the first period t1, the first gate driving signal GS1 supplied to the first gate line GL1 has an on voltage level Von, and the second to fourth gate lines GL2, GL3, and GL4 Each of the gate driving signals GS2, GS3, and GS4 supplied to each may have an off voltage level (Voff). Additionally, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1. Accordingly, during the first period t1, only the fifth thin film transistor T5 among the first to sixth thin film transistors T1, T2, T3, T4, T5, and T6 has the first gate at the on voltage level Von. By being turned on by the driving signal GS1, the voltage of the first node N1 is initialized through the turned-on fifth thin film transistor T5, and the first voltage level V1 supplied from the initialization power line Lvini is initialized. It can be initialized with voltage (EVini). In addition, the storage capacitor Cst has a pixel driving voltage EVdd supplied from the pixel driving power line Lvdd and a first voltage level supplied from the initialization power line Lvini through the turned-on fifth thin film transistor T5. It can be initialized with the voltage difference (EVdd-Vini) between the initialization voltages (EVini) having (V1).

The second period (t2) follows the first period (t1) and may be a sampling period in which the data voltage (Vdata) and the threshold voltage of the driving thin film transistor (Tdr) are stored in the storage capacitor (Cst). For example, the second period (t2) may be set to a time corresponding to one horizontal period.

In the second period t2, the second gate driving signal GS2 supplied to the second gate line GL2 has an on voltage level Von, and the first, third, and fourth gate lines GL1, Each of the gate driving signals GS1, GS3, and GS4 supplied to each of GL3 and GL4 may have an off voltage level (Voff). And, the data voltage Vdata is supplied to the data line DL. Additionally, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1. Accordingly, during the second period t2, only the first and second thin film transistors T1 and T2 among the first to sixth thin film transistors T1, T2, T3, T4, T5, and T6 are at the on voltage level (Von). ) is turned on by the second gate driving signal GS2. The voltage of the second node N2 is changed to the data voltage Vdata supplied from the data line DL through the turned-on first thin film transistor T1, and the driving thin film transistor Tdr is turned on to the data voltage Vdata. As the gate electrode N1 and the second source/drain electrode N3 are short-circuited by the thin film transistor T2, they are connected in the form of a diode, and as a result, the gate electrode and the first source/drain electrode of the driving thin film transistor Tdr are connected. A voltage difference equal to the threshold voltage of the driving thin film transistor (Tdr) may occur. In other words, a voltage level (Vdata-Vth) lower than the voltage level of the data voltage (Vdata) applied to the first source/drain electrode (N2) of the driving thin film transistor (Tdr) by the threshold voltage of the driving thin film transistor (Tdr). (For example, a data voltage in which the threshold voltage is compensated) may be applied to the gate electrode N1 of the driving thin film transistor Tdr, and the storage capacitor Cst may be applied to the gate electrode of the driving thin film transistor Tdr. The voltage (Vdata-Vth) can be maintained for a preset time.

The third period (t3) follows the second period (t2) and may be an anode reset period for discharging the voltage of the fourth node (N4). For example, the third period t3 may be set to a time corresponding to one horizontal period.

In the third period t3, the third gate driving signal GS3 supplied to the third gate line GL3 has an on voltage level Von, and the first, second, and fourth gate lines GL1, Each of the gate driving signals GS1, GS2, and GS4 supplied to each of GL2 and GL4 may have an off voltage level (Voff). Additionally, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1. Accordingly, during the third period t3, only the sixth thin film transistor T6 among the first to sixth thin film transistors T1, T2, T3, T4, T5, and T6 has the third gate at the on voltage level Von. It is turned on by the driving signal (GS3). Accordingly, the voltage of the fourth node N4 can be initialized to the initialization voltage EVini of the first voltage level V1 supplied from the initialization power line Lvini through the turned-on sixth thin film transistor T6. there is. In other words, in the third period (t3), the voltage of the fourth node (N4) or the voltage of the first electrode of the light emitting device (ELD) is input to the initialization power line (Lvini) through the turned-on sixth thin film transistor (T6). ) can be reset to the initialization voltage (EVini) of the first voltage level (V1).

The fourth period (t4) follows the third period (t3) and may be a light emission period in which the light emitting device (ELD) emits light. For example, in each frame of the normal driving mode, the fourth period (t4) may be set to the remaining period excluding the first to third periods (t1, t2, and t3). In addition, it may be set to the remaining period excluding the first to third periods (t1, t2, t3) in the refresh frame of the low-speed drive mode, but is not necessarily limited to this, and the fourth period (t4) is the hold period of the low-speed drive mode. It can also be set to a frame.

In the fourth period t4, the fourth gate driving signal GS4 supplied to the fourth gate line GL4 has an on voltage level Von, and the first to third gate lines GL1, GL2, and GL3 Each of the gate driving signals GS1, GS2, and GS3 supplied to each may have an off voltage level (Voff). Additionally, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1.

During the fourth period (t4), among the first to sixth thin film transistors (T1, T2, T3, T4, T5, T6), only the third and fourth thin film transistors (T3, T4) are at the turn-on voltage level (Von). 4 Turned on by the gate driving signal (GS4). Accordingly, the voltage of the second node N2 is changed to the pixel driving voltage EVdd supplied from the pixel driving power line Lvdd through the turned-on third thin film transistor T3, and the voltage of the first node N1 The voltage maintains the data voltage (Vdata-Vth) in which the threshold voltage of the driving thin film transistor (Tdr) is compensated by the storage capacitor (Cst), and the second source/drain electrodes of the driving thin film transistor (Tdr) are turned on. It can be connected to the first electrode of the light emitting device (ELD) through the fourth thin film transistor (T4).

Therefore, during the fourth period (t4), the driving thin film transistor (Tdr) has a voltage (EVdd-(Vdata-|Vth) obtained by subtracting the threshold voltage (Vth) from the gate-source voltage (EVdd-(Vdata-|Vth|)). |)-|Vth|) outputs a data current (idata) proportional to the square of ((EVdd-(Vdata-|Vth|)-|Vth|)2), and the data current output from the driving thin film transistor (Tdr) (idata) may be supplied to the light emitting device (ELD) through the turned-on fourth thin film transistor (T4). As a result, during the fourth period (t4), the data current (idata) flowing through the light emitting device (ELD) is not affected by the threshold voltage of the driving thin film transistor (Tdr), and as a result, the data current (idata) provided in each of the plurality of pixels (P) The threshold voltage deviation between the driving thin film transistors (Tdr) can be minimized.

As such, the method of driving the pixel P according to the first example of the present specification can compensate for the threshold voltage of the driving thin film transistor Tdr, and through this, the driving thin film transistor Tdr provided in each of the plurality of pixels P ) can minimize image quality degradation due to threshold voltage deviation between

FIG. 7 is a waveform diagram showing a signal supplied to the pixel shown in FIG. 5 according to a second example, which is a third period changed from the pixel driving method shown in FIG. 6.

Referring to FIGS. 5 and 7, the pixel P according to the second example of the present specification is in the first to fourth periods (t1, t2, t3, and t4) in the refresh frame according to the low-speed driving mode of the gate driving circuit. It can work.

Since each of the first period (t1) and the second period (t2) is substantially the same as the first period (t1) and the second period (t2) shown in FIG. 6, duplicate description thereof will be omitted.

The third period (t3) follows the second period (t2) and may be an anode voltage boost period that increases the voltage of the fourth node (N4). For example, the third period (t3) may be set as a time corresponding to one horizontal period.

In the third period t3, the third gate driving signal GS3 supplied to the third gate line GL3 has an on voltage level Von, and the first, second, and fourth gate lines GL1, Each of the gate driving signals GS1, GS2, and GS4 supplied to each of GL2 and GL4 may have an off voltage level (Voff). Additionally, the initialization voltage EVini supplied to the initialization power line Lvini may be changed to a second voltage level V2 that is higher than the first voltage level V1. Accordingly, during the third period t3, only the sixth thin film transistor T6 among the first to sixth thin film transistors T1, T2, T3, T4, T5, and T6 has the third gate at the on voltage level Von. It is turned on by the driving signal (GS3). Accordingly, the voltage of the fourth node N4 can be changed to the initialization voltage EVini of the second voltage level V2 supplied from the initialization power line Lvini through the turned-on sixth thin film transistor T6. there is. In other words, in the third period (t3), the voltage of the fourth node (N4) or the voltage of the first electrode of the light emitting device (ELD) is input to the initialization power line (Lvini) through the turned-on sixth thin film transistor (T6). ) is changed to the second voltage level (V2) of the initialization voltage (EVini) supplied from ), thereby preventing a decrease in luminance of the light emitting device (ELD) due to the initialization voltage (EVini). For example, during the third period (t3) of the refresh frame in the low-speed driving mode, the voltage of the fourth node (N4) increases from the first voltage level (V1) of the initialization voltage (EVini) to the second voltage level (V2). By doing so, the luminance of the light emitting device (ELD) is maintained without being lowered toward black, and as a result, the decrease in luminance of the light emitting device (ELD) occurring in the refresh frame of the low-speed driving mode can be prevented or minimized.

The fourth period (t4) is a light emission period that follows the third period (t3) and causes the light emitting element (ELD) to emit light. This is substantially the same as the fourth period (t4) shown in FIG. 6, so a duplicate description thereof is provided. Omit it.

As such, the method of driving the pixel P according to the second example of the present specification can compensate for the threshold voltage of the driving thin film transistor Tdr, and through this, the driving thin film transistor Tdr provided in each of the plurality of pixels P ) can minimize image quality degradation due to threshold voltage deviation between In addition, the method of driving the pixel P according to the second example of the present specification changes the initialization voltage EVini from the first voltage level V1 to the second voltage level V2 during the third period t3, thereby driving the pixel P at a low speed. A decrease in luminance of a light emitting device (ELD) occurring in a refresh frame in a driving mode can be prevented or minimized.

FIG. 8 is a waveform diagram showing a signal supplied to the pixel shown in FIG. 5 according to a third example, which is a change in the third period from the pixel driving method shown in FIG. 6.

Referring to FIGS. 5 and 8, the pixel P according to the third example of the present specification is in the first to fourth periods (t1, t2, t3, and t4) in the refresh frame according to the low-speed driving mode of the gate driving circuit. It can work.

Since each of the first period (t1) and the second period (t2) is substantially the same as the first period (t1) and the second period (t2) shown in FIG. 6, duplicate description thereof will be omitted.

The third period t3 follows the second period t2 and may be an anode voltage maintenance period for maintaining the voltage of the fourth node N4. For example, the third period (t3) may be set as a time corresponding to one horizontal period.

In the third period (t3), each of the gate driving signals (GS1, GS2, GS3, GS4) supplied to each of the first to fourth gate lines (GL1, GL2, GL3, and GL4) has an off voltage level (Voff). You can. Also, the initialization voltage EVini supplied to the initialization power line Lvini may be changed to the first voltage level V1. Accordingly, during the third period (t3), all of the first to sixth thin film transistors (T1, T2, T3, T4, T5, T6) receive the gate driving signals (GS1, GS2, GS3, It is turned off by GS4). Accordingly, the voltage of the fourth node N4 may be maintained without being discharged. In other words, in the third period t3, the voltage of the fourth node N4 or the voltage of the first electrode of the light emitting device ELD is not discharged according to the turn-off state of the sixth thin film transistor T6. By maintaining it as is, a decrease in luminance of the light emitting device (ELD) due to the initialization voltage (EVini) can be prevented. For example, during the third period (t3) of the refresh frame in the low-speed driving mode, the voltage of the fourth node (N4) is maintained without being discharged to the initialization voltage (EVini) of the first voltage level (V1), thereby causing the light emitting device ( The brightness of the ELD is maintained without decreasing toward black, and as a result, the decrease in brightness of the light emitting device (ELD) occurring in the refresh frame of the low-speed driving mode can be prevented or minimized.

The fourth period (t4) is a light emission period that follows the third period (t3) and causes the light emitting element (ELD) to emit light. This is substantially the same as the fourth period (t4) shown in FIG. 6, so a duplicate description thereof is provided. Omit it.

As such, the method of driving the pixel P according to the third example of the present specification can compensate for the threshold voltage of the driving thin film transistor Tdr, and through this, the driving thin film transistor Tdr provided in each of the plurality of pixels P ) can minimize image quality degradation due to threshold voltage deviation between In addition, in the method of driving the pixel P according to the third example of the present specification, the voltage of the first electrode of the light emitting device ELD is maintained as is during the third period t3, thereby causing light emission generated in the refresh frame of the low-speed driving mode. A decrease in luminance of the device (ELD) can be prevented or minimized.

FIG. 9 is a waveform diagram showing a signal supplied to the pixel shown in FIG. 5 according to a fourth example, which is a change in the second period from the pixel driving method shown in FIG. 6.

Referring to FIGS. 5 and 9, the pixel P according to the fourth example of the present specification is in the first to fourth periods (t1, t2, t3, t4) in the refresh frame according to the low-speed driving mode of the gate driving circuit. It can work.

Since the first period t1 is substantially the same as the first period t1 shown in FIG. 6, duplicate description thereof will be omitted.

The second period (t2) follows the first period (t1) and may be a sampling period in which the data voltage (Vdata) and the threshold voltage of the driving thin film transistor (Tdr) are stored in the storage capacitor (Cst). For example, the second period t2 may be set as a time corresponding to two horizontal periods.

In the second period t2, the second gate driving signal GS2 supplied to the second gate line GL2 has an on voltage level Von for two horizontal periods, and the first, third, and fourth gates Each of the gate driving signals GS1, GS3, and GS4 supplied to each of the lines GL1, GL3, and GL4 may have an off voltage level (Voff). Additionally, the data line DL may sequentially receive a dummy data voltage (Vdata) corresponding to the dummy digital data (DD) for each pixel and a real data voltage (Vdata) corresponding to the actual digital data (OD) for each pixel. . Additionally, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1.

The second period (t2) may be time divided into a 2-1 period (t2-1) and a 2-2 period (t2-2).

The 2-1 period (t2-1) is the first half of the second period (t2), and the dummy data voltage (Vdata) is supplied to the second node (N2) to charge the pixel (P). It may be defined as a dummy data charging period or a preliminary charging period, and the 2-2 period (t2-2) is the latter half of the second period (t2), and the actual data voltage (Vdata) is applied to the second node (N2). It may be defined as an actual data charging period or a main charging period during which the actual data voltage (Vdata) is supplied to the pixel (P).

The dummy data voltage (Vdata) may have a higher voltage level than the actual data voltage (Vdata). For example, when the actual digital data (OD) has a gray level value of 0 to 31, the dummy digital data (DD) has a gray level value that is higher than the actual digital data (OD) with a gray level value of 0 to 31 by a gray level value of 5. You can have When the actual digital data (OD) has a gray level value of 32 to 63, the dummy digital data (DD) may have a gray level value that is as high as a gray level value of 10 than the actual digital data (OD) with a gray level value of 32 to 63. . When the actual digital data (OD) has a gray level value of 64 to 127, the dummy digital data (DD) may have a gray level value that is as high as a gray level value of 15 than the actual digital data (OD) with a gray level value of 64 to 127. . When the actual digital data (OD) has a gray level value of 128 to 255, the dummy digital data (DD) may have a gray level value as high as a gray level value of 20 than the actual digital data (OD) with a gray level value of 128 to 255. , In this case, when the actual digital data (OD) has a gray level value of 235 or higher, the dummy digital data (DD) may have a gray level value of 255.

During the second period t2, only the first and second thin film transistors T1 and T2 among the first to sixth thin film transistors T1, T2, T3, T4, T5, and T6 are at the turn-on voltage level Von. 2 It is turned on for 2 horizontal periods by the gate driving signal (GS2). The driving thin film transistor (Tdr) is connected in the form of a diode as the gate electrode (N1) and the second source/drain electrode (N3) are short-circuited by the turned-on second thin film transistor (T2), which causes the driving thin film transistor ( A voltage difference equal to the threshold voltage of the driving thin film transistor (Tdr) may occur between the gate electrode of Tdr and the first source/drain electrode. In other words, a voltage level (Vdata-Vth) lower than the voltage level of the data voltage (Vdata) applied to the first source/drain electrode (N2) of the driving thin film transistor (Tdr) by the threshold voltage of the driving thin film transistor (Tdr). (For example, a data voltage in which the threshold voltage is compensated) may be applied to the gate electrode N1 of the driving thin film transistor Tdr, and the storage capacitor Cst may be applied to the gate electrode of the driving thin film transistor Tdr. The voltage (Vdata-Vth) can be maintained for a preset time.

For example, during the 2-1 period (t2-1) of the second period (t2), the voltage of the second node (N2) is supplied from the data line (DL) through the turned-on first thin film transistor (T1). The dummy data applied to the first source/drain electrode N2 is applied to the gate electrode of the driving thin film transistor Tdr connected in the form of a diode by the second thin film transistor T2 turned on by changing to the dummy data voltage Vdata. A voltage level (Vdata-Vth) that is lower than the voltage level of the data voltage (Vdata) by a threshold voltage of the driving thin film transistor (Tdr) may be applied. Accordingly, the storage capacitor Cst can store the dummy data voltage Vdata and the threshold voltage of the driving thin film transistor Tdr. For example, the storage capacitor Cst may store a voltage level (Vdata-Vth) that is lower than the voltage level of the dummy data voltage (Vdata) by a threshold voltage of the driving thin film transistor (Tdr).

During the 2-2 period (t2-2) of the second period (t2), the voltage of the second node (N2) is the actual data voltage supplied from the data line (DL) through the turned-on first thin film transistor (T1). The actual data voltage (Vdata) applied to the first source/drain electrode (N2) is applied to the gate electrode of the driving thin film transistor (Tdr) connected in the form of a diode by the second thin film transistor (T2) turned on by changing to (Vdata). ) A voltage level (Vdata-Vth) lower than the voltage level of the driving thin film transistor (Tdr) may be applied. Accordingly, the storage capacitor Cst can store a voltage level (Vdata-Vth) that is lower than the voltage level of the actual data voltage (Vdata) by the threshold voltage of the driving thin film transistor (Tdr), and the gate of the driving thin film transistor (Tdr) The voltage (Vdata-Vth) applied to the electrode can be maintained for a preset time.

Since each of the third period (t3) and the fourth period (t4) is substantially the same as the third period (t3) and the fourth period (t4) shown in FIG. 6, duplicate description thereof will be omitted.

In this way, the method of driving the pixel P according to the fourth example of the present specification can compensate for the threshold voltage of the driving thin film transistor Tdr, and through this, the driving thin film transistor Tdr provided in each of the plurality of pixels P ) can minimize image quality degradation due to threshold voltage deviation between In addition, the method of driving the pixel P according to the fourth example of the present specification includes a preliminary charging period (t2-) in which a dummy data voltage (Vdata) is applied before applying the actual data voltage (Vdata) during the second period (t2). 1) By shortening the charging time of the data voltage (Vdata) or implementing fast charging of the data voltage (Vdata), the luminance of the light emitting device (ELD) due to the slow charging of the data voltage generated in the refresh frame in low-speed driving mode Deterioration can be prevented or minimized.

Additionally, in the method of driving the pixel P according to the fourth example of the present specification, the initialization voltage EVini in the third period t3 is, as shown in FIG. 7, the first voltage level V1 ) can be changed to the second voltage level (V2). In this case, the method of driving the pixel P according to the fourth example of the present specification changes the initialization voltage EVini from the first voltage level V1 to the second voltage level V2 during the third period t3. It is possible to prevent or minimize the decrease in luminance of the light emitting device (ELD) that occurs in the refresh frame of the low-speed driving mode.

Optionally, in the method of driving the pixel P according to the fourth example of the present specification, in the third period t3, the first to sixth thin film transistors T1, T2, T3, T4, T5, and T6 are, As shown in FIG. 8, all of them can maintain the turn-off state. In this case, the method of driving the pixel P according to the fourth example of the present specification generates a refresh frame in the low-speed driving mode by maintaining the voltage of the first electrode of the light emitting device ELD during the third period t3. A decrease in luminance of a light emitting device (ELD) can be prevented or minimized.

FIG. 10 is a waveform diagram showing a signal according to a fifth example supplied to the pixel shown in FIG. 5.

Referring to FIGS. 5 and 10, the pixel P according to the fifth example of the present specification is used for the first to third periods (t1) in each frame according to the normal driving mode of the gate driving circuit or the refresh frame according to the low-speed driving mode. , t2, t3).

Since the first period t1 is substantially the same as the first period t1 shown in FIG. 6, duplicate description thereof will be omitted.

The second period (t2) follows the first period (t1) and is a sampling period for storing the data voltage (Vdata) and the threshold voltage of the driving thin film transistor (Tdr) in the storage capacitor (Cst) and the voltage of the fourth node (N4). It may be an anode reset period for discharging. For example, the second period (t2) may be set to a time corresponding to one horizontal period.

In the second period t2, the second gate driving signal GS2 supplied to the second gate line GL2 has an on voltage level Von, and the third gate driving signal supplied to the third gate line GL3 The signal GS3 may have an on voltage level (Von), and each of the gate driving signals GS1 and GS4 supplied to the first and fourth gate lines GL1 and GL4 may have an off voltage level (Voff). . And, the data voltage Vdata is supplied to the data line DL. Additionally, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1. Accordingly, during the second period (t2), the first and second thin film transistors (T1, T2) and the sixth thin film transistor (T1, T2, T3, T4, T5, T6) among the first to sixth thin film transistors (T1, T2, T3, T4, T5, T6) Only T6) is turned on by the gate driving signals GS2 and GS3 at the on voltage level Von. The voltage of the second node N2 is changed to the data voltage Vdata supplied from the data line DL through the turned-on first thin film transistor T1, and the driving thin film transistor Tdr is turned on the second thin film transistor T1. As the gate electrode N1 and the second source/drain electrode N3 are short-circuited by the thin film transistor T2, they are connected in the form of a diode, and as a result, the gate electrode and the first source/drain electrode of the driving thin film transistor Tdr are connected. A voltage difference equal to the threshold voltage of the driving thin film transistor (Tdr) may occur. In other words, a voltage level (Vdata-Vth) lower than the voltage level of the data voltage (Vdata) applied to the first source/drain electrode (N2) of the driving thin film transistor (Tdr) by the threshold voltage of the driving thin film transistor (Tdr). (For example, a data voltage with the threshold voltage compensated) may be applied to the gate electrode N1 of the driving thin film transistor Tdr, and the storage capacitor Cst may be applied to the gate electrode of the driving thin film transistor Tdr. The voltage (Vdata-Vth) can be maintained for a preset time.

And, during the second period t2, the voltage of the fourth node N4 is the initialization voltage of the first voltage level V1 supplied from the initialization power line Lvini through the turned-on sixth thin film transistor T6. It can be initialized with (EVini). In other words, in the third period (t2), the voltage of the fourth node (N4) or the voltage of the first electrode of the light emitting device (ELD) is input to the initialization power line (Lvini) through the turned-on sixth thin film transistor (T6). ) can be reset to the initialization voltage (EVini) of the first voltage level (V1).

The third period (t3) is a light emission period that follows the second period (t2) and causes the light emitting element (ELD) to emit light. This is substantially the same as the fourth period (t4) shown in FIG. 6, so a duplicate description thereof is provided. Omit it.

As such, the method of driving the pixel P according to the fifth example of the present specification may have the same effect as the method of driving the pixel P according to the first example of the present specification, and the second gate driving signal GS2 As the and third gate driving signals GS3 are implemented as the same signal, either the second gate line GL2 or the third gate line GL3 may be omitted, which may result in the structure of the pixel P and the gate The structure of the driving circuit can be simplified.

Additionally, in the method of driving the pixel P according to the fifth example of the present specification, the initialization voltage EVini in the second period t2 is, as shown in FIG. 11, the first voltage level V1 ) can be changed to the second voltage level (V2). In this case, the method of driving the pixel P according to the fifth example of the present specification changes the initialization voltage EVini from the first voltage level V1 to the second voltage level V2 during the third period t3. It is possible to prevent or minimize the decrease in luminance of the light emitting device (ELD) that occurs in the refresh frame of the low-speed driving mode.

Optionally, in the method of driving the pixel P according to the fifth example of the present specification, the second period (t2) is the 2-1 period (t2-1) and the 2-1st period (t2-1) as shown in FIG. 12. It can be time divided into 2 periods (t2-2). In this case, in the method of driving the pixel P according to the fifth example of the present specification, the second period t2 is substantially the same as the second period t2 shown in FIG. 9, so the duplicate description thereof is Omit it. Accordingly, the method of driving the pixel P according to the fifth example of the present specification includes a preliminary charging period (t2) in which the dummy data voltage (Vdata) is applied before applying the actual data voltage (Vdata) during the second period (t2). -1) By shortening the charging time of the data voltage (Vdata) or implementing fast charging of the data voltage (Vdata), the light emitting element (ELD) is damaged due to the slow charging of the data voltage generated in the refresh frame of the low-speed driving mode. Brightness degradation can be prevented or minimized.

FIG. 13 is a diagram showing a gate driving circuit according to the present specification, and is for explaining the gate driving circuit shown in FIG. 1.

Referring to FIGS. 1 and 13 , the gate driving circuit 700 according to the present specification may include a shift register 710 and a mode control circuit 730.

The shift register 710 may output gate group driving signals for driving each of the first to mth gate line groups (GLG1 to GLGm) in a predetermined order. For example, the shift register 710 converts the corresponding shift clock signal of the plurality of shift clock signals CLK1 to CLK8 supplied from each of the plurality of gate clock lines into a gate driving signal in response to the plurality of start signals Vst. Can be printed.

The shift register 710 according to one example may include first to mth stage blocks SB1 to SBm.

Each of the first to m stage blocks (SB1 to SBm) is selectively connected to the first to eighth gate clock lines, and the stage driving voltage line to which the stage driving voltage (GVdd) is supplied and the stage common voltage (GVss) are supplied. It can be commonly connected to each of the stage driving voltage lines. For example, some (or odd-numbered) stage blocks (SB1, SB3, ... SBm-1) of the first to m-th stage blocks (SB1 to SBm) are some (or odd-numbered) of the first to eighth gate clock lines. ) can be connected to the clock line. The remaining (or even-numbered) stage blocks (SB2, SB4, ... SBm) among the first to m-th stage blocks (SB1 to SBm) may be connected to the remaining (or even-numbered) clock lines among the first to eighth gate clock lines. there is.

According to one example, each of the first to eighth shift clock signals CLK1 to CLK8 individually supplied to each of the first to eighth gate clock lines may include an on-voltage period and an off-voltage period that are cyclically repeated at regular intervals. there is. The on voltage period may have a voltage level that can turn the transistor on, and the off voltage period may have a voltage level that can turn the transistor off.

Each of the on-voltage period and off-voltage period of the first and second shift clock signals CLK1 and CLK2 may correspond to one horizontal period in each of the normal driving mode and the low-speed driving mode. Each of the first and second shift clock signals CLK1 and CLK2 may be used to generate a first gate driving signal or a first scan signal to be supplied to the first gate line of the gate line group GLG.

Each of the on-voltage period and the off-voltage period of the third and fourth shift clock signals (CLK3 and CLK4) may correspond to 1 horizontal period in normal driving mode, and 1 horizontal period or 2 horizontal periods in low-speed driving mode. It can be. Each of these third and fourth shift clock signals CLK3 and CLK4 may be used to generate a second gate driving signal or a second scan signal to be supplied to the second gate line of the gate line group GLG. In the low-speed driving mode according to one example, the pixel P operates in the first to fourth periods (t1, t2, t3, and t4) shown in FIGS. 6 to 8 or in the first to fourth periods (t1, t2, t3, and t4) shown in FIGS. 10 and 11. When operating in the first to third periods (t1, t2, t3), each of the on-voltage period and the off-voltage period of the third and fourth shift clock signals (CLK3, CLK4) may correspond to one horizontal period. In a low-speed driving mode according to another example, the pixel P operates in the first to fourth periods (t1, t2, t3, and t4) shown in FIG. 9 or in the first to third periods (t1, t2, t3, and t4) shown in FIG. 12. When operating as t1, t2, and t3), each of the on-voltage period and off-voltage period of the third and fourth shift clock signals CLK3 and CLK4 may correspond to two horizontal periods.

Each of the on-voltage period and the off-voltage period of the fifth and sixth shift clock signals (CLK5 and CLK6) may correspond to 1 horizontal period in normal driving mode, and may correspond to 1 horizontal period or 2 horizontal periods in low-speed driving mode. It can be. Each of these fifth and sixth shift clock signals CLK5 and CLK6 may be used to generate a third gate driving signal or a third scan signal to be supplied to the third gate line of the gate line group GLG. In a low-speed driving mode according to an example, the pixel P operates in the first to fourth periods (t1, t2, t3, and t4) shown in FIGS. 6, 7, and 9, or in the first to fourth periods (t1, t2, t3, and t4) shown in FIGS. 10 and 11. When operating in the illustrated first to third periods (t1, t2, t3), each of the on voltage period and the off voltage period of the fifth and sixth shift clock signals (CLK5, CLK6) corresponds to one horizontal period. You can. In a low-speed driving mode according to another example, when the pixel P operates in the first to fourth periods (t1, t2, t3, and t4) shown in FIG. 8, the third and fourth shift clock signals (CLK5) , CLK6) each may include only an off-voltage period. In a low-speed driving mode according to another example, when the pixel P operates in the first to third periods (t1, t2, and t3) shown in FIG. 12, the fifth and sixth shift clock signals (CLK5, CLK6) Each of the on voltage period and the off voltage period may correspond to two horizontal periods.

Each of the on-voltage period and the off-voltage period of the seventh and eighth shift clock signals (CLK7 and CLK8) may correspond to 2 horizontal periods or 3 horizontal periods in the normal driving mode, and 2 horizontal periods and 3 horizontal periods in the low-speed driving mode. It can correspond to a horizontal period, or 4 horizontal periods. Each of these seventh and eighth shift clock signals CLK7 and CLK8 may be used to generate a fourth gate driving signal or light emission control signal to be supplied to the fourth gate line of the gate line group GLG.

In the normal driving mode according to one example, when the pixel P operates in the first to fourth periods (t1, t2, t3, and t4) shown in FIG. 6, the seventh and eighth shift clock signals CLK7 , CLK8) Each of the on-voltage period and the off-voltage period may correspond to three horizontal periods. In the normal driving mode according to another example, when the pixel P operates in the first to third periods (t1, t2, and t3) shown in FIG. 10, the seventh and eighth shift clock signals (CLK7, CLK8) ) Each of the on-voltage period and the off-voltage period may correspond to two horizontal periods.

In a low-speed driving mode according to an example, when the pixel P operates in the first to fourth periods (t1, t2, t3, and t4) shown in FIGS. 6 to 8, the 7th and 8th shifts Each on-voltage period and off-voltage period of each of the clock signals CLK7 and CLK8 may correspond to three horizontal periods. In a low-speed driving mode according to another example, when the pixel P operates in the first to fourth periods (t1, t2, t3, and t4) shown in FIG. 9, the 7th and 8th shift clock signals ( CLK7, CLK8) Each of the on voltage period and the off voltage period may correspond to 4 horizontal periods. In a low-speed driving mode according to another example, when the pixel P operates in the first to third periods (t1, t2, and t3) shown in FIGS. 10 to 12, the 7th and 8th shift clock Each of the on-voltage period and off-voltage period of each of the signals CLK7 and CLK8 may correspond to two horizontal periods.

According to one example, some (or odd-numbered) stage blocks (SB1, SB3, ... SBm-1) of the first to m-th stage blocks (SB1 to SBm) are some (or odd-numbered) of the first to eighth gate clock lines. (th) can be connected to the gate clock line. The remaining (or even-numbered) stage blocks (SB2, SB4, ... SBm) among the first to m-th stage blocks (SB1 to SBm) are the remaining (or even-numbered) gate clock lines of the first to eighth gate clock lines ( can be connected

Each of the first to m stage blocks (SB1 to SBm) has a shift clock during the on-voltage period supplied to the corresponding gate clock line based on the start signal (Vst), the stage driving voltage (GVdd), and the stage common voltage (GVss). Signals (CLK1 to CLK8) can be output as gate driving signals.

According to one example, the first stage block SB1 is provided by the start signal Vst from the timing control unit 300 in the normal driving mode or the refresh frame of the Nth unit time in the low-speed driving mode. In response to the start signal (Vst), a gate group driving signal corresponding to the shift clock signal (CLK1, CLK3, CLK5, CLK7) supplied from some (or odd-numbered) clock lines of the first to eighth gate clock lines is provided. 1 Can be supplied to gate line group (GLG1).

According to one example, the second stage block SB2 receives a start signal supplied through the mode control circuit 730 in the normal driving mode or from the timing control unit 300 in the refresh frame of the N+1th unit time in the low-speed driving mode. Driving a gate group corresponding to the shift clock signal (CLK2, CLK4, CLK6, CLK8) supplied from some (or even number) gate clock lines of the first to eighth gate clock lines in response to the provided start signal (Vst) A signal may be supplied to the second gate line group GLG2.

Each of the third to m stage blocks (SB3 to SBm) receives a shift clock signal (CLK1) supplied from the corresponding gate clock line among the first to eighth gate clock lines in response to the start signal supplied from the mode control circuit 730. to CLK8) may be sequentially supplied to the third to m-th gate line groups (GLG3 to GLGm). For example, the third to m-th stage blocks SB3 to SBm may each be dependently connected to each other through the mode control circuit 730.

The mode control circuit 730 selects the i (i is any natural number from 1 to m-1) stage block (SBi) among the first to m-th stage blocks (SB1 to SBm) in response to the mode control signal (MCS). Normal driving mode or low-speed driving of the gate driving circuit 700 by supplying the gate group driving signal output from the gate as a start signal to the i+1 stage block (SBi+1) or the i+2 stage block (SBi+2). You can control the mode.

The mode control signal MCS may include a first mode control signal MCS1 for a normal driving mode and a second mode control signal MCS2 for a low-speed driving mode. As an example, when the gate driving circuit 700 operates in normal driving mode, the first mode control signal MCS1 may have a first logic voltage level (or low voltage level) that can turn on the transistor. And the second mode control signal MCS2 may have a second logic voltage level (or high voltage level) that can turn off the transistor. As another example, when the gate driving circuit 700 operates in a low-speed driving mode, the first mode control signal MCS1 may have a second logic voltage level (or low voltage level), and the second mode control signal (MCS1) may have a second logic voltage level (or low voltage level). MCS2) may have a first logic voltage level or a second logic voltage level depending on unit time. For example, when the gate driving circuit 700 operates in a low-speed driving mode, the second mode control signal MCS2 may have a first logic voltage level for the Nth unit time, and may have a first logic voltage level for the N+1th unit time. It may have a second logic voltage level.

The mode control circuit 730 according to one example may include a first switching unit 731, an inverter circuit 733, and a second switching unit 735.

The first switching unit 731 may be implemented to control the gate driving circuit 700 in normal driving mode. The first switching unit 731 supplies the gate group driving signal output from the i-th stage block (SBi) to the i+1-th stage block (SBi+1) as a start signal in response to the first mode control signal (MCS1). You can. Accordingly, the first stage block SB1 is driven by the start signal Vst provided from the timing control unit 300, and each of the second to m stage blocks SB1 to SBm is driven by the first mode control signal MCS1. Accordingly, it can be driven in a normal driving mode by being sequentially driven in response to the start signal (Vst) supplied through the first switching unit 731.

The first switching unit 731 may include first to jth (j is m-1) transistor units (TU1 to TUj) disposed between the first to mth stage blocks (SB1 to SBm).

Each of the first to j transistor units TU1 to TUj uses the gate group driving signal output from the i stage block SBi in response to the first mode control signal MCS1 as a start signal to the i+1 stage block ( It can be supplied to SBi+1). For example, the first transistor unit TU1 is turned on according to the first logic voltage level and supplies the gate group driving signal output from the first stage block SB1 to the second stage block SB2 as a start signal. You can. Likewise, the second to j transistor units (TU2 to TUj) are turned on according to the first mode control signal (MCS) of the first logic voltage level and the second to m-1 stage blocks (SB2 to SBm- 1) The gate group driving signal output from each can be supplied as a start signal to the third to m-th stage blocks SB3 to SBm, respectively. Accordingly, each of the first to m stage blocks (SB1 to SBm) is turned on according to the start signal (Vst) provided from the timing control unit 300 and the first mode control signal (MCS) of the first logic voltage level. It is driven sequentially in response to the start signal Vst sequentially supplied through the first switching unit 731, and as a result, the gate driving circuit 700 can be driven in the normal driving mode shown in FIG. 2.

The inverter circuit 733 may invert the second mode control signal MCS2 provided from the timing controller 300 and output the third mode control signal MCS3. The inverter circuit 733 may output a third mode control signal MCS3 in which the logic level of the second mode control signal MCS2 is inverted. For example, the inverter circuit 733 may invert the second mode control signal MCS2 having the second logic voltage level and output the third mode control signal MCS3 having the first logic voltage level. Conversely, the inverter circuit 733 may invert the second mode control signal MCS2 having the first logic voltage level and output the third mode control signal MCS3 having the second logic voltage level.

The second switching unit 735 may be implemented to control the gate driving circuit 700 in a low-speed driving mode. For example, the second switching unit 735 may be implemented to control the gate driving circuit 700 in an interlace driving low-speed driving mode.

The second switching unit 735 uses the gate group driving signal output from the i stage block SBi in response to the second mode control signal MCS2 and the third mode control signal MCS3 as a start signal to the i+2 It can be supplied to the stage block (SBi+2). Accordingly, the first to m stage blocks (SB1 to SBm) perform the first stage according to the start signal (Vst), the second mode control signal (MCS2), and the third mode control signal (MCS3) provided from the timing control unit 300. 2 It can be driven sequentially according to the interlace driving method in response to a start signal supplied through the switching unit 735, and thus can be driven in a low-speed driving mode of the interlace driving method.

The second switching unit 735 may include first to jth switching units (SU1 to SUj) disposed between the first to mth stage blocks (SB1 to SBm).

The first to j switching units SU1 to SUj may be grouped into a first switching group switched according to the second mode control signal MCS2 and a second switching group switched according to the third mode control signal MCS3. there is. For example, some (or odd numbers) of the first to j switching units SU1 to SUj are grouped into a first switching group that switches according to the second mode control signal MCS2, and the first to j switching units The remaining (or even numbered) units of the units SU1 to SUj may be grouped into a second switching group that is switched according to the third mode control signal MCS3. In other words, the 2k-1 (k is 1 to j/2) switching unit (SU2k-1) among the first to j switching units (SU1 to SUj) is grouped into the first switching group, and the first to j switching units (SU1 to SUj) are grouped into the first switching group. The 2k switching unit (SU2k) among the j switching units (SU1 to SUj) may be grouped into the second switching group.

The 2k-1 switching unit (SU2k-1) according to an example includes a 2y-1 (y is 1 to m/2) stage block (SB2y-1) among the first to m stage blocks (SB1 to SBm). It can be connected between the 2y+1 stage blocks (SB2y+1). The 2k-1 switching unit (SU2k-1) uses the gate group driving signal output from the 2y-1 stage block (SB2y-1) in response to the second mode control signal (MCS2) as a start signal to the 2y+1 stage. Can be supplied to block (SB2y+1). Accordingly, the 2y-1 stage block (SB2y-1) among the first to m stage blocks (SB1 to SBm) includes a start signal (Vst) and a second mode control signal (MCS2) provided from the timing control unit 300. Accordingly, the second switching unit 735 is sequentially driven in response to the start signal (Vst) supplied through the 2k-1 switching unit (SU2k-1) (or the first switching group), thereby performing low-speed interlace driving. It can be driven in mode. For example, among the first to m stage blocks (SB1 to SBm), the 2y-1 stage block (SB2y-1) is a start provided from the timing control unit 300 during the refresh frame of the Nth unit time in the low-speed driving mode. A start signal (Vst) supplied through the 2k-1 switching unit (SU2k-1) (or first switching group) of the second switching unit 735 according to the signal (Vst) and the second mode control signal (MCS2) It is driven sequentially in response to , and as a result, the gate driving circuit 700 can be driven in the low-speed driving mode of the interlace driving method shown in FIG. 3A.

The 2k switching unit SU2k according to an example may be connected between the 2y stage block SB2y and the 2y+2 stage block SB2y+2 among the first to m stage blocks SB1 to SBm. Accordingly, the 2y stage block SB2y among the first to m stage blocks SB1 to SBm performs the second stage according to the start signal Vst and the third mode control signal MCS3 provided from the timing control unit 300. By sequentially driving in response to a start signal supplied through the 2k switching unit (SU2k) (or second switching group) of the switching unit 735, it can be driven in an interlace driving low-speed driving mode. For example, the 2y stage block SB2y among the first to m stage blocks SB1 to SBm receives a start signal ( Vst) and the third mode control signal MCS3 are sequentially driven in response to a start signal supplied through the 2k switching unit (SU2k) (or second switching group) of the second switching unit 735, and thus Therefore, the gate driving circuit 700 may be driven in the interlace driving low-speed driving mode shown in FIG. 3B.

FIG. 14 is a diagram showing the first stage block, first transistor unit, and first switching unit shown in FIG. 13.

1, 13, and 14, the first stage block SB1 of the shift register 710 of the gate driving circuit according to the present specification receives first to fourth start signals ( Vst1, Vst2, Vst3, Vst4) of the 1st, 3rd, 5th, and 7th shift clock signals (CLK1, CLK3, CLK5, and CLK7) supplied to the 1st, 3rd, 5th, and 7th gate clock lines, respectively, Each of the first to fourth gate driving signals GS1, GS2, GS3, and GS4 corresponding to the on-voltage period is connected to the first to fourth gate lines GL1, GL2, GL3, and GL4 of the first gate line group GLG1. Can be supplied to each.

The first stage block SB1 according to one embodiment may include first to fourth stage circuits ST1, ST2, ST3, and ST4.

The first stage circuit ST1 may be implemented to supply the first gate driving signal GS1 to the first gate line GL1 of the first gate line group GLG1. For example, the first stage circuit (ST1) is connected to the first gate clock line based on the first start signal (Vst1), the stage driving voltage (GVdd), and the stage common voltage (GVss) provided from the timing controller 300. The first gate driving signal GS1 corresponding to the on-voltage period of the supplied first shift clock signal CLK1 may be output to the first gate line GL1 of the first gate line group GLG1.

The second stage circuit ST2 may be implemented to supply the second gate driving signal GS2 to the second gate line GL2 of the first gate line group GLG1. For example, the second stage circuit (ST2) is connected to the third gate clock line based on the second start signal (Vst2), the stage driving voltage (GVdd), and the stage common voltage (GVss) provided from the timing controller 300. The second gate driving signal GS2 corresponding to the on-voltage period of the supplied third shift clock signal CLK3 may be output to the second gate line GL2 of the first gate line group GLG1.

The third stage circuit ST3 may be implemented to supply the third gate driving signal GS3 to the third gate line GL3 of the first gate line group GLG1. For example, the third stage circuit (ST3) is connected to the fifth gate clock line based on the third start signal (Vst3), the stage driving voltage (GVdd), and the stage common voltage (GVss) provided from the timing controller 300. The third gate driving signal GS3 corresponding to the on-voltage period of the supplied fifth shift clock signal CLK5 may be output to the third gate line GL3 of the first gate line group GLG1.

The fourth stage circuit ST4 may be implemented to supply the fourth gate driving signal GS4 to the fourth gate line GL4 of the first gate line group GLG1. For example, the fourth stage circuit (ST4) is connected to the seventh gate clock line based on the fourth start signal (Vst4), the stage driving voltage (GVdd), and the stage common voltage (GVss) provided from the timing control unit 300. The fourth gate driving signal GS4 corresponding to the on-voltage period of the supplied seventh shift clock signal CLK7 may be output to the fourth gate line GL4 of the first gate line group GLG1.

Additionally, the second stage block SB2 of the shift register 710 performs the second and fourth start signals Vst1, Vst2, Vst3, and Vst4 provided from the timing control unit 300, respectively. The first to fourth voltage periods corresponding to the on-voltage periods of the second, fourth, sixth, and eighth shift clock signals (CLK2, CLK4, CLK6, and CLK8) supplied to the fourth, sixth, and eighth gate clock lines, respectively. Each of the four gate driving signals GS1, GS2, GS3, and GS4 may be supplied to each of the first to fourth gate lines GL1, GL2, GL3, and GL4 of the second gate line group GLG2.

In addition, the third, fifth to m-1th stage blocks (SB3, SB5, ... SBm-1) of the shift register 710 each receive the first to fourth start signals supplied through the mode control circuit 730. On-voltage periods of the first, third, fifth, and seventh shift clock signals (CLK1, CLK3, CLK5, and CLK7) supplied to the first, third, fifth, and seventh gate clock lines, respectively, in response to Each of the first to fourth gate driving signals (GS1, GS2, GS3, GS4) corresponding to It can be supplied to each of the 4 gate lines (GL1, GL2, GL3, and GL4).

In addition, each of the fourth, sixth to m-th stage blocks (SB4, SB6, ... SBm) of the shift register 710 operates in response to each of the first to fourth start signals supplied through the mode control circuit 730. The first voltage corresponding to the on-voltage period of the second, fourth, sixth, and eighth shift clock signals (CLK2, CLK4, CLK6, and CLK8) supplied to the 2nd, 4th, 6th, and 8th gate clock lines, respectively. The first to fourth gate driving signals (GS1, GS2, GS3, GS4) are connected to the first to fourth gate lines (GL1, GL2, It can be supplied to each of GL3 and GL4).

Since each of the first to fourth stage circuits (ST1, ST2, ST3, and ST4) is a stage circuit of a known gain driving circuit that uses one start signal and one shift clock signal, a detailed circuit description thereof is given below. Omit it.

In the mode control circuit 730 of the gate driving circuit according to the present specification, the first transistor unit TU1 uses the gate group driving signal output from the first stage block SB1 of the shift register 710 as the first signal. It can be supplied to the second stage block SB2 according to the mode control signal MCS1.

The first transistor unit TU1 according to an example may include first to fourth transistors Ta, Tb, Tc, and Td.

The first transistor Ta is turned on according to the first mode control signal MCS1 and uses the first gate driving signal GS1 output from the first stage circuit ST1 of the first stage block SB1 as a start signal. It can be supplied to the first stage circuit of the second stage block SB2. The first transistor Ta according to an example includes a gate electrode connected to the first mode control signal line to which the first mode control signal MCS1 is supplied, and an output line of the first stage circuit of the first stage block SB1 (or It may include a first source/drain electrode connected to the first gate line (GL1), and a second source/drain electrode connected to the start signal input line of the first stage circuit of the second stage block (SB2).

The second transistor Tb is turned on according to the first mode control signal MCS1 and uses the second gate driving signal GS2 output from the second stage circuit ST2 of the first stage block SB1 as a start signal. It can be supplied to the second stage circuit of the second stage block SB2. The second transistor Tb according to an example includes a gate electrode connected to the first mode control signal line, and a second electrode connected to the output line (or second gate line GL2) of the second stage circuit of the first stage block SB1. It may include one source/drain electrode, and a second source/drain electrode connected to the start signal input line of the second stage circuit of the second stage block SB2.

The third transistor Tc is turned on according to the first mode control signal MCS1 and uses the third gate driving signal GS3 output from the third stage circuit ST3 of the first stage block SB1 as a start signal. It can be supplied to the third stage circuit of the second stage block SB2. The third transistor Tc according to an example includes a gate electrode connected to the first mode control signal line, and a third transistor connected to the output line (or third gate line GL3) of the third stage circuit of the first stage block SB1. It may include one source/drain electrode, and a second source/drain electrode connected to the start signal input line of the third stage circuit of the second stage block SB2.

The fourth transistor Td is turned on according to the first mode control signal MCS1 and uses the fourth gate driving signal GS4 output from the fourth stage circuit ST4 of the first stage block SB1 as a start signal. It can be supplied to the fourth stage circuit of the second stage block SB2. The fourth transistor Td according to an example includes a gate electrode connected to the first mode control signal line, and a fourth transistor connected to the output line (or fourth gate line GL4) of the fourth stage circuit of the first stage block SB1. It may include one source/drain electrode, and a second source/drain electrode connected to the start signal input line of the fourth stage circuit of the second stage block SB2.

Additionally, each of the second to j transistor units (TU2 to TUj) according to an example may also include first to fourth transistors (Ta, Tb, Tc, and Td).

The first transistor Ta of each of the second to j transistor units TU2 to TUj is turned on according to the first mode control signal MCS1 to operate the first to m-1 stage blocks SB1 to SBm-1. ) The first gate driving signal GS1 output from each first stage circuit ST1 may be supplied as a start signal to the first stage circuits of each of the second to m stage blocks SB2 to SBm.

The second transistor Tb of each of the second to j transistor units TU2 to TUj is turned on according to the first mode control signal MCS1 to operate the first to m-1th stage blocks SB1 to SBm-1. ) The second gate driving signal GS2 output from each second stage circuit ST2 may be supplied as a start signal to the second stage circuits of each of the second to mth stage blocks SB2 to SBm.

The third transistor Tc of each of the second to j transistor units TU2 to TUj is turned on according to the first mode control signal MCS1 to operate the first to m-1 stage blocks SB1 to SBm-1. ) The third gate driving signal GS3 output from each third stage circuit ST3 may be supplied as a start signal to the third stage circuits of each of the second to mth stage blocks SB2 to SBm.

The fourth transistor Td of each of the second to j transistor units TU2 to TUj is turned on according to the first mode control signal MCS1 to operate the first to m-1 stage blocks SB1 to SBm-1. ) The fourth gate driving signal GS4 output from each fourth stage circuit ST4 may be supplied as a start signal to the fourth stage circuits of each of the second to mth stage blocks SB2 to SBm.

Each of the first to j transistor units (TU1 to TUj) is turned on according to the first mode control signal (MCS1), and the first transistor units output from each of the first to m-1th stage blocks (SB1 to SBm-1) are By supplying the to fourth gate driving signals GS1, GS2, GS3, and GS4 as start signals to each of the second to m stage blocks SB2 to SBm, the gate driving circuit 700 uses the progressive driving method shown in FIG. 2. It can be driven in normal driving mode.

In the mode control circuit 730 of the gate driving circuit according to the present specification, the first switching unit SU1 uses the gate group driving signal output from the first stage block SB1 of the shift register 710 as a start signal to the second switching unit SU1. It can be supplied to the third stage block SB3 according to the mode control signal MCS2.

The first switching unit SU1 according to an example may include first to fourth switch elements SWa, SWb, SWc, and SWd.

The first switch element (SWa) is turned on according to the second mode control signal (MCS2) and starts the first gate driving signal (GS1) output from the first stage circuit (ST1) of the first stage block (SB1). It can be supplied as a signal to the first stage circuit of the third stage block SB3. The first switch element SWa according to an example includes a gate electrode connected to a second mode control signal line to which the second mode control signal MCS2 is supplied, and an output line of the first stage circuit of the first stage block SB1 ( Alternatively, it may include a first source/drain electrode connected to the first gate line (GL1), and a second source/drain electrode connected to the start signal input line of the first stage circuit of the third stage block (SB3).

The second switch element (SWb) is turned on according to the second mode control signal (MCS2) and starts the second gate driving signal (GS2) output from the second stage circuit (ST2) of the first stage block (SB1). It can be supplied as a signal to the second stage circuit of the third stage block SB3. The second switch element (SWb) according to an example includes a gate electrode connected to the second mode control signal line and an output line (or second gate line (GL2)) of the second stage circuit of the first stage block (SB1). It may include a first source/drain electrode and a second source/drain electrode connected to the start signal input line of the second stage circuit of the third stage block SB3.

The third switch element (SWc) is turned on according to the second mode control signal (MCS2) and starts the third gate driving signal (GS3) output from the third stage circuit (ST3) of the first stage block (SB1). It can be supplied as a signal to the third stage circuit of the third stage block SB3. The third switch element (SWc) according to an example includes a gate electrode connected to the second mode control signal line and an output line (or third gate line (GL3)) of the third stage circuit of the first stage block (SB1). It may include a first source/drain electrode and a second source/drain electrode connected to the start signal input line of the third stage circuit of the third stage block SB3.

The fourth switch element SWd is turned on according to the second mode control signal MCS2 to start the fourth gate driving signal GS4 output from the fourth stage circuit ST4 of the first stage block SB1. It can be supplied as a signal to the fourth stage circuit of the third stage block SB3. The fourth switch element (SWd) according to an example includes a gate electrode connected to the second mode control signal line and an output line (or fourth gate line (GL4)) of the fourth stage circuit of the first stage block (SB1). It may include a first source/drain electrode and a second source/drain electrode connected to the start signal input line of the fourth stage circuit of the third stage block SB3.

Similarly, in the first to j switching units (SU1 to SUj), the third, fifth to j-1 switching units (SU3, SU5, ... SUj-1) also have the first to fourth switch elements (SWa). , Tb, Tc, Td). The first to fourth switch elements (SWa, Tb, Tc, Td) of the third, fifth to j-1 switching units (SU3, SU5, ... SUj-1) are connected to the second mode control signal (MCS2). The first circuit is turned on and output from each of the first to fourth stage circuits (ST1, ST2, ST3, ST4) of the third, fifth to m-1 stage blocks (SB3, SB5 to SBm-1). The first to fourth stages of each of the fifth, seventh to m-1 stage blocks (SB5, SB7, ... SBm-1) are respectively used as start signals. It can be supplied to each of the circuits (ST1, ST2, ST3, and ST4).

Additionally, the second switching unit SU2 according to one example may also include first to fourth switch elements SWa, SWb, SWc, and SWd.

The first switch element (SWa) of the second switching unit (SU2) is turned on according to the third mode control signal (MCS3) and the first switch output from the first stage circuit (ST1) of the second stage block (SB2) is turned on. The gate driving signal GS1 may be supplied as a start signal to the first stage circuit of the fourth stage block SB4.

The second switch element (SWb) of the second switching unit (SU2) is turned on according to the third mode control signal (MCS3) and the second switch element (SWb) output from the second stage circuit (ST2) of the second stage block (SB2) is turned on. The gate driving signal GS2 may be supplied as a start signal to the second stage circuit of the fourth stage block SB4.

The third switch element (SWc) of the second switching unit (SU2) is turned on according to the third mode control signal (MCS3) and the third switch element (SWc) output from the third stage circuit (ST3) of the second stage block (SB2) is turned on. The gate driving signal GS3 may be supplied as a start signal to the third stage circuit of the fourth stage block SB4.

The fourth switch element (SWd) of the second switching unit (SU2) is turned on according to the third mode control signal (MCS3) and the fourth switch element (SWd) output from the fourth stage circuit (ST4) of the second stage block (SB2) is turned on. The gate driving signal GS4 may be supplied as a start signal to the fourth stage circuit of the fourth stage block SB4.

Likewise, in the first to j switching units (SU1 to SUj), the fourth, sixth to j switching units (SU4, SU6, ... SUj) also have first to fourth switch elements (SWa, Tb, Tc), respectively. , Td). The first to fourth switch elements (SWa, Tb, Tc, Td) of the fourth, sixth to j switching units (SU4, SU6, ... SUj) are turned on according to the third mode control signal (MCS3). The first to fourth gate driving signals (GS1) are output from the first to fourth stage circuits (ST1, ST2, ST3, ST4) of the fourth, sixth to m stage blocks (SB4, SB6 to SBm), respectively. , GS2, GS3, GS4) as start signals, respectively, to the first to fourth stage circuits (ST1, ST2, ST3, ST4) of each of the sixth, eighth to m stage blocks (SB6, SB8, ... SBm). can be supplied.

FIG. 15 is a diagram illustrating a comparison between the luminance drop width of a light-emitting display device driven in a low-speed drive mode of the interlace driving method according to an example of the present specification and the luminance drop width of a light-emitting display device driven in a low-speed drive mode according to a comparative example. am. In FIG. 15 , graph A represents the luminance decrease of the light-emitting display device according to the comparative example, and graph B represents the luminance decrease of the light-emitting display device according to an example of the present specification.

Referring to FIG. 15 , the light emitting display device according to the comparative example may update images of pixels arranged in all horizontal lines by sequentially driving all gate line groups in a refresh frame in a low-speed driving mode. Accordingly, the light emitting display device according to the comparative example has a problem in that flicker occurs due to an excessive drop in luminance (DW1) in the refresh frame compared to the hold frame, as shown in graph A.

In comparison, the light emitting display device according to an example of the present specification sequentially drives some of the gate line groups in refresh frame units in the low-speed driving mode of the interlace driving method, as shown in FIG. 3A or 3B. Images of pixels placed on some of the horizontal lines can be updated. Accordingly, in the light emitting display device according to the example of the present specification, as shown in graph B, the flicker phenomenon can be minimized by generating a luminance drop (DW2) that is half of the luminance drop (DW1) according to the comparative example in the refresh frame. For example, in this specification, the luminance drop is divided into a refresh frame of the Nth unit time and a refresh frame of the N+1th unit time, so that the flicker phenomenon can be minimized.

The light emitting display device according to the present specification updates the image through refresh frames at each N-th and N+1-th unit time according to the interlace driving method in the low-speed driving mode, thereby reducing the luminance drop rate generated in the refresh frame. Accordingly, the flicker phenomenon that occurs in low-speed driving mode can be minimized.

FIG. 16 is a diagram showing a comparison between the pixel charging time of a light-emitting display device driven in a low-speed drive mode according to an example of the present specification and the pixel charging time of a light-emitting display device driven in a low-speed drive mode according to a comparative example. In FIG. 16 , graph C represents the pixel charging time according to the comparative example, and graph D represents the pixel charging time of the data voltage according to the pixel driving method shown in FIG. 9 or FIG. 12 .

Referring to FIG. 16, the light emitting display device according to the comparative example can charge only the actual data voltage in the refresh frame of the low-speed driving mode. Accordingly, it can be seen that the light emitting display device according to the comparative example has a first pixel charging time (tc1), as shown in graph C.

In comparison, the light emitting display device according to an example of the present specification may charge the real data voltage after pre-charging the dummy data voltage in the refresh frame of the low-speed driving mode shown in FIG. 9 or FIG. 12. Accordingly, it can be seen that the light emitting display device according to the example of the present specification has a second pixel charging time (tc2) that is relatively shorter than the first pixel charging time (tc1) according to the comparative example, as shown in graph D.

Therefore, the light emitting display device according to an example of the present specification reduces the pixel charging time by pre-charging the dummy data voltage before charging the actual data voltage in the low-speed driving mode or implements fast charging of the data voltage in the low-speed driving mode. It is possible to prevent or minimize the decrease in brightness of the light emitting device due to slow charging of the data voltage generated in the refresh frame.

A light emitting display device according to some examples of the present specification may be described as follows.

A light emitting display device according to some examples of the present specification includes a light emitting display panel including a plurality of data lines and pixels disposed in pixel areas defined by first to mth gate line groups, and a first display panel disposed on the light emitting display panel and and a gate driving circuit that drives the to mth gate line group in a normal driving mode or a low-speed driving mode, wherein the gate driving circuit operates in the low-speed driving mode for the Nth unit time (N is a natural number) of the plurality of unit times. Some of the m-th gate line groups may be driven, and remaining gate line groups among the first to m-th gate line groups may be driven for an (N+1)th unit time.

According to some examples of the present specification, in the low-speed driving mode, each of the plurality of unit times includes a refresh frame and a hold frame, and the gate driving circuit is configured to operate some of the first to mth gate line groups during the refresh frame of the Nth unit time. The gate line group may be driven, and the remaining gate line groups among the first to m gate line groups may be driven during the refresh frame of the N+1th unit time.

According to some examples herein, the unit time is 1 second, and within the unit time, the time of the refresh frame may be shorter than the time of the hold frame.

According to some examples of the present specification, the gate driving circuit drives the odd-numbered gate line group among the first to m-th gate line groups during the refresh frame of the N-th unit time, and the first gate line group during the refresh frame of the N+1-th unit time. The even-numbered gate line group among the to m-th gate line groups can be driven.

According to some examples of the present specification, the unit time is 1 second, the image displayed on the odd-numbered horizontal line among the images displayed on the light-emitting display panel is updated in the refresh frame of the Nth unit time, and the image displayed on the light-emitting display panel The image displayed on the even-numbered horizontal line may be updated in the refresh frame of the N+1th unit of time.

According to some examples herein, the gate driving circuit includes a shift register having first to m-th stage blocks that output gate group driving signals in response to a start signal, and first to m-th stages in response to a mode control signal. A mode control circuit that supplies the gate group driving signal output from the i (i is a natural number from 1 to m-1) stage block among the blocks to the i+1-th stage block or the i+2-th stage block as a start signal. may include.

According to some examples herein, the mode control signal includes a first mode control signal for a normal drive mode and a second mode control signal for a low-speed drive mode, and the mode control circuit is in response to the first mode control signal to control the first mode control signal. A first switching unit that supplies the gate group driving signal output from the i stage block to the i+1 stage block as a start signal, an inverter circuit that inverts the second mode control signal and outputs a third mode control signal, and a first switching unit. It may include a second switching unit that supplies the gate group driving signal output from the i-th stage block as a start signal to the i+2-th stage block in response to the two-mode control signal and the third mode control signal.

According to some examples of the present specification, the first switching unit is disposed between the first to m-th stage blocks and uses the gate group driving signal output from the i-th stage block in response to the first mode control signal as a start signal to the i+-th stage block. It may include first to jth (j is m-1) transistor units supplied to the first stage block.

According to some examples of the present specification, the second switching unit is disposed between the first to m-th stage blocks and receives a gate group driving signal output from the i-th stage block in response to the second mode control signal and the third mode control signal. It may include first to jth switching units that supply the i+2th stage block as a start signal.

According to some examples of the present specification, the 2k-1 (k is 1 to j/2) switching unit among the first to j switching units is the 2y-1 (y is 1 to m) among the first to m stage blocks. /2) The gate group driving signal connected between the stage block and the 2y+1 stage block and output from the 2y-1 stage block in response to the second mode control signal is supplied to the 2y+1 stage block as a start signal, , the 2k switching unit among the 1st to jth switching units is connected between the 2y stage block and the 2y+2 stage block among the 1st to mth stage blocks and is switched from the 2y stage block in response to the third mode control signal. The output gate group driving signal can be supplied to the 2y+2 stage block as a start signal.

According to some examples of the present specification, each of the plurality of pixels includes a light emitting device; A driving thin film transistor having a gate electrode connected to a first node, a first source/drain electrode connected to a second node, and a second source/drain electrode connected to a third node; a first thin film transistor selectively connecting a data line and a second node; a second thin film transistor selectively connecting the first node and the third node; a third thin film transistor selectively connecting the pixel driving power line and the second node; a fourth thin film transistor selectively connecting the third node and the light emitting element; a fifth thin film transistor selectively connecting the initialization power line and the first node; a sixth thin film transistor selectively connecting the fourth node between the fourth thin film transistor and the light emitting device and the initialization power line; and a storage capacitor connected between the pixel driving power line and the first node.

According to some examples herein, the refresh frame is a first period connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor, followed by the first period and the turn-on of the first and second thin film transistors. A second period for storing the data voltage and the threshold voltage of the driving thin film transistor in the storage capacitor according to the turn-on, a third period for connecting the fourth node and the initialization power line according to the turn-on of the sixth transistor following the second period, and a fourth period following the third period and causing the light emitting device to emit light according to the turn-on of the third and fourth thin film transistors.

According to some examples herein, the initialization voltage supplied to the initialization power line has a first voltage level to discharge the voltage of the fourth node in the third period or is lower than the first voltage level to increase the voltage of the fourth node. It may have a high second voltage level.

According to some examples herein, in a refresh frame, a second period is a 2-1 period that follows the first period and supplies a dummy data voltage to the second node, and a second period that follows the 2-1 period and supplies a real data voltage to the second node. It may include a 2-2 period of supplying to the node.

According to some examples herein, the dummy data voltage may have a higher voltage level than the data voltage.

According to some examples herein, the refresh frame is a first period connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor, followed by the first period and the turn-on of the first and second thin film transistors. A second period for storing the data voltage and the threshold voltage of the driving thin film transistor in the storage capacitor according to the on, a third period for maintaining the voltage of the fourth node according to the turn-off of the sixth transistor following the second period, and a first period. It may be followed by three periods and may include a fourth period in which the light emitting device emits light according to the turn-on of the third and fourth thin film transistors.

According to some examples herein, the refresh frame is a first period connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor, followed by the first period and the turn-on of the first and second thin film transistors. A second period in which the data voltage and the threshold voltage of the driving thin film transistor are stored in the storage capacitor according to the turn-on of the sixth transistor, and the fourth node and the initialization power line are connected according to the turn-on of the sixth transistor, and the second period continues with the light emitting device. It may include a third period of emitting light.

According to some examples herein, the initialization voltage supplied to the initialization power line has a first voltage level to discharge the voltage of the fourth node in the second period or is lower than the first voltage level to increase the voltage of the fourth node. It may have a high second voltage level.

According to some examples herein, in a refresh frame, a second period is a 2-1 period that follows the first period and supplies a dummy data voltage to the second node, and a second period that follows the 2-1 period and supplies a real data voltage to the second node. It may include a 2-2 period of supplying to the node.

According to some examples herein, the dummy data voltage may have a higher voltage level than the data voltage.

The features, structures, effects, etc. described in the examples of the present specification described above are included in at least one example of the present specification and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. illustrated in at least one example of the present specification can be combined or modified and implemented in other examples by those skilled in the art in the field to which the technical idea of the present specification pertains. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible without departing from the technical spirit of the present specification. It will be obvious to those skilled in the art. Therefore, the scope of the present specification is indicated by the claims described later, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present specification.

100: light emitting display panel 300: timing control unit
500: data driving circuit 700: gate driving circuit
710: shift register 730: mode control circuit
731: first switching unit 733: inverter circuit
735: second switching unit 900: power circuit

Claims (20)

A light emitting display panel including pixels arranged in a pixel area defined by a plurality of data lines and first to mth gate line groups; and
a gate driving circuit disposed on the light emitting display panel and driving the first to mth gate line groups in a normal driving mode or a low-speed driving mode;
The gate driving circuit drives some of the first to mth gate line groups during a refresh frame of the Nth unit time (N is a natural number) among a plurality of unit times in the low speed driving mode, and N+ Driving the remaining gate line groups among the first to m gate line groups during the refresh frame of the first unit time,
Each of the plurality of unit times includes the refresh frame and the hold frame,
When the corresponding gate line group is driven during the refresh frame, the image of the pixel area connected to the driven gate line group is updated and maintained during the hold frame,
The gate driving circuit is,
a shift register having first to m-th stage blocks that output a gate group driving signal in response to a start signal; and
The gate group driving signal output from the i (i is a natural number from 1 to m-1) stage block among the first to m stage blocks in response to the mode control signal is used as the start signal for the i+1 stage. a mode control circuit supplying the block or the i+2 stage block;
The mode control signal includes a first mode control signal for the normal driving mode and a second mode control signal for the low-speed driving mode,
The mode control circuit is,
a first switching unit that supplies a gate group driving signal output from the i-th stage block as the start signal to the i+1-th stage block in response to the first mode control signal;
an inverter circuit that inverts the second mode control signal and outputs a third mode control signal; and
Comprising a second switching unit that supplies a gate group driving signal output from the i-th stage block to the i+2-th stage block as the start signal in response to the second mode control signal and the third mode control signal, Luminous display device. delete According to claim 1,
The unit time is 1 second,
Within the unit time, a time of the refresh frame is shorter than a time of the hold frame. According to claim 1,
The gate driving circuit drives an odd-numbered gate line group among the first to m-th gate line groups during the refresh frame of the N-th unit time, and drives the first to m-th gate line groups during the refresh frame of the N+1-th unit time. A light emitting display device that drives an even-numbered gate line group among the m-th gate line groups. According to claim 4,
The unit time is 1 second,
Among the images displayed on the light emitting display panel, the image displayed on the odd-numbered horizontal line is updated in the refresh frame of the Nth unit time,
Among the images displayed on the light emitting display panel, the image displayed on the even-numbered horizontal line is updated in the refresh frame of the N+1th unit time. delete delete According to claim 1,
The first switching unit is disposed between the first to m-th stage blocks and uses the gate group driving signal output from the i-th stage block in response to the first mode control signal as the start signal to the i+1-th stage. A light emitting display device comprising first to jth (j is m-1) transistor units supplied to a block. According to claim 1,
The second switching unit is disposed between the first to m-th stage blocks and converts a gate group driving signal output from the i-th stage block in response to the second mode control signal and the third mode control signal to the start signal. A light emitting display device comprising first to jth switching units supplying power to the i+2th stage block. According to clause 9,
The 2k-1 (k is 1 to j/2) switching unit among the first to j switching units is a 2y-1 (y is 1 to m/2) stage block among the first to mth stage blocks. A gate group driving signal connected between 2y+1 stage blocks and output from the 2y-1 stage block in response to the second mode control signal is supplied to the 2y+1 stage block as the start signal,
The 2k switching unit among the first to j switching units is connected between the 2y stage block and the 2y+2 stage block among the first to m stage blocks and switches on the 2y stage in response to the third mode control signal. A light emitting display device that supplies a gate group driving signal output from a stage block to the 2y+2 stage block as the start signal. According to any one of claims 1, 3 to 5, and 8 to 10,
Each of the plurality of pixels is,
light emitting device;
A driving thin film transistor having a gate electrode connected to a first node, a first source/drain electrode connected to a second node, and a second source/drain electrode connected to a third node;
a first thin film transistor selectively connecting the data line and the second node;
a second thin film transistor selectively connecting the first node and the third node;
a third thin film transistor selectively connecting a pixel driving power line and the second node;
a fourth thin film transistor selectively connecting the third node and the light emitting device;
a fifth thin film transistor selectively connecting an initialization power line and the first node;
a sixth thin film transistor selectively connecting the initialization power line to a fourth node between the fourth thin film transistor and the light emitting device; and
A light emitting display device comprising a storage capacitor connected between the pixel driving power line and the first node. According to claim 11,
The refresh frame is,
a first period connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor;
a second period following the first period and storing the data voltage and the threshold voltage of the driving thin film transistor in the storage capacitor according to the turn-on of the first and second thin film transistors;
a third period following the second period and connecting the fourth node and the initialization power line according to the turn-on of the sixth thin film transistor; and
A light emitting display device comprising a fourth period following the third period and causing the light emitting element to emit light in accordance with the turn-on of the third and fourth thin film transistors. According to claim 12,
The initialization voltage supplied to the initialization power line has a first voltage level to discharge the voltage of the fourth node in the third period, or a second voltage level higher than the first voltage level to increase the voltage of the fourth node. A light emitting display device having a voltage level. According to claim 12,
The second period in the refresh frame is,
a 2-1 period following the first period and supplying a dummy data voltage to the second node; and
A light emitting display device comprising a 2-2 period following the 2-1 period and supplying an actual data voltage to the second node. According to claim 14,
The dummy data voltage has a higher voltage level than the data voltage. According to claim 11,
The refresh frame is,
a first period connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor;
a second period following the first period and storing the data voltage and the threshold voltage of the driving thin film transistor in the storage capacitor according to the turn-on of the first and second thin film transistors;
a third period following the second period and maintaining the voltage of the fourth node according to the turn-off of the sixth thin film transistor; and
A light emitting display device comprising a fourth period following the third period and causing the light emitting element to emit light in accordance with the turn-on of the third and fourth thin film transistors. According to claim 11,
The refresh frame is,
a first period connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor;
Following the first period, the data voltage and the threshold voltage of the driving thin film transistor are stored in the storage capacitor according to the turn-on of the first and second thin film transistors, and the first period is stored in the storage capacitor according to the turn-on of the sixth thin film transistor. a second period connecting the 4 nodes and the initialization power line; and
A light emitting display device comprising a third period following the second period and causing the light emitting element to emit light. According to claim 17,
The initialization voltage supplied to the initialization power line has a first voltage level to discharge the voltage of the fourth node in the second period or a second voltage level higher than the first voltage level to increase the voltage of the fourth node. A light emitting display device having a voltage level. According to claim 17,
The second period in the refresh frame is,
a 2-1 period following the first period and supplying a dummy data voltage to the second node; and
A light emitting display device comprising a 2-2 period following the 2-1 period and supplying an actual data voltage to the second node. According to claim 19,
The dummy data voltage has a higher voltage level than the data voltage.

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