KR20210068814A - Light emitting display apparatus - Google Patents

Abstract

According to the present specification, a light emitting display device includes: a light emitting display panel including pixels disposed in a pixel area defined by a plurality of data lines and first to m^th gate line groups; and a gate driving circuit disposed on the light emitting display panel and driving the first to m^th gate line groups in a normal driving mode or a low speed driving mode. The gate driving circuit drives some of the first to m^th gate line groups during an N (N is a natural number)^th unit time among a plurality of unit times in the low-speed driving mode, and the rate driving circuit may drive the remaining gate line groups among the first to m^th gate line groups during the N+1^th unit time. Accordingly, a flicker phenomenon occurring during low speed driving can be minimized.

Description

Light Emitting Display {LIGHT EMITTING DISPLAY APPARATUS}

This specification relates to a light emitting display device.

The light emitting display device is widely used as a display screen of a notebook computer, a tablet computer, a smart phone, a smart watch, a portable display device, a portable information device, etc. in addition to the display device of a television or a monitor. Since the light emitting display device displays an image by using a self-luminous element, it has a high response speed, low power consumption, and has no problem in viewing angle, so it is attracting attention as a next-generation display device.

Recently, when displaying an image in which the change in gradation between frames is not large, such as a still image, a variable refresh rate driving method (or a low speed driving method) capable of reducing power consumption has been applied to a light emitting display device. Research and development is in progress.

The variable refresh rate driving type light emitting display device is driven in a refresh period (or refresh frame) for updating an image within a plurality of frames and a hold period (or hold frame) for continuously displaying the updated image. As a result, the image is updated at a low speed, and thus power consumption can be reduced. For example, when the driving frequency of the light emitting display device is 60 Hz, the image is updated during the first frame among first to 60 frames constituting 1 second, and the same updated image is updated during the remaining second to 60th frames. Images can be displayed continuously.

However, in the light emitting display device of the variable refresh rate driving method, a flicker phenomenon may occur due to a luminance deviation between the refresh period and the hold period, and thus the visibility characteristics may be deteriorated.

The content of the background art described above is technical information that the inventor of the present specification possessed to derive the example of the present specification or acquired in the process of deriving the example of the present specification, and must be provided to the general public prior to the filing of the present specification. It cannot be said that it is publicly known technology.

An object of the present specification is to provide a light emitting display device capable of minimizing a flicker phenomenon that occurs when driving at a low speed.

In addition to the tasks of the present specification mentioned above, other features and advantages of the present specification may be described below or clearly understood by those of ordinary skill in the art to which the technical spirit of the present specification belongs from such descriptions and descriptions. will be.

A light emitting display device according to the present specification includes a light emitting display panel including a plurality of data lines and pixels disposed in a pixel area defined by first to m th gate line groups, and first to m th gate line groups disposed on the light emitting display panel. a gate driving circuit for driving the gate line group in a normal driving mode or a low-speed driving mode, wherein the gate driving circuit includes first to m-th gates during an N (N is a natural number)-th unit time among a plurality of unit times in the low-speed driving mode A part of the gate line groups among the line groups may be driven, and the remaining gate line groups among the first to mth gate line groups may be driven for an N+1 th unit time.

In the light emitting display device according to the present specification, a flicker phenomenon occurring when driving at a low speed may be minimized.

In addition to the effects of the present specification mentioned above, other features and advantages of the present specification will be described below or will be clearly understood by those skilled in the art from such description and description.

1 is a diagram illustrating a light emitting display device according to an example of the present specification.
2 is a diagram illustrating a method of driving a gate line group in a normal driving mode of a gate driving circuit according to the present specification.
3A and 3B are diagrams illustrating a method of driving a gate line group in a low speed driving mode of a gate driving circuit according to the present specification.
4A and 4B are views illustrating images updated on a light emitting display panel according to a low speed driving mode in the light emitting display device according to the present specification.
FIG. 5 is an equivalent circuit diagram according to an example of the pixel illustrated in FIG. 1 .
6 is a waveform diagram illustrating a signal according to the first example that is supplied to the pixel shown in FIG. 5 .
7 is a waveform diagram illustrating a signal according to the second example that is supplied to the pixel shown in FIG. 5 .
8 is a waveform diagram illustrating a signal according to a third example supplied to the pixel shown in FIG. 5 .
9 is a waveform diagram illustrating a signal according to a fourth example that is supplied to the pixel shown in FIG. 5 .
FIG. 10 is a waveform diagram illustrating a signal according to a fifth example that is supplied to the pixel shown in FIG. 5 .
11 is a waveform diagram illustrating a modified example of a signal according to the fifth example shown in FIG. 10 .
12 is a waveform diagram illustrating another modified example of a signal according to the fifth example shown in FIG. 10 .
13 is a diagram illustrating a gate driving circuit according to the present specification.
14 is a diagram illustrating a first stage block, a first transistor unit, and a first switching unit shown in FIG. 13 .
15 is a view illustrating a comparison of the luminance fall width of the light emitting display device driven in the interlace driving mode low speed driving mode according to an example of the present specification and the luminance drop width of the light emitting display device driven in the low speed driving mode according to the comparative example. to be.
16 is a diagram illustrating a comparison between a pixel charging time of a light emitting display device driven in a low speed driving mode according to an example of the present specification and a pixel charging time of a light emitting display device driven in a low speed driving mode according to a comparative example.

Advantages and features of the present specification, and a method of achieving them will become apparent with reference to examples described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the examples disclosed below, but will be implemented in various different forms, and only examples of the present specification allow the disclosure of the present specification to be complete, and in the technical field to which the technical spirit of the present specification belongs It is provided to fully inform those of ordinary skill in the scope of the technical idea of the present specification, and examples of the present specification are only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining an example of the present specification are exemplary and are not limited to those illustrated in the drawings of the present specification. Like reference numerals refer to like elements throughout. In addition, in describing an example of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various examples of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each example may be implemented independently of each other or may be implemented together in a related relationship. .

Hereinafter, a preferred example of a light emitting display device according to the present specification will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. And, since the scales of the components shown in the accompanying drawings have different scales from the actual for convenience of explanation, the scales shown in the drawings are not limited thereto.

1 is a diagram illustrating a light emitting display device according to an example of the present specification.

Referring to FIG. 1 , a light emitting display device according to an example of the present specification may include a light emitting display panel 100 , a timing controller 300 , a data driving circuit 500 , and a gate driving circuit 700 .

The light emitting display panel 100 may include a display area AA (or an active area) defined on a substrate, and a non-display area IA (or a non-active area) surrounding the display area AA.

The display area AA may include a plurality of pixels P disposed in a pixel area defined by intersections of the first to mth gate line groups GLG1 to GLGm and the plurality of data lines DL1 to DLn. have.

Each of the first to mth gate line groups GLG1 to GLGm may include a plurality of gate lines arranged to be spaced apart from each other on the substrate. For example, each of the first to mth gate line groups GLG1 to GLGm may include a first to fourth gate line.

Each of the plurality of data lines DL1 to DLn may be disposed on the substrate to cross the first to mth gate line groups GLG1 to GLGm while being spaced apart from each other.

Each of the plurality of pixels P according to an example may be a red pixel, a green pixel, or a blue pixel. In this case, the adjacent red pixel, green pixel, and blue pixel may implement one unit pixel.

Each of the plurality of pixels P according to an example may be a red pixel, a green pixel, a blue pixel, or a white pixel. In this case, the adjacent red pixel, green pixel, blue pixel, and white pixel may implement one unit pixel for displaying one color image.

The plurality of pixels P may be implemented in a stripe structure or a pentile structure on the display area AA.

One unit pixel implemented in a pentile structure may include at least one red pixel, at least one green pixel, and at least one blue pixel arranged in a planar polygonal shape. For example, a unit pixel having a pentile structure may be arranged such that one red pixel, two green pixels, and one blue pixel have an octagonal shape in a plane, and in this case, the blue pixel has the largest size. and the green pixel may have the smallest size.

Each of the plurality of pixels P emits light based on the light emitting device, a plurality of gate signals supplied from the adjacent gate line groups GLG1 to GLGm, and data voltages supplied from the adjacent data lines DL1 to DLn. It may include a pixel circuit.

The non-display area IA may be provided along an edge of the substrate to surround the display area AA. One non-display area of the non-display area IA may include a pad portion provided on the substrate and connected to the plurality of data lines DL1 to DLn.

The timing controller 300 aligns the input image data Idata to be suitable for driving the light emitting display panel 100 to generate digital data Pdata for each pixel, and generates data based on the input timing synchronization signal TSS. A control signal DCS may be generated and provided to the data driving circuit 500 .

The timing controller 300 may generate a gate control signal GCS including a start signal and a plurality of shift clock signals based on the timing synchronization signal TSS and provide it to the gate driving circuit 700 .

The timing controller 300 may generate a mode control signal MCS for driving the gate driving circuit 700 in the normal driving mode or the low speed driving mode and provide it to the gate driving circuit 700 . For example, the normal mode may be a progressive driving mode (or a sequential driving mode). The low speed driving mode may be a variable refresh rate driving mode. In addition, the low-speed driving mode may be a variable refresh rate driving mode using an interlace driving method.

The timing controller 300 according to an example analyzes the image data Idata of one frame image to determine whether the input image is a moving image or a still image, and when the input image is a moving image, a mode control signal (MCS) for a normal driving mode ) and when the input image is a still image, a mode control signal MCS for the low-speed driving mode may be generated. For example, when the input image does not change for a plurality of frames, the timing controller 300 may determine the input image as a still image and generate the mode control signal MCS for the low-speed driving mode.

The data driving circuit 500 may be connected to a plurality of data lines DL1 to DLn provided on the light emitting display panel 100 . The data driving circuit 500 according to an example uses digital data for each pixel Pdata and a data control signal DCS provided from the timing controller 300 and a plurality of reference gamma voltages provided from a power supply for each pixel. The data Pdata may be converted into an analog data voltage for each pixel, and the converted data voltage for each pixel may be supplied to the corresponding data lines DL1 to DLn.

Optionally, the data driving circuit 500 according to an example may generate a dummy data voltage for each pixel immediately before supplying the original data voltage for each pixel and supply it to the corresponding data lines DL1 to DLn. For example, in the low-speed driving mode of the interlace driving method, the data driving circuit 500 may supply a dummy data voltage for each pixel to the corresponding data lines DL1 to DLn during a blank period between horizontal periods according to the interlace driving method. can In this case, the timing controller 300 may generate dummy digital data for each pixel based on the original digital data for each pixel. For example, the dummy digital data for each pixel may have a higher grayscale value than the corresponding original digital data for each pixel.

The gate driving circuit 700 may be disposed in the non-display area IA of the light emitting display panel 100 and may be electrically connected to the first to mth gate line groups GLG1 to GLGm. For example, the gate driving circuit 700 may be integrated on one edge or both edges of the substrate according to a manufacturing process of the thin film transistor and may be connected to the first to mth gate line groups GLG1 to GLGm one-to-one. Alternatively, the gate driving circuit 700 may be configured in an integrated circuit and mounted on a substrate or mounted on a flexible circuit film to be connected to the first to mth gate line groups GLG1 to GLGm one-to-one.

The gate driving circuit 700 operates the first to mth gate line groups GLG1 to GLGm in a normal driving mode or a low speed based on the gate control signal GCS and the mode control signal MCS supplied from the timing controller 300 . It can be driven in drive mode.

The gate driving circuit 700 according to an example may sequentially drive the first to mth gate line groups GLG1 to GLGm in the normal driving mode according to the mode control signal MCS. For example, the gate driving circuit 700 according to the normal driving mode may include the first to mth gate line groups GLG1 to GLGm for each of 60 frames of 1/60 second based on a driving frequency of 60 Hz. can be driven sequentially. In other words, the gate driving circuit 700 according to the normal driving mode sequentially operates the first to mth gate line groups GLG1 to GLGm in each of the first to 60th frames included within a unit time of 1 second. can be driven by

The gate driving circuit 700 according to an example may drive the first to mth gate line groups GLG1 to GLGm according to the interlace driving method in the low speed driving mode according to the mode control signal MCS. For example, the gate driving circuit 700 according to the low speed driving mode may include the first to mth gate line groups GLG1 to GLGm for each refresh period of 1/60 second based on a driving frequency of 1 Hz. may be sequentially driven according to the interlace driving method.

In the low-speed driving mode of the interlace driving method, the gate driving circuit 700 according to an example includes the first to m-th refresh frames of the N (N is a natural number)-th unit time among a plurality of unit times having a refresh frame and a hold frame. Some of the gate line groups GLG1 to GLGm may be driven, and the remaining gate line groups among the first to mth gate line groups GLG1 to GLGm may be driven during the refresh frame of the N+1th unit time. have. The unit time may be 1 second, and the time of the refresh frame within the unit time may be shorter than the time of the hold frame. As an example, when the gate driving circuit 700 according to the low speed driving mode is driven based on a driving frequency of 1 Hz, the time of the refresh frame may be set to 0 second to 1/60 second, and , the time of the hold frame may be set to 1/60 second to 1 second following the refresh frame. As another example, taking a driving frequency of 60 Hz as an example, the refresh frame may correspond to the first frame among the first to 60th frames made of 1/60 second, and the hold frame may correspond to the second to 60th frames. can be matched.

The gate driving circuit 700 according to the low speed driving mode may sequentially drive only a portion of the first to mth gate line groups GLG1 to GLGm for each refresh frame according to the interlace driving method. For example, the gate driving circuit 700 according to the low-speed driving mode of the interlace driving method includes the odd-numbered gate line groups GLG1 among the first to m-th gate line groups GLG1 to GLGm during the refresh frame of the N-th unit time. GLG3, ... GLGm-1) are sequentially driven, and even-numbered gate line groups GLG2, GLG4, ... GLGm among the first to m-th gate line groups GLG1 to GLGm are sequentially driven during the refresh frame of the N+1-th unit time. can be driven sequentially.

Additionally, the light emitting display device according to the present specification may further include a power circuit 900 .

Based on the input power source Vin, the power supply circuit 900 provides a pixel driving voltage EVdd, a pixel common voltage EVss, an initialization voltage EVini, a stage driving voltage GVdd, and a stage common voltage GVss, respectively. can be generated and provided to the light emitting display panel 100 . For example, the power circuit 900 may supply the pixel driving voltage EVdd, the pixel common voltage EVss, and the initialization voltage EVini to the pixels P, respectively. In addition, the power circuit 900 may supply each of the stage driving voltage GVdd and the stage common voltage GVss to the gate driving circuit 700 .

As described above, the light emitting display device according to the present specification may be driven in a normal driving mode or a low speed driving mode according to an input image, and power consumption may be reduced by the low speed driving mode. In addition, in the light emitting display device according to the present specification, the image displayed on the light emitting display panel 100 is updated through each refresh frame of the N-th and N+1-th unit times according to the interlace driving method in the low-speed driving mode in the refresh frame. As the generated luminance drop rate is reduced, the flicker phenomenon generated in the low-speed driving mode may be minimized.

2 is a diagram illustrating a method of driving a gate line group in a normal driving mode of a gate driving circuit according to the present specification.

1 and 2 , the gate driving circuit 700 according to the present specification operates in the normal driving mode according to the mode control signal MCS supplied from the timing controller 300 within a unit time of 1 second (1 second). For each of the included frames F1 to Fn, a gate group driving signal is generated based on the gate control signal GCS supplied from the timing controller 300 to the first to mth gate line groups GLG1 to GLGm. It can be supplied sequentially. For example, when the light emitting display device is driven according to a driving frequency of 60 Hz, the gate driving circuit 700 according to the normal driving mode performs timing in each of the first to 60th frames included within a unit time of 1 second (1 second). A gate group driving signal having an on voltage level Von may be generated based on the gate control signal GCS supplied from the controller 300 and may be sequentially supplied to the first to mth gate line groups GLG1 to GLGm. As such, when the gate driving circuit 700 is driven in the normal driving mode, the image displayed on the light emitting display panel 100 is to be updated for each of the plurality of frames F1 to Fn included within a unit time (1 second). can

3A and 3B are diagrams illustrating a method of driving a gate line group in a low-speed driving mode of a gate driving circuit according to the present specification.

1, 3A, and 3B , the gate driving circuit 700 according to the present specification operates in a low-speed driving mode according to the mode control signal MCS supplied from the timing control unit 300, the timing control unit 300 A gate group driving signal having the on voltage level Von may be generated based on the gate control signal GCS supplied from the , and may be sequentially supplied to a portion of the first to mth gate line groups GLG1 to GLGm. For example, the gate driving circuit 700 according to the low speed driving mode generates a gate group driving signal having an on voltage level Von according to an interlace driving method based on a unit time of 1 second to generate a gate group driving signal of the first to mth gate lines. Groups (GLG1 to GLGm) can be supplied.

According to an example, the gate driving circuit 700 according to the low speed driving mode of the interlace driving method, as shown in FIG. 3A , the timing controller 300 in the refresh frame Fr of the Nth unit time (N second) The odd-numbered gate line groups GLG1, GLG3, and the first to m-th gate line groups GLG1 to GLGm are generated by generating a gate group driving signal of the on voltage level Von based on the gate control signal GCS supplied from … GLGm-1) can be supplied sequentially. As such, when the gate driving circuit 700 is driven in the low-speed driving mode of the interlace driving method, the image displayed on the odd-numbered horizontal line among the images displayed on the light emitting display panel 100 is the N-th unit time (N second). It may be updated in the refresh frame Fr of , and maintained during the hold frame Fh. For example, an image displayed on an odd-numbered horizontal line of the light emitting display panel 100 may be updated every 2 seconds.

In addition, as shown in FIG. 3B , the gate driving circuit 700 according to the low speed driving mode of the interlace driving method has the timing controller 300 in the refresh frame Fr of the N+1th unit time (N+1 second). ) by generating a gate group driving signal of the on voltage level Von based on the gate control signal GCS supplied from the first to mth gate line groups GLG1 to GLGm, and the even-numbered gate line groups GLG2 and GLG4 , ... GLGm) can be supplied sequentially. As such, when the gate driving circuit 700 is driven in the low-speed driving mode of the interlace driving method, the image displayed on the even-numbered horizontal line among the images displayed on the light emitting display panel 100 is the N+1-th unit time (N). +1 second) and may be updated in the refresh frame Fr and maintained during the hold frame Fh. For example, an image displayed on an even-numbered horizontal line of the light emitting display panel 100 may be updated every 2 seconds. Accordingly, when the gate driving circuit 700 is driven in the low-speed driving mode of the interlace driving method, the image displayed on the light emitting display panel 100 is refreshed frame Fr in each of the Nth unit time and the N+1th unit time. ) can be updated over

4A and 4B are views illustrating images updated on a light emitting display panel according to a low speed driving mode in the light emitting display device according to the present specification.

1, 3A, and 4A , in the light emitting display device according to the present specification, the gate driving circuit 700 performs the second refresh frame Fr of the N-th unit time (N second) according to the low-speed driving mode. The gate group driving signal is sequentially supplied to the odd-numbered gate line groups GLG1, GLG3, ... GLGm-1 among the first to m-th gate line groups GLG1 to GLGm, and the data driving circuit 500 is configured to operate the odd-numbered gate line group. A data voltage for each pixel in synchronization with the gate group driving signal sequentially supplied to the groups GLG1, GLG3, ... GLGm-1 may be supplied. Accordingly, the image displayed on the odd-numbered horizontal lines A1, A3, ... Am-1 among the images displayed on the light emitting display panel 100 is updated in the refresh frame Fr of the N-th unit time (N second), and It may be maintained during the hold frame Fh. Here, the image displayed on the odd-numbered horizontal lines A1, A3, ... Am-1 may be maintained until it is updated by the refresh frame Fr of the N+2th unit time.

1, 3B, and 4B, in the light emitting display device according to the present specification, the gate driving circuit 700 performs a refresh frame (N+1 second) of the N+1th unit time (N+1 second) according to the low-speed driving mode. During Fr), the gate group driving signals are sequentially supplied to the even-numbered gate line groups GLG2, GLG4, ... GLGm among the first to m-th gate line groups GLG1 to GLGm, and the data driving circuit 500 operates the even-numbered gate line groups GLG2, GLG4, ... GLGm. A data voltage for each pixel synchronized with the gate group driving signal sequentially supplied to the gate line groups GLG2, GLG4, ... GLGm may be supplied. Accordingly, the image displayed on the even-numbered horizontal lines A2, A4, ... Am among the images displayed on the light emitting display panel 100 is displayed in the refresh frame Fr of the N+1-th unit time (N+1 second). It may be updated and maintained during the hold frame Fh. Here, the image displayed on the even-numbered horizontal lines A2, A4, ... Am may be maintained until it is updated by the refresh frame Fr of the N+3 th unit time.

FIG. 5 is an equivalent circuit diagram of the pixel illustrated in FIG. 1 , which illustrates one pixel disposed on the i-th horizontal line of the light emitting display panel.

1 and 5 , a pixel P according to the present specification may include a light emitting device ELD and a pixel circuit PC.

The light emitting device ELD may emit white light or color light having a predetermined luminance by emitting light in proportion to the size of the data current idata supplied from the pixel circuit PC.

The light emitting device ELD according to an example includes a first electrode (or anode electrode) connected to the pixel circuit PC and a second electrode (or cathode electrode) connected to the pixel common power line Lvss (or a low potential power line). It may include a light emitting layer interposed therebetween. The light emitting layer may include an organic light emitting layer, a quantum dot light emitting layer, an inorganic light emitting layer, or a micro light emitting diode.

The pixel circuit PC emits a data current idata based on the data voltage Vdata supplied to the data line DL in response to a gate group driving signal applied to the gate line group GLGi from the gate driving circuit. By supplying to the element LED, light emission of the light emitting element LED can be controlled.

The gate line group GLGi may include first to fourth gate lines GL1 , GL2 , GL3 , and GL4 . The gate group driving signal is applied to the first gate driving signal GS1 (or the initialization control signal) supplied to the first gate line GL1 (or the initialization control line) and the second gate line GL2 (or the scan control line). The second gate driving signal GS2 (or the scan control signal) supplied, the third gate driving signal GS3 (or the anode reset control signal) supplied to the third gate line GL3 (or the anode reset control line); and a fourth gate driving signal GS4 (or an emission control signal) supplied to the fourth gate line GL4 (or an emission control line).

The pixel circuit PC according to an example may include a driving thin film transistor Tdr, first to sixth transistors T1, T2, T3, T4, T5, and T6, and a storage capacitor Cst.

According to an example, the thin film transistors Tdr, T1, T2, T3, T4, T5, and T6 may be implemented as low-temperature poly-Si (LTPS) thin film transistors having excellent response characteristics. For example, the thin film transistors Tdr, T1, T2, T3, T4, T5, and T6 may be PMOS type LTPS thin film transistors.

According to another example, the thin film transistors Tdr, T1, T2, T3, T4, T5, and T6 may be implemented as oxide thin film transistors having excellent off current characteristics. For example, the thin film transistors Tdr, T1, T2, T3, T4, T5, and T6 may be NMOS-type oxide thin film transistors.

According to another example, at least one thin film transistor of the thin film transistors Tdr, T1, T2, T3, T4, T5, and T6 is implemented as an NMOS type oxide thin film transistor, and the other thin film transistors are implemented as a PMOS type LTPS thin film transistor. can be implemented. For example, the driving thin film transistor Tdr and the third, fourth, and sixth thin film transistors T3, T4, and T6 are implemented as PMOS-type LTPS thin film transistors, and first, second, and fifth thin film transistors (T1, T2, T5) may be implemented as an NMOS-type oxide thin film transistor.

The driving thin film transistor Tdr may control the data current idata flowing through the light emitting device ELD. The driving thin film transistor Tdr according to an example has a gate electrode connected to a first node N1 , a first source/drain electrode connected to a second node N2 , and a second source/drain electrode connected to a third node N3 . A drain electrode may be included. The driving thin film transistor Tdr is turned on according to the voltage between the first node N1 and the second node N2 during the light emission period of the pixel P, whereby the data current idata flowing through the light emitting device ELD is can control

The first thin film transistor T1 may selectively connect the data line DL and the second node N2 in response to the second gate driving signal GS2 supplied to the second gate line GL2 . The first thin film transistor T1 according to an example has a gate electrode connected to the second gate line GL2 , a first source/drain electrode connected to the data line DL, and a second source connected to the second node N2 . /drain electrode may be included. The first thin film transistor T1 is turned on by the second gate driving signal GS2 of the transistor-on voltage level supplied to the second gate line GL2 during the sampling period of the pixel P, and thus the data line DL ) may be supplied to the second node N2 of the data voltage Vdata.

The second thin film transistor T2 may selectively connect the first node N1 and the third node N3 in response to the second gate driving signal GS2 supplied to the second gate line GL2 . The second thin film transistor T2 according to an example has a gate electrode connected to the second gate line GL2 , a first source/drain electrode connected to the first node N1 , and a second connected to the third node N3 . It may include source/drain electrodes. The second thin film transistor T2 is turned on by the second gate driving signal GS2 of the transistor-on voltage level supplied to the second gate line GL2 during the sampling period of the pixel P, thereby forming the first node ( N1) and the third node N3 are electrically connected, and through this, the driving thin film transistor Tdr is connected in the form of a diode.

The third thin film transistor T3 is connected to the pixel driving power line Lvdd (or high potential power line) and the second node N2 in response to the fourth gate driving signal GS4 supplied to the fourth gate line GL4 . can be optionally connected. The third thin film transistor T3 according to an example has a gate electrode connected to the fourth gate line GL4 , a first source/drain electrode connected to the second node N2 , and a first electrode connected to the pixel driving power line Lvdd. Two source/drain electrodes may be included. The third thin film transistor T3 is turned on by the fourth gate driving signal GS4 of the transistor-on voltage level supplied to the fourth gate line GL4 during the light emission period of the pixel P, thereby causing the pixel driving power line The pixel driving voltage EVdd supplied from Lvdd may be supplied to the first source/drain electrodes of the driving thin film transistor Tdr through the second node N2 .

The fourth thin film transistor T4 may selectively connect the third node N3 and the fourth node N4 in response to the fourth gate driving signal GS4 supplied to the fourth gate line GL4 . The fourth thin film transistor T4 according to an example has a gate electrode connected to the fourth gate line GL4 , a first source/drain electrode connected to the third node N3 , and a second electrode connected to the fourth node N4 . It may include source/drain electrodes. The fourth thin film transistor T4 is turned on by the fourth gate driving signal GS4 of the transistor-on voltage level supplied to the fourth gate line GL4 during the light emission period of the pixel P, thereby forming the third node ( The data current Idata supplied from the driving thin film transistor Tdr through N3 may be supplied to the first electrode of the light emitting device ELD through the fourth node N4 .

The fifth thin film transistor T5 may selectively connect the initialization power line Lvini and the first node N1 in response to the first gate driving signal GS1 supplied to the first gate line GL1 . The fifth thin film transistor T5 according to an example has a gate electrode connected to the first gate line GL1 , a first source/drain electrode connected to the first node N1 , and a second connected to the initialization power line Lvini. It may include source/drain electrodes. The fifth thin film transistor T5 is turned on by the first gate driving signal GS1 of the transistor-on voltage level supplied to the first gate line GL1 during the initialization period of the pixel P, and thus the initialization power line ( The initialization power Vini supplied from Lvini) may be supplied to the first node N1.

The sixth thin film transistor T6 may selectively connect the initialization power line Lvini and the fourth node N4 in response to the third gate driving signal GS3 supplied to the third gate line GL3 . The sixth thin film transistor T6 according to an example has a gate electrode connected to the third gate line GL3 , a first source/drain electrode connected to the fourth node N4 , and a second connected to the initialization power line Lvini. It may include source/drain electrodes. The sixth thin film transistor T6 is turned on by the third gate driving signal GS3 of the transistor-on voltage level supplied to the third gate line GL3 during the anode reset period of the pixel P, thereby forming an initialization power line. By supplying the initialization power Vini supplied from Lvini to the fourth node N4, and discharging the voltage of the fourth node N4 to the initialization power line Lvini through this, the first of the light emitting device ELD The voltage of the electrode can be reset.

The storage capacitor Cst may be connected between the pixel driving power line Lvdd and the first node N1 .

Alternatively, each of the second and fifth thin film transistors T2 and T5 connected to the first node N1 may include a dual channel structure. That is, since each of the second and fifth thin film transistors T2 and T5 is electrically connected to the gate electrode of the driving thin film transistor Tdr, a dual-channel structure is used to keep the gate voltage of the driving thin film transistor Tdr constant. can be implemented. According to the dual-channel structure, since the channel length becomes longer than that of the single-gate structure, the off-resistance increases and the off-current decreases, thereby ensuring operation stability. For example, each of the second and fifth thin film transistors T2 and T5 may be implemented as at least two thin film transistors connected in series to each other so as to be simultaneously turned on according to the corresponding gate driving signals GS1 and GS2.

6 is a waveform diagram illustrating a signal according to the first example that is supplied to the pixel shown in FIG. 5 .

5 and 6 , the pixel P according to the first example of the present specification has first to fourth periods t1 in each frame according to the normal driving mode of the gate driving circuit or in the refresh frame according to the low speed driving mode. , t2, t3, t4).

The first period t1 may be an initialization period for initializing the first node N1. For example, the first period t1 may be set to a time corresponding to one horizontal period.

In the first period t1 , the first gate driving signal GS1 supplied to the first gate line GL1 has the on voltage level Von, and the second to fourth gate lines GL2 , GL3 , and GL4 . Each of the gate driving signals GS2 , GS3 , and GS4 supplied to each may have an off voltage level Voff. In addition, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1 . Accordingly, during the first period t1 , only the fifth thin film transistor T5 among the first to sixth thin film transistors T1 , T2 , T3 , T4 , T5 and T6 has the first gate of the on voltage level Von. The voltage of the first node N1 is turned on by the driving signal GS1 so that the first voltage level V1 supplied from the initialization power line Lvini through the turned-on fifth thin film transistor T5 is initialized. It may be initialized to the voltage EVini. In addition, the storage capacitor Cst has a pixel driving voltage EVdd supplied from the pixel driving power line Lvdd and a first voltage level supplied from the initialization power line Lvini through the turned-on fifth thin film transistor T5. It may be initialized with a voltage difference EVdd-Vini between the initialization voltage EVini having (V1).

The second period t2 may be a sampling period following the first period t1 and storing the data voltage Vdata and the threshold voltage of the driving thin film transistor Tdr in the storage capacitor Cst. For example, the second period t2 may be set to a time corresponding to one horizontal period.

In the second period t2 , the second gate driving signal GS2 supplied to the second gate line GL2 has the on voltage level Von, and the first, third, and fourth gate lines GL1 , Each of the gate driving signals GS1 , GS3 , and GS4 supplied to each of GL3 and GL4 may have an off voltage level Voff. Then, the data voltage Vdata is supplied to the data line DL. Also, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1 . Accordingly, during the second period t2, only the first and second thin film transistors T1 and T2 among the first to sixth thin film transistors T1, T2, T3, T4, T5, and T6 have the on voltage level Von. ) is turned on by the second gate driving signal GS2. The voltage of the second node N2 is changed to the data voltage Vdata supplied from the data line DL through the turned-on first thin film transistor T1, and the driving thin film transistor Tdr is the turned-on second thin film transistor T1. As the gate electrode N1 and the second source/drain electrode N3 are short-circuited by the thin film transistor T2, they are connected in a diode form, and thereby the gate electrode of the driving thin film transistor Tdr and the first source/drain electrode A voltage difference equal to the threshold voltage of the driving thin film transistor Tdr may occur therebetween. In other words, the voltage level (Vdata-Vth) lower than the voltage level of the data voltage Vdata applied to the first source/drain electrode N2 of the driving thin film transistor Tdr by the threshold voltage of the driving thin film transistor Tdr. (For example, the threshold voltage compensated data voltage) may be applied to the gate electrode N1 of the driving thin film transistor Tdr, and the storage capacitor Cst may be applied to the gate electrode of the driving thin film transistor Tdr. The voltage Vdata-Vth may be maintained for a preset time.

The third period t3 may be an anode reset period following the second period t2 and discharging the voltage of the fourth node N4 . For example, the third period t3 may be set to a time corresponding to one horizontal period.

In the third period t3, the third gate driving signal GS3 supplied to the third gate line GL3 has the on voltage level Von, and the first, second, and fourth gate lines GL1, Each of the gate driving signals GS1 , GS2 , and GS4 supplied to each of GL2 and GL4 may have an off voltage level Voff. In addition, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1 . Accordingly, during the third period t3 , only the sixth thin film transistor T6 among the first to sixth thin film transistors T1 , T2 , T3 , T4 , T5 , and T6 has the third gate of the on voltage level Von. It is turned on by the driving signal GS3. Accordingly, the voltage of the fourth node N4 may be initialized to the initialization voltage EVini of the first voltage level V1 supplied from the initialization power line Lvini through the turned-on sixth thin film transistor T6. have. In other words, in the third period t3 , the voltage of the fourth node N4 or the voltage of the first electrode of the light emitting device ELD is applied to the initialization power line Lvini through the turned-on sixth thin film transistor T6 . ) may be reset to the initialization voltage EVini of the first voltage level V1.

The fourth period t4 may be a light emitting period following the third period t3 and causing the light emitting device ELD to emit light. For example, in each frame of the normal driving mode, the fourth period t4 may be set to a period other than the first to third periods t1, t2, and t3. In addition, the period other than the first to third periods t1, t2, and t3 in the refresh frame of the low-speed driving mode may be set, but is not limited thereto, and the fourth period t4 is the hold in the low-speed driving mode. It can also be set as a frame.

In the fourth period t4 , the fourth gate driving signal GS4 supplied to the fourth gate line GL4 has the on voltage level Von, and the first to third gate lines GL1 , GL2 , and GL3 . Each of the gate driving signals GS1 , GS2 , and GS3 supplied to each may have an off voltage level Voff. In addition, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1 .

During the fourth period t4 , only the third and fourth thin film transistors T3 and T4 among the first to sixth thin film transistors T1 , T2 , T3 , T4 , T5 , and T6 have the on-voltage level Von. 4 It is turned on by the gate driving signal GS4. Accordingly, the voltage of the second node N2 is changed to the pixel driving voltage EVdd supplied from the pixel driving power line Lvdd through the turned-on third thin film transistor T3, and the first node N1 maintains the data voltage Vdata-Vth for which the threshold voltage of the driving thin film transistor Tdr is compensated by the storage capacitor Cst, and the second source/drain electrodes of the driving thin film transistor Tdr are turned on. It may be connected to the first electrode of the light emitting device ELD through the fourth thin film transistor T4 .

Therefore, during the fourth period t4, the driving thin film transistor Tdr is a voltage EVdd-(Vdata-|Vth) obtained by subtracting the threshold voltage Vth from the gate-source voltage EVdd-(Vdata-|Vth|). A data current idata proportional to the square ((EVdd-(Vdata-|Vth|)-|Vth|)2) of |)-|Vth|) is output, and the data current outputted from the driving thin film transistor Tdr (idata) may be supplied to the light emitting device ELD through the turned-on fourth thin film transistor T4 . As a result, during the fourth period t4 , the data current idata flowing through the light emitting device ELD is not affected by the threshold voltage of the driving thin film transistor Tdr. A threshold voltage deviation between the driving thin film transistors Tdr may be minimized.

As described above, in the method of driving the pixel P according to the first example of the present specification, the threshold voltage of the driving thin film transistor Tdr can be compensated, and through this, the driving thin film transistor Tdr provided in each of the plurality of pixels P. ) can minimize the deterioration of image quality due to the threshold voltage deviation between them.

FIG. 7 is a waveform diagram showing a signal according to the second example that is supplied to the pixel shown in FIG. 5 , which is a change in the third period in the method of driving the pixel shown in FIG. 6 .

5 and 7 , the pixel P according to the second example of the present specification is displayed in the first to fourth periods t1, t2, t3, and t4 in the refresh frame according to the low-speed driving mode of the gate driving circuit. can be operated.

Since each of the first period t1 and the second period t2 is substantially the same as each of the first period t1 and the second period t2 illustrated in FIG. 6 , a redundant description thereof will be omitted.

The third period t3 may be an anode voltage boost period following the second period t2 and increasing the voltage of the fourth node N4 . For example, the third period t3 may be set to a time corresponding to one horizontal period.

In the third period t3, the third gate driving signal GS3 supplied to the third gate line GL3 has the on voltage level Von, and the first, second, and fourth gate lines GL1, Each of the gate driving signals GS1 , GS2 , and GS4 supplied to each of GL2 and GL4 may have an off voltage level Voff. In addition, the initialization voltage EVini supplied to the initialization power line Lvini may be changed to a second voltage level V2 higher than the first voltage level V1 . Accordingly, during the third period t3 , only the sixth thin film transistor T6 among the first to sixth thin film transistors T1 , T2 , T3 , T4 , T5 , and T6 has the third gate of the on voltage level Von. It is turned on by the driving signal GS3. Accordingly, the voltage of the fourth node N4 may be changed to the initialization voltage EVini of the second voltage level V2 supplied from the initialization power line Lvini through the turned-on sixth thin film transistor T6. have. In other words, in the third period t3 , the voltage of the fourth node N4 or the voltage of the first electrode of the light emitting device ELD is applied to the initialization power line Lvini through the turned-on sixth thin film transistor T6 . ) is changed to the second voltage level V2 of the initialization voltage EVini supplied from ), thereby preventing a decrease in luminance of the light emitting device ELD according to the initialization voltage EVini. For example, during the third period t3 of the refresh frame of the low-speed driving mode, the voltage of the fourth node N4 increases from the first voltage level V1 of the initialization voltage EVini to the second voltage level V2. By doing so, the luminance of the light emitting device ELD is maintained without being lowered toward black, thereby preventing or minimizing the luminance degradation of the light emitting device ELD occurring in the refresh frame in the low speed driving mode.

The fourth period t4 is a light emitting period that follows the third period t3 and causes the light emitting device ELD to emit light, which is substantially the same as the fourth period t4 shown in FIG. omit

As described above, in the method of driving the pixel P according to the second example of the present specification, the threshold voltage of the driving thin film transistor Tdr can be compensated, and through this, the driving thin film transistor Tdr provided in each of the plurality of pixels P. ) can minimize the deterioration of image quality due to the threshold voltage deviation between them. Also, in the method of driving the pixel P according to the second example of the present specification, the initialization voltage EVini is changed from the first voltage level V1 to the second voltage level V2 during the third period t3, so that the low speed A decrease in luminance of the light emitting device ELD occurring in the refresh frame in the driving mode may be prevented or minimized.

FIG. 8 is a waveform diagram showing a signal according to a third example that is supplied to the pixel shown in FIG. 5 , which is a change in the third period in the method of driving the pixel shown in FIG. 6 .

5 and 8 , the pixel P according to the third example of the present specification is displayed in the first to fourth periods t1, t2, t3, and t4 in the refresh frame according to the low-speed driving mode of the gate driving circuit. can be operated.

Since each of the first period t1 and the second period t2 is substantially the same as each of the first period t1 and the second period t2 illustrated in FIG. 6 , a redundant description thereof will be omitted.

The third period t3 may be an anode voltage maintenance period in which the voltage of the fourth node N4 is maintained following the second period t2 . For example, the third period t3 may be set to a time corresponding to one horizontal period.

In the third period t3 , each of the gate driving signals GS1 , GS2 , GS3 and GS4 supplied to each of the first to fourth gate lines GL1 , GL2 , GL3 and GL4 has an off voltage level Voff. can In addition, the initialization voltage EVini supplied to the initialization power line Lvini may be changed to the first voltage level V1 . Accordingly, during the third period t3 , all of the first to sixth thin film transistors T1 , T2 , T3 , T4 , T5 , and T6 turn off the gate driving signals GS1 , GS2 , GS3 , It is turned off by GS4). Accordingly, the voltage of the fourth node N4 may be maintained without being discharged. In other words, in the third period t3, the voltage of the fourth node N4 or the voltage of the first electrode of the light emitting device ELD is not discharged according to the turn-off state of the sixth thin film transistor T6. As it is maintained, a decrease in luminance of the light emitting device ELD according to the initialization voltage EVini may be prevented. For example, during the third period t3 of the refresh frame in the low-speed driving mode, the voltage of the fourth node N4 is maintained as it is without being discharged to the initialization voltage EVini of the first voltage level V1. The luminance of the ELD is maintained as it is without being lowered toward black, so that the luminance deterioration of the light emitting device ELD occurring in the refresh frame in the low-speed driving mode may be prevented or minimized.

The fourth period t4 is a light emitting period that follows the third period t3 and causes the light emitting device ELD to emit light, which is substantially the same as the fourth period t4 shown in FIG. omit

As described above, the method of driving the pixel P according to the third example of the present specification may compensate for the threshold voltage of the driving thin film transistor Tdr, and through this, the driving thin film transistor Tdr provided in each of the plurality of pixels P. ) can minimize the deterioration of image quality due to the threshold voltage deviation between them. In addition, in the method of driving the pixel P according to the third example of the present specification, the voltage of the first electrode of the light emitting device ELD is maintained as it is during the third period t3 , so that light emission generated in the refresh frame of the low speed driving mode A decrease in luminance of the device ELD may be prevented or minimized.

FIG. 9 is a waveform diagram showing a signal according to a fourth example that is supplied to the pixel shown in FIG. 5 , which is a change in the second period in the method of driving the pixel shown in FIG. 6 .

5 and 9 , the pixel P according to the fourth example of the present specification is displayed in the first to fourth periods t1, t2, t3, and t4 in the refresh frame according to the low-speed driving mode of the gate driving circuit. can be operated.

Since the first period t1 is substantially the same as the first period t1 illustrated in FIG. 6 , a redundant description thereof will be omitted.

The second period t2 may be a sampling period following the first period t1 and storing the data voltage Vdata and the threshold voltage of the driving thin film transistor Tdr in the storage capacitor Cst. For example, the second period t2 may be set to a time corresponding to two horizontal periods.

In the second period t2 , the second gate driving signal GS2 supplied to the second gate line GL2 has the on voltage level Von for two horizontal periods, and the first, third, and fourth gates Each of the gate driving signals GS1 , GS3 , and GS4 supplied to each of the lines GL1 , GL3 , and GL4 may have an off voltage level Voff. In addition, the data line DL may sequentially receive a dummy data voltage Vdata corresponding to the dummy digital data DD for each pixel and an actual data voltage Vdata corresponding to the actual digital data OD for each pixel. . Also, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1 .

The second period t2 may be time-divided into a 2-1 period t2-1 and a 2-2 period t2-2.

The 2-1 period t2-1 is the first half of the second period t2, and the dummy data voltage Vdata is supplied to the second node N2 to charge the pixel P with the dummy data voltage Vdata. may be defined as a dummy data charging period or a preliminary charging period. The second period t2-2 is the second half of the second period t2, and the actual data voltage Vdata is applied to the second node N2. It may be defined as an actual data charging period or a main charging period in which the actual data voltage Vdata is supplied to the pixel P to be charged.

The dummy data voltage Vdata may have a higher voltage level than the actual data voltage Vdata. For example, when the actual digital data OD has a grayscale value of 0 to 31, the dummy digital data DD has a grayscale value higher than the actual digital data OD having a grayscale value of 0 to 31 by a grayscale value of 5. can have When the actual digital data OD has a grayscale value of 32 to 63, the dummy digital data DD may have a grayscale value higher than the actual digital data OD having a grayscale value of 32 to 63 by a grayscale value of 10. . When the actual digital data OD has a grayscale value of 64 to 127, the dummy digital data DD may have a grayscale value higher than the actual digital data OD having a grayscale value of 64 to 127 by a grayscale value of 15. . When the actual digital data OD has a grayscale value of 128 to 255, the dummy digital data DD may have a grayscale value higher than the actual digital data OD having a grayscale value of 128 to 255 by a grayscale value of 20, , in this case, when the actual digital data OD has a grayscale value of 235 or more, the dummy digital data DD may have a grayscale value of 255.

During the second period t2 , only the first and second thin film transistors T1 and T2 among the first to sixth thin film transistors T1 , T2 , T3 , T4 , T5 , and T6 have the on-voltage level Von. It is turned on for 2 horizontal periods by the 2 gate driving signal GS2. The driving thin film transistor Tdr is connected in a diode form as the gate electrode N1 and the second source/drain electrodes N3 are shorted by the turned-on second thin film transistor T2, and thus the driving thin film transistor ( A voltage difference equal to the threshold voltage of the driving thin film transistor Tdr may occur between the gate electrode of the Tdr and the first source/drain electrodes. In other words, the voltage level (Vdata-Vth) lower than the voltage level of the data voltage Vdata applied to the first source/drain electrode N2 of the driving thin film transistor Tdr by the threshold voltage of the driving thin film transistor Tdr. (For example, the threshold voltage compensated data voltage) may be applied to the gate electrode N1 of the driving thin film transistor Tdr, and the storage capacitor Cst may be applied to the gate electrode of the driving thin film transistor Tdr. The voltage Vdata-Vth may be maintained for a preset time.

For example, during the 2-1 th period t2-1 of the second period t2, the voltage of the second node N2 is supplied from the data line DL through the turned-on first thin film transistor T1. The dummy applied to the first source/drain electrode N2 is applied to the gate electrode of the driving thin film transistor Tdr connected in a diode form by the second thin film transistor T2 turned on by being changed to the dummy data voltage Vdata. A voltage level Vdata-Vth lower than the voltage level of the data voltage Vdata by the threshold voltage of the driving thin film transistor Tdr may be applied. Accordingly, the storage capacitor Cst may store the dummy data voltage Vdata and the threshold voltage of the driving thin film transistor Tdr. For example, the storage capacitor Cst may store a voltage level Vdata-Vth that is lower than the voltage level of the dummy data voltage Vdata by the threshold voltage of the driving thin film transistor Tdr.

During the second period t2 - 2 of the second period t2 , the voltage of the second node N2 is the actual data voltage supplied from the data line DL through the turned-on first thin film transistor T1 . The actual data voltage Vdata applied to the first source/drain electrode N2 has the gate electrode of the driving thin film transistor Tdr connected in a diode form by the second thin film transistor T2 turned on by being changed to (Vdata). A voltage level Vdata-Vth lower by the threshold voltage of the driving thin film transistor Tdr than the voltage level of ) may be applied. Accordingly, the storage capacitor Cst may store a voltage level Vdata-Vth that is lower than the voltage level of the actual data voltage Vdata by the threshold voltage of the driving thin film transistor Tdr, and the gate of the driving thin film transistor Tdr. The voltage (Vdata-Vth) applied to the electrode may be maintained for a preset time.

Since each of the third period t3 and the fourth period t4 is substantially the same as each of the third period t3 and the fourth period t4 illustrated in FIG. 6 , a redundant description thereof will be omitted.

As described above, in the method of driving the pixel P according to the fourth example of the present specification, the threshold voltage of the driving thin film transistor Tdr can be compensated, and through this, the driving thin film transistor Tdr provided in each of the plurality of pixels P. ) can minimize the deterioration of image quality due to the threshold voltage deviation between them. And, in the method of driving the pixel P according to the fourth example of the present specification, a preliminary charging period t2- in which the dummy data voltage Vdata is applied before the actual data voltage Vdata is applied during the second period t2. 1) shortens the charging time of the data voltage Vdata or implements fast charging of the data voltage Vdata through 1), so that the luminance of the light emitting device ELD due to the slow charging of the data voltage generated in the refresh frame of the low-speed driving mode degradation can be prevented or minimized.

Additionally, in the method of driving the pixel P according to the fourth example of the present specification, in the third period t3 , the initialization voltage EVini is set at the first voltage level V1 as shown in FIG. 7 . ) to the second voltage level V2. In this case, in the method of driving the pixel P according to the fourth example of the present specification, the initialization voltage EVini is changed from the first voltage level V1 to the second voltage level V2 during the third period t3. It is possible to prevent or minimize a decrease in luminance of the light emitting device ELD that occurs in the refresh frame in the low-speed driving mode.

Optionally, in the method of driving the pixel P according to the fourth example of the present specification, the first to sixth thin film transistors T1, T2, T3, T4, T5, and T6 in the third period t3 include: As shown in FIG. 8 , both may maintain a turned-off state. In this case, in the method of driving the pixel P according to the fourth example of the present specification, the voltage of the first electrode of the light emitting device ELD is maintained as it is during the third period t3, so that it is generated in the refresh frame of the low speed driving mode. A decrease in brightness of the light emitting device ELD may be prevented or minimized.

FIG. 10 is a waveform diagram illustrating a signal according to a fifth example that is supplied to the pixel shown in FIG. 5 .

5 and 10 , the pixel P according to the fifth example of the present specification has a first to third period t1 in each frame according to the normal driving mode of the gate driving circuit or a refresh frame according to the low speed driving mode. , t2, t3).

Since the first period t1 is substantially the same as the first period t1 illustrated in FIG. 6 , a redundant description thereof will be omitted.

The second period t2 is followed by the first period t1, a sampling period in which the data voltage Vdata and the threshold voltage of the driving thin film transistor Tdr are stored in the storage capacitor Cst, and the voltage of the fourth node N4 It may be an anode reset period that discharges . For example, the second period t2 may be set to a time corresponding to one horizontal period.

In the second period t2 , the second gate driving signal GS2 supplied to the second gate line GL2 has the on voltage level Von and the third gate driving signal supplied to the third gate line GL3 is The signal GS3 may have an on voltage level Von, and each of the gate driving signals GS1 and GS4 supplied to the first and fourth gate lines GL1 and GL4 may have an off voltage level Voff. . Then, the data voltage Vdata is supplied to the data line DL. Also, the initialization voltage EVini supplied to the initialization power line Lvini may be maintained at the first voltage level V1 . Accordingly, during the second period t2, among the first to sixth thin film transistors T1, T2, T3, T4, T5, and T6, the first and second thin film transistors T1 and T2 and the sixth thin film transistor ( Only T6 is turned on by the gate driving signals GS2 and GS3 of the on voltage level Von. The voltage of the second node N2 is changed to the data voltage Vdata supplied from the data line DL through the turned-on first thin film transistor T1, and the driving thin film transistor Tdr is the turned-on second thin film transistor T1. As the gate electrode N1 and the second source/drain electrode N3 are short-circuited by the thin film transistor T2, they are connected in a diode form, and thereby the gate electrode of the driving thin film transistor Tdr and the first source/drain electrode A voltage difference equal to the threshold voltage of the driving thin film transistor Tdr may occur therebetween. In other words, the voltage level Vdata-Vth lower than the voltage level of the data voltage Vdata applied to the first source/drain electrode N2 of the driving thin film transistor Tdr by the threshold voltage of the driving thin film transistor Tdr. (For example, the threshold voltage compensated data voltage) may be applied to the gate electrode N1 of the driving thin film transistor Tdr, and the storage capacitor Cst may be applied to the gate electrode of the driving thin film transistor Tdr. The voltage Vdata-Vth may be maintained for a preset time.

And, during the second period t2 , the voltage of the fourth node N4 is the initialization voltage of the first voltage level V1 supplied from the initialization power line Lvini through the turned-on sixth thin film transistor T6 . It can be initialized to (EVini). In other words, in the third period t2 , the voltage of the fourth node N4 or the voltage of the first electrode of the light emitting device ELD is applied to the initialization power line Lvini through the turned-on sixth thin film transistor T6 . ) may be reset to the initialization voltage EVini of the first voltage level V1.

The third period t3 is a light emitting period following the second period t2 and causing the light emitting device ELD to emit light, which is substantially the same as the fourth period t4 shown in FIG. omit

As such, the driving method of the pixel P according to the fifth example of the present specification may have the same effect as the driving method of the pixel P according to the first example of the present specification, and the second gate driving signal GS2 Since and the third gate driving signal GS3 are implemented as the same signal, either the second gate line GL2 or the third gate line GL3 may be omitted, and thus the structure of the pixel P and the gate The structure of the driving circuit can be simplified.

Additionally, in the method of driving the pixel P according to the fifth example of the present specification, in the second period t2 , the initialization voltage EVini is set at the first voltage level V1 as shown in FIG. 11 . ) to the second voltage level V2. In this case, in the method of driving the pixel P according to the fifth example of the present specification, the initialization voltage EVini is changed from the first voltage level V1 to the second voltage level V2 during the third period t3. It is possible to prevent or minimize a decrease in luminance of the light emitting device ELD that occurs in the refresh frame in the low-speed driving mode.

Optionally, in the method of driving the pixel P according to the fifth example of the present specification, the second period t2 includes a 2-1 th period t2-1 and a 2-th period t2 as shown in FIG. 12 . It may be time-divided into two periods t2-2. In this case, in the method of driving the pixel P according to the fifth example of the present specification, the second period t2 is substantially the same as the second period t2 shown in FIG. omit Accordingly, in the method of driving the pixel P according to the fifth example of the present specification, the preliminary charging period t2 in which the dummy data voltage Vdata is applied before the actual data voltage Vdata is applied during the second period t2. -1) to shorten the charging time of the data voltage Vdata or implement fast charging of the data voltage Vdata, thereby reducing the light emitting device ELD due to the slow charging of the data voltage generated in the refresh frame of the low-speed driving mode. It is possible to prevent or minimize the decrease in luminance.

13 is a diagram illustrating a gate driving circuit according to the present specification, and this is for explaining the gate driving circuit shown in FIG. 1 .

1 and 13 , the gate driving circuit 700 according to the present specification may include a shift register 710 and a mode control circuit 730 .

The shift register 710 may output gate group driving signals for driving each of the first to mth gate line groups GLG1 to GLGm according to a predetermined order. For example, the shift register 710 converts a corresponding shift clock signal from among a plurality of shift clock signals CLK1 to CLK8 supplied from each of a plurality of gate clock lines in response to a plurality of start signals Vst to a gate driving signal. can be printed out.

The shift register 710 according to an example may include first to m-th stage blocks SB1 to SBm.

Each of the first to mth stage blocks SB1 to SBm is selectively connected to the first to eighth gate clock lines, and a stage driving voltage line to which the stage driving voltage GVdd is supplied and a stage common voltage GVss are supplied. and may be commonly connected to each of the stage driving voltage lines. For example, some (or odd-numbered) stage blocks SB1 , SB3 , ... SBm-1 among the first to m-th stage blocks SB1 to SBm may include some (or odd-numbered) stage blocks of the first to eighth gate clock lines ) to the clock line. The remaining (or even-numbered) stage blocks SB2, SB4, ... SBm among the first to m-th stage blocks SB1 to SBm may be connected to the remaining (or even-numbered) clock lines among the first to eighth gate clock lines. have.

According to an example, each of the first to eighth shift clock signals CLK1 to CLK8 individually supplied to each of the first to eighth gate clock lines may include an on voltage period and an off voltage period that are cyclically repeated at a constant cycle. have. The on voltage period may have a voltage level capable of turning on the transistor, and the off voltage period may have a voltage level capable of turning off the transistor.

Each of the on voltage period and the off voltage period of each of the first and second shift clock signals CLK1 and CLK2 may correspond to one horizontal period in each of the normal driving mode and the low speed driving mode. Each of the first and second shift clock signals CLK1 and CLK2 may be used to generate a first gate driving signal or a first scan signal to be supplied to the first gate line of the gate line group GLG.

Each of the on voltage period and the off voltage period of each of the third and fourth shift clock signals CLK3 and CLK4 may correspond to one horizontal period in the normal driving mode, and may correspond to one horizontal period or two horizontal periods in the low speed driving mode. can be Each of the third and fourth shift clock signals CLK3 and CLK4 may be used to generate a second gate driving signal or a second scan signal to be supplied to the second gate line of the gate line group GLG. In the low-speed driving mode according to an example, the pixel P operates in the first to fourth periods t1, t2, t3, and t4 shown in FIGS. 6 to 8 or the first to fourth periods shown in FIGS. 10 and 11 . When operating in the first to third periods t1, t2, and t3, the on voltage period and the off voltage period of each of the third and fourth shift clock signals CLK3 and CLK4 may correspond to one horizontal period. In the low-speed driving mode according to another example, the pixel P operates in the first to fourth periods t1, t2, t3, and t4 shown in FIG. 9 or the first to third periods shown in FIG. 12 ( When operating at t1, t2, and t3), each of the on voltage period and the off voltage period of each of the third and fourth shift clock signals CLK3 and CLK4 may correspond to two horizontal periods.

Each of the on voltage period and the off voltage period of each of the fifth and sixth shift clock signals CLK5 and CLK6 may correspond to one horizontal period in the normal driving mode, and may correspond to one horizontal period or two horizontal periods in the low speed driving mode. can be Each of the fifth and sixth shift clock signals CLK5 and CLK6 may be used to generate a third gate driving signal or a third scan signal to be supplied to the third gate line of the gate line group GLG. In the low-speed driving mode according to an example, the pixel P operates in the first to fourth periods t1, t2, t3, and t4 shown in FIGS. 6, 7 and 9 or in FIGS. 10 and 11 . When operating in the illustrated first to third periods t1, t2, and t3, the on voltage period and the off voltage period of each of the fifth and sixth shift clock signals CLK5 and CLK6 may correspond to one horizontal period. can In the low-speed driving mode according to another example, when the pixel P operates in the first to fourth periods t1, t2, t3, and t4 illustrated in FIG. 8 , the third and fourth shift clock signals CLK5 , CLK6) each may include only an off voltage period. In the low-speed driving mode according to still another example, when the pixel P operates in the first to third periods t1, t2, and t3 shown in FIG. 12 , the fifth and sixth shift clock signals CLK5, CLK6) Each on-voltage period and each off-voltage period may correspond to two horizontal periods.

Each of the on voltage period and the off voltage period of each of the seventh and eighth shift clock signals CLK7 and CLK8 may correspond to 2 horizontal periods or 3 horizontal periods in the normal driving mode, and 2 horizontal periods and 3 in the low speed driving mode. It may correspond to a horizontal period, or 4 horizontal periods. Each of the seventh and eighth shift clock signals CLK7 and CLK8 may be used to generate a fourth gate driving signal or an emission control signal to be supplied to the fourth gate line of the gate line group GLG.

In the normal driving mode according to an example, when the pixel P operates in the first to fourth periods t1, t2, t3, and t4 illustrated in FIG. 6 , the seventh and eighth shift clock signals CLK7 , CLK8) Each on-voltage period and each off-voltage period may correspond to three horizontal periods. In the normal driving mode according to another example, when the pixel P operates in the first to third periods t1, t2, and t3 illustrated in FIG. 10 , the seventh and eighth shift clock signals CLK7 and CLK8 ) each of the on-voltage period and each of the off-voltage period may correspond to two horizontal periods.

In the low-speed driving mode according to an example, when the pixel P operates in the first to fourth periods t1, t2, t3, and t4 shown in FIGS. 6 to 8 , the seventh and eighth shifts Each of the on voltage period and the off voltage period of each of the clock signals CLK7 and CLK8 may correspond to three horizontal periods. In the low-speed driving mode according to another example, when the pixel P operates in the first to fourth periods t1, t2, t3, and t4 shown in FIG. 9, the seventh and eighth shift clock signals ( Each of the on-voltage periods and the off-voltage periods of CLK7 and CLK8) may correspond to 4 horizontal periods. In the low-speed driving mode according to still another example, when the pixel P operates in the first to third periods t1, t2, and t3 shown in FIGS. 10 to 12, the seventh and eighth shift clocks Each of the on-voltage period and the off-voltage period of each of the signals CLK7 and CLK8 may correspond to two horizontal periods.

According to an example, some (or odd-numbered) stage blocks SB1 , SB3 , ... SBm-1 among the first to m-th stage blocks SB1 to SBm are some (or odd-numbered) of the first to eighth gate clock lines. (th) may be connected to the gate clock line. The remaining (or even-numbered) stage blocks SB2, SB4, ... SBm among the first to m-th stage blocks SB1 to SBm are connected to the remaining (or even-numbered) gate clock lines of the first to eighth gate clock lines. can be connected

Each of the first to mth stage blocks SB1 to SBm is a shift clock of an on voltage period supplied to a corresponding gate clock line based on the start signal Vst, the stage driving voltage GVdd, and the stage common voltage GVss. The signals CLK1 to CLK8 may be output as gate driving signals.

According to an example, the first stage block SB1 is provided from the start signal Vst provided from the timing controller 300 in the normal driving mode or the timing controller 300 in the refresh frame of the Nth unit time in the low speed driving mode. A gate group driving signal corresponding to the shift clock signals CLK1, CLK3, CLK5, and CLK7 supplied from some (or odd-numbered) clock lines among the first to eighth gate clock lines is generated in response to the start signal Vst. One gate line group GLG1 may be supplied.

According to an example, the second stage block SB2 is generated from the start signal supplied through the mode control circuit 730 in the normal driving mode or the timing controller 300 in the refresh frame of the N+1th unit time in the low speed driving mode. Driving a gate group corresponding to the shift clock signals CLK2, CLK4, CLK6, and CLK8 supplied from some (or even-numbered) gate clock lines of the first to eighth gate clock lines in response to the provided start signal Vst A signal may be supplied to the second gate line group GLG2 .

Each of the third to mth stage blocks SB3 to SBm is a shift clock signal CLK1 supplied from a corresponding one of the first to eighth gate clock lines in response to a start signal supplied from the mode control circuit 730 . The gate group driving signals corresponding to the to CLK8 may be sequentially supplied to the third to mth gate line groups GLG3 to GLGm. For example, each of the third to mth stage blocks SB3 to SBm may be dependently connected to each other through the mode control circuit 730 .

In response to the mode control signal MCS, the mode control circuit 730 generates an i-th (i is a natural number from any one of 1 to m-1) stage blocks SBi among the first to m-th stage blocks SB1 to SBm. Normal driving mode or low-speed driving of the gate driving circuit 700 by supplying the gate group driving signal output from the to the i+1th stage block SBi+1 or the i+2th stage block SBi+2 as a start signal mode can be controlled.

The mode control signal MCS may include a first mode control signal MCS1 for a normal driving mode and a second mode control signal MCS2 for a low speed driving mode. As an example, when the gate driving circuit 700 operates in the normal driving mode, the first mode control signal MCS1 may have a first logic voltage level (or low voltage level) capable of turning on the transistor. and the second mode control signal MCS2 may have a second logic voltage level (or high voltage level) capable of turning off the transistor. As another example, when the gate driving circuit 700 operates in the low speed driving mode, the first mode control signal MCS1 may have a second logic voltage level (or a low voltage level), and the second mode control signal MCS1 MCS2) may have a first logic voltage level or a second logic voltage level according to a unit time. For example, when the gate driving circuit 700 operates in the low speed driving mode, the second mode control signal MCS2 may have a first logic voltage level for an N th unit time, and for an N+1 th unit time. It may have a second logic voltage level.

The mode control circuit 730 according to an example may include a first switching unit 731 , an inverter circuit 733 , and a second switching unit 735 .

The first switching unit 731 may be implemented to control the gate driving circuit 700 in the normal driving mode. The first switching unit 731 supplies the gate group driving signal output from the i-th stage block SBi to the i+1-th stage block SBi+1 as a start signal in response to the first mode control signal MCS1. can Accordingly, the first stage block SB1 is driven by the start signal Vst provided from the timing controller 300 , and each of the second to mth stage blocks SB1 to SBm is a first mode control signal MCS1 . Accordingly, it may be driven in the normal driving mode by sequentially driving in response to the start signal Vst supplied through the first switching unit 731 .

The first switching unit 731 may include first to j-th (j is m−1) transistor units TU1 to TUj disposed between the first to m-th stage blocks SB1 to SBm.

Each of the first to j-th transistor units TU1 to TUj uses the gate group driving signal output from the i-th stage block SBi in response to the first mode control signal MCS1 as a start signal to the i+1-th stage block ( SBi+1) can be supplied. For example, the first transistor unit TU1 is turned on according to the first logic voltage level and supplies the gate group driving signal output from the first stage block SB1 to the second stage block SB2 as a start signal. can Similarly, the second to j-th transistor units TU2 to TUj are turned on according to the first mode control signal MCS of the first logic voltage level, and the second to m-1 th stage blocks SB2 to SBm- 1) The gate group driving signal output from each may be supplied as a start signal to the third to mth stage blocks SB3 to SBm, respectively. Accordingly, each of the first to mth stage blocks SB1 to SBm is turned on according to the start signal Vst provided from the timing controller 300 and the first mode control signal MCS of the first logic voltage level. It is sequentially driven in response to the start signal Vst that is sequentially supplied through the first switching unit 731 , and thus the gate driving circuit 700 may be driven in the normal driving mode illustrated in FIG. 2 .

The inverter circuit 733 may invert the second mode control signal MCS2 provided from the timing controller 300 to output the third mode control signal MCS3 . The inverter circuit 733 may output the third mode control signal MCS3 in which the logic level of the second mode control signal MCS2 is inverted. For example, the inverter circuit 733 may invert the second mode control signal MCS2 of the second logic voltage level to output the third mode control signal MCS3 having the first logic voltage level. Conversely, the inverter circuit 733 may invert the second mode control signal MCS2 of the first logic voltage level to output the third mode control signal MCS3 having the second logic voltage level.

The second switching unit 735 may be implemented to control the gate driving circuit 700 in a low speed driving mode. For example, the second switching unit 735 may be implemented to control the gate driving circuit 700 in an interlaced driving mode in a low speed driving mode.

The second switching unit 735 uses the gate group driving signal output from the i-th stage block SBi as a start signal in response to the second mode control signal MCS2 and the third mode control signal MCS3 as a start signal (i+2 th). It can be supplied to the stage block (SBi+2). Accordingly, the first to m-th stage blocks SB1 to SBm are configured according to the start signal Vst, the second mode control signal MCS2 and the third mode control signal MCS3 provided from the timing controller 300 . 2 In response to a start signal supplied through the switching unit 735 , they are sequentially driven according to the interlace driving method, so that they may be driven in the low speed driving mode of the interlace driving method.

The second switching unit 735 may include first to j-th switching units SU1 to SUj disposed between the first to m-th stage blocks SB1 to SBm.

The first to j-th switching units SU1 to SUj may be grouped into a first switching group switched according to the second mode control signal MCS2 and a second switching group switched according to the third mode control signal MCS3. have. For example, some (or odd-numbered) of the first to j-th switching units SU1 to SUj are grouped into a first switching group switched according to the second mode control signal MCS2, and the first to j-th switching units The remaining (or even-numbered) of the units SU1 to SUj may be grouped into a second switching group that is switched according to the third mode control signal MCS3 . In other words, the 2k-1 (k is 1 to j/2) switching units SU2k-1 among the first to j-th switching units SU1 to SUj are grouped into the first switching group, The 2k second switching units SU2k among the j switching units SU1 to SUj may be grouped into a second switching group.

The 2k-1th switching unit SU2k-1 according to an example includes a 2y-1 (y is 1 to m/2) stage block SB2y-1 among the first to mth stage blocks SB1 to SBm and It may be connected between the 2y+1th stage blocks SB2y+1. The 2k-1th switching unit SU2k-1 uses the gate group driving signal output from the 2y-1th stage block SB2y-1 as a start signal in response to the second mode control signal MCS2 as a start signal for the 2y+1th stage It can be supplied to the block SB2y+1. Accordingly, the 2y-1th stage block SB2y-1 among the first to mth stage blocks SB1 to SBm includes the start signal Vst and the second mode control signal MCS2 provided from the timing controller 300 . Accordingly, the second switching unit 735 is sequentially driven in response to the start signal Vst supplied through the 2k-1 switching unit SU2k-1 (or the first switching group), so that the interlace driving method low-speed driving mode can be driven. For example, the 2y-1th stage block SB2y-1 among the first to mth stage blocks SB1 to SBm is a start provided from the timing controller 300 during the refresh frame of the Nth unit time in the low speed driving mode. The start signal Vst supplied through the 2k-1st switching unit SU2k-1 (or the first switching group) of the second switching unit 735 according to the signal Vst and the second mode control signal MCS2 is sequentially driven in response to , so that the gate driving circuit 700 may be driven in the low-speed driving mode of the interlace driving method shown in FIG. 3A .

The 2k-th switching unit SU2k according to an example may be connected between the 2y-th stage block SB2y and the 2y+2-th stage block SB2y+2 among the first to m-th stage blocks SB1 to SBm. Accordingly, the 2y-th stage block SB2y among the first to m-th stage blocks SB1 to SBm is configured to be a second stage block SB2y according to the start signal Vst and the third mode control signal MCS3 provided from the timing controller 300 . By being sequentially driven in response to a start signal supplied through the 2k-th switching unit SU2k (or the second switching group) of the switching unit 735 , it may be driven in an interlaced driving mode in a low-speed driving mode. For example, the 2y-th stage block SB2y among the first to m-th stage blocks SB1 to SBm has a start signal ( ) provided from the timing controller 300 during the refresh frame of the N+1-th unit time in the low-speed driving mode. Vst) and the third mode control signal MCS3, sequentially driven in response to a start signal supplied through the 2k switching unit SU2k (or the second switching group) of the second switching unit 735, thereby Therefore, the gate driving circuit 700 may be driven in the low speed driving mode of the interlace driving method shown in FIG. 3B .

FIG. 14 is a diagram illustrating a first stage block, a first transistor unit, and a first switching unit shown in FIG. 13 .

1, 13 and 14 , the first stage block SB1 of the shift register 710 of the gate driving circuit according to the present specification includes first to fourth start signals ( of the first, third, fifth, and seventh shift clock signals CLK1, CLK3, CLK5, and CLK7 supplied to the first, third, fifth, and seventh gate clock lines respectively in response to Vst1, Vst2, Vst3, and Vst4, respectively. Each of the first to fourth gate driving signals GS1 , GS2 , GS3 and GS4 corresponding to the on voltage period is applied to the first to fourth gate lines GL1 , GL2 , GL3 and GL4 of the first gate line group GLG1 , respectively. Each can be supplied.

The first stage block SB1 according to an exemplary embodiment may include first to fourth stage circuits ST1 , ST2 , ST3 , and ST4 .

The first stage circuit ST1 may be implemented to supply the first gate driving signal GS1 to the first gate line GL1 of the first gate line group GLG1 . For example, the first stage circuit ST1 is connected to the first gate clock line based on the first start signal Vst1 provided from the timing controller 300 , the stage driving voltage GVdd, and the stage common voltage GVss. The first gate driving signal GS1 corresponding to the on voltage period of the supplied first shift clock signal CLK1 may be output to the first gate line GL1 of the first gate line group GLG1 .

The second stage circuit ST2 may be implemented to supply the second gate driving signal GS2 to the second gate line GL2 of the first gate line group GLG1 . For example, the second stage circuit ST2 is connected to the third gate clock line based on the second start signal Vst2 provided from the timing controller 300 , the stage driving voltage GVdd, and the stage common voltage GVss. The second gate driving signal GS2 corresponding to the on voltage period of the supplied third shift clock signal CLK3 may be output to the second gate line GL2 of the first gate line group GLG1 .

The third stage circuit ST3 may be implemented to supply the third gate driving signal GS3 to the third gate line GL3 of the first gate line group GLG1 . For example, the third stage circuit ST3 is connected to the fifth gate clock line based on the third start signal Vst3 provided from the timing controller 300 , the stage driving voltage GVdd, and the stage common voltage GVss. The third gate driving signal GS3 corresponding to the on voltage period of the supplied fifth shift clock signal CLK5 may be output to the third gate line GL3 of the first gate line group GLG1 .

The fourth stage circuit ST4 may be implemented to supply the fourth gate driving signal GS4 to the fourth gate line GL4 of the first gate line group GLG1 . For example, the fourth stage circuit ST4 is connected to the seventh gate clock line based on the fourth start signal Vst4 provided from the timing controller 300 , the stage driving voltage GVdd and the stage common voltage GVss. The fourth gate driving signal GS4 corresponding to the on voltage period of the supplied seventh shift clock signal CLK7 may be output to the fourth gate line GL4 of the first gate line group GLG1 .

Additionally, the second stage block SB2 of the shift register 710 is configured to respond to the first to fourth start signals Vst1 , Vst2 , Vst3 , and Vst4 provided from the timing controller 300 , respectively. The first to fourth corresponding to the turn-on voltage periods of the second, fourth, sixth, and eighth shift clock signals CLK2 , CLK4 , CLK6 and CLK8 supplied to the fourth, sixth, and eighth gate clock lines, respectively. Each of the four gate driving signals GS1 , GS2 , GS3 , and GS4 may be supplied to each of the first to fourth gate lines GL1 , GL2 , GL3 , and GL4 of the second gate line group GLG2 .

In addition, each of the third, fifth to m-1 th stage blocks SB3 , SB5 , ... SBm-1 of the shift register 710 includes first to fourth start signals supplied through the mode control circuit 730 , respectively. The turn-on voltage period of the first, third, fifth, and seventh shift clock signals CLK1 , CLK3 , CLK5 , and CLK7 respectively supplied to the first, third, fifth, and seventh gate clock lines in response to The first to fourth gate driving signals GS1, GS2, GS3, GS4 corresponding to the first to fourth gate line groups GLG3, GLG5, ... GLGm-1 of the third, fifth, and m-1th gate line groups GLG3, GLG5, ... GLGm-1, respectively Each of the four gate lines GL1, GL2, GL3, and GL4 may be supplied.

In addition, each of the fourth, sixth to mth stage blocks SB4 , SB6 , ... SBm of the shift register 710 responds to the first to fourth start signals supplied through the mode control circuit 730 , respectively. The second, fourth, sixth, and eighth gate clock lines are respectively supplied to the second, fourth, sixth, and eighth shift clock signals CLK2, CLK4, CLK6, and CLK8. Each of the first to fourth gate driving signals GS1, GS2, GS3, GS4 is applied to the first to fourth gate lines GL1, GL2, GL3, GL4) can be supplied respectively.

As such, since each of the first to fourth stage circuits ST1, ST2, ST3, and ST4 is a stage circuit of a known gate driving circuit using one start signal and one shift clock signal, a detailed circuit description thereof is omit

In the mode control circuit 730 of the gate driving circuit according to the present specification, the first transistor unit TU1 uses the gate group driving signal output from the first stage block SB1 of the shift register 710 as the first start signal. It may be supplied to the second stage block SB2 according to the mode control signal MCS1 .

The first transistor unit TU1 according to an example may include first to fourth transistors Ta, Tb, Tc, and Td.

The first transistor Ta is turned on according to the first mode control signal MCS1 to receive the first gate driving signal GS1 output from the first stage circuit ST1 of the first stage block SB1 as a start signal. may be supplied to the first stage circuit of the second stage block SB2. The first transistor Ta according to an example includes a gate electrode connected to a first mode control signal line to which the first mode control signal MCS1 is supplied, and an output line (or a first stage circuit of the first stage block SB1 ). It may include a first source/drain electrode connected to the first gate line GL1 ), and a second source/drain electrode connected to a start signal input line of the first stage circuit of the second stage block SB2 .

The second transistor Tb is turned on according to the first mode control signal MCS1 and receives the second gate driving signal GS2 output from the second stage circuit ST2 of the first stage block SB1 as a start signal. may be supplied to the second stage circuit of the second stage block SB2. The second transistor Tb according to an example has a gate electrode connected to the first mode control signal line, and a second transistor connected to the output line (or the second gate line GL2 ) of the second stage circuit of the first stage block SB1 . It may include a first source/drain electrode and a second source/drain electrode connected to a start signal input line of a second stage circuit of the second stage block SB2 .

The third transistor Tc is turned on according to the first mode control signal MCS1 to receive the third gate driving signal GS3 output from the third stage circuit ST3 of the first stage block SB1 as a start signal. may be supplied to the third stage circuit of the second stage block SB2. The third transistor Tc according to an example has a gate electrode connected to the first mode control signal line and a third transistor connected to the output line (or the third gate line GL3 ) of the third stage circuit of the first stage block SB1 . It may include a first source/drain electrode and a second source/drain electrode connected to a start signal input line of a third stage circuit of the second stage block SB2 .

The fourth transistor Td is turned on according to the first mode control signal MCS1 and receives the fourth gate driving signal GS4 output from the fourth stage circuit ST4 of the first stage block SB1 as a start signal. may be supplied to the fourth stage circuit of the second stage block SB2. The fourth transistor Td according to an example has a gate electrode connected to the first mode control signal line, and a fourth transistor connected to the output line (or the fourth gate line GL4 ) of the fourth stage circuit of the first stage block SB1 . It may include a first source/drain electrode and a second source/drain electrode connected to a start signal input line of a fourth stage circuit of the second stage block SB2 .

Additionally, each of the second to j-th transistor units TU2 to TUj according to an example may also include the first to fourth transistors Ta, Tb, Tc, and Td.

The first transistor Ta of each of the second to j-th transistor units TU2 to TUj is turned on according to the first mode control signal MCS1 to turn on the first to m-1 th stage blocks SB1 to SBm-1 ) The first gate driving signal GS1 output from each of the first stage circuits ST1 may be supplied as a start signal to the first stage circuits of each of the second to mth stage blocks SB2 to SBm.

The second transistor Tb of each of the second to j-th transistor units TU2 to TUj is turned on according to the first mode control signal MCS1 to turn on the first to m-1 th stage blocks SB1 to SBm-1 ) The second gate driving signal GS2 output from each of the second stage circuits ST2 may be supplied as a start signal to the second stage circuits of each of the second to mth stage blocks SB2 to SBm.

The third transistor Tc of each of the second to j-th transistor units TU2 to TUj is turned on according to the first mode control signal MCS1 to turn on the first to m-1 th stage blocks SB1 to SBm-1 ) The third gate driving signal GS3 output from each of the third stage circuits ST3 may be supplied as a start signal to the third stage circuits of each of the second to mth stage blocks SB2 to SBm.

The fourth transistor Td of each of the second to j-th transistor units TU2 to TUj is turned on according to the first mode control signal MCS1 to turn on the first to m-1 th stage blocks SB1 to SBm-1 ) The fourth gate driving signal GS4 output from each of the fourth stage circuits ST4 may be supplied as a start signal to the fourth stage circuits of each of the second to mth stage blocks SB2 to SBm.

Each of the first to j-th transistor units TU1 to TUj is turned on according to the first mode control signal MCS1 and first outputted from the first to m-1 th stage blocks SB1 to SBm-1, respectively. By supplying the to fourth gate driving signals GS1 , GS2 , GS3 , and GS4 as start signals to each of the second to m-th stage blocks SB2 to SBm, the gate driving circuit 700 operates in the progressive driving method shown in FIG. 2 . It can be driven in the normal driving mode of .

In the mode control circuit 730 of the gate driving circuit according to the present specification, the first switching unit SU1 uses the gate group driving signal output from the first stage block SB1 of the shift register 710 as the second start signal. It may be supplied to the third stage block SB3 according to the mode control signal MCS2 .

The first switching unit SU1 according to an example may include first to fourth switch elements SWa, SWb, SWc, and SWd.

The first switch element SWa is turned on according to the second mode control signal MCS2 to start the first gate driving signal GS1 output from the first stage circuit ST1 of the first stage block SB1 The signal may be supplied to the first stage circuit of the third stage block SB3. The first switch element SWa according to an example includes a gate electrode connected to a second mode control signal line to which the second mode control signal MCS2 is supplied, and an output line ( Alternatively, it may include a first source/drain electrode connected to the first gate line GL1 ) and a second source/drain electrode connected to a start signal input line of the first stage circuit of the third stage block SB3 .

The second switch element SWb is turned on according to the second mode control signal MCS2 to start the second gate driving signal GS2 output from the second stage circuit ST2 of the first stage block SB1. The signal may be supplied to the second stage circuit of the third stage block SB3. The second switch element SWb according to an example has a gate electrode connected to the second mode control signal line, and an output line (or the second gate line GL2 ) of the second stage circuit of the first stage block SB1 . It may include a first source/drain electrode and a second source/drain electrode connected to a start signal input line of a second stage circuit of the third stage block SB3 .

The third switch element SWc is turned on according to the second mode control signal MCS2 to start the third gate driving signal GS3 output from the third stage circuit ST3 of the first stage block SB1. The signal may be supplied to the third stage circuit of the third stage block SB3. The third switch element SWc according to an example has a gate electrode connected to the second mode control signal line and an output line (or the third gate line GL3 ) of the third stage circuit of the first stage block SB1 . It may include a first source/drain electrode and a second source/drain electrode connected to a start signal input line of a third stage circuit of the third stage block SB3 .

The fourth switch element SWd is turned on according to the second mode control signal MCS2 to start the fourth gate driving signal GS4 output from the fourth stage circuit ST4 of the first stage block SB1 A signal may be supplied to the fourth stage circuit of the third stage block SB3. The fourth switch element SWd according to an example has a gate electrode connected to the second mode control signal line and an output line (or the fourth gate line GL4 ) of the fourth stage circuit of the first stage block SB1 . It may include a first source/drain electrode and a second source/drain electrode connected to a start signal input line of a fourth stage circuit of the third stage block SB3 .

Similarly, in the first to j-th switching units SU1 to SUj, each of the third, fifth to j-1th switching units SU3, SU5, ... SUj-1 is also the first to fourth switch element SWa , Tb, Tc, Td). The first to fourth switch elements SWa, Tb, Tc, Td of each of the third, fifth to j-1th switching units SU3, SU5, ... SUj-1 are connected to the second mode control signal MCS2. are turned on according to the first to fourth stage circuits ST1, ST2, ST3, and ST4 respectively of the third, fifth to m-1 th stage blocks SB3, SB5 to SBm-1, respectively. The first to fourth stages of the fifth, seventh, and m-1 th stage blocks SB5, SB7, ... SBm-1, respectively, are respectively used as start signals for the first to fourth gate driving signals GS1, GS2, GS3, and GS4. It can be supplied to each of the circuits ST1, ST2, ST3, and ST4.

Additionally, the second switching unit SU2 according to an example may also include the first to fourth switch elements SWa, SWb, SWc, and SWd.

The first switch element SWa of the second switching unit SU2 is turned on according to the third mode control signal MCS3 to be output from the first stage circuit ST1 of the second stage block SB2. The gate driving signal GS1 may be supplied as a start signal to the first stage circuit of the fourth stage block SB4 .

The second switch element SWb of the second switching unit SU2 is turned on according to the third mode control signal MCS3 and is output from the second stage circuit ST2 of the second stage block SB2. The gate driving signal GS2 may be supplied as a start signal to the second stage circuit of the fourth stage block SB4 .

The third switch element SWc of the second switching unit SU2 is turned on according to the third mode control signal MCS3 and is outputted from the third stage circuit ST3 of the second stage block SB2. The gate driving signal GS3 may be supplied to the third stage circuit of the fourth stage block SB4 as a start signal.

The fourth switch element SWd of the second switching unit SU2 is turned on according to the third mode control signal MCS3 and is outputted from the fourth stage circuit ST4 of the second stage block SB2. The gate driving signal GS4 may be supplied as a start signal to the fourth stage circuit of the fourth stage block SB4 .

Similarly, in the first to j-th switching units SU1 to SUj, the fourth, sixth to j-th switching units SU4, SU6, ... SUj, respectively, also the first to fourth switch elements SWa, Tb, Tc , Td). The first to fourth switch elements SWa, Tb, Tc, Td of each of the fourth, sixth to j-th switching units SU4, SU6, ... SUj are turned on according to the third mode control signal MCS3. and the first to fourth gate driving signals GS1 outputted from the first to fourth stage circuits ST1, ST2, ST3, and ST4 of the fourth, sixth to mth stage blocks SB4, SB6 to SBm, respectively. , GS2, GS3, GS4) as a start signal to each of the first to fourth stage circuits ST1, ST2, ST3, ST4 of each of the sixth, eighth to m-th stage blocks SB6, SB8, ... SBm can supply

15 is a view illustrating a comparison of the luminance fall width of the light emitting display device driven in the interlace driving mode low speed driving mode according to an example of the present specification and the luminance drop width of the light emitting display device driven in the low speed driving mode according to the comparative example. to be. In FIG. 15 , graph A shows the luminance drop width of the light emitting display device according to the comparative example, and graph B shows the luminance drop width of the light emitting display device according to the example of the present specification.

Referring to FIG. 15 , the light emitting display device according to the comparative example may update images of pixels disposed on all horizontal lines by sequentially driving all gate line groups in the refresh frame of the low speed driving mode. Accordingly, as shown in graph A, the light emitting display device according to the comparative example has a problem in that an excessive luminance drop DW1 occurs in the refresh frame compared to the hold frame, thereby causing flicker.

In comparison, the light emitting display device according to an example of the present specification sequentially drives some of the gate line groups in units of refresh frames in the interlace driving mode of the low speed driving mode, as shown in FIG. 3A or 3B , Images of pixels disposed on some of the horizontal lines may be updated. Accordingly, in the light emitting display device according to the example of the present specification, as shown in graph B, a luminance drop DW2 of half compared to the luminance drop DW1 according to the comparative example occurs in the refresh frame, so that the flicker phenomenon can be minimized. For example, in the present specification, the luminance drop is divided into the refresh frame of the N th unit time and the refresh frame of the N+1 th unit time, so that the flicker phenomenon can be minimized.

In the light emitting display device according to the present specification, the image is updated through each refresh frame of the N-th and N+1-th unit times according to the interlace driving method in the low-speed driving mode, so that the luminance drop rate generated in the refresh frame is reduced. Accordingly, a flicker phenomenon occurring in the low-speed driving mode may be minimized.

16 is a diagram illustrating a comparison between a pixel charging time of a light emitting display device driven in a low speed driving mode according to an example of the present specification and a pixel charging time of a light emitting display device driven in a low speed driving mode according to a comparative example. In FIG. 16 , graph C shows the pixel charging time according to the comparative example, and graph D shows the pixel charging time of the data voltage according to the driving method of the pixel shown in FIG. 9 or 12 .

Referring to FIG. 16 , the light emitting display device according to the comparative example may charge only the actual data voltage in the refresh frame of the low speed driving mode. Accordingly, it can be seen that the light emitting display device according to the comparative example has the first pixel charging time tc1 as shown in graph C.

In comparison, the light emitting display device according to an example of the present specification may pre-charge the dummy data voltage and then charge the actual data voltage in the refresh frame of the low-speed driving mode shown in FIG. 9 or FIG. 12 . Accordingly, it can be seen that the light emitting display device according to the example of the present specification has a second pixel charging time tc2 that is relatively shorter than the first pixel charging time tc1 according to the comparative example, as shown in graph D.

Accordingly, in the light emitting display device according to an example of the present specification, the pixel charging time is shortened by pre-charging the dummy data voltage before the actual data voltage is charged in the low-speed driving mode, or the low-speed driving mode is performed by implementing fast charging of the data voltage. It is possible to prevent or minimize a decrease in luminance of the light emitting device due to the slow charging of the data voltage generated in the refresh frame.

A light emitting display device according to some examples of the present specification may be described as follows.

A light emitting display device according to some examples of the present specification includes a light emitting display panel including pixels disposed in a pixel area defined by a plurality of data lines and first to m th gate line groups, and a first light emitting display panel disposed on the light emitting display panel. and a gate driving circuit for driving the to mth gate line group in a normal driving mode or a low speed driving mode, wherein the gate driving circuit includes first to mth gate line groups for N (N is a natural number) th unit time among a plurality of unit times in the low speed driving mode. Some of the m-th gate line groups may be driven, and the remaining gate line groups among the first to m-th gate line groups may be driven for an (N+1)-th unit time.

According to some examples of the present specification, in the low-speed driving mode, each of the plurality of unit times includes a refresh frame and a hold frame, and the gate driving circuit performs a portion of the first to m-th gate line groups during the refresh frame of the N-th unit time. The gate line group may be driven, and the remaining gate line groups among the first to mth gate line groups may be driven during the refresh frame of the N+1 th unit time.

According to some examples of the present specification, the unit time is 1 second, and within the unit time, the time of the refresh frame may be shorter than the time of the hold frame.

According to some examples of the present specification, the gate driving circuit drives the odd-numbered gate line group among the first to m-th gate line groups during the refresh frame of the N-th unit time, and the first gate line group during the refresh frame of the N+1-th unit time. An even-numbered gate line group among the to m-th gate line groups may be driven.

According to some examples of the present specification, the unit time is 1 second, the image displayed on the odd-numbered horizontal line among the images displayed on the light emitting display panel is updated in the refresh frame of the Nth unit time, and the image displayed on the light emitting display panel The image displayed on the even-numbered horizontal line may be updated in the refresh frame of the N+1-th unit time.

According to some examples of the present specification, the gate driving circuit includes a shift register having first to m-th stage blocks for outputting a gate group driving signal in response to a start signal, and first to m-th stages in response to a mode control signal. A mode control circuit for supplying the gate group driving signal output from the i-th stage block (i is a natural number from 1 to m-1) as a start signal to the i+1th stage block or the i+2th stage block among the blocks may include.

According to some examples of the present specification, the mode control signal includes a first mode control signal for a normal driving mode and a second mode control signal for a low speed driving mode, and the mode control circuit is configured to perform a first mode control signal in response to the first mode control signal. A first switching unit for supplying the gate group driving signal output from the i stage block as a start signal to the i+1th stage block, an inverter circuit for outputting a third mode control signal by inverting the second mode control signal, and and a second switching unit configured to supply the gate group driving signal output from the i-th stage block to the i+2 stage block as a start signal in response to the second mode control signal and the third mode control signal.

According to some examples of the present specification, the first switching unit is disposed between the first to m-th stage blocks and uses the gate group driving signal output from the i-th stage block in response to the first mode control signal as the i+th start signal. It may include first to j-th (j is m-1) transistor units supplying the first stage block.

According to some examples of the present specification, the second switching unit is disposed between the first to m-th stage blocks and receives the gate group driving signal output from the i-th stage block in response to the second mode control signal and the third mode control signal. 1st to jth switching units for supplying the i+2th stage block as a start signal may be included.

According to some examples of the present specification, the 2k-1th (k is 1 to j/2) switching unit among the first to jth switching units is the 2y-1th (y is 1 to m) of the first to mth stage blocks. /2) a gate group driving signal connected between the stage block and the 2y+1th stage block and output from the 2y-1th stage block in response to the second mode control signal is supplied to the 2y+1th stage block as a start signal; , a 2k second switching unit of the first to j-th switching units is connected between a 2y-th stage block and a 2y+2-th stage block of the first to m-th stage blocks and is removed from the 2y-th stage block in response to a third mode control signal The output gate group driving signal may be supplied to the 2y+2 stage block as a start signal.

According to some examples of the present specification, each of the plurality of pixels includes a light emitting element; a driving thin film transistor having a gate electrode connected to a first node, a first source/drain electrode connected to a second node, and a second source/drain electrode connected to a third node; a first thin film transistor selectively connecting the data line and the second node; a second thin film transistor selectively connecting the first node and the third node; a third thin film transistor selectively connecting the pixel driving power line and the second node; a fourth thin film transistor selectively connecting the third node and the light emitting device; a fifth thin film transistor selectively connecting the initialization power line and the first node; a sixth thin film transistor selectively connecting a fourth node between the fourth thin film transistor and the light emitting device and an initialization power line; and a storage capacitor connected between the pixel driving power line and the first node.

According to some examples of the present specification, the refresh frame is a first period connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor, the first period is followed by the turn-on of the first and second thin film transistors; A second period for storing the data voltage and the threshold voltage of the driving thin film transistor in the storage capacitor according to the turn-on, a third period for connecting the fourth node and the initialization power line according to the turn-on of the sixth transistor following the second period; and a fourth period following the third period and allowing the light emitting device to emit light according to turn-on of the third and fourth thin film transistors.

According to some examples of the present specification, the initialization voltage supplied to the initialization power line has a first voltage level for discharging the voltage of the fourth node in the third period or higher than the first voltage level to increase the voltage of the fourth node. It may have a high second voltage level.

According to some examples of the present specification, in the refresh frame, the second period is followed by the first period and is followed by the 2-1 period in which the dummy data voltage is supplied to the second node, and the 2-1 period is followed by the actual data voltage in the second period. It may include a 2-2 period of supply to the node.

According to some examples herein, the dummy data voltage may have a higher voltage level than the data voltage.

According to some examples of the present specification, the refresh frame is a first period connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor, the first period is followed by the turn-on of the first and second thin film transistors; a second period in which the data voltage and the threshold voltage of the driving thin film transistor are stored in the storage capacitor according to the on, a third period following the second period and maintaining the voltage of the fourth node according to the turn-off of the sixth transistor; and Following the third period, a fourth period in which the light emitting device emits light according to the turn-on of the third and fourth thin film transistors may be included.

According to some examples of the present specification, the refresh frame is a first period connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor, the first period is followed by the turn-on of the first and second thin film transistors; A second period of connecting the fourth node and the initialization power line according to the turn-on of the sixth transistor while storing the data voltage and the threshold voltage of the driving thin film transistor in the storage capacitor according to the turn-on, and a light emitting device following the second period It may include a third period for emitting light.

According to some examples of the present specification, the initialization voltage supplied to the initialization power line has a first voltage level for discharging the voltage of the fourth node in the second period or higher than the first voltage level to increase the voltage of the fourth node. It may have a high second voltage level.

According to some examples of the present specification, in the refresh frame, the second period is followed by the first period and is followed by the 2-1 period in which the dummy data voltage is supplied to the second node, and the 2-1 period is followed by the actual data voltage in the second period. It may include a 2-2 period of supply to the node.

According to some examples of the present specification, the dummy data voltage may have a higher voltage level than the data voltage.

Features, structures, effects, etc. described in the examples of the present specification described above are included in at least one example of the present specification, and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. illustrated in at least one example of the present specification can be combined or modified for other examples by those of ordinary skill in the art to which the technical idea of the present specification belongs. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is the technical spirit of the present specification that various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present specification. It will be clear to one of ordinary skill in the art. Therefore, the scope of the present specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present specification.

100: light emitting display panel 300: timing control unit
500: data driving circuit 700: gate driving circuit
710: shift register 730: mode control circuit
731: first switching unit 733: inverter circuit
735: second switching unit 900: power circuit

Claims (20)

a light emitting display panel including pixels disposed in a pixel area defined by a plurality of data lines and first to mth gate line groups; and
a gate driving circuit disposed on the light emitting display panel and configured to drive the first to mth gate line groups in a normal driving mode or a low speed driving mode;
The gate driving circuit drives some of the first to m-th gate line groups for an N (N is a natural number)-th unit time among a plurality of unit times in the low-speed driving mode, and an N+1-th unit time and driving the remaining gate line groups among the first to m-th gate line groups during operation. The method of claim 1,
In the low-speed driving mode, each of the plurality of unit times includes a refresh frame and a hold frame,
The gate driving circuit drives some of the first to m-th gate line groups during the refresh frame of the N-th unit time, and the first to m-th gate line groups during the refresh frame of the N+1-th unit time. A light emitting display device for driving the remaining gate line group among the mth gate line group. 3. The method of claim 2,
The unit time is 1 second,
and a time of the refresh frame is shorter than a time of the hold frame within the unit time. 3. The method of claim 2,
The gate driving circuit drives an odd-numbered gate line group among the first to m-th gate line groups during the refresh frame of the N-th unit time, and the first to m-th gate line groups during the refresh frame of the N+1-th unit time. A light emitting display device for driving an even-numbered gate line group among the mth gate line group. 5. The method of claim 4,
The unit time is 1 second,
an image displayed on an odd-numbered horizontal line among images displayed on the light emitting display panel is updated in the refresh frame of the N-th unit time;
and an image displayed on an even-numbered horizontal line among the images displayed on the light emitting display panel is updated in the refresh frame of the N+1th unit time. The method of claim 1,
The gate driving circuit is
a shift register having first to m-th stage blocks for outputting a gate group driving signal in response to a start signal; and
In response to a mode control signal, a gate group driving signal output from an i-th stage block among the first to m-th stage blocks (i is a natural number from any one of 1 to m-1) is used as the start signal for the i+1th stage A light emitting display device comprising a mode control circuit for supplying a block or an i+2th stage block. 7. The method of claim 6,
The mode control signal includes a first mode control signal for the normal driving mode and a second mode control signal for the low speed driving mode,
The mode control circuit,
a first switching unit configured to supply a gate group driving signal output from the i-th stage block as the start signal to the i+1-th stage block in response to the first mode control signal;
an inverter circuit for inverting the second mode control signal to output a third mode control signal; and
and a second switching unit configured to supply a gate group driving signal output from the i-th stage block to the i+2 stage block as the start signal in response to the second mode control signal and the third mode control signal, luminescent display. 8. The method of claim 7,
The first switching unit is disposed between the first to m-th stage blocks and uses a gate group driving signal output from the i-th stage block in response to the first mode control signal as the start signal for the i+1-th stage. A light emitting display device comprising: first to j-th (j is m-1) transistor units supplying the block. 8. The method of claim 7,
The second switching unit is disposed between the first to m-th stage blocks and applies a gate group driving signal output from the i-th stage block in response to the second mode control signal and the third mode control signal to the start signal. and first to j-th switching units for supplying to the i+2-th stage block as a light emitting display device. 10. The method of claim 9,
A 2k-1 (k is 1 to j/2) switching unit among the first to j-th switching units includes a 2y-1 (y is 1 to m/2) stage block among the first to m-th stage blocks, and A gate group driving signal connected between 2y+1th stage blocks and output from the 2y-1th stage block in response to the second mode control signal is supplied to the 2y+1th stage block as the start signal,
A 2k second switching unit of the first to j-th switching units is connected between a 2y-th stage block and a 2y+2-th stage block among the first to m-th stage blocks, and in response to the third mode control signal, the 2y-th switching unit and supplying a gate group driving signal output from a stage block as the start signal to the 2y+2 stage block. 11. The method according to any one of claims 2 to 10,
Each of the plurality of pixels,
light emitting element;
a driving thin film transistor having a gate electrode connected to a first node, a first source/drain electrode connected to a second node, and a second source/drain electrode connected to a third node;
a first thin film transistor selectively connecting the data line and the second node;
a second thin film transistor selectively connecting the first node and the third node;
a third thin film transistor selectively connecting a pixel driving power line and the second node;
a fourth thin film transistor selectively connecting the third node and the light emitting device;
a fifth thin film transistor selectively connecting an initialization power line and the first node;
a sixth thin film transistor selectively connecting a fourth node between the fourth thin film transistor and the light emitting device and the initialization power line; and
and a storage capacitor connected between the pixel driving power line and the first node. 12. The method of claim 11,
The refresh frame is
a first period for connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor;
a second period following the first period and storing a data voltage and a threshold voltage of the driving thin film transistor in the storage capacitor according to turn-on of the first and second thin film transistors;
a third period following the second period and connecting the fourth node and the initialization power line according to turn-on of the sixth transistor; and
and a fourth period following the third period and allowing the light emitting element to emit light according to turn-on of the third and fourth thin film transistors. 13. The method of claim 12,
The initialization voltage supplied to the initialization power line has a first voltage level for discharging the voltage of the fourth node in the third period, or a second voltage level higher than the first voltage level to increase the voltage of the fourth node. A light emitting display device having a voltage level. 13. The method of claim 12,
In the refresh frame, the second period is
a 2-1 period following the first period and supplying a dummy data voltage to the second node; and
and a 2-2 period following the 2-1 period and supplying an actual data voltage to the second node. 15. The method of claim 14,
and the dummy data voltage has a higher voltage level than the data voltage. 12. The method of claim 11,
The refresh frame is
a first period for connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor;
a second period following the first period and storing a data voltage and a threshold voltage of the driving thin film transistor in the storage capacitor according to turn-on of the first and second thin film transistors;
a third period following the second period and maintaining the voltage of the fourth node according to turn-off of the sixth transistor; and
and a fourth period following the third period and allowing the light emitting element to emit light according to turn-on of the third and fourth thin film transistors. 12. The method of claim 11,
The refresh frame is
a first period for connecting the first node and the initialization power line according to the turn-on of the fifth thin film transistor;
Following the first period and storing the data voltage and the threshold voltage of the driving thin film transistor in the storage capacitor according to the turn-on of the first and second thin film transistors, the fourth transistor according to the turn-on of the sixth transistor a second period for connecting a node to the initialization power line; and
and a third period following the second period and allowing the light emitting element to emit light. 18. The method of claim 17,
The initialization voltage supplied to the initialization power line has a first voltage level for discharging the voltage of the fourth node in the second period, or a second voltage level higher than the first voltage level to increase the voltage of the fourth node. A light emitting display device having a voltage level. 18. The method of claim 17,
In the refresh frame, the second period is
a 2-1 period following the first period and supplying a dummy data voltage to the second node; and
and a 2-2 period following the 2-1 period and supplying an actual data voltage to the second node. 20. The method of claim 19,
and the dummy data voltage has a higher voltage level than the data voltage.

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