KR20180003402A - Organic light emitting diode display - Google Patents

Abstract

Provided is an organic light emitting display device, which comprises: a gate driving circuit for supplying a gate signal through a plurality of gate lines connected to a display panel; and a luminance control unit disposed between the gate driving circuit and the display panel, and electrically connected to the gate lines and a power line. The luminance control unit includes: a first switching element electrically connected to each of the gate lines; a second switching element electrically connected between each of the gate lines and the power line; and a luminance control signal line electrically connected to the first and second switching elements. The organic light emitting display device according to an embodiment of the present invention separates a gate signal during a plurality of refresh periods, and supplies the same to a pixel, and thus, an decrease in luminance in the pixel can be significantly reduced during the entire refresh period.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting display, and more particularly, to an organic light emitting display capable of suppressing a flicker phenomenon.

Recently, as the information age has come to the age of information, a display field for visually expressing electrical information signals has been rapidly developed. In response to this, various display devices having excellent performance in thinning, light weighting, Is being developed.

Specific examples of such a display device include a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display device (FED), an organic light emitting display device Organic Light Emitting Display Device (OLED).

Each of the plurality of pixels constituting the organic light emitting display includes an organic light emitting element composed of an organic light emitting layer between the anode and the cathode and a pixel circuit for independently driving the organic light emitting element. The pixel circuit includes a switching thin film transistor (hereinafter referred to as TFT), a driving TFT, and a capacitor. Here, the switching TFT charges the data voltage in the capacitor in response to the scan pulse, and the driving TFT controls the amount of current supplied to the organic light emitting element according to the data voltage charged in the capacitor to control the amount of light emitted from the organic light emitting element.

The organic light emitting display device is a self-emission type display device, unlike a liquid crystal display device, a separate light source is not required, and thus it can be manufactured in a light and thin shape. In addition, the organic light emitting display device is not only advantageous in terms of power consumption by low voltage driving, but also has excellent hue, response speed, viewing angle, and contrast ratio (CR), and has been studied as a next generation display device in various fields. Further, since the organic light emitting element has a surface light emitting structure, it is easy to realize a flexible form.

In the OLED display device having the above advantages, a characteristic difference such as a threshold voltage (Vth) and a mobility of a driving TFT is generated for each pixel due to a process variation or the like, and a voltage drop of the high potential voltage (VDD) And the amount of current for driving the organic light emitting diode is changed, so that a luminance deviation occurs between the pixels. In general, there is a problem in that unevenness or pattern that is unintended on the screen is generated due to the difference in characteristics of the initial driving TFTs, and a characteristic difference due to the deterioration of the driving TFTs generated while driving the organic light emitting elements, And there is a problem that afterimage is generated. Thus, attempts have been made to improve image quality by reducing the luminance deviation between pixels by introducing a compensation circuit that compensates for the characteristic deviation of the drive TFT and compensates for the voltage drop of the high-potential voltage (VDD).

2. Description of the Related Art In recent years, a demand for a wearable display device has rapidly increased, and a wearable display device with a compact design as an essential condition has recently emerged as a problem of minimizing power consumption. In addition, efforts are being made to minimize the power consumption for the always-on display. Accordingly, there has been a need to design a pixel circuit and drive an organic light emitting display device so as to minimize power consumption when driving an organic light emitting display device having a compensation circuit in a pixel structure.

Accordingly, various attempts have been made to reduce the power consumption of the OLED display by variously changing the driving method of the OLED display. One of such driving methods is to control the duration for driving the organic light emitting display device to be shorter than the basic driving frequency and to hold the light emitting state.

However, as the organic light emitting display device is driven at a low driving frequency and the period for holding the light emitting state is controlled to be long, the luminance may be lowered during a period in which a scan signal is applied or during a holding period. Such a luminance decline may cause a flickering phenomenon that is visible to the human eye and flickers.

Accordingly, there is a demand for a method capable of driving the organic light emitting display device at a low driving frequency and reducing the flicker phenomenon in order to reduce power consumption.

[Related Technical Literature]

One. Display device (Korean Patent Publication No. KR-10-2015-0106370)

The inventors of the present invention have recognized that, when performing low-speed driving in an organic light emitting diode display, it is possible to suppress a decrease in luminance during a refresh interval by an internal compensation circuit or an external voltage compensation method for each pixel of the organic light emitting diode display . Accordingly, the present inventors have invented an organic light emitting display device and a driving method thereof that can reduce the flicker phenomenon while reducing the power consumption of the organic light emitting display device.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an organic light emitting display device capable of reducing a luminance drop in a pixel during a whole refresh period by supplying a gate signal to a plurality of pixels separately from a plurality of refresh periods.

Another object of the present invention is to provide an organic light emitting display device capable of suppressing a flicker phenomenon in a display panel and improving image quality by reducing a luminance drop in a pixel during a whole refresh period.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

An organic light emitting display according to an embodiment of the present invention is provided. The organic light emitting display includes a gate driving circuit for supplying a gate signal through each of a plurality of gate lines connected to a display panel, and a luminance control unit disposed between the gate driving circuit and the display panel and electrically connected to the plurality of gate lines and the power source line . The luminance control section includes a first switching element electrically connected to each of the plurality of gate lines, a second switching element electrically connected between each of the plurality of gate lines and the power source line, and a second switching element electrically connected to the first switching element and the second switching element And a luminance control signal line. The organic light emitting display according to an embodiment of the present invention can separate gate signals during a plurality of refresh periods and supply the gate signals to the pixels, thereby significantly reducing the luminance drop in the pixels during the entire refresh period.

An organic light emitting display according to another embodiment of the present invention is provided. The organic light emitting display includes a gate driver circuit and a luminance controller including a part of a plurality of gate lines electrically connecting the display panel and a part of a power supply line. The luminance control section includes a first switching element for determining whether or not a gate signal including a gate high voltage is supplied to each of the plurality of gate lines for a predetermined time, a second switching element for supplying a gate low voltage to each of the plurality of gate lines for a predetermined time, 2 switching element, and a luminance control signal line electrically connected to the first switching element and the second switching element. The organic light emitting display according to another embodiment of the present invention can significantly reduce the luminance drop in the pixels during the entire refresh period, thereby suppressing flicker in the display panel and improving the image quality of the organic light emitting display.

The details of other embodiments are included in the detailed description and drawings.

The present invention can separate gate signals for a plurality of refresh periods and supply them to the pixels, thereby significantly reducing the luminance drop in the pixels during the entire refresh period.

The present invention can remarkably reduce the luminance drop in the pixels during the entire refresh period, thereby suppressing the flicker phenomenon in the display panel and improving the image quality of the organic light emitting display device.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a schematic block diagram of a display device for explaining a gate driving circuit according to an embodiment of the present invention.
2 is a circuit diagram showing a configuration of a luminance controller according to an embodiment of the present invention.
3 is a waveform diagram showing a gate signal and a luminance control signal according to the low-speed driving mode of the organic light emitting diode display according to the embodiment of the present invention.
4 is a graph of a luminance according to a low-speed driving mode of an OLED display according to an exemplary embodiment of the present invention.
5 is a waveform diagram illustrating a gate signal according to a low-speed driving mode of an OLED display according to another embodiment of the present invention.
FIG. 6 is a graph illustrating a luminance according to a low-speed driving mode of an OLED display according to another embodiment of the present invention.
7 is a waveform diagram showing a gate signal according to a low-speed driving mode of an OLED display according to another embodiment of the present invention.
8 is a graph of a luminance according to a low-speed driving mode of an OLED display according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

It will be understood that when an element or layer is referred to as being on another element or layer, it encompasses the case where it is directly on or intervening another element or intervening another element or element.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or entirely and technically various interlocking and driving is possible as will be appreciated by those skilled in the art, It may be possible to cooperate with each other in association.

In the present invention, the TFT may be of P type or N type. In describing the pulse-shaped signal, the gate high voltage (VGH) state is defined as a "high state", and the gate low voltage (VGL) state is defined as a "low state".

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a display device for explaining a gate driving circuit according to an embodiment of the present invention.

1, an OLED display 100 includes a display panel 110 including a plurality of pixels P, a gate driving circuit 130 for supplying a gate signal to each of the plurality of pixels P, And a timing controller 120 for controlling the gate driving circuit 130 and the data driving circuit 140. The data driving circuit 140 supplies a data signal to each of the pixels P of the data driver 140,

The timing controller 120 processes image data RGB input from outside according to the size and the resolution of the display panel 110 and supplies the image data RGB to the data driving circuit 140. The timing controller 120 generates a plurality of gate control signals (GCS) using externally input synchronizing signals SYNC, for example, a dot clock signal, a data enable signal, a horizontal synchronizing signal, And a plurality of data control signals (DCS). The gate driving circuit 130 and the data driving circuit 140 are supplied by supplying the generated plurality of gate control signals GCS and the plurality of data control signals DCS to the gate driving circuit 130 and the data driving circuit 140, ). Here, the plurality of gate control signals GCS may include a luminance control signal CS, and specific characteristics of the luminance control signal CS will be described later with reference to FIG.

The gate driving circuit 130 supplies a gate signal to the gate line GL in accordance with the gate control signal GCS supplied from the timing control unit 120. [ Here, the gate signal includes at least one scan signal and a light emission control signal. In FIG. 1, the gate driving circuit 130 is shown as being disposed on one side of the display panel 110, but the number and arrangement positions of the gate driving circuits 130 are not limited thereto. That is, the gate driving circuit 130 may be disposed on one side or both sides of the display panel 110 in a GIP (Gate In Panel) manner.

The data driving circuit 140 converts the image data RGB into a data voltage according to the data control signal DCS supplied from the timing controller 120 and supplies the converted data voltage to the pixels P .

A plurality of gate lines GL and a plurality of data lines DL are intersected with each other in the display panel 110 and each of the plurality of pixels P is connected to a gate line GL and a data line DL. Specifically, one pixel P receives the gate signal from the gate driving circuit 130 through the gate line GL, receives the data signal from the data driving circuit 140 through the data line DL, Various power sources are supplied through power supply lines.

Here, the gate line GL may include a first scan signal line SCAN1, a second scan signal line SCAN2, and a light emission control signal line EM, and the data line DL may include a voltage line . The voltage line is configured to supply the data voltage (Vdata), the reference voltage (Vref), and the initialization voltage (Vini) to each of the plurality of pixels (P). The power supply line may be connected to the display panel 110 through the timing control unit 120 and may be supplied to each of the plurality of pixels P. [

One pixel P receives the scan signal and the emission control signal through the gate line GL and supplies the data voltage Vdata, the reference voltage Vref, and the initialization voltage Vini through the data line DL. And receives a high potential voltage (VDD) and a low potential potential (VSS) through a power supply line.

Each of the pixels P includes an organic light emitting element and a pixel driving circuit for controlling driving of the organic light emitting element. Here, the organic light emitting element comprises an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The pixel driving circuit includes a plurality of switching elements, a driving switching element, and a capacitor. In the pixel driving circuit, the driving TFT controls the amount of current supplied to the organic light emitting element according to the difference between the data voltage charged in the capacitor and the reference voltage, thereby adjusting the amount of light emitted from the organic light emitting element . In addition, the plurality of switching TFTs receives the scan signal and the emission control signal supplied through the gate line GL to charge the data voltage to the capacitor.

The luminance controller 150 is disposed between the gate driving circuit 130 and the display panel 110. The brightness controller 150 is electrically connected to the gate driving circuit 130 and the display panel 110 through the gate line GL. The brightness controller 150 may distribute the gate signal provided from the gate driver circuit 130 to the display panel 110 during a plurality of divided refresh periods. The specific configuration of the luminance controller 150 will be described later with reference to Fig.

The OLED display 100 according to an embodiment of the present invention includes a gate driving circuit 130 for driving a display panel 110 including a plurality of pixels P, a data driving circuit 140, And a timing control unit 120 for controlling the timing. The OLED display 100 may further include a brightness controller 150 between the display panel 110 and the gate driving circuit 130 to control the brightness of the plurality of pixels P. [ The luminance controller 150 can control the timing of supplying the gate signal in the refresh interval for refreshing the display panel 110 to suppress the luminance of the display panel 110 from falling. Accordingly, the brightness of the display panel 110 is prevented from dropping, and the flicker due to the brightness drop can be reduced. A specific configuration of the luminance control unit will be described later with reference to Fig.

2 is a circuit diagram showing a configuration of a luminance controller according to an embodiment of the present invention. Will be described with reference to Fig. 1 for convenience of explanation.

Referring to FIG. 2, a luminance controller 150 is disposed between the gate driving circuit 130 and the display panel 110. Specifically, the brightness controller 150 is disposed between the gate driving circuit 130 and the display panel 110, and is electrically connected to the plurality of gate lines G1 to Gn and the power source line VSS. The luminance controller 150 controls the luminance controller 150 and the display panel 110 such that a part of a plurality of gate lines electrically connecting the gate drive circuit 130 and the display panel 110 between the gate drive circuit 130 and the display panel 110, . Here, the power supply line VSS is a low potential power supply line for supplying the gate low voltage VGL. The power supply line VSS may be replaced with a high potential power supply line that supplies the gate high voltage VGH according to the embodiment.

The luminance controller 150 includes a first switching device Tx1, a second switching device Tx2, and a first luminance control signal line 151a. Here, x means a number indicating the arrangement order of the gate lines GL, and x is a natural number that is 1 or more and less than or equal to the maximum number of the gate lines GL. For example, x is a natural number from 1 to 1536.

The first switching element Tx1 is electrically connected to each of the plurality of gate lines G1 to Gn. Specifically, the first switching device Tx1 includes a gate connected to the first luminance control signal line 151a, and a gate line connected to the output node onx of the gate driving circuit 130 and a gate line connected to the display panel 110 And between the gate lines connected to the input node inx. For example, the first switching element T11 of the first gate line is connected to the output node onx of the gate driving circuit 130 and the input node inx of the display panel 110 in the first gate line G1, And is connected to the first gate line G1.

Thus, the first switching device Tx1 determines whether or not the gate signal GS including the gate high voltage VGH is supplied to each of the plurality of gate lines G1 to Gn for a predetermined time. Specifically, the first switching element Tx1 short-circuits or opens each of the plurality of gate lines G1 to Gn by a luminance control signal input through the first luminance control signal line 151a connected to the gate, (open). For example, when the luminance control signal is in the high state, the first switching device Tx1 is turned on to short-circuit the gate line Gx to which the first switching device Tx1 is connected. Thus, the gate line Gx connected to the turned-on first switching element Tx1 can supply the gate signal GSx to the display panel 110. [ The waveform of the luminance control signal and thus the output and luminance of the gate signal will be described later with reference to FIGS. 3 and 4. FIG.

The second switching element Tx2 is electrically connected between each of the plurality of gate lines and the power source line. Specifically, the second switching element Tx2 includes a gate connected to the second luminance control signal line 151b, and a power supply line VSS connected to an output node onx of the gate driving circuit 130 and a display panel Lt; RTI ID = 0.0 > 110 < / RTI > Here, the second luminance control signal line 151b is connected to the output node of the inverter INV from the first luminance control signal line 151a. That is, the second switching element Tx2 includes a gate electrically connected to the output node of the inverter INV.

Thus, the second switching device Tx2 supplies the gate-low voltage VGL to each of the plurality of gate lines G1 to Gn for a predetermined time. Specifically, the second switching element Tx2 is connected to the gate line Gx from the input node inx of the display panel 110 by the luminance control signal input through the second luminance control signal line 151b The gate-low voltage VGL through the VSS is short-circuited or opened. For example, when the luminance control signal is in the high state, the luminance control signal in the low state is input to the gate of the second switching element Tx2 through the second luminance control signal line 151b, and the second switching element Tx2 Is turned off. On the contrary, when the luminance control signal is in a low state, a high-level luminance control signal is input to the gate of the second switching element Tx2 through the second luminance control signal line 151b, and the second switching element Tx2 is turned - Turns on. Thus, the gate line Gx connected to the turned-on second switching element Tx2 can supply the gate line voltage VGL to the display panel 110. [ The waveform of the luminance control signal and thus the output and luminance of the gate signal will be described later with reference to FIGS. 3 and 4. FIG.

The luminance control signal line 151 includes a first luminance control signal line 151a and a second luminance control signal line 151b. The luminance control signal line 151 is electrically connected to the first switching device Tx1 and the second switching device Tx2. Specifically, the first luminance control signal line 151a is connected to the gate of the first switching element Tx1, and the second luminance control signal line 151b is connected to the gate of the second switching element Tx2. In addition, the brightness controller 150 may include an inverter INV that controls the first switching device Tx1 and the second switching device Tx2 to operate in an inverted manner. The second luminance control signal line 151b is connected to the gate of the second switching element Tx2 at the output node of the inverter INV connected to the first luminance control signal line 151a.

The luminance control signal line 151 supplies a luminance control signal to the first switching device Tx1 and the second switching device Tx2. Specifically, the luminance control signals inverted from each other through the first luminance control signal line 151a and the second luminance control signal line 151b are supplied to the first switching element Tx1 and the second switching element Tx2, respectively . Accordingly, the first switching device Tx1 and the second switching device Tx2 connected to the same gate line Gx operate in opposite directions. For example, the first switching element Tx1 is turned on during a period in which a high-level luminance control signal is supplied to the first luminance control signal line 151a, and the low- The second switching element Tx2 is turned off while the luminance control signal of the second switching element Tx2 is supplied.

Further, when the first switching device Tx1 is turned on, the second switching device Tx2 is turned off, the gate signal GSx is output through the gate line Gx, The second switching device Tx2 is turned on and the gate low voltage VGL is output as the low potential voltage signal through the gate line Gx. Accordingly, the gate line Gx for outputting the gate signal GSx during the refresh period can be determined by adjusting the high-level period of the luminance control signal. A specific operation control method of the switching element according to the waveform of the luminance control signal will be described later with reference to Figs. 3 and 4. Fig.

The OLED display 100 according to an exemplary embodiment of the present invention includes a first switching device Tx1 connected to each of the plurality of gate lines G1 through Gn, a power source line VSS, and a plurality of gate lines G1 through Gn And a luminance control signal line 151 connected to the gates of the first switching device Tx1 and the second switching device Tx2, respectively. Thus, only the first switching device Tx1 connected to the predetermined gate line Gx by the luminance control signal input through the luminance control signal line 151 during the predetermined refresh period is turned on and the gate signal GSx is turned on, Is output. That is, the luminance control signal can determine the gate line Gx from which the gate signal GSx is output during one refresh period. Further, a plurality of refresh periods may be set in one frame by the luminance control signal, and gate signals may be output through different gate lines during each of the plurality of refresh periods.

3 is a waveform diagram showing a gate signal and a luminance control signal according to the low-speed driving mode of the organic light emitting diode display according to the embodiment of the present invention. 4 is a graph of a luminance according to a low-speed driving mode of an OLED display according to an exemplary embodiment of the present invention. Will be described with reference to Figs. 1 and 2 for convenience of explanation.

The slow driving mode of the OLED display 100 controls the entire refresh period to be shorter than the horizontal holding period for a unit time.

Referring to FIG. 3, the entire refresh period includes k refresh periods. A gate signal having one pulse having a gate high voltage (VGH) for a short period can be output (GSx) in one gate line during the entire refresh period. That is, the gate signal GSx may be irregularly output over each of the k refresh periods, but only one gate signal GSx is supplied to the entire gate line Gx during the entire refresh period.

For example, each of the plurality of refresh periods may be maintained for a time period in which the entire refresh period 16.6 msec is divided by k. The first gate signal GS1 is output through the first gate line G1 and the fourth gate signal GS4 is output through the fourth gate line G4 during the first refresh period, The n-1 gate signal GSn-1 may be output through the line Gn-1. The second gate signal GS2 is output through the second gate line G2 during the second refresh period and the n-2 gate signal GSn-2 is output through the (n-2) th gate line Gn- And the n-th gate signal GSn may be output through the n-th gate line Gn. The third gate signal GS3 is output through the third gate line G3 during the kth refresh period and the n-3 gate signal GSn-3 is output through the (n-3) th gate line Gn- Can be output. Thus, one gate signal GS1 through GSn is output through each of the gate lines G1 through Gn during the k refresh period in the first refresh period.

The luminance control signal CS controls whether or not a gate signal is output for each of a plurality of gate lines. Specifically, the luminance control signal CS controls the operation of the first switching element connected to the gate line to output the gate signal for a predetermined refresh period. At the same time, the luminance control signal CS controls the operation of the second switching element to output the gate-low voltage for a predetermined refresh period.

In this way, the luminance control signal CS is supplied to the luminance controller 150 so that the gate signals can be distributed to the respective gate lines during the entire refresh period. The luminance controller 150 controls the luminance control signal CS to be supplied to the luminance control signal line 151 so that the gate signal GSx is output through the predetermined gate line Gx for each of the plurality of refresh periods can do.

In particular, the entire refresh period may include two refresh periods. That is, the entire refresh period may include a first refresh period and a second refresh period, and a gate signal may be output only to a predetermined gate line in each of the first refresh period and the second refresh period.

Thus, the luminance control signal can determine the gate line for outputting the gate signal in each of the first refresh period and the second refresh period. For example, the luminance control signal controls the gate signal to be output to the odd-numbered gate lines during the first refresh period of the plurality of refresh periods, and outputs the gate signal to the even-numbered gate lines during the second refresh period of the plurality of refresh periods . When the entire refresh period is divided into two refresh periods, the output gate signal and the corresponding luminance change will be described later with reference to FIGS. 5 and 6. FIG. Furthermore, it is also possible to control whether the gate signal is output so as to include a refresh blank interval between a plurality of refresh periods. When the entire refresh period includes the refresh blank period, the output gate signal and the corresponding luminance change will be described later with reference to FIGS. 7 and 8. FIG.

4, a solid line is a graph showing a change in luminance during a refresh period and a holding period according to the low-speed driving method according to the embodiment of FIG. 3, and the one-dot chain line indicates a refresh period and a brightness period It is a graph showing the change. The comparative example is a graph according to a method of sequentially outputting the gate signals GS1 to GSn from the first gate line G1 to the nth gate line Gn without dividing the refresh interval according to the low-speed driving method.

Referring to FIG. 4, the brightness of the organic light emitting display decreases in each of the plurality of refresh periods by the low-speed driving mode shown in FIG. That is, the luminance decline is divided into k times during the entire refresh period. Specifically, only pixels arranged in the first gate line G1, the fourth gate line G4, and the (n-1) th gate line Gn-1 are initialized during the first refresh period, Are not initialized, the luminance decline during the first refresh period is reduced as compared with the case where all the pixels are initialized. During the second refresh period, only the pixels arranged in the second gate line G2, the n-2th gate line Gn-2 and the nth gate line Gn are initialized, and the pixels arranged in the remaining gate lines Since the initialization is not performed, the luminance decline during the second refresh period is reduced as compared with the case where all the pixels are initialized. The luminance drop can be reduced in the same manner during each refresh period up to the kth refresh period than when all the pixels are initialized.

Accordingly, the luminance decline during the entire refresh period is separated by the luminance decline during each of the k refresh periods, and the minimum value of the luminance is remarkably increased. As a result, a brightness drop to the extent of being visible is not generated during the refresh period, and the flicker phenomenon can be remarkably reduced even in the low-speed drive mode. In this case, the entire refresh period may be somewhat longer than the refresh period in the comparative example. However, even if the entire refresh period is prolonged, it is not visibly recognized by the human eye, and a plurality of refresh periods are separated, so that the brightness increases and the flicker phenomenon can be suppressed.

In particular, in an organic light emitting display device including a multi-type TFT, a switching TFT of a pixel is made of an oxide semiconductor TFT and a driving TFT of a pixel is made of an LTPS TFT. In this case, by separating the refresh period by the interlace method, the reliability of the switching TFT can be ensured by securing the time interval during which the switching TFT is driven during the refresh period as much as possible, and the luminance decline during the refresh period can also be reduced.

5 is a waveform diagram showing a gate signal according to a low-speed driving mode of an OLED display according to another embodiment of the present invention. FIG. 6 is a graph illustrating a luminance according to a low-speed driving mode of an OLED display according to another embodiment of the present invention. The waveform diagram according to still another embodiment of the present invention shown in Fig. 5 and the luminance graph shown in Fig. 6 are different from each other only in the number of refresh periods in the waveform diagram shown in Fig. 3 and the luminance graph shown in Fig. , And the remaining components are substantially the same, and a duplicate description thereof will be omitted.

Referring to FIG. 5, the entire refresh period includes an odd refresh period and an even refresh period. That is, k is 2 when the entire refresh period includes k refresh periods. For example, in the low-speed driving mode, the entire refresh period can be maintained for 16.6 msec and the horizontal holding period can be maintained for 983.4 msec in one second. Therefore, the odd refresh period can be maintained for 8.3 msec, and the even refresh period can be maintained for 8.3 msec.

The odd refresh period means a period for refreshing the odd-numbered gate lines, and the even-numbered refresh period means the period for refreshing the even-numbered gate lines.

5, the gate signal GS sequentially shifted to the odd-numbered gate lines is supplied during the odd-numbered refresh period, the gate signal GS sequentially shifted to the even-numbered gate lines during the even- . Specifically, during the odd-numbered refresh period, the scan signals are sequentially shifted and supplied only to the odd-numbered gate lines, and the even-numbered gate lines are supplied with the scan signals in the low-level state. Similarly, during the even-numbered refresh period, the scan signals are sequentially shifted and supplied only to the even-numbered gate lines, and the low-level scan signals are supplied to the odd-numbered gate lines. For example, the scan signals shifted in the order of the first gate line, the third gate line, and the fifth gate line are sequentially supplied in the odd-numbered refresh period for 0 sec to 8.3 msec, and the scan signals in the low state are supplied to the even- . In the even-numbered refresh period of 8.3 msec to 16.6 msec, the scan signals shifted in the order of the second gate line, the fourth gate line and the sixth gate line are sequentially supplied, and the scan signals in the low state are supplied to the odd gate lines .

In FIG. 5, although the odd refresh period is shown earlier than the even refresh period in the entire refresh period, the even refresh period may precede the odd refresh period.

6 is a graph showing a change in luminance during a refresh interval and a hold interval according to the low-speed driving method according to the embodiment of FIG.

Referring to FIG. 6, the brightness of the organic light emitting display decreases during the odd refresh period and decreases during the even refresh period due to the low speed driving mode shown in FIG. That is, the luminance drop occurs twice during the entire refresh period. Specifically, only the pixels arranged in the odd-numbered gate lines during the odd-numbered refresh period are initialized, and the pixels arranged in the even-numbered gate lines are not initialized, so that the luminance decline during the odd-numbered refresh period is about 50% . Since the pixels arranged in the even-numbered gate lines are initialized and the pixels arranged in the odd-numbered gate lines are not initialized during the even-numbered refresh period, the luminance drop during the even-numbered refresh period is about 50% .

Thus, the luminance decline during the entire refresh period is separated by the luminance decline during the odd-numbered refresh period and the luminance decline during the even-numbered refresh period, and the minimum value of the luminance is remarkably increased. As a result, a brightness drop to the extent of being visible is not generated during the refresh period, and the flicker phenomenon can be remarkably reduced even in the low-speed drive mode.

In particular, in an organic light emitting display device including a multi-type TFT, a switching TFT of a pixel is made of an oxide semiconductor TFT and a driving TFT of a pixel is made of an LTPS TFT. In this case, by separating the refresh period by the interlace method, the reliability of the switching TFT can be ensured by securing the time interval during which the switching TFT is driven during the refresh period as much as possible, and the luminance decline during the refresh period can also be reduced.

7 is a waveform diagram showing a gate signal according to a low-speed driving mode of an OLED display according to another embodiment of the present invention. 8 is a graph of a luminance according to a low-speed driving mode of an OLED display according to another embodiment of the present invention. The waveform diagram according to still another embodiment of the present invention shown in Fig. 7 and the luminance graph shown in Fig. 8 differ only in the refresh blank section in the waveform diagram shown in Fig. 5 and the luminance graph shown in Fig. Since the remaining configuration is substantially the same, a duplicate description thereof will be omitted.

Referring to FIG. 7, the slow driving mode of the OLED display according to another embodiment of the present invention controls the gate signal GS so that the refresh blank interval is included between the odd refresh period and the even refresh period. That is, the entire refresh period includes an odd refresh period, an even refresh period, and a refresh blank period. For example, in the low-speed driving mode, the entire refresh period is maintained for 16.6 msec in one second, while the odd refresh period and the even refresh period are controlled to 8 msec, and the refresh blank period is set between the odd refresh period and the even refresh period 0.6 msec, and the horizontal holding period can be maintained at 983.4 msec.

In FIG. 8, a solid line is a graph showing a change in luminance during a refresh period and a holding period by a low-speed driving method according to the embodiment of FIG.

Referring to FIG. 8, in the low-speed driving mode shown in FIG. 7, the brightness of the organic light emitting display decreases during the odd refresh period, the brightness is restored and maintained during the refresh blank period, The luminance of the display device decreases. That is, there occurs a period in which the luminance decline is divided twice during the entire refresh period, and the luminance is recovered and maintained between the two luminance declines.

Accordingly, the luminance drop occurring during the odd-numbered refresh period and the luminance drop occurring during the even-numbered refresh period can be distinguished by the refresh blank period. That is, the luminance drop occurring during the odd-numbered refresh period and the luminance drop occurring during the even-numbered refresh period are not overlapped by the refresh blank period. Thus, the refresh blank section prevents superimposition of the luminance drop between the odd-numbered refresh section and the even-numbered refresh section. Thus, the refresh blank section can suppress the increase in the luminance drop during the entire refresh period and reduce the luminance drop in the entire refresh period.

In particular, in an organic light emitting display device including a multi-type TFT, a switching TFT of a pixel is made of an oxide semiconductor TFT and a driving TFT of a pixel is made of an LTPS TFT. In this case, by separating the refresh period by the interlace method, the reliability of the switching TFT can be ensured by securing the time interval during which the switching TFT is driven during the refresh period as much as possible, and the luminance decline during the refresh period can also be reduced.

That is, when the refresh period is not divided, the luminance drop occurring during each of the odd refresh period and the even refresh period is reduced by about 50% or more from the luminance drop occurring during the entire refresh period. Particularly, since the luminance decline does not occur during the refresh blank period, the luminance declines occurring during each of the odd refresh period and the even refresh period are separated and the luminance decline occurring during the entire refresh period can be further suppressed.

The organic light emitting display according to embodiments of the present invention can be described as follows.

An organic light emitting display according to an embodiment of the present invention is provided. The organic light emitting display includes a gate driving circuit for supplying a gate signal through each of a plurality of gate lines connected to a display panel, and a luminance control unit disposed between the gate driving circuit and the display panel and electrically connected to the plurality of gate lines and the power source line . The luminance control section includes a first switching element electrically connected to each of the plurality of gate lines, a second switching element electrically connected between each of the plurality of gate lines and the power source line, and a second switching element electrically connected to the first switching element and the second switching element And a luminance control signal line. The organic light emitting display according to an embodiment of the present invention can separate gate signals during a plurality of refresh periods and supply the gate signals to the pixels, thereby significantly reducing the luminance drop in the pixels during the entire refresh period.

The luminance controller may further include an inverter for controlling the first switching element and the second switching element to operate in an inverted manner.

The first luminance control signal line is connected to the gate of the first switching element and the second luminance control signal line is connected to the first luminance control signal line and the second luminance control signal line, And may be connected to the gate of the second switching element at the output node of the inverter connected to the signal line.

The luminance control signal line may supply a luminance control signal to the first switching device and the second switching device.

The luminance control signal may control the operation of the first switching element connected to the gate line to output the gate signal for a predetermined refresh period.

The luminance control signal may control the operation of the second switching element to output the gate-low voltage for a predetermined refresh period.

The luminance control signal can control whether or not a gate signal is output for each of a plurality of gate lines.

An organic light emitting display according to another embodiment of the present invention is provided. The organic light emitting display includes a gate driver circuit and a luminance controller including a part of a plurality of gate lines electrically connecting the display panel and a part of a power supply line. The luminance control section includes a first switching element for determining whether or not a gate signal including a gate high voltage is supplied to each of the plurality of gate lines for a predetermined time, a second switching element for supplying a gate low voltage to each of the plurality of gate lines for a predetermined time, 2 switching element, and a luminance control signal line electrically connected to the first switching element and the second switching element. The organic light emitting display according to another embodiment of the present invention can significantly reduce the luminance drop in the pixels during the entire refresh period, thereby suppressing flicker in the display panel and improving the image quality of the organic light emitting display.

The luminance control section may control the luminance control signal supplied to the luminance control signal line to output the gate signal through a predetermined gate line for each of the plurality of refresh periods.

The first switching element can charge the Q node to a high state when the start voltage is in a high state.

The luminance control signal controls the gate signal to be outputted to the odd gate lines during the first refresh period of the plurality of refresh periods and controls to output the gate signal to the even gate lines during the second refresh period of the plurality of refresh periods .

The luminance control signal can control whether or not a gate signal is output so as to include a refresh blank interval between a plurality of refresh periods.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Display panel
120:
130: Gate drive circuit
140: Data driving circuit
150:
151: luminance control signal line

Claims (11)

A gate driving circuit for supplying a gate signal through each of the plurality of gate lines connected to the display panel; And
And a brightness control section disposed between the gate driving circuit and the display panel and electrically connected to the plurality of gate lines and the power source line,
Wherein the brightness control unit comprises:
A first switching element electrically connected to each of the plurality of gate lines;
A second switching device electrically connected between each of the plurality of gate lines and the power source line; And
And a luminance control signal line electrically connected to the first switching device and the second switching device. The method according to claim 1,
Wherein the luminance controller further comprises an inverter for controlling the first switching element and the second switching element to operate in an inverted manner with respect to each other. 3. The method of claim 2,
Wherein the brightness control signal line includes a first brightness control signal line and a second brightness control signal line,
The first luminance control signal line is connected to the gate of the first switching element,
And the second luminance control signal line is connected to the gate of the second switching element at an output node of the inverter connected to the first luminance control signal line. The method according to claim 1,
The brightness control signal line includes:
And supplies a luminance control signal to the first switching device and the second switching device. 5. The method of claim 4,
The luminance control signal may be,
And controls the operation of the first switching element connected to the gate line to output the gate signal for a predetermined refresh period. 5. The method of claim 4,
The luminance control signal may be,
And controls the operation of the second switching element to output a gate-low voltage for a predetermined refresh period. 5. The method of claim 4,
The luminance control signal may be,
And controls whether to output the gate signal for each of the plurality of gate lines. And a luminance control section including a part of a plurality of gate lines and a part of a power supply line electrically connecting the gate drive circuit and the display panel,
Wherein the brightness control unit comprises:
A first switching device for determining whether or not a gate signal including a gate high voltage is supplied to each of the plurality of gate lines for a predetermined time;
A second switching element for supplying a gate-low voltage to each of the plurality of gate lines for a predetermined time; And
And a luminance control signal line electrically connected to the first switching device and the second switching device. 9. The method of claim 8,
Wherein the brightness control unit comprises:
And controls the gate driver to output the gate signal through a predetermined gate line for each of a plurality of refresh periods by a luminance control signal supplied to the luminance control signal line. 10. The method of claim 9,
The luminance control signal may be,
Numbered gate lines during a first refresh period of the plurality of refresh periods and outputting the gate signals to even-numbered gate lines during a second refresh period of the plurality of refresh periods, Organic light emitting display 10. The method of claim 9,
The luminance control signal may be,
And controls whether to output the gate signal so as to include a refresh blank interval between the plurality of refresh periods.

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