KR102648992B1 - Display apparatus - Google Patents

Abstract

A display device according to an embodiment of the present specification includes a display panel provided with a plurality of pixel circuits to display an image, a gate driver for supplying gate signals to the pixels, a data driver for supplying data voltages to the pixels, and a gate driver and a data driver. and a timing controller that controls, wherein during one frame period in a low-speed driving mode, a data voltage is applied to a first section, the data voltage is maintained in a second section, and the second voltage is varied to compensate for the voltage drop. Authorize. Since different second voltages are variably applied to each line at different positions, it is possible to further compensate for luminance deviations due to different voltage drops at each position.

Description

DISPLAY APPARATUS}

This specification relates to a display device, and more specifically, to a display device that improves the flicker phenomenon between frames in a low-speed driving mode and the luminance deviation by position due to voltage drop.

Recently, as we have entered the information age, the field of displays that visually express electrical information signals has developed rapidly, and in response to this, a variety of display devices with excellent performance such as thinness, lightness, and low power consumption have been developed. is being developed.

Examples of such display devices include Liquid Crystal Display Apparatus (LCD), Organic Light Emitting Display Apparatus (OLED), and Quantum Dot Display Apparatus. Light-emitting displays are self-luminous devices that are not only advantageous in terms of power consumption due to low-voltage operation, but also have high-speed response speeds, high luminous efficiency, excellent viewing angles, and contrast ratios, and are being studied as next-generation displays. A display device implements an image through a plurality of sub-pixels arranged in a matrix form. Each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit (P) consisting of a plurality of transistors that independently drive the light-emitting element.

In order to reduce power consumption, such a display device may be driven at a driving frequency lower than the driving frequency of a normal driving mode, such as in a low-power mode or a low-speed driving mode.

As an example, while the display device is turned off, during a period of driving in AoD (Always On Display) mode that displays specific information (e.g., time, etc.) in some areas of the display panel, the driving frequency of the normal driving mode (e.g., The display device may be driven at a driving frequency lower than 60 Hz (eg, 1 Hz, 30 Hz, etc.), for example, in a low-speed driving mode.

In this case, as one frame period becomes longer in the low-speed driving mode, the extent to which luminance deteriorates during the frame period may increase. As a result, the luminance difference between frames may increase, which may be recognized as flicker on the display panel, and a voltage drop may occur due to wiring resistance inside the display panel, which is a problem in that the luminance difference may worsen depending on the position of the display panel. exist.

Accordingly, the inventors of the present specification conducted several experiments to improve the luminance difference by location due to voltage drop. Through various experiments, a display device with a new structure was invented that can reduce the flicker phenomenon between frames and improve the luminance deviation at each position of the display panel due to voltage drop.

This specification relates to a display device that improves the flicker phenomenon between frames in a low-speed driving mode and the luminance deviation by position due to voltage drop.

A display device according to an embodiment of the present specification includes a light-emitting element that emits light with a brightness corresponding to the size of the driving current, a driving transistor that provides a driving current to the light-emitting element, a plurality of switching transistors that control the driving of the driving transistor, and a second transistor. It includes a first wire supplying a voltage and a second wire supplying a second voltage, wherein during one frame period in a low-speed driving mode, a data voltage is applied to the first section, and the first and second wires are applied to the second section. The first and second voltages are applied at least once through two wires, and the second voltage may be applied variably for each line in the second section.

In addition, a display device according to an embodiment of the present specification includes a display panel provided with a plurality of pixel circuits to display an image, a gate driver supplying a gate signal to the plurality of pixels, a data driver supplying a data voltage to the plurality of pixels, and It includes a timing controller that controls the gate driver and the data driver, and applies a data voltage to a first section during one frame period in a low-speed drive mode, maintains the data voltage in a second section, and provides a device to compensate for the voltage drop. 2 Voltage can be applied in a variable manner.

In addition to the technical problems of the present specification mentioned above, other features and advantages of the present specification are described below, or can be clearly understood by those skilled in the art from such descriptions and descriptions.

According to embodiments of the present specification, when driving in a low-speed drive mode, the second voltage is periodically supplied to the second section after the first section, so that the luminance waveform appearing in the second section can be the same as that of the first section. , by preventing flicker from being recognized in a section driven in a low-speed drive mode, power consumption of the display device can be reduced while maintaining image quality.

In addition, since different second voltages are variably applied to different positions, luminance deviation due to different voltage drops in each position can be further compensated.

The effects according to the present specification are not limited to the contents exemplified above, and further various effects are included in the present specification.

1 is a block diagram of a display device according to an embodiment of the present specification.
2 is a pixel circuit of a display device according to an embodiment of the present specification.
FIG. 3 shows an example of driving timing of the pixel circuit shown in FIG. 2.
It is a drawing.
FIG. 4 is a diagram of a voltage waveform applied on a line-by-line basis in a display device according to an embodiment of the present specification.
FIG. 5 is a diagram of a voltage waveform variably applied to each line for 1H in a display device according to an embodiment of the present specification.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms. The embodiments of the present specification only serve to ensure that the disclosure of the present specification is complete, and that the present specification is not limited to the embodiments disclosed below. It is provided to fully inform those skilled in the art of the scope of the invention, and the invention of this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative and are not limited to the matters shown in the specification. Like reference numerals refer to like elements throughout the specification. Additionally, when describing examples of the present specification, if it is determined that detailed descriptions of related known technologies may unnecessarily obscure the gist of the present specification, the detailed descriptions will be omitted.

When “comprises,” “has,” “consists of,” etc. are used as mentioned in this specification, other parts may be added unless “only” is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as “on,” “at the top,” “at the bottom,” “next to,” etc., “immediately” or “directly.” Unless used, one or more other parts may be placed between the two parts.

In the case of a description of a temporal relationship, for example, when a temporal relationship is described as “after,” “sequentially,” “next,” “before,” etc., ‘immediately’ or ‘directly’ is not used. Cases that are not consecutive may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical idea of the present specification.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, “at least one of the first, second, and third items” means each of the first, second, or third items, as well as two of the first, second, and third items. It can mean a combination of all items that can be presented from more than one.

Each feature of the various examples of the present specification can be partially or entirely combined or combined with each other, and various technological interconnections and operations are possible, and each example can be implemented independently of each other or together in a related relationship. .

Hereinafter, an example of a display device according to an embodiment of the present specification will be described in detail with reference to the attached drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, the scale of the components shown in the attached drawings has a different scale from the actual scale for convenience of explanation, and is therefore not limited to the scale shown in the drawings.

1 is a block diagram of a display device according to an embodiment of the present specification.

The display device according to the present specification includes a display panel 100, a gate driver 110, a data driver 120, and a timing controller (T-CON) 130.

The display panel 100 includes a display area and a non-display area provided around the display area. The display area is an area where pixel circuits (P) are provided to display images. The non-display area is located on the outside of the display panel 100 and is an area that protects the display area from external shock. The display panel 100 is provided with gate lines (GL1 to GLp, p is a positive integer of 2 or more), data lines (DL1 to DLq, q is a positive integer of 2 or more), and sensing lines (SL1 to SLq). do. The data lines (DL1 to DLq) and the sensing lines (SL1 to SLq) may intersect the gate lines (GL1 to GLp). The data lines (DL1 to DLq) and the sensing lines (SL1 to SLq) may be parallel to each other. The display panel 100 may include a lower substrate on which pixel circuits P are provided and an upper substrate that performs an encapsulation function to protect the pixel circuits P from external foreign substances. Each of the pixel circuits P may be connected to one of the gate lines GL1 to GLp, one of the data lines DL1 to DLq, and one of the sensing lines SL1 to SLq.

The gate driver 110 receives a gate driver control signal (GCS) from the timing controller 130. The gate driver 110 generates gate signals according to the gate driver control signal (GCS). The gate driver 110 supplies gate signals to the gate lines G1 to Gp in a predetermined order. The predetermined order may be a sequential order. The gate driver 110 according to the embodiment may be implemented in a gate in panel (GIP) method integrated or built into one side of the non-display area of the display panel 100 along with the transistor manufacturing process. Each stage of the gate driver 110 implemented in the gate-in-panel method may be connected one-to-one with the gate lines GL1 to GLp, but the present invention is not limited to this.

The data driver 120 receives a data driver control signal (DCS) from the timing controller 130, generates data voltages according to the data driver control signal (DCS), and supplies them to the data lines DL1 to DLq. The data driver 120 according to the embodiment may be implemented using a drive integrated circuit (Drive IC, D-IC) integrated or embedded in one side of the non-display area of the display panel 100.

The data driver 120 senses the voltage and current characteristics of each pixel circuit P through the sensing lines SL1 to SLq. The data driver 120 generates sensing data (SEN) and supplies it to the timing controller 130.

The timing controller 130 may be integrated or built into one side of the non-display area of the display panel 100. The timing controller 130 receives from the outside a timing signal (TS) that controls the display timing of an image and digital video data (DATA) containing color-specific information for implementing an image. A timing signal (TS) and digital video data (DATA) are input to the input terminal of the timing controller 130 according to a set protocol. Additionally, the timing controller 130 receives sensing data SEN according to the voltage and current characteristics of each pixel circuit P from the data driver 120.

The timing signal (TS) includes a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and a dot clock (DCLK). Includes. The timing controller 130 compensates the digital video data (DATA) based on the sensing data (SEN).

The timing controller 130 generates driver control signals for controlling the operation timing of the gate driver 110, the data driver 120, and the sensing driver. The driver control signals include a gate driver control signal (GCS) for controlling the operation timing of the gate driver 110, a data driver control signal (DCS) for controlling the operation timing of the data driver 120, and an operation timing of the sensing driver. Includes a sensing driver control signal for controlling.

The timing controller 130 operates the data driver 120 and the sensing driver in one of the display mode and the sensing mode according to the mode signal. The display mode is a mode in which the pixel circuits (P) of the display panel 100 display an image, and the sensing mode is a mode in which the current or voltage of the driving transistor (DT) of each pixel circuit (P) of the display panel 100 is sensed. This is the mode. When the waveform of the scan signal and the sensing signal supplied to each of the pixel circuits (P) change in the display mode and the sensing mode, the data driver control signal (DCS) and the sensing driver control in the display mode and the sensing mode, respectively. Signals can also change. Therefore, depending on which mode is the display mode or the sensing mode, the timing controller 130 generates a data driver control signal (DCS) and a sensing driver control signal in response to the corresponding mode.

The timing controller 130 outputs the gate driver control signal (GCS) to the gate driver 110. The timing controller 130 outputs compensated digital video data and a data driver control signal (DCS) to the data driver 120. The timing controller 130 outputs a sensing driver control signal to the sensing driver.

The timing controller 130 generates a mode signal for driving the data driver 120 and the sensing driver according to whether the display mode or the sensing mode is to be driven. The timing controller 130 operates the data driver 120 and the sensing driver in one of the display mode and the sensing mode according to the mode signal.

The gate driver 110, data driver 120, and timing controller 130 of the display device according to the present specification may be implemented as an integrated drive integrated circuit (One Chip Drive IC) implemented as a single integrated circuit.

2 is a pixel circuit of a display device according to an embodiment of the present specification.

The pixel circuit (P) according to an embodiment of the present specification includes first to sixth switching transistors (T1 to T6), a driving transistor (D-TFT), a capacitor (Cstg), and a light emitting element (EL). Here, the light emitting device (EL) may be a self-luminous device that can emit light on its own, such as an organic light emitting diode (OLED). The first to third switching transistors (T1 to T3), the fifth to sixth switching transistors (T5 to T6), and the driving transistor (D-TFT) of the pixel circuit (P) according to another example of the present specification are P-type MOS. A transistor will be described as an example, and the fourth switching transistor T4 will be described as an N-type MOS transistor.

P-type MOS transistors are relatively more reliable than N-type MOS transistors. When the transistor is a P-type MOS transistor, there is an advantage that the current flowing through the light emitting element (EL) is not shaken by the capacitor (Cstg) because the drain electrode is fixed to the high potential driving voltage (VDDEL). Therefore, it has the advantage of being easy to supply current stably. For example, the P-type MOS transistor must be connected to the anode electrode of the light emitting device (EL), so the OLED part must be connected to the corresponding part in the top emission, so when the transistor operates in the saturation region, the light emitting device Reliability is relatively high because a constant current can flow regardless of changes in (EL) current and threshold voltage. The display device according to an embodiment of the present invention has been described using a pixel circuit structure using a P-type MOS transistor as an example, but is not limited thereto.

The gate electrode of the first switching transistor (T1) receives the second scan signal (Scan2n). The drain electrode of the first switching transistor (T1) is supplied with the data voltage (Vdata). The source electrode of the first switching transistor (T1) is connected to the drain electrode of the driving transistor (D-TFT). The first switching transistor T1 is turned on by the second scan signal Scan2n and supplies the data voltage Vdata to the drain electrode of the driving transistor D-TFT.

The gate electrode of the second switching transistor T2 receives the emission control signal EMn. The drain electrode of the second switching transistor (T2) is supplied with a high potential driving voltage (VDDEL). The source electrode of the second switching transistor (T2) is connected to the drain electrode of the driving transistor (D-TFT). The second switching transistor T2 is turned on by the emission control signal EMn and supplies the high potential driving voltage VDDEL to the drain electrode of the driving transistor D-TFT.

The gate electrode of the third switching transistor T3 receives the third scan signal Scan3n. The drain electrode of the third switching transistor (T3) is supplied with the first voltage (Vini).

The source electrode of the third switching transistor (T3) is connected to the source electrode of the driving transistor (D-TFT). The third switching transistor T3 is turned on by the third scan signal Scan3n to initialize the third node N3.

The gate electrode of the fourth switching transistor T4 receives the first scan signal Scan1n. The drain electrode of the fourth switching transistor (T4) is connected to the gate electrode of the driving transistor (D-TFT).

The source electrode of the fourth switching transistor (T4) is connected to the source electrode of the driving transistor (D-TFT).

The fourth switching transistor T4 is turned on by the first scan signal Scan1n and controls the operation of the driving transistor D-TFT through the high potential driving voltage VDDEL stored in the capacitor Cstg.

The fourth switching transistor T4 can mainly be an N-type MOS transistor to form an oxide semiconductor. Because the N-type MOS transistor uses electrons rather than holes as carriers, the mobility is faster than the P-type MOS transistor, so the switching speed can be fast. In addition, since the N-type MOS transistor must be connected to the cathode electrode of the light emitting element (EL), an oxide semiconductor with N-type characteristics can be configured as an N-type MOS transistor in the bottom emission method. However, it is not limited to this and can be configured with other types of transistors.

The gate electrode of the fifth switching transistor T5 receives the emission control signal EMn. The drain electrode of the fifth switching transistor (T5) is connected to the source electrode of the driving transistor (D-TFT). The source electrode of the fifth switching transistor T5 is connected to the anode electrode of the light emitting element EL. The fifth switching transistor T5 is turned on by the light emission control signal EMn to supply a driving current to the anode electrode of the light emitting element EL.

The gate electrode of the sixth switching transistor (T6) receives the third scan signal (Scan3n+1). The drain electrode of the sixth switching transistor T6 is supplied with the second voltage Var. The source electrode of the sixth switching transistor (T6) is connected to the anode electrode of the light emitting element (EL). The sixth switching transistor (T6) is turned on by the third scan signal (Scan3n+1) and supplies the second voltage (Var) to the anode electrode of the light emitting element (EL).

The gate electrode of the driving transistor (D-TFT) is connected to the drain electrode of the fourth switching transistor (T4). The drain electrode of the driving transistor (D-TFT) is connected to the source electrode of the first switching transistor (T1). The source electrode of the driving transistor (D-TFT) is connected to the source electrode of the third switching transistor (T4). The driving transistor (D-TFT) is turned on by the voltage difference between the source electrode and the drain electrode of the fourth switching transistor (T4), and flows a driving current to the light emitting element (EL).

One side of the capacitor (Cstg) is supplied with a high potential driving voltage (VDDEL). The other side of the capacitor (Cstg) is connected to the gate electrode of the driving transistor (D-TFT). The capacitor (Cstg) stores the voltage of the gate electrode of the driving transistor (D-TFT).

The anode electrode of the light emitting element EL is connected to the source electrode of the fifth switching transistor T5 and the source electrode of the sixth switching transistor T6. The cathode electrode of the light emitting element (EL) is supplied with a low potential driving voltage (VSSEL). The light emitting element (EL) emits light with a predetermined brightness by the driving current flowing through the driving transistor (D-TFT).

In this specification, the first voltage (Vini) is supplied to compensate for the stress of the driving transistor (D-TFT), and the second voltage (Var) is supplied to perform an anode reset operation.

During the anode reset operation, the switching transistor located between the anode electrode of the light emitting element (EL) and the driving transistor (D-TFT) and controlled by the light emission control signal (EM) is turned off, and the light emitting element (EL) A second voltage (Var) is supplied to the anode electrode. The sixth switching transistor T6 that supplies the second voltage Var is connected to the anode electrode of the light emitting element EL.

The pixel circuit P according to the embodiment of the present specification is driven using the first to third scan signals (Scan1 to Scan3). The third scan signal (Scan3) is a different signal from the first scan signal (Scan1). For example, the first to third scan signals (Scan1 to Scan3) may have the same signal size but different phases. Three scan drivers are required to generate the first to third scan signals (Scan1 to Scan3). The pixel circuit (P) according to an embodiment of the present specification turns on the first to fifth switching transistors (T1 to T5) using the third scan signal (Scan3) that turns on the sixth switching transistor (T6). The sixth transistor (T6) can be turned on in the off state.

The sixth switching transistor T6 that supplies the second voltage Var is turned on by the scan signal. To drive the driving transistor (D-TFT) and supply the second voltage (Var) to the anode electrode of the light emitting element (EL) separately, the driving transistor (D-TFT) is driven or the driving transistor (D- The scan signal (Scan) that initializes the TFT and the scan signal (Scan) that controls the sixth switching transistor (T6) that controls the supply of the second voltage (Var) to the anode electrode of the light emitting element (EL) are separated from each other. do.

The third switching transistor T3 and the sixth switching transistor T6 may be used together with the third scan signal Scan3 of odd-numbered lines and even-numbered lines in one pixel circuit P. The third scan signal (Scan3n) of the nth line may be supplied to the third switching transistor (T3), and the third scan signal (Scan3n+1) of the n+1th line may be supplied to the sixth switching transistor (T6). there is. In other words, the third scan signal (Scan3) supplied to the pixel circuit (P) of the n-th line is the third scan signal (Scan3n) of the n-th line and the third scan signal (Scan3n+1) of the n+1-th line. can be used. Accordingly, the third scan signal Scan3 supplied to the pixel circuit P may have the same operating waveform and have different phases.

The pixel circuit (P) according to an embodiment of the present specification turns on the switching transistor that supplies the first voltage (Vini) and the second voltage (Var) by using a light emission control signal and a scan signal to turn on the driving transistor (D). -TFT) turns off the switching transistor connecting the source electrode and the anode electrode of the light emitting element (EL) to block the driving current of the driving transistor (D-TFT) from flowing to the anode electrode of the light emitting element (EL), The pixel circuit (P) can be configured so that the anode electrode is not affected by any voltage other than the voltage for resetting the anode.

In this specification, in order to reduce the difference between discharge between the first section and the second section, the driving current of the driving transistor (D-TFT) is blocked and then the anode reset of the light emitting element (EL) is performed. The magnitude of the first voltage (Vini) and the second voltage (Var) in the second section may be equal to or smaller than the magnitude of the first voltage (Vini) and the second voltage (Var) in the first section. However, it is not limited to this. For example, the sizes of the first voltage (Vini) and the second voltage (Var) in the second section may have arbitrary sizes to perform an anode reset. In this case, the magnitude of the first voltage (Vini) and the second voltage (Var) in the second section may be greater than the magnitude of the first voltage (Vini) and the second voltage (Var) in the first section.

FIG. 3 is a diagram showing an example of driving timing of the pixel circuit shown in FIG. 2.

Referring to FIG. 3, one frame period may be divided into a first section and a second section in accordance with the synchronization signal (SYNC).

In the first section, a data voltage (Vdata), a first voltage (Vini), and a second voltage (Var) for driving the pixel circuit (P) may be applied to the pixel circuit (P).

The first section is a section for initializing the voltage charged or remaining in the capacitor Cstg and the first to fourth nodes N1 to N4. The first section is provided in part at the start of each frame. In the first section, the influence of the data voltage (Vdata) and driving voltage stored in the previous frame (Frame) is removed.

After the refresh operation, the light emitting element EL may emit light according to the data voltage Vdata applied to the pixel circuit P.

The second section is a section for charging or setting the data voltage (Vdata) and driving voltage of each frame in the capacitor C1 and the first to fourth nodes (N1 to N4). The second section lasts after the first section of each frame is completed until the first section of the next frame begins. In the second section, the driving transistor (D-TFT) and the light emitting element (EL) are driven according to the first to third scan signals (Scan1 to Scan3) and the light emission control signal (EM).

That is, initialization and application of the data voltage (Vdata) may be performed in the first section of one frame period, and light emission of the light emitting element (EL) may be performed in the second section.

In the second section, when driving at low speed with a low frame frequency, the anode reset operation is not performed, or the anode reset operation is performed at least once. In the second section, the anode electrode of the light emitting element (EL) is reset to the second voltage (Var). In the second section, in order to improve flicker that occurs as the second section becomes longer during low-speed driving, the fourth node N4 is periodically reset to a constant voltage in the second section within the frame.

In the second section, when the flicker problem is not serious, such as when the flicker problem due to relatively low-speed driving is small or when the frame frequency is relatively high during low-speed driving, the anode reset operation may not be performed or may be performed only once. On the other hand, when the flicker problem is serious, such as when the flicker problem is large due to relatively low-speed driving or when the frame frequency is relatively low during low-speed driving, each frame is divided into sub-frames and sub-frames are used. Anode reset operation can be applied depending on the frame.

For example, in 1Hz low-speed driving, if 1 frame is divided into 60 sub-frames, the anode reset operation can be performed 60 times.

Specifically, in the second section, the data voltage (Vdata) maintains the low logic level (L). Additionally, the first scan signal (Scan1) maintains a low logic level (L) in the second section, and the second scan signal (Scan2) maintains a high logic level (H) in the second section.

Accordingly, the data voltage (Vdata) is not supplied in the second section. Additionally, the first and fourth switching transistors T1 and T4 remain turned off in the second period.

The third scan signal (Scan3) is applied to the odd-numbered scan line and the even-numbered scan line with a phase difference.

The third scan signal (Scan3) has a low logic level (L) in part of the second section and maintains a high logic level (H) in the remaining section. In a section where the third scan signal (Scan3) of the odd-numbered line has a low logic level (L), the third switching transistor (T3) is turned on. The turned-on third switching transistor T3 supplies the first voltage Vini to the third node N3. In a section where the third scan signal (Scan3) of the even-numbered line has a low logic level (L), the sixth switching transistor (T6) is turned on. The turned-on sixth switching transistor T6 supplies the second voltage Var to the fourth node N4.

The emission control signal (EM) has a high logic level (H) in the second section and maintains a low logic level (L) in the remaining sections. In a section where the emission control signal EM has a low logic level L, the second switching transistor T2 and the fifth switching transistor T5 are turned on.

Since the emission control signal (EM) maintains the high logic level (H) during anode reset, the second switching transistor (T2) and the fifth switching transistor (T5) are turned off. Accordingly, the current of the driving transistor (D-TFT) can be blocked during anode reset.

The display device according to an embodiment of the present specification applies a second voltage (Var) to the fourth node (N4) through the sixth switching transistor (T6) using the third scan signal (Scan3) during an anode reset operation, The anode electrode of the light emitting element (EL) connected to the fourth node (N4) is reset to the second voltage (Var).

Additionally, since the second voltage Var is applied to the anode electrode of the light emitting device EL during the anode reset operation, the brightness displayed by the light emitting device EL may vary depending on the second voltage Var.

The second voltage Var is a voltage to prevent flicker from being recognized in a low-speed driving mode, and may be a voltage to match the luminance shown by the light emitting element EL to the luminance shown during the refresh period.

Additionally, by allowing the luminance waveform shown by the light emitting device EL in the first section to appear repeatedly in the second section, it is possible to prevent flicker from being recognized due to a decrease in luminance in the second section in the low-speed driving mode.

FIG. 4 is a diagram of a voltage waveform applied on a line-by-line basis in a display device according to an embodiment of the present specification. FIG. 5 is a diagram of a voltage waveform variably applied to each line for 1H in a display device according to an embodiment of the present specification.

Referring to FIGS. 4 and 5 , the second voltage may be subdivided and variably applied for each horizontal line depending on the position of the pixel circuit P within each sub frame.

The display panel experiences a voltage drop (IR drop) in the high potential driving voltage (VDDEL) due to the resistance component of the internal wiring. The magnitude of the voltage drop (IR drop) may vary depending on the resistance value for each position, and accordingly, a level difference may occur in the high potential driving voltage (VDDEL) applied to each pixel circuit (P).

Voltage drop (IR drop) can be compensated by varying the high-potential driving voltage (VDDEL) in real time, but in this case, capacitor (Cstg) coupling is performed, so the degree of compensation may vary depending on the time constant or charging time, and the parasitic capacitor component There may be changes in current due to influence or voltage fluctuations.

When a display device according to an embodiment of the present specification improves flicker by applying a second voltage in a second section, the second voltage is varied in units of 1H (horizontal time) rather than in units of sub frames. By applying , flicker and voltage drop (IR drop) can be improved at the same time. In other words, referring to the enlarged view of A in FIG. 4, the second voltage varied in 1H units is sequentially applied to each sub frame, so the second voltage is applied in sub frame units. Flicker can be improved more effectively, and the purpose of voltage drop (IR drop) can also be achieved at the same time. For example, in the first anode reset section (t1) of 1H (Horizontal time), the first anode reset section (t1) of 5V 2 When voltage (Var) is applied, only the third scan signal (Scan3n+1) of the n+1th line operates in the first anode reset section (t1), and the third scan signal (Scan3) operates in the remaining lines. You may not. For example, 5V may be applied to the nth line, and no voltage may be applied to the remaining lines. In addition, when the second voltage (Var) of 4V is applied in the second anode reset period (t2) of 1H (horizontal time), only the third scan signal (Scan3n+2) of the n+2th line resets the second anode. It operates in the section t2, and the third scan signal Scan3 may not operate in the remaining lines. Therefore, 4V may be applied to the n+1th line, and no voltage may be applied to the remaining lines.

In the display device according to the embodiment of the present specification, the second power wiring that supplies the second voltage is commonly connected to all pixel circuits (P), but the third scan signal (Scan3) is applied at a low logic level (L). The second voltage can be supplied only to the pixel circuit (P) where the sixth switching transistor (T6) is turned on.

In addition, since the second voltage (Var) is variably applied to different positions in units of 1H (Horizontal time) rather than in units of sub frames, the luminance deviation due to different voltage drops (IR Drop) at each location is further compensated. can do.

In addition, instead of the power driving circuit required when changing the high potential driving voltage (VDDEL) using a large current, the effect of improving the voltage drop (IR drop) can be achieved by simply applying the second voltage (Var) to each line, thereby reducing costs. You can also get effects.

A display device according to an embodiment of the present specification includes a light-emitting element that emits light with brightness corresponding to the magnitude of the driving current, a driving transistor that provides a driving current to the light-emitting element, a plurality of switching transistors that control the driving of the driving transistor, and a first It includes a first wire supplying a voltage and a second wire supplying a second voltage, wherein a data voltage is applied to a first section during one frame period in a low-speed driving mode, and the first and second lines are applied to a second section. The display panel may be one in which the first and second voltages are applied at least once through two wires, and the second voltage is applied variably for each line in the second section.

In the display device according to an embodiment of the present specification, the second section may be a display panel that operates by dividing into at least one subframe to maintain a data voltage.

In the display device according to an embodiment of the present specification, the subframe may be a display panel that is maintained the same as or longer than the length of the first section.

In a display device according to an embodiment of the present specification, the first voltage is supplied to compensate for the stress of the driving transistor, and the second voltage is supplied to compensate for the anode reset operation and voltage drop, and may be a display panel.

In a display device according to an embodiment of the present specification, the second voltage may be applied sequentially to a display panel, varying one line at a time in 1H units for each subframe.

In a display device according to an embodiment of the present specification, the magnitude of the first and second voltages applied in the second section may be the same as or different from the magnitude of the first and second voltages applied in the first section.

In the display device according to an embodiment of the present specification, one switching transistor may be a display panel connected between the source electrode of the driving transistor and the anode electrode of the light emitting device, and turned on by a light emission control signal.

In the display device according to the embodiment of the present specification, a plurality of switching transistors are connected between the first wiring and the source electrode of the driving transistor, or are connected to the second wiring and the anode electrode of the light emitting device, and are turned on by different scan signals. It can be a display panel that comes on.

In a display device according to an embodiment of the present specification, different scan signals may have the same operating waveform and different phases of the display panel.

In the display device according to an embodiment of the present specification, a plurality of switching transistors include,

A first switching transistor that is turned on by the second scan signal and supplies the data voltage to the first node, and a fourth switching transistor that is turned on by the first scan signal and supplies the voltage of the second node to the third node. , a second switching transistor that is turned on by a light emission control signal and supplies a high-potential driving voltage to the first node, a fifth switching transistor that supplies the voltage of the third node to the fourth node, and a third scan signal. - It may be a display panel including a sixth switching transistor that is turned on to supply the first voltage to a third node and the second voltage to a fourth node.

The display device according to an embodiment of the present specification may be a display panel that further includes a capacitor for storing a data voltage.

In a display device according to an embodiment of the present specification, a display panel is provided with a plurality of pixel circuits to display images, a gate driver for supplying gate signals to the pixels, a data driver for supplying data voltages to the pixels, and the gate driver and the data It includes a timing controller that controls the driver, and in a low-speed driving mode, during one frame period, a data voltage is applied to a first section, the data voltage is maintained in a second section, and the second voltage is varied to compensate for the voltage drop. It may be a display device that authorizes.

In the display device according to an embodiment of the present specification, the second section may be a display device that operates divided into at least one subframe to maintain a data voltage.

In a display device according to an embodiment of the present specification, a subframe may be maintained the same as or longer than the length of the first section.

In the display device according to an embodiment of the present specification, the pixel circuit includes a driving transistor and a plurality of switching transistors, the first voltage is supplied to compensate for the stress of the driving transistor, and the second voltage is supplied to perform the anode reset operation and voltage drop. It may be an indication device supplied to compensate.

In a display device according to an embodiment of the present specification, the second voltage may be applied sequentially by varying one line in units of 1H for each subframe.

In a display device according to an embodiment of the present specification, the second voltage supplied to the light emitting element in the second section may be varied to have the same luminance as the data voltage applied in the first section.

In a display device according to an embodiment of the present specification, the magnitude of the first and second voltages applied in the second section may be the same as or different from the magnitude of the first and second voltages applied in the first section.

In the display device according to an embodiment of the present specification, the gate driver may be a display device that turns on the plurality of switching transistors according to different scan signals.

In a display device according to an embodiment of the present specification, different scan signals may have the same operating waveform and different phases.

The features, structures, effects, etc. described in the examples of the present specification described above are included in at least one example of the present specification and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. exemplified in at least one example of this specification can be combined or modified for other examples by those skilled in the art to which this specification pertains. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this specification pertains that various substitutions, modifications, and changes are possible without departing from the technical details of the present specification. It will be clear to those who have the knowledge of. Therefore, the scope of the present specification is indicated by the claims described later, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present specification.

100: display panel
110: Gate driver
120: data driving unit
130: Timing controller

Claims (20)

A light emitting element that emits light according to a driving current;
a driving transistor providing the driving current to the light emitting device;
a plurality of switching transistors that control driving of the driving transistor; and
It includes a first wire supplying a first voltage to the light emitting device and a second wire supplying a second voltage,
One frame period is divided into a first section and a second section, and a data voltage is applied to the first section, and the first and second voltages are applied at least once through the first and second wirings in the second section. is applied, and the second voltage is applied variably for each line in the second section,
The display device operates by dividing the second section into at least one sub-frame to maintain the data voltage.
delete According to claim 1,
The display device wherein the sub-frame is maintained the same as or longer than the length of the first section.
According to claim 3,
The first voltage is supplied to compensate for the stress of the driving transistor,
The second voltage is supplied to compensate for anode reset operation and voltage drop.
According to claim 4,
The display device wherein the second voltage is applied sequentially, varying one line at a time in units of 1H for each subframe.
According to claim 5,
The magnitude of the first and second voltages applied in the second section is the same as or different from the magnitude of the first and second voltages applied in the first section.
According to claim 6,
At least one of the plurality of switching transistors is connected between the source electrode of the driving transistor and the anode electrode of the light emitting device,
A display device that is turned on by a light-emitting control signal.
According to claim 7,
The plurality of switching transistors are connected between the first wiring and the source electrode of the driving transistor, or are connected to the second wiring and the anode electrode of the light emitting device, and are turned on by different scan signals.
According to claim 8,
The different scan signals have the same operating waveform and different phases.
According to claim 1,
The plurality of switching transistors are:
a first switching transistor that is turned on by a second scan signal to supply a data voltage to the first node;
a fourth switching transistor that is turned on by the first scan signal to supply the voltage of the second node to the third node;
a second switching transistor that is turned on by a light emission control signal to supply a high potential driving voltage to the first node and a fifth switching transistor to supply the voltage of the third node to the fourth node; and
A display device comprising a sixth switching transistor that is turned on by a third scan signal to supply the first voltage to the third node and the second voltage to the fourth node.
According to claim 10,
A display device further comprising a capacitor storing the data voltage.
A display panel comprising a plurality of pixel circuits to which first and second voltages are applied to display an image;
a gate driver that supplies gate signals to the plurality of pixels;
a data driver that supplies data voltage to the plurality of pixels; and
It includes a timing controller that controls the gate driver and the data driver,
One frame period is divided into a first section and a second section, and a data voltage is applied to the first section, the data voltage is maintained in the second section, and the second voltage is varied to compensate for the voltage drop, so that the plurality of applied to at least one light emitting element of the pixel circuit,
The display device operates by dividing the second section into at least one sub-frame to maintain the data voltage.
delete According to claim 12,
The display device wherein the sub-frame is maintained the same as or longer than the length of the first section.
According to claim 14,
The pixel circuit includes a driving transistor and a plurality of switching transistors,
The first voltage is supplied to compensate for the stress of the driving transistor,
The second voltage is supplied to compensate for anode reset operation and voltage drop.
According to claim 15,
The display device wherein the second voltage is applied sequentially, varying one line at a time in units of 1H for each subframe.
According to claim 16,
The second voltage supplied to the light emitting element in the second section is varied to have the same luminance as the data voltage applied in the first section.
According to claim 17,
The magnitude of the first and second voltages applied in the second section is the same as or different from the magnitude of the first and second voltages applied in the first section.
According to claim 18,
The gate driver,
A display device that turns on the plurality of switching transistors according to different scan signals.
According to claim 19,
The different scan signals have the same operating waveform and different phases.

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