KR20210073129A - Display apparatus - Google Patents

Abstract

A display apparatus in accordance with an embodiment of the present invention comprises: a display panel provided with a plurality of pixel circuits and configured to display an image; a gate driver configured to supply gate signals to pixels; a data driver configured to supply a data voltage to the pixels; and a timing controller configured to control the gate driver and the data driver. In a low-speed driving mode, during one frame period, a data voltage is applied to a first section, and a second voltage is varied and applied to a second section so that the data voltage is maintained in the second section and a voltage drop is compensated. Since different second voltages are variably applied to lines at different positions, respectively, a luminance deviation, caused by voltage drops that are different for respective locations, can be further compensated.

Description

display device {DISPLAY APPARATUS}

The present specification relates to a display device, and more particularly, to a display device having improved flicker between frames in a low-speed driving mode and a luminance deviation for each location due to a voltage drop.

Recently, as we enter the information age, the field of display that visually expresses electrical information signals has developed rapidly, and in response to this, various display devices (Display Apparatus) with excellent performance of thinness, light weight, and low power consumption have been developed. is being developed

Examples of such a display device include a Liquid Crystal Display Apparatus (LCD), an Organic Light Emitting Display Apparatus (OLED), and a Quantum Dot Display Apparatus. The light emitting display device is a self-luminous device, which is not only advantageous in terms of power consumption due to low voltage driving, but also has excellent high-speed response speed, high luminous efficiency, viewing angle, and contrast ratio, and is being studied as a next-generation display. A display device implements an image through a plurality of sub-pixels arranged in a matrix form. Each of the plurality of sub-pixels includes a pixel circuit P including a light emitting element and a plurality of transistors independently driving the light emitting element.

In order to reduce power consumption, the display device may be driven at a lower driving frequency than that of a normal driving mode in a low power mode or a low speed driving mode.

For example, during a period in which the display device is driven in an Always On Display (AoD) mode that displays specific information (eg, time, etc.) on a partial area of the display panel in a state in which the display device is turned off, the driving frequency of the normal driving mode (eg, The display device may be driven in a driving frequency (eg, 1 Hz, 30 Hz, etc.) lower than 60 Hz), for example, in a low-speed driving mode.

In this case, as one frame period becomes longer in the low-speed driving mode, the width at which the luminance decreases during the frame period may increase. As a result, the luminance deviation between frames increases, which may be recognized as flicker on the display panel, and a voltage drop may occur due to wiring resistance inside the display panel, so that the luminance deviation may become more severe for each position of the display panel. exist.

Accordingly, the inventors of the present specification conducted several experiments to improve the luminance deviation for each location due to the voltage drop. Through various experiments, a display device having a new structure that can reduce the flicker between frames and improve the luminance deviation for each position of the display panel due to the voltage drop was invented.

The present specification relates to a display device in which a flicker phenomenon between frames and a luminance deviation for each location due to a voltage drop are improved in a low-speed driving mode.

A display device according to an exemplary embodiment of the present specification includes a light emitting device that emits light with a brightness corresponding to a level of a driving current, a driving transistor that provides a driving current to the light emitting device, a plurality of switching transistors that control driving of the driving transistor, and a first a first wiring supplying a first voltage and a second wiring supplying a second voltage, wherein the data voltage is applied to a first period during one frame period in a low-speed driving mode, and the first and second wirings are applied to the second period The first and second voltages may be applied at least once through the second wiring, and the second voltage may be varied and applied for each line in the second section.

In addition, the display device according to the exemplary embodiment of the present specification includes a display panel provided with a plurality of pixel circuits to display an image, a gate driver supplying a gate signal to the plurality of pixels, a data driver supplying a data voltage to the plurality of pixels, and a timing controller for controlling the gate driver and the data driver, wherein the data voltage is applied in a first period during one frame period in a low speed driving mode, the data voltage is maintained in a second period, and the second period is configured to compensate for a voltage drop. 2 The voltage can be varied and applied.

In addition to the technical problems of the present specification mentioned above, other features and advantages of the present specification will be described below or will be clearly understood by those of ordinary skill in the art to which this specification belongs from the description and description.

According to the embodiments of the present specification, when driving in the low-speed driving mode, by periodically supplying the second voltage to the second section after the first section, the luminance waveform appearing in the second section can be the same as the first section. , it is possible to prevent flicker from being recognized in a section driven in the low speed driving mode, thereby reducing power consumption of the display device while maintaining image quality.

In addition, since different second voltages are variably applied to different positions, it is possible to further compensate for a luminance deviation due to different voltage drops for each position.

Effects according to the present specification are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram of a display device according to an exemplary embodiment of the present specification.
2 is a pixel circuit of a display device according to an exemplary embodiment of the present specification.
3 is an example of driving timing of the pixel circuit shown in FIG.
It is a drawing.
4 is a diagram of a voltage waveform applied in line units in a display device according to an exemplary embodiment of the present specification.
FIG. 5 is a diagram of a voltage waveform that is varied and applied for 1H per line in a display device according to an exemplary embodiment of the present specification.

Advantages and features of the present specification and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments of the present specification allow the disclosure of the present specification to be complete, and It is provided to fully inform those of ordinary skill in the scope of the invention, and the invention of the present specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary and are not limited to the matters shown in the present specification. Like reference numerals refer to like elements throughout. In addition, in describing an example of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

When "includes," "has," "consisting of," etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as "on," "upper," "lower," "nextly", "directly" or 'directly' One or more other parts may be placed between the two parts unless this is used.

In the case of a description of a temporal relationship, for example, when the temporal precedence is described as "after," "following," "after," "before", etc., 'immediately' or 'directly' are not used. It may include a case where it is not more continuous.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various examples of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each example may be implemented independently of each other or may be implemented together in a related relationship. .

Hereinafter, an example of a display device according to an embodiment of the present specification will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. And, since the scales of the components shown in the accompanying drawings have different scales from the actual for convenience of explanation, the scales shown in the drawings are not limited thereto.

1 is a block diagram of a display device according to an exemplary embodiment of the present specification.

The display device according to the present specification includes a display panel 100 , a gate driver 110 , a data driver 120 , and a timing controller (T-CON) 130 .

The display panel 100 includes a display area and a non-display area provided around the display area. The display area is an area in which pixel circuits P are provided to display an image. The non-display area is outside the display panel 100 and is an area that protects the display area from external impact. The display panel 100 includes gate lines GL1 to GLp, where p is a positive integer greater than or equal to 2), data lines DL1 to DLq, q is a positive integer greater than or equal to 2), and sensing lines SL1 to SLq. do. The data lines DL1 to DLq and the sensing lines SL1 to SLq may cross the gate lines GL1 to GLp. The data lines DL1 to DLq and the sensing lines SL1 to SLq may be parallel to each other. The display panel 100 may include a lower substrate on which the pixel circuits P are provided and an upper substrate that performs an encapsulation function to protect the pixel circuits P from external foreign substances. Each of the pixel circuits P may be connected to any one of the gate lines GL1 to GLp, any one of the data lines DL1 to DLq, and any one of the sensing lines SL1 to SLq.

The gate driver 110 receives the gate driver control signal GCS from the timing controller 130 . The gate driver 110 generates gate signals according to the gate driver control signal GCS. The gate driver 110 supplies gate signals to the gate lines G1 to Gp in a predetermined order. The predetermined order may be a sequential order. The gate driver 110 according to the embodiment may be implemented in a gate-in-panel (GIP) method integrated or embedded in one side of the non-display area of the display panel 100 together with a transistor manufacturing process. Each stage of the gate driver 110 implemented in the gate-in-panel method may be connected one-to-one with the gate lines GL1 to GLp, but is not limited thereto.

The data driver 120 receives the data driver control signal DCS from the timing controller 130 , generates data voltages according to the data driver control signal DCS and supplies them to the data lines DL1 to DLq. The data driver 120 according to the embodiment may be implemented in a driving integrated circuit (Drive IC, D-IC) method integrated or embedded in one side of the non-display area of the display panel 100 .

The data driver 120 senses voltage and current characteristics of each of the pixel circuits P through the sensing lines SL1 to SLq. The data driver 120 generates the sensing data SEN and supplies it to the timing controller 130 .

The timing controller 130 may be integrated or embedded in one side of the non-display area of the display panel 100 . The timing controller 130 receives from the outside a timing signal TS for controlling the display timing of an image and digital video data DATA including color-specific information for realizing an image. A timing signal TS and digital video data DATA are input to the input terminal of the timing controller 130 according to a set protocol. Also, the timing controller 130 receives sensing data SEN according to voltage and current characteristics of each of the pixel circuits P from the data driver 120 .

The timing signal TS includes a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and a dot clock (DCLK). include The timing controller 130 compensates the digital video data DATA based on the sensed data SEN.

The timing controller 130 generates driver control signals for controlling operation timings of the gate driver 110 , the data driver 120 , and the sensing driver. The driver control signals include the gate driver control signal GCS for controlling the operation timing of the gate driver 110 , the data driver control signal DCS for controlling the operation timing of the data driver 120 , and the operation timing of the sensing driver and a sensing driver control signal for controlling the .

The timing controller 130 operates the data driver 120 and the sensing driver in any one of a display mode and a sensing mode according to a mode signal. The display mode is a mode in which the pixel circuits P of the display panel 100 display an image, and the sensing mode senses the current or voltage of the driving transistor DT of each of the pixel circuits P of the display panel 100 . is the mode to When the waveform of the scan signal supplied to each of the pixel circuits P and the waveform of the sensing signal are changed in each of the display mode and the sensing mode, the data driver control signal DCS and the sensing driver control in each of the display mode and the sensing mode Signals can also be changed. Accordingly, the timing controller 130 generates the data driver control signal DCS and the sensing driver control signal corresponding to the corresponding mode according to which mode is the display mode and the sensing mode.

The timing controller 130 outputs the gate driver control signal GCS to the gate driver 110 . The timing controller 130 outputs the compensated digital video data and the data driver control signal DCS to the data driver 120 . The timing controller 130 outputs the sensing driver control signal to the sensing driver.

The timing controller 130 generates a mode signal for driving the data driver 120 and the sensing driver according to which mode of the display mode and the sensing mode is driven. The timing controller 130 operates the data driver 120 and the sensing driver in any one of a display mode and a sensing mode according to a mode signal.

The gate driver 110 , the data driver 120 , and the timing controller 130 of the display device according to the present specification may be implemented in an integrated driving integrated circuit (One Chip Drive IC) method implemented as a single integrated circuit.

2 is a pixel circuit of a display device according to an exemplary embodiment of the present specification.

The pixel circuit P according to the exemplary embodiment of the present specification includes first to sixth switching transistors T1 to T6 , a driving transistor D-TFT, a capacitor Cstg, and a light emitting device EL. Here, the light emitting device EL may be, for example, a self-luminous device capable of emitting light by itself, such as an organic light emitting diode (OLED). The first to third switching transistors T1 to T3 , the fifth to sixth switching transistors T5 to T6 , and the driving transistor D-TFT of the pixel circuit P according to another example of the present specification are P-type MOSs. A case of a transistor will be described as an example, and a case where the fourth switching transistor T4 is an N-type MOS transistor will be described as an example.

The P-type MOS transistor is relatively more reliable than the N-type MOS transistor. When the transistor is a P-type MOS transistor, since the drain electrode is fixed to the high potential driving voltage VDDEL, there is an advantage that the current flowing through the light emitting device EL is not shaken by the capacitor Cstg. Therefore, there is an advantage in that it is easy to stably supply current. For example, since the P-type MOS transistor must be connected to the anode electrode of the light emitting element EL, the OLED portion must be connected to the corresponding portion in top emission. Therefore, when the transistor operates in the saturation region, the light emitting element Reliability is relatively high because a constant current can flow regardless of changes in current and threshold voltage of (EL). The display device according to the embodiment of the present invention has been described as an example of a pixel circuit structure to which a P-type MOS transistor is applied, but is not limited thereto.

The gate electrode of the first switching transistor T1 receives the second scan signal Scan2n. The drain electrode of the first switching transistor T1 is supplied with the data voltage Vdata. The source electrode of the first switching transistor T1 is connected to the drain electrode of the driving transistor D-TFT. The first switching transistor T1 is turned on by the second scan signal Scan2n to supply the data voltage Vdata to the drain electrode of the driving transistor D-TFT.

The gate electrode of the second switching transistor T2 receives the emission control signal EMn. The drain electrode of the second switching transistor T2 is supplied with the high potential driving voltage VDDEL. The source electrode of the second switching transistor T2 is connected to the drain electrode of the driving transistor D-TFT. The second switching transistor T2 is turned on by the emission control signal EMn to supply the high potential driving voltage VDDEL to the drain electrode of the driving transistor D-TFT.

The gate electrode of the third switching transistor T3 receives the third scan signal Scan3n. The drain electrode of the third switching transistor T3 is supplied with the first voltage Vini.

The source electrode of the third switching transistor T3 is connected to the source electrode of the driving transistor D-TFT. The third switching transistor T3 is turned on by the third scan signal Scan3n to initialize the third node N3.

The gate electrode of the fourth switching transistor T4 receives the first scan signal Scan1n. A drain electrode of the fourth switching transistor T4 is connected to a gate electrode of the driving transistor D-TFT.

The source electrode of the fourth switching transistor T4 is connected to the source electrode of the driving transistor D-TFT.

The fourth switching transistor T4 is turned on by the first scan signal Scan1n to control the operation of the driving transistor D-TFT through the high potential driving voltage VDDEL stored in the capacitor Cstg.

For the fourth switching transistor T4 to constitute an oxide semiconductor, an N-type MOS transistor may be mainly applied. Since the N-type MOS transistor uses electrons, not holes, as carriers, and thus has higher mobility than the P-type MOS transistor, the switching speed may be faster. In addition, since the N-type MOS transistor must be connected to the cathode electrode of the light emitting element EL, an oxide semiconductor having an N-type characteristic in a bottom emission method can be configured as an N-type MOS transistor. However, the present invention is not limited thereto, and other types of transistors may be used.

The gate electrode of the fifth switching transistor T5 receives the emission control signal EMn. A drain electrode of the fifth switching transistor T5 is connected to a source electrode of the driving transistor D-TFT. The source electrode of the fifth switching transistor T5 is connected to the anode electrode of the light emitting element EL. The fifth switching transistor T5 is turned on by the light emission control signal EMn to supply a driving current to the anode electrode of the light emitting element EL.

The gate electrode of the sixth switching transistor T6 receives the third scan signal Scan3n+1. The drain electrode of the sixth switching transistor T6 is supplied with the second voltage Var. The source electrode of the sixth switching transistor T6 is connected to the anode electrode of the light emitting element EL. The sixth switching transistor T6 is turned on by the third scan signal Scan3n+1 to supply the second voltage Var to the anode electrode of the light emitting element EL.

The gate electrode of the driving transistor D-TFT is connected to the drain electrode of the fourth switching transistor T4 . The drain electrode of the driving transistor D-TFT is connected to the source electrode of the first switching transistor T1 . The source electrode of the driving transistor D-TFT is connected to the source electrode of the third switching transistor T4 . The driving transistor D-TFT is turned on by a voltage difference between the source electrode and the drain electrode of the fourth switching transistor T4 to flow a driving current to the light emitting element EL.

One side of the capacitor Cstg is supplied with the high potential driving voltage VDDEL. The other side of the capacitor Cstg is connected to the gate electrode of the driving transistor D-TFT. The capacitor Cstg stores the voltage of the gate electrode of the driving transistor D-TFT.

The anode electrode of the light emitting element EL is connected to the source electrode of the fifth switching transistor T5 and the source electrode of the sixth switching transistor T6 . The cathode electrode of the light emitting element EL is supplied with the low potential driving voltage VSSEL. The light emitting element EL emits light with a predetermined brightness by a driving current flowing through the driving transistor D-TFT.

In the present specification, the first voltage Vini is supplied to compensate the stress of the driving transistor D-TFT, and the second voltage Var is supplied to perform an anode reset operation.

During the anode reset operation, the light emitting element EL is positioned between the anode electrode of the light emitting element EL and the driving transistor D-TFT and in a state in which the switching transistor controlled by the light emission control signal EM is turned off. A second voltage Var is supplied to the anode electrode of The sixth switching transistor T6 supplying the second voltage Var is connected to the anode electrode of the light emitting element EL.

The pixel circuit P according to the exemplary embodiment of the present specification is driven using the first to third scan signals Scan1 to Scan3. The third scan signal Scan3 is different from the first scan signal Scan1 . For example, the first to third scan signals Scan1 to Scan3 may be signals having the same magnitude and different phases. Three scan drivers are required to generate the first to third scan signals Scan1 to Scan3. In the pixel circuit P according to the embodiment of the present specification, the first to fifth switching transistors T1 to T5 are turned-on using the third scan signal Scan3 for turning on the sixth switching transistor T6. In the off state, the sixth transistor T6 may be turned on.

The sixth switching transistor T6 supplying the second voltage Var is turned on by the scan signal. Driving the driving transistor D-TFT or driving the driving transistor D- so that the driving of the driving transistor D-TFT and the supply of the second voltage Var to the anode electrode of the light emitting element EL can be performed separately The scan signal Scan for initializing the TFT) and the scan signal Scan for controlling the sixth switching transistor T6 for controlling the supply of the second voltage Var to the anode electrode of the light emitting element EL are separated from each other. do.

The third switching transistor T3 and the sixth switching transistor T6 may be used together with the third scan signal Scan3 of the odd-numbered line and the even-numbered line in one pixel circuit P. A third scan signal Scan3n of an n-th line may be supplied to the third switching transistor T3 , and a third scan signal Scan3n+1 of an n+1-th line may be supplied to the sixth switching transistor T6 . have. In other words, the third scan signal Scan3 supplied to the pixel circuit P on the n-th line includes the third scan signal Scan3n on the n-th line and the third scan signal Scan3n+1 on the n+1-th line. can be used Accordingly, the third scan signals Scan3 supplied to the pixel circuit P may have the same operation waveform and may have different phases from each other.

The pixel circuit P according to the embodiment of the present specification uses the emission control signal and the scan signal to turn on the switching transistor for supplying the first voltage Vini and the second voltage Var to the driving transistor D -TFT) and a switching transistor connecting the anode electrode of the light emitting element (EL) is turned off by turning off the driving current of the driving transistor (D-TFT) from flowing to the anode electrode of the light emitting element (EL), The pixel circuit P may be configured so that the anode electrode is not affected by voltages other than the voltage for resetting the anode.

In the present specification, the anode reset of the light emitting element EL is performed after the driving current of the driving transistor D-TFT is cut off in order to reduce the difference between the first period and the second period during discharge. The magnitudes of the first voltage Vini and the second voltage Var in the second period may be equal to or smaller than the magnitudes of the first voltage Vini and the second voltage Var in the first period. However, the present invention is not limited thereto. For example, the magnitudes of the first voltage Vini and the second voltage Var in the second period may have arbitrary magnitudes for performing anode reset. In this case, the magnitudes of the first voltage Vini and the second voltage Var in the second section may be greater than the magnitudes of the first voltage Vini and the second voltage Var in the first section.

FIG. 3 is a diagram illustrating an example of driving timing of the pixel circuit shown in FIG. 2 .

Referring to FIG. 3 , one frame period may be divided into a first period and a second period according to the synchronization signal SYNC.

In the first period, the data voltage Vdata for driving the pixel circuit P, the first voltage Vini, and the second voltage Var may be applied to the pixel circuit P.

The first section is a section for initializing the voltage charged or remaining in the capacitor Cstg and the first to fourth nodes N1 to N4. The first section is partially provided at the start section of each frame. In the first section, the influence of the data voltage Vdata and the driving voltage stored in the previous frame is removed.

After the refresh operation, the light emitting element EL may emit light according to the data voltage Vdata applied to the pixel circuit P.

The second section is a section for charging or setting the data voltage Vdata and the driving voltage of each frame in the capacitor C1 and the first to fourth nodes N1 to N4. The second section continues after the first section of each frame is completed until the first section of the next frame starts. In the second section, the driving transistor D-TFT and the light emitting element EL are driven according to the first to third scan signals Scan1 to Scan3 and the emission control signal EM.

That is, initialization and application of the data voltage Vdata may be performed in a first period of one frame period, and light emitting device EL may emit light in a second period.

In the second section, an anode reset operation is not performed or an anode reset operation is performed at least once during low-speed driving with a low frame frequency. In the second period, the anode electrode of the light emitting element EL is reset to the second voltage Var. In the second section, the fourth node N4 is periodically reset to a constant voltage in the second section within the frame in order to improve flicker that occurs as the second section lengthens during low-speed driving.

In the second section, when the flicker problem due to the relatively low speed driving is small or when the flicker problem is not serious, such as when the frame frequency is relatively high during the low speed driving, the anode reset operation may not be performed or may be performed only once. On the other hand, when the flicker problem due to relatively low-speed driving is large or when the flicker problem is serious, such as when the frame frequency is relatively low during low-speed driving, each frame is divided into sub-frames and divided into sub-frames. frame), the anode reset operation can be applied.

For example, when one frame is divided into 60 sub-frames in 1Hz low-speed driving, the anode reset operation may be performed 60 times.

Specifically, in the second section, the data voltage Vdata maintains the low logic level L. Also, the first scan signal Scan1 maintains a low logic level L in the second section, and the second scan signal Scan2 maintains a high logic level H in the second section.

Accordingly, the data voltage Vdata is not supplied in the second section. In addition, the first and fourth switching transistors T1 and T4 maintain a turned-off state in the second period.

The third scan signal Scan3 is applied to the odd-numbered scan line and the even-numbered scan line with a phase difference.

The third scan signal Scan3 has a low logic level L in a portion of the second section and maintains a high logic level H in the remaining section. In a section in which the third scan signal Scan3 of the odd-numbered line has a low logic level L, the third switching transistor T3 is turned on. The turned-on third switching transistor T3 supplies the first voltage Vini to the third node N3. In a section in which the third scan signal Scan3 of an even-numbered line has a low logic level L, the sixth switching transistor T6 is turned on. The turned-on sixth switching transistor T6 supplies the second voltage Var to the fourth node N4 .

The light emission control signal EM has a high logic level H in the second section and maintains a low logic level L in the remaining sections. In a period in which the emission control signal EM has a low logic level L, the second switching transistor T2 and the fifth switching transistor T5 are turned on.

Since the light emission control signal EM maintains the high logic level H when the anode is reset, the second switching transistor T2 and the fifth switching transistor T5 are turned off. Accordingly, the current of the driving transistor D-TFT may be cut off when the anode is reset.

The display device according to the embodiment of the present specification applies the second voltage Var through the sixth switching transistor T6 using the third scan signal Scan3 during the anode reset operation to the fourth node N4, The anode electrode of the light emitting element EL connected to the fourth node N4 is reset to the second voltage Var.

In addition, since the second voltage Var is applied to the anode electrode of the light emitting element EL during the anode reset operation, the brightness of the light emitting element EL may vary according to the second voltage Var.

The second voltage Var is a voltage for preventing flicker from being recognized in the low-speed driving mode, and may be a voltage for matching the luminance displayed by the light emitting device EL to the luminance displayed in the refresh period.

In addition, by making the luminance waveform displayed by the light emitting element EL in the first period repeatedly appear in the second period, it is possible to prevent the flicker from being recognized due to the decrease in luminance in the second period in the low-speed driving mode.

4 is a diagram of a voltage waveform applied in line units in a display device according to an exemplary embodiment of the present specification. FIG. 5 is a diagram of a voltage waveform that is varied and applied for 1H per line in a display device according to an exemplary embodiment of the present specification.

4 and 5 , the second voltage may be subdivided and varied for each horizontal line according to the position of the pixel circuit P in each sub frame.

In the display panel, a voltage drop (IR drop) of the high potential driving voltage VDDEL occurs due to a resistance component of an internal wiring. The magnitude of the voltage drop IR drop may be different according to the resistance value for each position, and accordingly, a level difference may also occur in the high potential driving voltage VDDEL applied to each pixel circuit P.

The voltage drop (IR drop) can be compensated by varying the high potential driving voltage (VDDEL) in real time, but in this case, since the capacitor Cstg is coupled, the degree of compensation may vary depending on the time constant or charging time, and There may be changes in the amount of current due to influence or voltage fluctuations.

When the display device according to the embodiment of the present specification improves flicker by applying the second voltage in the second period, the second voltage is varied in units of horizontal time (1H) rather than units of sub frames. Flicker and voltage drop (IR drop) can be improved simultaneously by applying . In other words, referring to the enlarged view A of FIG. 4 , since the second voltage varied in units of 1H is sequentially applied to each sub-frame, applying the second voltage in units of sub-frames Flicker can be improved more effectively and the purpose of voltage drop (IR drop) can be achieved at the same time. For example, in the first anode reset period t1 of 1H (horizontal time), 5V When the 2 voltage Var is applied, only the third scan signal Scan3n+1 of the n+1-th line operates in the first anode reset period t1, and the third scan signal Scan3 operates in the remaining lines. may not For example, 5V may be applied to the n-th line and no voltage may be applied to the remaining lines. In addition, when the second voltage Var of 4V is applied in the second anode reset period t2 of 1H (horizontal time), only the third scan signal Scan3n+2 of the n+2th line is the second anode reset. The operation is performed in the period t2 and the third scan signal Scan3 may not operate in the remaining lines. Accordingly, 4V may be applied to the n+1th line and no voltage may be applied to the remaining lines.

In the display device according to the exemplary embodiment of the present specification, the second power wiring supplying the second voltage is commonly connected to all the pixel circuits P, but the low logic level L is applied to the third scan signal Scan3. The second voltage may be supplied only to the pixel circuit P in which the sixth switching transistor T6 is turned on.

In addition, since the second voltage Var is variably applied to different positions in units of 1H (horizontal time) rather than in units of sub frames, luminance deviation due to different voltage drops (IR Drop) is further compensated for at each position. can do.

In addition, instead of the power driving circuit required when the high potential driving voltage VDDEL using a large current is varied, the effect of improving the voltage drop (IR drop) can be obtained only by applying the second voltage Var for each line, thereby reducing costs. effect can be obtained.

A display device according to an exemplary embodiment of the present specification includes a light emitting device that emits light with a brightness corresponding to a level of a driving current, a driving transistor that provides a driving current to the light emitting device, a plurality of switching transistors that control driving of the driving transistor, and a first a first wire for supplying a voltage and a second wire for supplying a second voltage, wherein a data voltage is applied to a first period during one frame period in a low-speed driving mode, and the first and second lines are applied to a second period The display panel may be a display panel in which the first and second voltages are applied at least once through two wirings, and the second voltage is applied in a variable manner for each line in the second section.

In the display device according to the embodiment of the present specification, the second period may be a display panel that is divided into at least one or more sub-frames to maintain the data voltage.

In the display device according to the embodiment of the present specification, the sub-frame may be a display panel that is maintained to be equal to or longer than the length of the first section.

In the display device according to the embodiment of the present specification, the first voltage may be supplied to compensate the stress of the driving transistor, and the second voltage may be supplied to compensate the anode reset operation and voltage drop, and may be a display panel.

In the display device according to the embodiment of the present specification, the second voltage may be a display panel in which the second voltage is sequentially applied by varying one line by 1H unit for each subframe.

In the display device according to the embodiment of the present specification, the magnitudes of the first and second voltages applied in the second period may be the same as or different from the magnitudes of the first and second voltages applied in the first period, and may be a display panel.

In the display device according to the exemplary embodiment of the present specification, any one of the switching transistors may be a display panel connected between a source electrode of a driving transistor and an anode electrode of the light emitting device and turned on by a light emission control signal.

In the display device according to the exemplary embodiment of the present specification, the plurality of switching transistors are connected between the first wiring and the source electrode of the driving transistor, or connected to the second wiring and the anode electrode of the light emitting device, and are turned on by different scan signals. It may be a display panel that is turned on.

In the display device according to the exemplary embodiment of the present specification, different scan signals may be a display panel having the same operation waveform and different phases.

A plurality of switching transistors in the display device according to the embodiment of the present specification,

The first switching transistor is turned on by the second scan signal to supply the data voltage to the first node, and the fourth switching transistor is turned on by the first scan signal to supply the voltage from the second node to the third node. , the second switching transistor is turned on by the light emission control signal to supply the high potential driving voltage to the first node, the fifth switching transistor to supply the voltage of the third node to the fourth node, and the third scan signal The display panel may include a sixth switching transistor that is turned on to supply the first voltage to a third node and supply a second voltage to a fourth node.

In the display device according to the embodiment of the present specification, the display panel may further include a capacitor for storing a data voltage.

In the display device according to the exemplary embodiment of the present specification, a display panel provided with a plurality of pixel circuits to display an image, a gate driver supplying a gate signal to the pixels, a data driver supplying a data voltage to the pixels, and a gate driver, and the data a timing controller for controlling the driving unit, wherein a data voltage is applied to a first period during one frame period in a low-speed driving mode, the data voltage is maintained in a second period, and the second voltage is varied to compensate for a voltage drop It may be a display device that is applied by

In the display device according to the embodiment of the present specification, the second period may be a display device that operates by dividing it into at least one or more sub-frames to maintain a data voltage.

In the display device according to the embodiment of the present specification, the sub-frame may be a display device that is maintained to be equal to or longer than the length of the first section.

In the display device according to the exemplary embodiment of the present specification, the pixel circuit includes a driving transistor and a plurality of switching transistors, a first voltage is applied to compensate stress of the driving transistor, and a second voltage is applied to the anode reset operation and voltage drop. It may be a display device, which is supplied to compensate.

In the display device according to the embodiment of the present specification, the second voltage may be a display device in which the second voltage is sequentially applied by varying one line by 1H unit for each subframe.

In the display device according to the embodiment of the present specification, the second voltage supplied to the light emitting device in the second section may be varied to have the same luminance as the data voltage applied in the first section, and may be a display device.

In the display device according to the exemplary embodiment of the present specification, the magnitudes of the first and second voltages applied in the second period may be the same as or different from the magnitudes of the first and second voltages applied in the first period.

In the display device according to the embodiment of the present specification, the gate driver may be a display device that turns on the plurality of switching transistors according to different scan signals.

In the display device according to the exemplary embodiment of the present specification, different scan signals may have the same operation waveform and have different phases.

Features, structures, effects, etc. described in the above-described examples of the present specification are included in at least one example of the present specification, and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. illustrated in at least one example of the present specification may be combined or modified with respect to other examples by those of ordinary skill in the art to which this specification belongs. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this specification belongs that various substitutions, modifications and changes are possible within the scope without departing from the technical details of the present specification. It will be clear to those who have the knowledge of Therefore, the scope of the present specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present specification.

100: display panel
110: gate driver
120: data driving unit
130: timing controller

Claims (20)

a light emitting device that emits light according to a driving current;
a driving transistor providing the driving current to the light emitting device;
a plurality of switching transistors for controlling driving of the driving transistors; and
a first wiring supplying a first voltage to the light emitting element and a second wiring supplying a second voltage;
One frame period is divided into a first period and a second period, a data voltage is applied to the first period, and the first and second voltages are applied to the first and second wires at least once in the second period. is applied, and the second voltage is varied and applied for each line in the second section.
The method of claim 1,
The display device of claim 1, wherein the second period is divided into at least one sub-frame to maintain the data voltage.
3. The method of claim 2,
The sub-frame is maintained to be equal to or longer than the length of the first section.
4. The method of claim 3,
the first voltage is supplied to compensate the stress of the driving transistor;
and the second voltage is supplied to compensate an anode reset operation and a voltage drop.
5. The method of claim 4,
and the second voltage is sequentially applied by varying one line for each sub-frame in units of 1H.
6. The method of claim 5,
magnitudes of the first and second voltages applied in the second period are equal to or different from magnitudes of the first and second voltages applied in the first period.
7. The method of claim 6,
At least one of the plurality of switching transistors is connected between the source electrode of the driving transistor and the anode electrode of the light emitting device,
A display device that is turned on by a light emission control signal.
8. The method of claim 7,
The plurality of switching transistors are connected between the first wiring and the source electrode of the driving transistor, or connected to the second wiring and the anode electrode of the light emitting device, and are turned on by different scan signals.
9. The method of claim 8,
The different scan signals have the same operation waveform and have different phases.
The method of claim 1,
The plurality of switching transistors,
a first switching transistor turned on by the second scan signal to supply a data voltage to the first node;
a fourth switching transistor turned on by the first scan signal to supply the voltage of the second node to the third node;
a second switching transistor turned on by a light emission control signal to supply a high potential driving voltage to the first node and a fifth switching transistor to supply a voltage from the third node to a fourth node; and
and a sixth switching transistor turned on by a third scan signal to supply the first voltage to the third node and supply the second voltage to the fourth node.
11. The method of claim 10,
and a capacitor configured to store the data voltage.
a display panel having a plurality of pixel circuits to display an image;
a gate driver supplying a gate signal to the plurality of pixels;
a data driver supplying a data voltage to the plurality of pixels; and
a timing controller for controlling the gate driver and the data driver;
One frame period is divided into a first period and a second period, the data voltage is applied to the first period, the data voltage is maintained in the second period, and the second voltage is applied by varying the voltage drop to compensate, display device.
13. The method of claim 12,
The display device of claim 1, wherein the second period is divided into at least one sub-frame to maintain the data voltage.
14. The method of claim 13,
The sub-frame is maintained to be equal to or longer than the length of the first section.
15. The method of claim 14,
The pixel circuit includes a driving transistor and a plurality of switching transistors,
the first voltage is supplied to compensate the stress of the driving transistor;
and the second voltage is supplied to compensate an anode reset operation and a voltage drop.
16. The method of claim 15,
and the second voltage is sequentially applied by varying one line by 1H unit for each subframe.
17. The method of claim 16,
The second voltage supplied to the light emitting device in the second period is varied to have the same luminance as the data voltage applied in the first period.
18. The method of claim 17,
magnitudes of the first and second voltages applied in the second period are equal to or different from magnitudes of the first and second voltages applied in the first period.
19. The method of claim 18,
The gate driver,
and turning on the plurality of switching transistors according to different scan signals.
20. The method of claim 19,
The different scan signals have the same operation waveform and have different phases.

Images