JP2009210993A - El display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that display irregularities are caused since variations in the characteristic of a driving transistor cannot be corrected sufficiently. <P>SOLUTION: As an initializing voltage for a driving transistor before an offset canceling operation, different voltages are applied so as to adjust the gate voltage-drain current characteristic of the transistor. This facilitates the cancellation of variations in the characteristic of the driving transistor even if a canceling time is short. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an EL display device using a self-luminous display panel such as an EL display panel (display device) using an organic or inorganic electroluminescence (EL) element.

  In an active matrix image display device using an organic EL material or an inorganic EL material as an electro-optic conversion substance, light emission luminance changes according to a current written to a pixel. The EL display device is a self-luminous type having a light emitting element in each pixel. The EL display device has advantages such as high image visibility, high luminous efficiency, no need for a backlight, and high response speed compared to a liquid crystal display panel.

For organic EL (PLED, OLED, OEL) panels, active matrix systems have been developed. In this method, the current flowing in the light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit. For example, Patent Documents 1 and 2 have been proposed.
JP 2003-255856 A JP 2003-271095 A

  The EL display panel is configured using a transistor array made of low-temperature or high-temperature polysilicon. However, display variations occur in organic EL elements when the transistor characteristics of the polysilicon transistor array vary.

  That is, if there is a characteristic variation in the driving transistor that supplies the driving current to the EL element, the converted current signal also varies. Usually, the transistor has a characteristic variation of 50% or more. For this reason, there is a problem that the characteristic variation of the driving transistor is displayed as display unevenness, and the image display quality is lowered.

  Therefore, the present invention provides an EL display device capable of realizing image display without characteristic display unevenness.

  The present invention provides an EL display device having a display screen in which a plurality of pixels each having an EL element are arranged in a matrix in the vertical and horizontal directions. The pixel includes a driving transistor for supplying a driving current to the EL element. The driving transistor has an EL display having a first power source that performs an offset canceling operation and changes a voltage of a gate electrode of the driving transistor by a current during a first period that is a period before the offset canceling operation. Device.

  According to the present invention, it is possible to realize image display without characteristic display unevenness.

  Hereinafter, an EL display device according to an embodiment of the present invention will be described with reference to the drawings.

(1) Pixel Configuration FIG. 1 shows a pixel configuration of an EL display device. FIG. 3 is a configuration diagram in which the gate driver circuit 12 and the source driver circuit 14 are connected to the display region 31 in which the pixels 16 are arranged in a matrix.

  In FIG. 1, the pixel 16 includes two capacitors 19a and 19b, five switching transistors 11b, 11c, 11d, 11e, and 11f, and one driving transistor 11a.

  The switching transistor 11b is a threshold voltage compensation transistor for compensating the threshold voltage by diode-connecting the transistor 11a.

  The switching transistor 11f is an initialization transistor for applying a reset voltage Vrst to initialize the capacitor 19a.

  The switching transistor 11d is a transistor for controlling the light emission of the EL element 15.

  Since the switching transistors 11b and 11f need to be made small with an off-leakage, a multi-gate structure having a dual gate or higher is used.

  The capacitor 19a is a holding capacitor that holds the potential of the gate terminal of the driving transistor 11a.

  The capacitor 19 b is applied to the source signal line 18 and holds the video signal applied to the pixel 16 in the pixel 16.

  The switching transistor 11c has a gate electrode connected to the gate signal line 17a, a source electrode connected to the source signal line 18, and is turned on / off by a selection signal from the gate driver circuit 12a.

  The source electrode of the driving transistor 11a is connected to the drain electrode of the transistor 11c. The source or drain electrode of the threshold voltage compensation transistor 11b and the first terminal of the capacitor 19a are commonly connected to determine the gate voltage of the driving transistor 11a. Therefore, the driving transistor 11a generates a driving current corresponding to the voltage applied to the gate electrode.

  The threshold voltage compensation transistor 11b is connected between the gate electrode and the source electrode of the driving transistor 11a, and diode-connects the driving transistor 11a in response to a scan signal applied to the gate signal line 17c. Accordingly, the driving transistor 11a is in a diode-like state by the scan signal, and the voltage Vdata−Vth [V] is applied to the gate terminal of the driving transistor 11a, which becomes the gate voltage of the driving transistor 11a. . The voltage Vdata is a video signal output from the source driver circuit 14 to the source signal line 18. At Vth, the threshold voltage is applied to the driving transistor 11a.

  The switch initialization transistor 11f, which is an initialization transistor, is connected between the reset voltage line Vrst and the first terminal of the capacitor 19a, and fills the capacitor 19a in response to the scan signal of the gate signal line 17d. The electric charge is discharged through the reset voltage line Vrst to initialize the capacitor 19a.

  The switching transistor 11e is connected between the first power supply voltage line Vdd and the source electrode of the driving transistor 11a, and is turned on by a light emission control signal transmitted through the gate signal line 17b connected to the gate electrode. The first power supply voltage Vdd is applied to the source electrode of the driving transistor 11a.

  The switching transistor 11d is connected between the driving transistor 11a and the EL element 15, and is generated by the driving transistor 11a in response to a light emission control signal transmitted through the gate signal line 17b connected to the gate electrode. Is transmitted to the EL element 15.

  The capacitor 19a is connected between the first power supply voltage line Vdd and the gate electrode of the driving transistor 11a, and the voltage Vdata−Vth [V applied to the first power supply voltage Vdd and the gate electrode of the driving transistor 11a. The charge corresponding to the voltage difference is maintained for one frame.

(2) Gate signal line The voltages applied to the gate signal line 17 are an off voltage (VGH) and an on voltage (VGL). By applying the VGH voltage, the switching transistors 11b, 11c, 11d, 11e, and 11f The switching transistors 11b, 11c, 11d, 11e, and 11f are turned on by applying the VGL voltage. However, as shown in FIG. 3, if the VGH voltage is common to the gate driver circuit 12a and the gate driver circuit 12b, the VGL voltage is VGL1 in the gate driver circuit 12a, and VGL2 in the gate driver circuit 12b. . That is, the on-voltages are different between the gate driver circuits 12a and 12b.

  Therefore, the ON voltage applied to the gate signal line 17a and the gate signal line 17c is VGL1, and the ON voltage applied to the gate signal line 17b and the gate signal line 17d is VGL2. In addition, the relation of VGL1> VGL2 is set. Note that VGH applied to the gate signal line 17a may be different from VGH applied to the gate signal line 17d.

(3) P-channel and N-channel transistors In this embodiment, the driving transistor 11a is a P-channel transistor, but is not limited thereto, and may be an N-channel transistor.

  In this case, the on voltage is VGH and the off voltage is VGL. In addition, the source terminal of the driving transistor 11a is described as being connected to the anode voltage Vdd, but the present invention is not limited to this. For example, it may be connected to the cathode voltage Vss or the ground voltage GND. The capacitor 18 may be replaced with a capacitor having a gate insulating film capacitance of the transistor 11.

(4) Gate Driver Circuit A start pulse ST1 for selecting the gate signal line 17a, a start pulse ST2 for selecting the gate signal line 17c, and a clock signal (CLK) for sequentially shifting the start pulse are applied to the gate driver circuit 12a. . UD is a signal for switching the up / down shift register direction of the start pulse in the gate driver circuit 12a.

  A start pulse ST3 for selecting the gate signal line 17b, a start pulse ST4 for selecting the gate signal line 17d, and a clock signal (CLK) for sequentially shifting the start pulse are applied to the gate driver circuit 12b.

  Note that it is preferable to add an enable control terminal to the gate driver circuit 12 as necessary. A shift register circuit is formed in the gate driver circuit 12, and the start pulse is sequentially shifted in synchronization with the clock signal (CLK) to change the position of the gate signal line 17 to be selected.

(5) Signals Applied to Gate Signal Lines FIG. 2 shows drive voltages applied to the gate signal lines 17a, 17b, 17c, and 17d, video signal voltages of the source signal lines 18, and light emission states of the EL elements 15.

  In FIG. 2, for ease of explanation, the off voltage is VGH and the on voltage is VGL. Further, the voltage Vdata applied to the source signal line 18 is set to the ground voltage (GND) = 0V and is equal to or lower than the anode voltage Vdd.

  1H is one horizontal scanning period. FIG. 2 is schematic, and 1H may be a few H, and 1H may be a period shorter than 1H. The VGH voltage is set to a voltage not lower than 0.5 V and not higher than 3.0 V than the Vdd voltage.

  The on-voltage is applied to the pixel 16 in the gate signal line 17d during the period from 1t to at. By applying the on voltage (VGL), the transistor 11f is turned on, and the reset voltage Vrst is applied to the gate terminal of the driving transistor 11a (point a).

  By applying the reset voltage Vrst, the driving transistor 11a is reset. The reset voltage Vrst should be set to a voltage not higher than the GND voltage and not lower than −5 (V). Further, the reset voltage Vrst may be changed corresponding to the video signal voltage Vdata. For example, the reset voltage Vrst is changed corresponding to the gradation number of the video signal. Further, the reset voltage Vrst may be changed by video signal voltages of red (R), green (G), and blue (B). This is because the amplitude of the video signal differs between RGB. In this case, a fixed reset voltage Vrst may be set for each RGB without corresponding to the gradation number. Further, the reset voltage Vrst may be changed in accordance with the current consumed on the display screen.

  After the reset voltage Vrst is applied (at), an ON voltage is applied to the gate signal line 17c. The period during which the on-voltage (VGL) is applied is 1H or more, but is not limited thereto, and may be a period of 1H or less. At least the period during which the on-voltage (VGL) is applied to the gate signal line 17c is longer than the period during which the on-voltage (VGL) is applied to the gate signal line 17a. Also overlap. Note that the application time of the reset voltage Vrst is preferably 2 μsec or more.

  By applying the gate signal line 17a on-voltage (VGL), the switching transistor 11c is turned on, and the Vdata applied to the source signal line 18 is applied to the capacitor 19b. The video signal Vdata applied to the point a is held while the switching transistor 11b is on.

  2 may be applied with an ON voltage (VGL) or an OFF voltage (VGH).

  When the switching transistor 11c and the switching transistor 11 are turned on, a path between the driving transistor and the channel of the transistor 11b is generated from the source signal line 18, and the capacitor 11a is charged. By applying Vdata, the driving transistor 11a changes the potential at the gate terminal b so that a current corresponding to Vdata flows, and the changed voltage is held in the capacitor 19a. This operation cancels the offset of the driving transistor 11a. The potential of the capacitor 19b is held for one frame period.

  After the above-described offset cancel operation, the ON voltage is applied to the gate signal line 17b, the switching transistor 11e is turned ON, and the Vdd voltage is supplied to the source terminal of the driving transistor 11a. Further, the switching transistor 11d is turned on, and the driving current for the EL element 15 is supplied from the driving transistor 11a to the EL element 15. The EL element 15 emits light by the applied current.

  An ON voltage or an OFF voltage is applied to the gate signal line 17b, and a current is supplied to the EL element 15 in synchronization with the ON / OFF voltage. The EL element emits light or goes out in synchronization with the application state of the on / off voltage.

  During an operation in which the EL element 15 emits light or is turned off (period other than the voltage programming period, a period from 3t), the transistor 11b is in an open state. At this time, the anode voltage Vdd (ignoring the channel voltage drop of the transistor 11e) is applied to the source terminal of the transistor 11a when the EL element 15 emits light. When the EL element 15 is turned off, the transistor 11e and the transistor 11d are opened. When the EL element 15 is turned off, the source terminal of the driving transistor 11a is substantially held at the anode potential Vdd by the capacitor 19b. Therefore, the potential stability of the transistor 11a is good.

  The EL element 15 is turned on and off by performing duty control on the transistor 11d (turning on / off the transistor 11d and the like, generating a strip-like non-display area on the display screen 31, The image may be displayed in synchronization with the frame period).

(6) Pixel change example 1
FIG. 10 is a first modification of the pixel in FIG.

  One terminal of the capacitor 19b is connected to the gate signal line 17a. An on voltage (VGL) or an off voltage (VGH) is applied to the gate signal line 17a, but the off voltage (VGH) is applied in a period other than after the video signal voltage is written to the pixel 16 (after voltage programming). Is applied. Therefore, the capacitor 19b holds a constant charge and is stable.

(7) Pixel change example 2
FIG. 11 is a second modification of the pixel in FIG.

  One terminal of the capacitor 19b is connected to the gate signal line 17b. An on voltage (VGL) or an off voltage (VGH) is applied to the gate signal line 17b. However, an off voltage (VGH) is applied during a period when the video signal voltage is written to the pixel 16 (at the time of voltage programming). Therefore, the capacitor 19b holds a constant charge and maintains a stable state.

  In FIG. 11, one terminal of the capacitor 19b is connected to the gate signal line 17b. However, the present invention is not limited to this and may be connected to the gate signal line 17d. The on-voltage (VGL) is applied to the gate signal line 17d only when the reset voltage Vrst is applied. However, the off voltage (VGH) is applied in other periods. An off voltage (VGH) is applied. Therefore, the capacitor 19b holds a constant charge and maintains a stable state.

(8) Pixel change example 3
FIG. 4 is a modification of the pixel in FIG.

  The difference between FIG. 1 and FIG. 4 is that a capacitor 11c is additionally formed. One object of the capacitor 11c is to realize a better black display (high contrast display) by generating a punch-through voltage due to a change in the voltage applied to the gate signal line 17a (VGL → VGL). The operation of VGL → VGH is an operation for writing and holding a video signal in the pixel 16. That is, this is a control operation of the switching transistor 11c.

  The capacitor 19c has a first electrode commonly connected to the current gate signal line 17a and the gate terminal of the transistor 11c, and a second electrode commonly connected to the capacitor 19a and the gate terminal of the driving transistor 11a.

  In the case where the driving transistor 11a is an N-channel transistor, the pixel 16 is configured so that the voltage applied to the gate signal line 17a (the voltage used when writing and holding the video signal in the pixel) is changed from VGL to VGH. To do.

  That is, the auxiliary capacitor 19b serves to boost the gate voltage (point b) of the driving transistor 11a while changing from the scanning period to the light emission period.

  When the off voltage applied to the gate signal line is VGH and the on voltage is VGL, when the voltage applied to the gate signal line 17a is changed from VGL to VGH, the gate voltage of the driving transistor 11a becomes the auxiliary voltage of the capacitor 19a. The correction voltage is increased by the coupling of the capacitor 19b. Therefore, the voltage of the gate terminal of the driving transistor 11a is shifted to the Vdd voltage side, and a good black display can be realized.

(9) Pixel change example 4
Next, pixel modification example 4 will be described with reference to FIGS. 5 and 6.

(9-1) Pixel Configuration In FIG. 5, the pixel 16 includes two capacitors 19a and 19b, five switch transistors 11b, 11c, 11d, 11e, and 11f, and one drive transistor 11a.

  The switching transistor 11b is a threshold voltage compensation transistor for compensating the threshold voltage by diode-connecting the driving transistor 11a.

  The switching transistor 11f is an initialization transistor for applying a reset voltage Vrst to initialize the capacitor 19a.

  The switching transistor 11d is a transistor for controlling the light emission of the EL element 15.

  Since the switching transistors 11b and 11f need to be made small with an off-leakage, a multi-gate structure having a dual gate or higher is used.

  The switching transistor 11c has a gate electrode connected to the gate signal line 17a, a source electrode connected to the source signal line 18, and is turned on / off by a selection signal from the gate driver circuit 12a.

  The source electrode of the driving transistor 11a is connected to the drain electrode of the transistor 11c. The source or drain electrode of the threshold voltage compensation transistor 11b and the first terminal of the capacitor 19a are commonly connected to determine the gate voltage of the driving transistor 11a. Therefore, the driving transistor 11a generates a driving current corresponding to the voltage applied to the gate electrode.

  The switching transistor 11b, which is a threshold voltage compensation transistor, is connected between the gate electrode and the source electrode of the driving transistor 11a, and causes the driving transistor 11a to be diode-connected in response to a scan signal applied to the gate signal line. . Accordingly, the driving transistor 11a is in a diode-like state by the scan signal, and the voltage Vdata−Vth [V] is applied to the gate terminal of the driving transistor 11a, which is equal to the gate voltage of the driving transistor 11a. Become.

  The switching transistor 11f, which is an initialization transistor, is connected between the reset voltage line Vrst and the first terminal of the capacitor 19a, and responds to the scan signal of the (n-1) th gate signal line 17a connected to the gate electrode. The charge charged in the capacitor 19a in the preceding frame is discharged through the reset voltage line Vrst to initialize the capacitor 19a.

  The switching transistor 11e is connected between the first power supply voltage line Vdd and the source electrode of the driving transistor 11a, and is turned on by a light emission control signal transmitted through the gate signal line 17b connected to the gate electrode. A first power supply voltage Vdd is applied to the source electrode of the driving transistor 11a.

  The switching transistor 11d is connected between the driving transistor 11a and the EL element 15, and is generated by the driving transistor 11a in response to a light emission control signal transmitted through the gate signal line 17b connected to the gate electrode. The drive current is transmitted to the EL element 15.

  The capacitor 19a is connected between the first power supply voltage line Vdd and the gate electrode of the driving transistor 11a, and the first power supply voltage Vdd and the voltage Vdata−Vth [applied to the gate electrode of the driving transistor 11a]. The charge corresponding to the voltage difference of V] is maintained for one frame.

  The auxiliary capacitor 19b has a first electrode commonly connected to the current gate signal line 17a and the gate terminal of the transistor 11b, and a second electrode commonly connected to the capacitor 19a and the gate terminal of the driving transistor 11a.

(9-2) Gate signal line A gate signal line 17a1 and a gate signal line 17a2 are branched from the gate signal line 17a, and an inverter circuit 51 is arranged in the gate signal line 17a1. Therefore, VGH and VGL are inverted and a voltage is applied to the gate signal line 17a1 and the gate signal line 17a2.

(9-3) Source Signal Line The source signal line 18a and the source signal line 18b are provided, and the pixels 16 (16a, 16b) adjacent in the vertical direction are connected to different source signal lines 18. In the present embodiment, the pixel 16b is connected to the source signal line 18b, and the pixel 16a is connected to the source signal line 18a.

  6 shows a connection state between the gate signal line 17 and the source signal line 18 in the pixel configuration of FIG. 5 and 6, the gate signal line for controlling the switching transistor 11f for applying the reset voltage Vrst and the gate signal line for controlling the switching transistor 11c for applying the video signal are provided. And can be made common. Therefore, the number of gate signal lines 17 can be reduced, and the aperture ratio of the pixels 16 can be improved.

  In addition, a plurality of pixel rows can be simultaneously set to the offset cancel state, and favorable offset cancellation can be realized.

(10) Duty Drive In this embodiment, the duty drive as shown in FIG. 12B can be realized by controlling on / off of at least one of the switching transistors 11e and 11d.

  In FIG. 12, 121 is a program pixel row (a pixel row in which a video signal is written), and 123 is a non-display region (non-display (EL element 15) by turning off at least one of the transistor 11e and the transistor 11d. The pixel row or the group of pixel rows) in which no current flows or is small even if it flows. Reference numeral 122 denotes a display region (a pixel row or a group of pixel rows in which both the transistor 11e and the transistor 11d are turned on and current is supplied to the EL element 15. The non-display region 123 and the display region 122 have a frame period or horizontal synchronization. The display screen 31 is scanned in the vertical direction in synchronization with the signal.

(10-1) Problems In the display of FIG. 13A, one display area 122 moves downward from the top of the screen. When the frame rate is low, it is visually recognized that the display area 122 moves. In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.

(10-2) Solution To solve this problem, as shown in FIGS. 12B and 12C, the display area 122 may be divided into a plurality of parts. The divided display areas 122 do not need to be equal (equally divided). For example, the display area is divided into four areas, the divided display area 122a has an area 1, the divided display area 122b has an area 2, and the divided display area 122c has an area 1. The area 4 may be 122d.

  It goes without saying that the display area 122 in several frames (fields) may be controlled so as to average the target area. For example, when the area of the display area 122 occupying the display screen 31 is 1/10, the area of the display area 122 is 1/10 for the first frame (field), and the area of the display area 122 is for the second frame (field). The area is 1/20, the area of the display region 122 is 1/20 in the third frame (field), and the area of the display region 122 is 1/5 in the fourth frame (field). A driving method for obtaining 1/10 of a predetermined display area (display luminance) is exemplified.

  Further, each of R, G, and B may be driven so that the average of the L periods is equal in several frames (fields). However, the number of frames (fields) is preferably 4 frames (fields) or less. This is because flicker may occur depending on the display image.

  Note that one frame or one field in the present embodiment is the same as the image rewriting cycle of the pixels 16 or the cycle in which the display display screen 31 is scanned from top to bottom (from bottom to top).

  Alternatively, driving may be performed so that an appropriate white balance can be obtained by varying the average of L periods in several frames (fields) for R, G, and B. This driving method is particularly effective when the RGB luminous efficiencies are different. Further, the number of divisions K (the number of divisions of the display area 122) may be different for RGB. In particular, since it is visually noticeable in G, it is effective in G to increase the number of divisions relative to RB.

  In the above embodiment, the display area 122 is described as being divided for easy understanding. However, dividing the area means dividing a period (time). Therefore, in FIG. 1, the on period of the transistor 11 d is divided, so dividing the area is the same as dividing the period (time).

(10-3) Effect As described above, screen flickering is reduced by dividing display area 122 into a plurality of parts. Therefore, no flicker occurs and a good image display can be realized. The division may be made finer. However, the moving image display performance decreases as it is divided. In addition, the frame rate of image display can be reduced, and low power consumption can be realized. For example, when the non-lighting areas 123 are integrated, flicker occurs when the frame rate is 45 Hz or less. However, when the non-lighting region 123 is divided into 6 or more, flicker does not occur up to 20 Hz or less.

(11) Brightness Adjustment Method FIG. 13A is a brightness adjustment method when the display area 122 is continuous as shown in FIG. The display brightness of the display screen 31 in FIG. The display brightness of the display screen 31 in FIG. 13 (a2) is the next brightest, and the display brightness of the display screen 31 in FIG. 13 (a3) is the darkest. The change from FIG. 13 (a1) to FIG. 13 (a3) (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. At this time, it is not necessary to change the Vdd voltage (anode voltage or the like) in FIG. Further, it is not necessary to change the magnitude of the program current or the program voltage output from the source driver circuit 14. That is, the luminance of the display display screen 31 can be changed without changing the power supply voltage and without changing the video signal.

  In addition, the gamma characteristic of the screen does not change at all when changing from FIG. 13 (a1) to FIG. 13 (a3). Therefore, the contrast and gradation characteristics of the display image are maintained regardless of the brightness of the display screen 31. This is the effect of this embodiment.

  In the conventional screen brightness adjustment, the gradation performance is degraded when the brightness of the display screen 31 is low. That is, even when 64 gradation display can be realized during high brightness display, only half or less gradations can be displayed during low brightness display. Compared to this, the driving method of the present embodiment can realize the highest 64 gradation display without depending on the display brightness of the screen.

  FIG. 13B shows a brightness adjustment method when the display area 122 is dispersed as described with reference to FIG. The display brightness of the display screen 31 in FIG. 13 (b1) is the brightest. The display brightness of the display screen 31 in FIG. 13 (b2) is the next brightest, and the display brightness of the display screen 31 in FIG. 13 (b3) is the darkest. The change from FIG. 13 (b1) to FIG. 13 (b3) (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. If the display area 122 is dispersed as shown in FIG. 13B, flicker does not occur even at a low frame rate.

  Further, in order to prevent flicker from occurring even at a low frame rate, the display area 122 may be finely dispersed as shown in FIG. However, the display performance of moving images decreases. Therefore, the driving method shown in FIG. 13A is suitable for displaying a moving image. When a still image is displayed and low power consumption is desired, the driving method shown in FIG. 13C is suitable. The switching of the driving method from FIG. 13A to FIG. 13C can be easily realized by controlling the shift register 61.

  In FIG. 13, the non-display areas 123 are configured at equal intervals, but the present invention is not limited to this. The display area 122 is driven so that a half area of the display screen 31 continuously forms the display area 122 and the remaining area 50 repeats the display area 122 and the non-display area 123 at equal intervals as shown in FIG. Needless to say.

(12) Display Device Next, the display device of this embodiment using the EL display device that implements the driving method of this embodiment as a display display will be described.

(12-1) First Application Example FIG. 7 is a plan view of a mobile phone of an information terminal device which is an example of an EL display device. An antenna 71 and the like are attached to the housing 73. Reference numeral 72a is a switching key for changing the brightness of the display screen, 72b is a power on / off key, and 72c is a key for switching the operation frame rate of the gate driver circuit 12b. Reference numeral 75 denotes a photo sensor. The photo sensor 75 automatically adjusts the luminance of the display screen 22 by changing the duty ratio and the like according to the intensity of external light.

(12-2) Second Application Example FIG. 8 is a perspective view of a video camera. The video camera includes a photographing (imaging) lens unit 83 and a video camera body 73. The EL display panel of this embodiment is also used as the display monitor 74. The display screen 22 can freely adjust the angle at a fulcrum 81. When the display screen 22 is not used, it is stored in the storage unit 83.

(12-3) Third Application Example The EL display panel or EL display device of the present embodiment can be applied not only to a video camera but also to an electronic camera as shown in FIG. The EL display device of this embodiment is used as the monitor 22 attached to the camera body 91. In addition to the shutter 93, switches 72 a and 72 c are attached to the camera body 91.

(13) Circuit Configuration FIG. 14 shows a circuit for one column of the EL display panel in the present embodiment. Here, the source signal line 18 has two source signal lines 18a and 18b for one column via the switching means 141, and the source signal lines connected to the pixels in the even and odd rows are different. It is a feature. The configuration of each pixel 16 includes, for example, circuits such as FIG. 1, FIG. 4, FIG. 10, and FIG. The gate driver circuit 12a has a shift register configuration, and a pulse is shifted by one stage for each clock. By connecting to the gate signal line 17 as shown in FIG. 14, a signal waveform as shown in FIG. 15 can be realized.

  The period of the shift clock is set to one horizontal scanning period, and a start pulse that outputs a pulse only for one horizontal scanning period is input. Thus, it is possible to realize a circuit that generates a pulse during one horizontal scanning period at a timing shifted by one horizontal scanning period for each row. The output of each stage of the shift register is taken into the gate signal line 17 as shown in FIG. 14, and the switching means 141 is operated as shown in FIG. 15, thereby driving the pixels 16a in the first row in the first one horizontal scanning period. The gate voltage of the transistor 11a is initialized by the Vrst power supply. At the same time, the signal voltage corresponding to the pixels in the first row corresponding to the predetermined gradation is charged from the source signal line to the source signal line 18b via the switching unit 141. The source signal line 18a is not charged. The switching means 141 separates it from the source driver circuit output. In the next one horizontal scanning period, the switching means 141 is operated to charge the source signal line 18a. At this time, since the source signal line 18b is disconnected from the source driver circuit output, the signal voltage corresponding to the pixel in the first row remains charged by the floating capacitance 142b of the source signal line. Therefore, the gate signal line 17a and the gate signal line 17c are scanned to turn on the transistors 11c and 11b of the pixel 16a, and the gradation signal is written into the pixel driving transistor 11a and the characteristic variation is canceled. At the same time, corresponding to the pixels in the second row, the gradation signal voltage corresponding to the pixel 16b is charged to the source signal line 18a, and the gate electrode of the driving transistor 11a is initialized by the Vrst power supply.

  By switching between the source signal line 18a and the source signal line 18b for each horizontal scanning period, the gradation signal to be applied to the source signal line is held for two horizontal scanning periods. You can be longer.

  In the configuration of the pixel circuit shown in FIG. 1 and the like, an operation of canceling the characteristic variation is performed while writing a gradation signal to the driving transistor 11a. The operation of canceling the characteristic variation is performed when the transistors 11f, 11d, and 11e are off and the transistor 11b is on, and the gate potential of the driving transistor 11a is set so that the drain current of the driving transistor 11a becomes zero. By changing, the characteristic variation is canceled. The gate potential of the driving transistor 11a is changed by the charge due to the drain current, and since the final state is 0 or an infinitely small current (picoampere order), the storage capacitor 19a that supports the gate potential. It takes time to charge and discharge. Therefore, it can be seen that the cancel operation takes time. When one horizontal scanning period is long, the canceling operation can be completed within one horizontal scanning period. However, when the number of vertical lines is large and one horizontal scanning period is shorter than 40 μsec, the canceling operation ends. Thus, there is a problem that the characteristic compensation becomes incomplete, and as a result, unevenness corresponding to the characteristic variation occurs.

  Therefore, as a method of extending the cancel time to one horizontal scanning period or more, as shown in FIG. 16, the gate driver circuit 12a is further composed of two gate driver circuits 12a1 and 12a2, and the initialization of the driving transistor 11a is performed. This is performed in advance before one horizontal scanning period in which the corresponding video signal is input, and gradation voltage writing and characteristic cancellation are performed in the driving transistor 11a from the horizontal scanning period in which the video signal is input to the source signal line 18a or 18b. Make an action. Since the video signal is held for two horizontal scanning periods by the operation of the switching unit 141, the gradation voltage writing and the characteristic canceling operation can be performed during the two horizontal scanning periods. In order to realize this, a start pulse 172b of the shift register 12a2 is input as shown in FIG. The transistors 17a and 17c in each row are turned on for two horizontal scanning periods. The turn-on timing is performed in synchronization with the video signals of the source signal lines 18 and 18a, 18b. Since the video signal is distributed to the two source signal lines 18a and 18c in the even and odd rows, the frequency is halved and the writing time can be doubled. Note that the enable signal 173 is a signal for preventing simultaneous selection of pixels in a plurality of rows due to waveform rounding at the time of pulse propagation. The simultaneous selection does not occur or the simultaneous selection operates without any problem. In some cases, this embodiment is unnecessary, and the present embodiment can be implemented without the enable signal 173. For example, as shown in FIG. 21, an input waveform and operation when the enable signal of the gate driver circuit 12a2 that generates a signal for canceling characteristics is deleted are shown.

  According to the waveform of FIG. 17, the characteristic correction operation of the driving transistor 11a is possible during two horizontal scanning periods, but the driving transistor 11a is initialized one horizontal scanning period before the video signal is input in advance. If the first row cannot be detected, it may not be possible to perform initialization in advance.

  Therefore, as shown in FIG. 18, a signal pattern has been devised in which the initialization operation is performed simultaneously with the video signal input in the first row. Since the characteristic correction operation cannot be performed during the initialization operation, the post-initialization characteristic correction operation is performed between two horizontal scanning periods. 18, the initialization operation is performed in the first half of the first horizontal scanning period of the two horizontal scanning periods, and the signal writing to the pixel and the characteristic compensation operation are performed in the remaining half and the next horizontal scanning period. I made it. When the gate driver circuit has a shift register configuration, when the horizontal scanning period and the shift clock coincide, the operation of different switches in the first half and the second half of the horizontal scanning period is performed by cutting the pulse width with the enable signal. It was realized. When the gate signal line 17d is at the low level, the drive transistor 11a is initialized. When the gate signal lines 17a and 17c are at the low level, the characteristics of the drive transistor 11a are canceled and the gradation is written into the pixel. It becomes. Since the low level period of 17a and 17c can be set longer than one horizontal scanning period, even if the horizontal scanning period is 30 μsec, a 1.5 times period can be obtained compared to the conventional case, so a 45 μsec cancellation period can be taken and driving It has become possible to correct variations in the characteristics of the transistors used. Since the initialization operation itself is completed in about 2 to 10 microseconds, the cancel period can be extended to a time obtained by subtracting 2 to 10 microseconds from a maximum of two horizontal scanning periods.

  19 and 20 show a method in which the shift register of the gate driver circuit 12a has one system and the cancel period is expanded to one horizontal scanning period or more.

  For example, when canceling during two horizontal scanning periods, the gate signal lines 17a and 17c need to be in a conductive state for two horizontal scanning periods. Therefore, the start pulse of the gate driver circuit 12a is input for the length of two horizontal scanning periods. Thus, the cancellation and gradation writing time can be set to two horizontal scanning periods. Similarly, it is necessary to generate a pulse for the gate signal line 17d for performing initialization. Since the pixel circuit configuration is as shown in FIGS. 1 and 25, the gate signal lines 17d and 11a and 11c must not be in a conductive state at the same time (different voltages are short-circuited). It is necessary not to overlap with the pulses for canceling and gradation writing for the other pixels. Specifically, a pulse before two horizontal scanning periods may be used as an initialization pulse. As shown in FIG. 19, when using the gate signal line for canceling the gradation signal writing and the output common to the gate signal line 17d for the shift register, it is the second stage (that is, after two horizontal scanning periods). , The same pixel 16a is initialized in two horizontal scanning periods 201 and 202 as shown in FIG. 20, and the characteristics of the driving transistor 11a in two horizontal scanning periods 203 and 204 are obtained. Cancel and gradation signal writing are performed. Similarly, the pixels 16b and 16c are also executed at a timing delayed by one horizontal scanning period.

  This method can be implemented not only for canceling two horizontal scanning periods but also for cases where three horizontal scanning periods or more are required. The number of source signal lines corresponding to one column of pixels is prepared for the number of necessary horizontal scanning periods (integer), and the pulse width of the start pulse of the gate driver circuit 12a is input for the required number of horizontal scanning periods. This is realized by extracting the gate signal for characteristic cancellation and gradation signal writing from the shift register stage after the required number of horizontal scanning periods from the stage of the shift register that takes out the gate signal corresponding to the shift, and inputting it to the pixels in the same row. Is possible. The start pulse needs to be input in advance to the video signal so that the video signal is written to the pixels in the corresponding row. It is necessary to input at least as much as the length of the horizontal scanning period to cancel. Also in FIG. 20, the input is performed earlier by two horizontal scanning periods.

  In order to reduce the cost of the source driver circuit, there is a case where a selective driving method is employed in which voltages corresponding to a plurality of pixels are output in time series from one output. Compared with the case where there is no selection driving method, the timing at which the video signal corresponding to the pixel is input differs depending on the display color. For example, in the case of 3-selective drive in which 3 pixels of red, green, and blue are output with 1 output, as shown in FIG. 22, green and blue are not the beginning of the horizontal scanning period but the signal changes midway as shown in FIG. You can see that When the gate signal lines 17a and 17c are input with the waveform 221 for the green and blue pixels, the video signal of the previous row is written to the pixel, and the video signal of the row is written by the change of the source signal line. . In the case of liquid crystal or the like, there is no problem because the final voltage at the time of writing (the voltage at the moment when the gate signal line is turned off) is held in the pixels for one frame and displayed at a predetermined luminance, but has the pixel configuration in this embodiment. In the organic EL panel, the operation of correcting the characteristic variation of the driving transistor 11a is performed when the video signal is written to the driving transistor 11a. In order to shorten the time required for the correction, an initialization operation is performed before writing, and the voltage is applied to the gate electrode of the driving transistor 11a at a lower voltage (the voltage at which the driving transistor 11a allows a current to flow than when white is displayed) in advance. Initialization is in progress. As the initialization voltage is lower, the characteristic correction is faster. When the voltage of the previous row is applied even a little during the selective driving, the gate voltage of the driving transistor 11a changes to the voltage of the previous row, and in the state where the voltage of the previous row is applied, The gradation signal is written by the video signal and the transistor variation characteristic correction is performed, and the effect of initialization is lost. This is a common problem when performing signal line selection driving of two or more selections, even if it is not three selection driving.

  Therefore, in this embodiment, when performing selective driving, the characteristic canceling operation is performed after all the voltages of the signal lines to be written are determined in the same horizontal scanning period.

  FIG. 23, FIG. 24 and FIG. 26 show one embodiment. Here, the selection driving is a three-selection driving method in which three signal lines of red, green, and blue are sequentially selected. The same can be realized with two selections or four or more selections. In order to ensure the cancellation time, two signal lines are prepared for each column, and different source signal lines are used for even rows and odd rows. FIG. 23 shows a configuration in which the gate driver circuit 12a is implemented by one shift register circuit. FIG. 26 shows signal input and operation of the signal line selection circuit 232 when the gate driver circuit 12a of FIG. 23 is used. The signal lines are switched to red (R), green (G), and blue (B) within one horizontal scanning period. The selection is performed by switching between the odd-numbered source lines 18b and the even-numbered source lines 18a every horizontal scanning period.

  In this method, the initialization timing and the writing of the video signal line in the row are the same, and the writing of the video signal to the inside of the pixel is performed in the next horizontal scanning period. The video signal does not change during signal line writing and characteristic variation correction, and similar driving can be performed even during selective driving. A timing chart focusing on one pixel is shown in FIG. Here, the gate signal line 17b which has not been described so far is also described. As for 17b, the switch to be connected must be non-conductive in the initialization period, the characteristic cancellation, and the period in which the gradation signal is written to the driving transistor. It may be in any non-conducting state. The same applies to other embodiments of the present embodiment. FIG. 24 shows an example in which conduction / non-conduction is repeatedly performed.

  The source signal line 18 sends a signal for three pixels during one horizontal scanning period in response to three selection driving. The voltage change of the source signal line 18bB corresponding to the blue pixels in the odd-numbered rows by the signal line selection circuit has a waveform indicated by 241.

  The change of the gradation signal corresponding to the first row changes at the timing of 242. At this time, the gate signal line 17b is in an OFF state, and the video signal of the previous line is not written to the gate electrode of the driving transistor 11a. The gate signal line 17a is off according to the configuration of the gate driver circuit of FIG. 23, but may be on. The configuration of the gate driver circuit may be changed and turned on. This is because the voltage of the previous row is applied to the source electrode of the driving transistor 11a but is not applied to the initialized gate electrode.

  After the time 2t, the gate signal lines 17c and 17a become conductive, and the gradation voltage and the characteristic canceling operation are performed on the driving transistor 11a. At this time, as shown in FIG. 26, the source signal line 18bB is separated from each source signal line by the signal line selection circuit 232, and the voltage written from the source driver circuit is caused by the floating capacitance 233 of the source signal line. Holds for two horizontal scan periods. The held voltage value is written to the pixel, and a predetermined voltage is written. Between times 2t and 3t, the gate voltage of the driving transistor 11a gradually changes to a potential lowered by the threshold voltage (Vth) from the written source voltage (Vs) to (Vs−Vth). After being written to a predetermined voltage at time 3t, a predetermined current flows through the EL element 15 by turning on the gate signal 17b to emit light.

  FIG. 27 is a diagram when the gate driver circuit 12a is constituted by two shift registers. According to this, by setting the start pulse individually, it is possible to set the gate signal lines 17a and 17c with different pulse widths with respect to the gate signal line 17d.

  FIG. 28 shows the input waveforms of the gate driver circuits 12a1 and 12a2 and the waveform of each gate signal line. A pulse for initialization is generated for the gate driver circuit 12a1 that generates a signal for initialization. The time required for initialization depends on the power supply capability for generating Vrst, but the initialization is completed in about 10 μsec. The gate signal line 17d is turned on in a short time. Since the time-consuming characteristic cancellation period and initialization period cannot be performed at the same time, it is important to shorten initialization in order to perform initialization to characteristic cancellation and gradation signal writing within two horizontal scanning periods. This is because. In FIG. 28, the operation is performed only during a period in which the source output is selected in red, but it may be a red and green selection period or a part of the red selection period. Since the voltage corresponding to the pixel is not applied to the source signal line 18aB or 18bB until the blue selection period is reached in the blue source signal line 18aB or 18bB in which the video signal of the row is written most slowly, the characteristics Cannot transition to the cancellation period. Since the characteristics cannot be canceled, the red / green selection period has no problem as the initialization period. In the characteristic cancellation and gradation signal writing, the shift register circuit of the gate driver circuit 12a2 generates a pulse that can be selected in two horizontal scanning periods, and excludes the initialization period or the period in which no video signal is written. An enable signal for providing an enable period for each even row is provided. The characteristic cancellation and gradation signal writing period of the first row is a period indicated by 281. The beginning of the period 281 is after completion of the blue pixel writing, but after the blue pixel is selected by the signal line selection circuit and the source signal line 18aB or 18bB is changed to a predetermined voltage, the gate signal line 17a and 17c may be set to a low level. The end of the period 281 may be set before a voltage corresponding to a pixel in a different row is next applied to the same source signal line. When the signal line selection speed is fast, the characteristic cancellation period can be set from the end of writing to the end of the next horizontal scanning period, and display with a high threshold voltage correction capability of the driving transistor 11a can be realized.

  Note that the gate signal line 17a may be at a low level in all two horizontal scanning periods. This is because the gate voltage of the driving transistor 11a is not affected even when the transistor 11c is turned on. In this case, a shift register output is input to the gate signal line 17c via an enable signal, and a shift register output is input to the gate signal line 17a without an enable signal or via a separate enable signal. It becomes composition.

  So far, the transistor used in the pixel circuit 16 has been described as a p-type transistor. However, the transistor may be an n-type transistor shown in FIG. Further, the organic EL element 15 may have a configuration in which the directions of the anode and the cathode are reversed and the Vss potential> the Vdd potential. Although the capacitor 19b is formed in FIG. 29, the present embodiment can be similarly implemented even without the capacitor 19b.

  When the capacitor 19b is formed, the voltage for one frame until the next video signal is written to the pixel is held, so that the potential at the point a is held. If the transistor 11b is turned on based on the held potential, it is possible to cancel the characteristic variation of the driving transistor 11a with a signal corresponding to the gradation signal. This is a cancel period 302 shown in FIG. This cancel period can be arbitrarily set depending on the configuration of the gate driver circuit regardless of the length of the horizontal scanning period. The writing of the video signal and the initialization of the driving transistor 11a are performed before the cancel period 302 (period 301). Only the transistors 11f and 11c are conductive. Thus, the gate potential of the driving transistor 11a is initialized by the Vrst power supply, and at the same time, a predetermined voltage is written from the source signal line 18 to the capacitor 19b. Since the predetermined gradation voltage is held in the capacitor 19b, the number of source signal lines 18 is one, and it is only necessary to turn on the transistor 11c only for one horizontal scanning period. A method in which the grayscale voltage is held by both the stray capacitance of the source signal line 18 and the capacitor 19b may be used by preparing two source signal lines 18. In this case, the capacity 19b can be reduced.

  When the cancellation is completed, a current is applied to the EL element 15 to obtain light emission with a predetermined luminance. This period is the light emission period 304. At this time, the transistors 11d and 11e are turned on to supply current to the EL element 15. The non-light emission periods 303 before and after are inserted when black is inserted to obtain an effect such as improvement of moving image visibility. At this time, at least one of the transistors 11d and 11e is non-conductive. Further, when black insertion is not performed in a constantly lit state, the period 303 may be omitted.

  In addition, the switching unit 141 and the signal line selection circuit 232 in the present embodiment are not necessarily on the array substrate, and may be configured to be incorporated in the source driver circuit IC.

  In this embodiment, the example in which there are two source signal lines connected to the pixels formed in the same column has been described. However, the present invention can be similarly applied to a plurality of three or more source signal lines. It is. In general, if N source signal lines are prepared and connected every N pixels, the source signal line can hold the gradation voltage during the N horizontal scanning period, and the characteristic canceling period is extended. Thus, the gate voltage closer to the characteristics of the driving transistor 11a can be held in the pixel circuit (maximum N horizontal scanning period), thereby improving display unevenness.

  In addition, for N source signal lines, if a pixel circuit is connected to a source signal line that differs at least between adjacent pixels, a gradation signal is held in the source signal line during two horizontal scanning periods. The characteristic cancellation period can be extended, and an EL display device with little display unevenness can be obtained.

(15) Power Supply for Initialization FIG. 31 is a circuit in which the power supply for initializing the gate voltage of the driving transistor 11a is changed from a voltage source to a current source. FIG. 32 shows the waveform of the gate signal line in the circuit configuration of FIG. In the circuit configuration in FIG. 31, the operation in one pixel is divided into a writing period 321, a light emission period 324, and a non-light emission period 323 during one frame. The non-light emitting period 323 is used when black is inserted to improve operation visibility. In the present embodiment, the non-light emitting period 323 may or may not exist. The compensation capability for characteristic variation can be improved in the same way.

  In the writing period 321, the transistors 11b, 11c, and 11f are turned on. As a result, the voltage of the source signal line 18 is applied to the source electrode of the driving transistor 11a. The gate and drain electrodes of the driving transistor 11a have the same potential by the transistor 11b, and the gate and drain voltages are such that the current supplied from the current source 312 becomes the drain current of the driving transistor 11a. Accordingly, in the writing period 321, the gate voltage of the transistor 11 a is (Vs−Vt1) when the voltage of the source signal line 18 is Vs. Here, Vt1 is a source-drain voltage when the current (Irst) of the current source 312 is passed through the driving transistor 11a, and has a different voltage value depending on the characteristics of the driving transistor 11a. When Irst flows through the driving transistor 11a, that is, the EL element 15, a voltage with corrected characteristic variation is applied to the gate electrode of the driving transistor 11a, and an EL display device without display unevenness can be realized. In the conventional configuration, the characteristic variation is completely corrected at the time of Irst = 0, that is, black display. As the current increases, current variation due to mobility variation that cannot be corrected occurs, and display unevenness occurs as the gray level increases. It was an easy situation. The display unevenness is less visible as the luminance is lower, and is more easily visible in the middle to high gradations. The correction in the middle to high gradations is easier to visually recognize than the characteristic correction with the current corresponding to the gradation 0. desirable. If the current value of the current source Irst for initialization is set to a middle to high gradation, display unevenness in gradations that are easily visible is not given priority, and mobility variations occur in gradations that are difficult to visually recognize. However, the display unevenness level in all gradation areas was improved by utilizing the fact that it is difficult to see. A feature is that the current Irst is allowed to flow during the canceling operation of the characteristic variation of the driving transistor so that the current region where the characteristic cancellation is most frequently performed can be changed.

  The circuit in FIG. 33 is characterized in that it has a voltage source 331 for initialization and a switching unit 333 for switching between the voltage source 331 and the current source 312 with respect to the configuration in FIG. This is because when the voltage of the transistor 11a is changed by the current source 312, it takes time until the current flowing through the driving transistor 11a changes to Irst in the case of a pixel displaying black one frame before, and the writing period 321. This is to solve the problem that the gate voltage of the driving transistor 11a is not easily Vs-Vt1. As the drain current of the driving transistor 11a increases, the gate voltage of the driving transistor 11a in the writing period 321 is easily changed. As the current flows more, the charge / discharge speed of the charge in the storage capacitor 19a becomes faster, and the gate voltage is likely to change. Therefore, a voltage source 331 is prepared for the purpose of improving the change speed of the gate voltage. The voltage source 331 is changed to the current source 312 at the beginning of the writing period 321, and the low voltage (in the case of the circuit configuration of FIG. By supplying the voltage to the driving transistor 11a, the drain current of the driving transistor 11a is increased at the beginning of the writing period 321 so that the canceling operation by the reset current source 312 is accelerated in the remaining period. I made it.

  FIG. 34 shows the operation of the gate signal and switching means in the circuit configuration of FIG. In the period 341 in which the voltage source is supplied in the writing period 321, the gate voltage of the driving transistor 11a becomes Vrst. The lower the voltage Vrst, the faster the change in the gate voltage when the switching means 333 switches to the current source 312. However, if the voltage Vrst is too low, the difference in the gate potential from the predetermined gradation becomes too large. There is a possibility that the voltage cannot be changed to the value. Therefore, Vrst is preferably about (voltage at white display) to (voltage at white display -5 [V]). In the subsequent period 342, the gate voltage changes to Vs−Vt1 based on the current signal 312 and the source signal line voltage Vs written. At this time, the drain current of the transistor 11a is larger than that in the configuration of FIG. 32, and the charge / discharge speed of the charge of the storage capacitor 19 is increased. Therefore, the speed changing up to Vs−Vt1 is the voltage application period 341. Even if it is included, the speed is increased and the characteristic can be corrected in a shorter time.

  FIG. 35 shows a circuit configuration in which the gate signal lines are individually controlled by the transistors 11e and 11d. In one pixel, one frame includes a reset period 361, a video signal writing and characteristic cancel period 362, a non-light emission period 363, and a light emission period 364. There are two power sources for initializing (resetting) the driving transistor 11a: a voltage source 331 and a current source 312, and a reset period in which the voltage source 331 is applied is 365, and a reset period in which the current source 312 is applied is 366. And In the reset period 361, the driving transistor 11a is initialized based on the current output from the current source 312, and the reset voltage and current are written to the pixels by using the same reset line 311 in the same column. It is necessary to carry out within the scanning period. The video signal writing and characteristic canceling period 362 need to be performed within one horizontal scanning period because the voltage corresponding to the video signal is supplied from the same source signal line 18 in the same column. When reset and characteristic cancellation do not take time, the reset period 361, video signal writing, and characteristic cancellation period 362 may be performed within one horizontal scanning period.

  The method of this embodiment is characterized in that the initialization of the gate voltage of the driving transistor 11a is performed using not only the voltage source 331 but also the current source 312. As shown in FIG. 36, in the period 365 of the reset period 361, the gate voltage of the driving transistor 11a is initialized to Vrst by the voltage source 331 as in the conventional case. At this time, the transistors 11e and 11b may be turned on or off by the gate signal lines 17e and 17c, but at least one of the transistors 11e and 11b is prevented from flowing through from the Vdd power supply to the Vrst power supply due to the characteristics of the driving transistor 11a. The transistor is preferably turned off. In this embodiment, a period 366 is further provided between the reset periods 361, the connection of the switching unit 333 is switched, and the driving transistor 11a is initialized by the current source 312. The transistors 11f, 11b, and 11e are turned on so that the current of the current source 312 becomes the drain current of the driving transistor 11a. The current value of the current source 312 is preferably set to a voltage such that the gate voltage of the driving transistor 11 a is near Vrst of the voltage source 331 in the period 366. Since there is a variation in characteristics of the driving transistor 11a, the average voltage of the pixels formed in the EL display device may be Vrst. During the period 366, the gate voltage of the driving transistor 11a changes to Vrst + ΔV1. Here, ΔV1 corresponds to the gate voltage variation when the current (Irst) of the current source 312 is passed.

  In the video signal writing and characteristic cancellation period 362, a video signal is input from the source signal line 18, the transistor 11b is in the on state, and the transistor 11f is in the off state, so that the gate voltage of the driving transistor 11a is equal to the video signal voltage. Vs changes until Vs−Vth (Vth is a threshold voltage). Vs−Vth is when the characteristic cancellation period is a sufficiently long time, and since it is necessary to end the period 362 in one horizontal scanning period, the characteristic cancellation period can be only about 40 μsec.

  Therefore, the gate voltage can change only to (Vs−Vth−ΔV2) in the conventional configuration (FIG. 41) in which the period 366 does not exist. The potential change for ΔV2 is insufficient. Therefore, the drain current ΔI2 of the driving transistor 11a flows as much as ΔV2. ΔI2 varies due to characteristic variations of the driving transistor 11a. Due to this influence, variations occur in the current flowing through the EL element 15 and display unevenness occurs.

  Here, if the period 366 exists, the potential at the end of the period 361 is shifted by ΔV1, so that the gate voltage at the end of the period 362 is (Vs−Vth−ΔV2 + ΔV1). Since the gate voltage of the transistor 11a is shifted by ΔV1 as a result of applying a constant current from the current source, in the case of the driving transistor 11a having a large ΔI2 with respect to ΔV2 (a transistor through which current flows well), ΔV1 becomes large and ΔV2 In the case of the driving transistor 11a having a small ΔI2 with respect to, ΔV1 is small (including a negative value). In a pixel in which a large amount of current flows due to display unevenness (ΔI2 relative to ΔV2 is large), ΔV1 increases and the gate voltage increases. In a pixel with a small current, ΔV1 becomes small, so the gate voltage decreases. In a pixel in which current easily flows, the gate voltage of 11a rises and the current flows, and in a pixel in which current does not easily flow, current flows due to a decrease in gate voltage. It becomes a direction which becomes small, and it becomes possible to improve display unevenness.

  In FIG. 40, when the reset period 361 is realized with only the voltage source for the driving transistor 11a having different current-voltage characteristics (a) and when the current source is used (b), the video signal writing and characteristic cancellation are performed. The difference in current value after the end of the period 362 is shown.

  In FIG. 40A, since the driving transistor 11a is initialized only by the voltage source, the gate voltage is Vrst in the driving transistors 11a of the two pixels having the characteristics 401 and 402. Is different from Irst1 and Irst2. In the characteristics 401, the points 403a and 402 are points 403b. Next, in the video signal writing and characteristic cancel period 362, the video signal is written to the source potential of the driving transistor 11a, and the gate potential tends to change to a point where the threshold voltage is lowered from the source potential by the threshold cancel operation. Since the time required for the change takes about 100 μs, the change does not sufficiently change to the cancel voltage 406 in one horizontal scanning period, but changes to a point indicated by 405. The amount of voltage change is determined by the flowing current and stray capacitance, and is expressed by voltage change amount ΔV = i × T / C (where i: current flowing, T: length of cancel period 362, C: stray capacitance), 403a Since the point has more current than the point 403b, the transistor indicated by the curve 401 has a larger potential change amount, and the voltage changes to V2. In the curve 402, the amount of change is small because the current at the point 403b is small, and the voltage changes only up to V1. The drain currents at the points 405a and 405b are different between I2 and I1, and this difference may be visually recognized as display unevenness. On the other hand, when the reset is performed using the current source, as shown in FIG. 40B, at the end of the reset period 361, the drain current is different from Irst and the gate voltage is different between the curves 401 and 402, and Vrst1, Vrst2 It becomes. (Points 404a and 404b) Next, when canceling in the video signal writing and characteristic canceling period 362, the flowing current is the same as Irst, there is no variation in stray capacitance, and the canceling time can be set the same because it is the same panel. Therefore, ΔV is the same for the curves 401 and 402, and becomes the voltages V1 and V2 shifted by the same potential. (Points 405c and 405d) The drain currents at this time are both I1, and even if there is a difference in the characteristics of the driving transistor 11a, the written current values after the characteristic cancellation period 362 are the same, and display unevenness is eliminated. The configuration was realized.

  Even if the gate voltage of the driving transistor 11a is completely different from the canceled voltage due to the short cancellation period, the gate voltage of the driving transistor 11a is individually set with a constant current in the reset period. A configuration with small variations could be realized. There is no period 365, and the reset may be performed only with the current source in the period 366. However, since it takes time to change the gate voltage to the vicinity of the Vrst voltage by the current source 312, the voltage source 331 previously supplies the voltage to the vicinity of Vrst. It is preferable to reset the current source 312 after changing the voltage. If the reset period 361 is long and the voltage can be changed to Vrst + ΔV1 only by the current source 312, the voltage source 331, the switching unit 333, and the period 365 may be omitted.

  In the EL display device having the pixel circuit configuration of FIG. 35, a plurality of source signal lines are prepared for pixels in the same column, and video signals are written from different source signal lines in pixels adjacent in the source signal line direction. Thus, it can be implemented in combination with a configuration in which the writing time is increased. For example, FIG. 37 shows a circuit in the case where two source signal lines are prepared. If two source signal lines 18 are prepared, the gradation signal applied to the source signal line 18 changes every two horizontal scanning periods as described with reference to FIGS. The signal writing and characteristic cancellation period 362 can be expanded to a maximum of two horizontal scanning periods. For example, a driving waveform as shown in FIG. 38 can be realized. By extending the period 362, the time for changing the gate voltage of the driving transistor 11a can be increased, the absolute value of the error ΔV2 can be reduced, and cancellation can be performed more accurately.

  In the configuration of FIG. 37, one reset line 311 is provided for one column of pixels. However, if there are a plurality of (for example, two) reset lines 3 as in the case of the source signal line 18, the reset period 361 is also in a maximum of two horizontal scanning periods. The reset voltage can also be set to a voltage according to the characteristics of the driving transistor 11a.

  In the configuration of FIG. 37 and the configuration of FIG. 35, the current source 312 and the voltage source 331 are connected to the reset line 311 via the switching unit 333. However, even without the voltage source 311, within one horizontal scanning period. If the gate voltage of the driving transistor 11a can be changed by the current source 312 until the predetermined initialization potential is reached, the reset period 361 can be configured only by the current source. At this time, the operation is performed for one frame period as shown in FIG. Although the change takes time due to the reset (initialization) operation using only the current source 312, the gate voltage of the driving transistor 11a converges to Vrst + ΔV1. Even when the voltage source 331 is used together, as shown in FIG. 36 and FIG. 38, it has the same value as Vrst + ΔV1 and is the same regardless of the effect of initialization.

(16) Modification Examples The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof.

  The transistor of this embodiment can be realized not only with a TFT but also with a bipolar transistor. The TFT can also be implemented in the same manner regardless of the constituent material such as polysilicon, crystalline silicon, and amorphous silicon.

  In addition, the pixel of the EL display device according to the present embodiment can be applied regardless of the display color, such as a single color pixel configuration, three colors of red, green and blue, four colors of red, green, and white, three colors of cyan yellow magenta, and a pen tile pixel configuration. Is possible.

  In addition, the pixel configuration in which red, green, and blue are arranged in this embodiment is only an example.

  14 and 16 and the like describe pixel configurations for one column. This is because the source signal lines are common regardless of whether they are formed in a stripe shape or in a delta arrangement. The same application is possible if there are a plurality of pixels.

  In addition, the present invention can be implemented by combining the embodiments.

  Since the EL display device according to the present embodiment can sufficiently secure the offset cancel period, it is possible to realize a good offset cancel. For this reason, even if the characteristic variation of the driving transistor 11a occurs, the characteristic variation can be canceled and a good image display can be realized.

It is a block diagram of a pixel of an EL display device. FIG. 46 is an explanatory diagram representing a driving method of an EL display device. It is an explanatory diagram of an EL display device. It is a block diagram of a pixel of an EL display device. It is a block diagram of a pixel of an EL display device. It is an explanatory diagram of an EL display device. It is explanatory drawing of the apparatus using EL display apparatus. It is explanatory drawing of the apparatus using EL display apparatus. It is explanatory drawing of the apparatus using EL display apparatus. It is a block diagram of a pixel of an EL display device. It is a block diagram of a pixel of an EL display device. FIG. 46 is an explanatory diagram representing a driving method of an EL display device. FIG. 46 is an explanatory diagram representing a driving method of an EL display device. It is the figure which showed the structure which takes in a video signal to a pixel from several source signal lines. FIG. 15 is a diagram showing an operation of the gate driver circuit 12a in the configuration of FIG. FIG. 5 is a diagram illustrating an example of a gate driver circuit and a pixel configuration when a characteristic cancel operation is performed over a plurality of horizontal scanning periods. FIG. 17 is a diagram illustrating an operation of the gate driver circuit of FIG. 16. FIG. 17 is a diagram illustrating an operation of the gate driver circuit of FIG. 16. FIG. 6 is a diagram illustrating a circuit in a case where a characteristic cancel operation is performed over a plurality of horizontal scanning periods in one shift register phase. FIG. 20 is a diagram showing the operation of the gate driver circuit when the circuit configuration of FIG. 19 is used. It is a figure showing an input waveform at the time of deleting an enable signal of gate driver circuit 12a2, and operation. It is the figure which showed the video signal change timing of each color signal line at the time of implementing 3 signal line selection drive. It is the figure which showed the circuit structure of EL display apparatus which has 3 signal line selection drive and 2 signal lines of each column. It is the figure which showed the operation | movement of the pixel 16c in FIG. It is the figure which showed the circuit of the pixel 16 in this invention. The figure which showed operation | movement of the gate driver circuit and the signal line selection circuit in the circuit of FIG. FIG. 6 is a diagram showing a circuit configuration of an EL display device having three signal line selection driving and two signal lines in each column, and a gate driver circuit separated for initialization, characteristic cancellation, and gradation signal writing. FIG. 28 is a diagram showing the operation of the gate driver circuit in the circuit configuration of FIG. 27. It is the figure which showed the pixel circuit using n-type TFT. FIG. 6 is a diagram showing the operation of a gate signal line for one frame in a pixel circuit in which a capacitor 19b is formed. FIG. 5 is a diagram illustrating a pixel circuit configuration in the case where a constant drain current is passed by a current source during an offset cancel operation of a driving transistor. FIG. 32 is a diagram showing input waveforms of a gate signal line and a source signal line, a gate voltage of a driving transistor, and an operation of an EL element in the pixel circuit configuration of FIG. 31. FIG. 5 is a diagram showing a pixel circuit configuration when a constant drain current is supplied from a current source during an offset cancel operation of a driving transistor and a gate voltage is set low using an initialization power supply before the cancel operation. FIG. 34 is a diagram showing input waveforms of a gate signal line, a source signal line, and switching means, a gate voltage of a transistor 11a, and an operation of an EL element in the circuit configuration of FIG. It is a diagram showing a pixel circuit for making the initialization voltage of the driving transistor 11a different according to the characteristic variation. FIG. 36 is a diagram showing an input pattern of a gate signal line 17, a switching unit 333, and a source signal line 18, a gate voltage of a transistor 11a, and an operation of an EL element 15 in the pixel configuration of FIG. FIG. 36 is a diagram showing a circuit configuration when gradation voltages are supplied from a plurality of source signal lines in the same column in the EL display device having the pixel circuit of FIG. FIG. 38 is a diagram showing an input signal waveform of a pixel 16a and operations of a driving transistor 11a and an EL element 15 in the circuit configuration of FIG. 38 is a diagram showing the input signal waveform of the pixel 16a, the operation of the driving transistor 11a, and the EL element 15 when the initialization power supply 331 is not used in the circuit of FIG. It is the figure which showed the mode of change when the gate voltage of the transistor 11a for a drive was initialized by (a) initialization power supply, and (b) it initialized by the current source. It is the figure which showed the change of the gate voltage of the driving transistor 11a when the characteristic cancellation period by a current source does not exist.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Transistor 12 Gate driver circuit 14 Source driver circuit 15 EL element 16 Pixel 17 Gate signal line 18 Source signal line 19 Storage capacity (addition capacitor, addition capacity)

Claims (7)

In an EL display device having a display screen in which a plurality of pixels having EL elements are arranged in a matrix form vertically and horizontally,
The pixel includes a driving transistor for supplying a driving current to the EL element,
The driving transistor includes a first power source that performs an offset canceling operation and changes a voltage of a gate electrode of the driving transistor with a current during a first period that is a period before the offset canceling operation.
EL display device. A second power source that applies a voltage to the gate electrode of the driving transistor during a second period that is a period before the first period;
The EL display device according to claim 1. Each of the pixels is
A drive transistor having a gate terminal connected to the first gate signal line, a source terminal connected to a drive terminal of a drive power supply, and supplying a drive current from the drive power supply to the EL element;
A source terminal is connected to a gate signal line for supplying a video signal, a gate terminal is connected to a second gate signal line, a drain terminal is connected to a front source terminal of the driving transistor, and the video signal is connected to the EL element. A first switch transistor for supplying a signal;
A second switching transistor connected between the EL element and a drain terminal of the driving transistor;
A first capacitor connected between the drain terminal and the power supply terminal of the first switching transistor;
A second capacitor connected between the gate terminal and the power supply terminal of the driving transistor;
The EL display device according to claim 1. Each of the pixels is
A drive transistor having a gate terminal connected to the first gate signal line, a source terminal connected to a drive terminal of a drive power supply, and supplying a drive current from the drive power supply to the EL element;
A source terminal is connected to a gate signal line for supplying a video signal, a gate terminal is connected to a second gate signal line, a drain terminal is connected to a front source terminal of the driving transistor, and the video signal is connected to the EL element. A first switch transistor for supplying a signal;
A second switching transistor connected between the EL element and a drain terminal of the driving transistor;
A first capacitor connected between the drain terminal and the gate terminal of the first switching transistor;
A second capacitor connected between the gate terminal and the power supply terminal of the driving transistor;
The EL display device according to claim 1. Each of the pixels is
A drive transistor having a gate terminal connected to the first gate signal line, a source terminal connected to a drive terminal of a drive power supply, and supplying a drive current from the drive power supply to the EL element;
A source terminal is connected to a gate signal line for supplying a video signal, a gate terminal is connected to a second gate signal line, a drain terminal is connected to a front source terminal of the driving transistor, and the video signal is connected to the EL element. A first switch transistor for supplying a signal;
A second switching transistor connected between the EL element and the drain terminal of the driving transistor, and having a gate terminal connected to a third gate signal line;
A third switching transistor having a source terminal connected to the power supply terminal, a drain terminal connected to the drain terminal of the first switching transistor, and a gate terminal connected to the third gate signal line;
A first capacitor connected between the drain terminal of the first switch transistor and the gate terminal of the third switch transistor;
A second capacitor connected between the gate terminal and the power supply terminal of the driving transistor;
The EL display device according to claim 1. Each of the pixels is
A driving transistor for supplying a current to the EL element;
A first switching transistor applied to the pixel;
A second switching transistor disposed between the EL element and the driving transistor;
A first capacitor connected to a drain terminal of the first switch transistor and a power supply terminal of the drive power supply;
A second capacitor connected to the gate terminal of the driving transistor and the power supply terminal;
Formed,
A drain terminal of the first switching transistor and a source terminal of the driving transistor are connected;
The EL display device according to claim 1. A third capacitor connected between the gate terminal of the first switching transistor and the gate terminal of the driving transistor;
The EL display device according to claim 3 or 6.