CN114023261A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN114023261A CN114023261A CN202111362006.XA CN202111362006A CN114023261A CN 114023261 A CN114023261 A CN 114023261A CN 202111362006 A CN202111362006 A CN 202111362006A CN 114023261 A CN114023261 A CN 114023261A
- Authority
- CN
- China
- Prior art keywords
- transistor
- light
- driving transistor
- compensation module
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Abstract
The invention discloses a display panel and a display device, the display panel comprises a pixel circuit and a light-emitting element, the pixel circuit comprises: the driving module is used for providing driving current for the light-emitting element and comprises a driving transistor; the data writing module is connected to the source electrode of the driving transistor; the compensation module is connected between the grid electrode and the drain electrode of the driving transistor and comprises a first compensation module and a second compensation module, and the first compensation module and the second compensation module are both connected between the grid electrode and the drain electrode of the driving transistor; in the data writing stage, the first compensation module starts the second compensation module and closes the second compensation module, and the data writing module writes a data signal into the grid electrode of the driving transistor; and in at least partial time period of the light-emitting stage, the first compensation module is closed and the second compensation module is opened, and the second compensation module is used for adjusting the potential difference between the grid and the drain of the driving transistor, improving the driving current of the light-emitting element and keeping the brightness of the light-emitting element.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the continuous development of display technologies, the development process of display panels is gradually accelerated. Organic Light-Emitting Diode (OLED) display panels are increasingly used as a current-type Light-Emitting device in high-performance display, and OLED display panels have excellent characteristics of self-luminescence, no need of backlight, wide color gamut, high contrast, thin thickness, wide viewing angle, fast response speed, applicability to flexible panels, wide temperature range, simple structure and process, and are also increasingly used for mobile phone display.
The pixel circuit of the organic display panel in the prior art has the problems that the potential difference between the grid electrode and the drain electrode of the driving transistor is overlarge in the light-emitting keeping stage, the current of a light-emitting element is reduced, and the brightness of the light-emitting element is poor to keep.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a display device to solve the problems of excessive potential difference between the gate and the drain of the driving transistor, reduced current of the light emitting device, and poor brightness retention of the light emitting device during the light emission retention period.
In one aspect, the present invention discloses a display panel, comprising:
a pixel circuit and a light emitting element;
the pixel circuit comprises a driving module, a compensation module and a data writing module;
the driving module is used for providing driving current for the light-emitting element and comprises a driving transistor;
the data writing module is connected to the source electrode of the driving transistor;
the compensation module is connected between the grid electrode and the drain electrode of the driving transistor and comprises a first compensation module and a second compensation module, the first compensation module is connected between the grid electrode and the drain electrode of the driving transistor, and the second compensation module is also connected between the grid electrode and the drain electrode of the driving transistor; wherein the content of the first and second substances,
the working process of the pixel circuit comprises a data writing frame, the data writing frame comprises a data writing stage and a light-emitting stage, in the data writing stage, the first compensation module is started, the second compensation module is closed, and the data writing module writes a data signal into the grid electrode of the driving transistor; and during at least part of the light-emitting period, the first compensation module is switched off and the second compensation module is switched on, and the second compensation module is used for adjusting the potential difference between the grid electrode and the drain electrode of the driving transistor.
In another aspect, the invention further provides a display device comprising the display panel.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the display panel of the present invention includes: a pixel circuit and a light emitting element; the pixel circuit comprises a driving module, a compensation module and a data writing module; the driving module is used for providing driving current for the light-emitting element and comprises a driving transistor; the data writing module is connected to the source electrode of the driving transistor; the compensation module is connected between the grid electrode and the drain electrode of the driving transistor and comprises a first compensation module and a second compensation module, the first compensation module is connected between the grid electrode and the drain electrode of the driving transistor, and the second compensation module is also connected between the grid electrode and the drain electrode of the driving transistor; the working process of the pixel circuit comprises a data writing frame, the data writing frame comprises a data writing stage and a light emitting stage, in the data writing stage, the driving transistor is conducted, the first compensation module is conducted, data voltage passes through the source electrode, the drain electrode and the first compensation module of the driving transistor, data are written into the grid electrode of the driving transistor, and data compensation is conducted on the grid electrode potential of the driving transistor; in at least partial time period of the light-emitting stage, the first compensation module is closed and the second compensation module is opened, the second compensation module is used for adjusting the potential difference between the grid electrode and the drain electrode of the driving transistor and pulling down the potential of the grid electrode of the driving transistor to the potential of the drain electrode of the driving transistor, so that Vdata' is a value smaller than the preset Vdata, the current I in the light-emitting stage is increased, the driving current of the driving module is compensated, and the problem of poor brightness maintenance in the light-emitting stage is solved.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a pixel driving circuit and a light emitting device in the prior art;
FIG. 2 is a schematic plan view of a display panel according to the present invention;
FIG. 3 is an enlarged view of the pixel cell of FIG. 2;
FIG. 4 is a timing diagram provided by the present invention;
FIG. 5 is a further enlarged view of the pixel cell of FIG. 2;
FIG. 6 is a further enlarged view of the pixel cell of FIG. 2;
FIG. 7 is a further enlarged view of the pixel cell of FIG. 2;
FIG. 8 is a timing diagram for the pixel circuit of FIG. 7;
FIG. 9 is yet another enlarged view of the pixel cell of FIG. 2;
FIG. 10 is a timing diagram for the pixel circuit of FIG. 9;
FIG. 11 is a timing diagram for the pixel circuit of FIG. 6;
FIG. 12 is a further enlarged view of the pixel cell of FIG. 2;
FIG. 13 is yet another enlarged view of the pixel cell of FIG. 2;
FIG. 14 is a cross-sectional view taken along line A-A' of FIG. 2;
fig. 15 is a schematic diagram of a display device according to an embodiment of the present application.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1, fig. 1 is a schematic diagram of a pixel driving circuit and a light emitting element in the prior art, and a pixel driving circuit 000 in fig. 1 includes: a first transistor M1 'having a gate electrically connected to the light-emitting signal input terminal, a first pole electrically connected to the first power signal terminal PVDD, and a second pole electrically connected to the first pole of the driving transistor M3'; a second transistor M2 'having a gate electrically connected to the second scan signal input terminal S2, a first pole electrically connected to the data signal input terminal Vdata, and a second pole electrically connected to the first pole of the driving transistor M3'; a driving transistor M3 'having a gate electrically connected to the second pole of the fifth transistor M5', a first pole electrically connected to the second pole of the first transistor M1 'and the second pole of the second transistor M2'; a fourth transistor M4 ' having a gate electrically connected to the second scan signal input terminal S2, a first pole electrically connected to the second pole of the fifth transistor M5 ' and the second pole of the storage capacitor Cst ', and a second pole electrically connected to the second pole of the driving transistor M3 ' and the first pole of the sixth transistor M6 '; a fifth transistor M5 'having a gate electrically connected to the first scan signal input terminal S1, a first pole electrically connected to the reference voltage signal input terminal Vref, and a second pole electrically connected to the gate of the driving transistor M3'; a sixth transistor M6 'having a gate electrically connected to the emission signal input terminal Emit, a first pole electrically connected to the second pole of the driving transistor M3' and the second pole of the fourth transistor M4 ', and a second pole electrically connected to the anode of the light emitting element O'; a seventh transistor M7' having a gate electrically connected to the second scan signal input terminal, a first pole connected to the reference voltage signal input terminalThe end is electrically connected, and the second electrode is electrically connected with the first electrode of the light-emitting element O'; the storage capacitor Cst 'has a first pole electrically connected to the first power signal terminal PVDD and a second pole electrically connected to the gate of the driving transistor M3', a first pole of the fourth transistor M4 ', and a second pole of the fifth transistor M5'. The first pole of the light emitting element O ' is electrically connected to the second pole of the sixth transistor M6 ' and the second pole of the seventh transistor M7 ', and the second pole is electrically connected to the second power signal terminal PVEE. The pixel circuit performs threshold compensation on the gate of the driving transistor M3 ' by data writing at the time of data writing, writes the data voltage Vdata into the first node N1 ', and cancels the threshold voltage of the driving transistor when the driving current is finally calculated, i.e., I ═ K (PVDD-N1 ' -/Vth)2＝K[PVDD-(Vdata-Vth)-Vth]2＝K(PVDD-Vdata)2Although the threshold voltage is a variable amount during light emission, the magnitude of the final driving current is independent of the threshold voltage; in the light-emitting holding phase, the first node N1 'will carry a voltage, which is equal to Vdata-Vth, where Vth is the threshold voltage of the driving transistor, and since the first node N1' carries a voltage, the driving transistor M3 'is operated in a non-saturated state, for example, the driving transistor M3' in fig. 1 is a PMOS type transistor, and if the driving transistor M3 'is made to be fully conductive, the gate thereof should be at a low potential, but since the first node N1' carries a voltage and may be at a high potential, the driving transistor M3 'cannot be fully conductive, the drain potential of the driving transistor M3' is low and is not equal to the potential of the source of the driving transistor M3 ', even lower than the potential of the gate of the driving transistor M3', the current Ioled of the light-emitting element is reduced, the potential of the third node N3 'is lower, resulting in that the potential difference between the gate and the drain of the driving transistor M3' is larger in the light-emitting holding phase, the brightness remains poor.
In view of the above, the present invention provides a display panel and a display device to improve the problems of excessive potential difference between the gate and the drain of the driving transistor, reduced current of the light emitting element, and poor brightness retention of the light emitting element in the light emission retention stage.
Referring to fig. 2, fig. 3 and fig. 4, fig. 2 is a schematic plan view of a display panel according to the present invention, fig. 3 is an enlarged view of a pixel unit in fig. 2, fig. 4 is a timing diagram according to the present invention, fig. 4 is a signal timing sequence for controlling the first compensation module and the second compensation module to be turned on and off, and fig. 4 illustrates an example in which an enable signal for controlling the first compensation module and the second compensation module to be turned on is at a high voltage level.
The display panel 1000 of the present invention includes: a pixel circuit 10 and a light emitting element 200; the pixel circuit 10 comprises a driving module 1, a compensation module 2 and a data writing module 3; the driving module 1 is used for providing a driving current for the light emitting element 200, and the driving module 1 includes a driving transistor M0; the data writing module 3 is connected to the source of the driving transistor M0; the compensation module 2 is connected between the gate and the drain of the driving transistor M0, the compensation module 2 includes a first compensation module 21 and a second compensation module 22, the first compensation module 21 is connected between the gate and the drain of the driving transistor M0, and the second compensation module 22 is also connected between the gate and the drain of the driving transistor M0; the working process of the pixel circuit 10 includes a data writing frame T0, the data writing frame T0 includes a data writing phase T01 and a light emitting phase T02, in the data writing phase T01, the first compensation module 21 is turned on and the second compensation module 22 is turned off, and the data writing module 3 writes a data signal to the gate of the driving transistor M0; during at least a part of the light emitting period T02, the first compensation module 21 is turned off and the second compensation module 22 is turned on, and the second compensation module 22 is used for adjusting the potential difference between the gate and the drain of the driving transistor M0.
Specifically, fig. 2 also shows that the display panel 1000 includes a display area AA and a non-display area BB surrounding the display area AA, the display area AA includes a plurality of pixels, and in conjunction with fig. 3, each pixel includes a pixel circuit 10 and a light-emitting element 200, and the pixel circuit 10 drives the light-emitting element 200 to emit light for image display. Of course, the non-display area BB also includes a gate driving circuit for driving the pixel circuit 10, which is not shown in the figure. The optional driving transistor M0 may be a PMOS type transistor or an NMOS type transistor, which is not limited herein, and of course, fig. 3 only illustrates the driving transistor M0 as an NMOS type transistor.
In this embodiment, referring to fig. 3, the pixel circuit 10 includes a driving module 1, a compensation module 2 and a data writing module 3, the driving module 1 is used for providing a driving current for the light emitting device 200, the driving module 1 includes a driving transistor M0, wherein the driving current of the driving transistor M0 is determined by the voltage of the gate and the drain of the driving transistor M0; the data writing module 3 is electrically connected with the source electrode of the driving transistor M0, and writes data into the gate electrode of the driving transistor M0 through the source electrode and the drain electrode of the driving transistor M0 and the first compensation module 21 when the driving transistor M0 is turned on; the compensation module 2 is connected between the gate and the drain of the driving transistor M0, the compensation module 2 includes a first compensation module 21 and a second compensation module 22, one end of the first compensation module 21 is electrically connected to the gate of the driving transistor M0, the other end of the first compensation module 21 is electrically connected to the drain of the driving transistor M0, meanwhile, one end of the second compensation module 22 is also electrically connected to the gate of the driving transistor M0, the other end of the second compensation module 22 is electrically connected to the drain of the driving transistor M0, the anode of the light emitting device 200 is electrically connected to the drain of the driving transistor M0, meanwhile, fig. 3 also shows a first power signal PVDD and a second power signal PVEE, where the first power signal PVDD is at a high potential, the second power signal PVEE is at a low potential, the first power signal PVDD is electrically connected to the source of the driving transistor M0, and the second power signal PVEE is electrically connected to the cathode of the light emitting source.
The optional data writing module 3 may have the same structure as the data writing module in the prior art, and a transistor, not shown, may be provided, where a source of the transistor is connected to the data signal, and a drain of the transistor is electrically connected to the source of the driving transistor M0.
With reference to fig. 4, the operation process of the pixel circuit 10 includes a data writing frame T0, the data writing frame T0 includes a data writing phase T01 and a light emitting phase T02, in the data writing phase T01, the first compensation module 21 is turned on, the second compensation module 22 is turned off, and the data writing module 3 writes a data signal to the gate of the driving transistor M0; during at least a portion of the light-emitting period T02, the first compensation module 21 is turned off and the second compensation module 22 is turned on, the second compensation module 22 is used to adjust the potential difference between the gate and the drain of the driving transistor M0, fig. 4 only shows that the second compensation module 22 is turned on during the whole light-emitting period T02, the high level of the signal S1 in fig. 4 controls the first compensation module 21 to be turned on, the low level of the signal S1 controls the first compensation module 21 to be turned off, the high level of the signal S2 controls the second compensation module 22 to be turned on, and the low level of the signal S2 controls the second compensation module 22 to be turned off.
Specifically, since the data writing module 3 is electrically connected to the source of the driving transistor M0, in the data writing phase T01, the driving transistor M0 is turned on, the first compensation module 21 is turned on, and the data voltage is written into the gate of the driving transistor M0 through the source and the drain of the driving transistor M0 and the first compensation module 21, so as to perform data compensation on the gate potential of the driving transistor M0; of course, the second compensation module 22 is turned off at this time, so that no data voltage passes through the second compensation module 22.
During at least a part of the light emitting period T02, the first compensation module 21 is turned off and the second compensation module 22 is turned on, and the second compensation module 22 is used for adjusting the potential difference between the gate and the drain of the driving transistor M0. Since the first compensation module 21 is turned off, the second compensation module 22 is disposed between the gate and the drain of the driving transistor M0, the second compensation module 22 is turned on, and the potential difference between the gate and the drain of the driving transistor M0 is adjusted to make the voltage of the gate of the driving transistor M0 equal to the voltage of the drain of the driving transistor M0, according to the lighting phase T02, the current formula I ═ K (PVDD-Vdata')2It can be seen that, since the second compensation module 22 adjusts the potential difference between the gate and the drain of the driving transistor M0 to pull down the potential of the gate of the driving transistor M0 to the potential of the drain of the driving transistor M0, Vdata' is a value smaller than the predetermined Vdata, so that the current I in the light emitting period T02 is increased, thereby compensating the driving current of the driving module 1 and improving the problem of poor brightness maintenance in the light emitting period T02.
In some alternative embodiments, with continued reference to fig. 4, the first compensation module 21 is turned on for a shorter time period than the second compensation module 22 during one data write frame T0.
It can be understood that the first compensation module 21 is turned on in the non-light emitting period T02, the second compensation module 22 is turned on in the light emitting period T02, so the on time of the first compensation module 21 should be as short as possible to shorten the time of the non-light emitting period T02, the second compensation module 22 is turned on in the light emitting period T02, and the duration of the light emitting period T02 is longer, so the on time of the second compensation module 22 can be longer to adjust the potential difference between the gate and the drain of the driving transistor M0 in the light emitting period T02, and pull down the potential of the gate of the driving transistor M0 to the potential of the drain of the driving transistor M0, so Vdata is a value less than the predetermined data, and thus the current I of the light emitting period T02 is increased, thereby compensating the driving current of the driving module 1 and improving the problem of poor brightness maintenance of the light emitting period T02.
In some alternative embodiments, referring to fig. 5 and 6, fig. 5 is a further enlarged view of the pixel unit in fig. 2, fig. 6 is a further enlarged view of the pixel unit in fig. 2, in this embodiment, the first compensation module 21 includes a first transistor M1, the second compensation module 22 includes a second transistor M2 and a first capacitor C1, and one of the first pole 31 or the second pole 32 of the second transistor M2 is connected to the first plate 41 of the first capacitor C1.
Specifically, in this embodiment, the first compensation module 21 includes a first transistor M1, a first pole of the first transistor M1 and a second pole of the first transistor M1 are electrically connected to the gate and the drain of the driving transistor M0, respectively, a first pole 31 of the second transistor M2 in fig. 5 is electrically connected to a first pole plate 41 of a first capacitor C1, a second pole 32 of the second transistor M2 is electrically connected to the drain of the driving transistor M0, a second pole plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M0, a second pole 32 of the second transistor M2 in fig. 6 is electrically connected to a first pole plate 41 of a first capacitor C1, a first pole 31 of the second transistor M2 is electrically connected to the gate of the driving transistor M0, and a second pole plate of the first capacitor C1 is electrically connected to the drain of the driving transistor M0.
It is understood that the first pole and the second pole may be a source or a drain, respectively.
Of course, the first transistor M1 may be a PMOS transistor or an NMOS transistor, the second transistor M2 may be a PMOS transistor or an NMOS transistor, and this is not limited specifically, fig. 5 only illustrates that the first transistor M1 and the second transistor M2 are both NMOS transistors, fig. 6 only illustrates that the first transistor M1 is an NMOS transistor and the second transistor M2 is a PMOS transistor, and certainly, the enable signal for controlling the second transistor M2 to be turned on is low when the first transistor M1 is a PMOS transistor.
With reference to fig. 4 and 5, the operation process of the pixel circuit 10 includes a data writing frame T0, the data writing frame T0 includes a data writing phase T01 and a light emitting phase T02, in the data writing phase T01, the first transistor M1 is turned on under the control of a high potential of the signal S1 and the second transistor M2 is turned off under the control of a low potential of the signal S2, and the data writing module 3 writes a data signal to the gate of the driving transistor M0; during at least a portion of the light-emitting period T02, the first transistor M1 is turned off under the control of the low level of the signal S1 and the second transistor M2 is turned on under the control of the high level of the signal S2, since the first transistor M1 is turned off, the second transistor M2 and the first capacitor C1 are disposed between the gate and the drain of the driving transistor M0, the second transistor M2 is turned on, due to the arrangement of the first capacitor C1, when the first plate 41 of the first capacitor C1 changes in potential, the second plate of the first capacitor C1 changes correspondingly, therefore, when the drain potential of the driving transistor M0 drops, the potential of the gate of the driving transistor M0 also drops under the action of the first capacitor C1, so that the voltage of the gate of the driving transistor M0 is equal to the voltage of the drain of the driving transistor M0, this reduces the potential difference between the gate and the drain of the driving transistor M0, and the current formula I ═ K (PVDD-Vdata') is set according to the emission period T02.2It is known that, since the first capacitor C1 can pull down the voltage of the gate of the driving transistor M0 to the voltage of the drain of the driving transistor M0, Vdata' is smaller than the predetermined value Vdata, so that the current I in the light-emitting period T02 is increased, thereby compensating the driving current of the driving module 1 and improving the problem of poor brightness maintenance in the light-emitting period T02.
In some alternative embodiments, with continued reference to fig. 5 and 6, the gate potential of the driving transistor M0 is Vg, the drain potential of the driving transistor M0 is Vd, and the potential difference between the gate potential and the drain potential of the driving transistor M0 is Δ V ═ Vg-Vd |;
when the delta V is larger than or equal to V0, the second compensation module 22 is started;
when Δ V < V0, the second compensation module 22 is closed;
v0 is a preset threshold greater than 0.
It is understood that V0 is any preset threshold greater than 0, and is not limited thereto.
In the light emitting period T02, the period when the second compensation module 22 is turned on may be determined according to the potential difference between the gate potential Vg of the driving transistor M0 and the drain potential Vd of the driving transistor M0, specifically, if the potential difference Δ V between the gate potential and the drain potential of the driving transistor M0 is small, that is, when Δ V is less than V0, the driving current does not need to be compensated, so that the second compensation module 22 is not required to be turned on, and when the potential difference Δ V between the gate potential and the drain potential of the driving transistor M0 is large, that is, when Δ V is greater than or equal to V0, the driving current needs to be compensated, and the second compensation module 22 is turned on, so as to improve the problem of luminance maintaining difference in the light emitting period T02.
In some alternative embodiments, with continued reference to fig. 6, the other of the first or second pole of the second transistor M2 is connected to the gate of the driving transistor M0, and the second plate of the first capacitor C1 is connected to the drain of the driving transistor M0.
In fig. 6, the second pole 32 of the second transistor M2 is electrically connected to the first pole plate 41 of the first capacitor C1, the first pole 31 of the second transistor M2 is electrically connected to the gate of the driving transistor M0, and the second pole plate of the first capacitor C1 is electrically connected to the drain of the driving transistor M0. Therefore, during at least a part of the light-emitting period T02, the second transistor M2 is turned on, and the second plate of the first capacitor C1 is electrically connected to the drain of the driving transistor M0, so that when the second plate of the first capacitor C1 changes in potential, the first plate 41 of the first capacitor C1 also changes in potential, and therefore when the drain potential of the driving transistor M0 decreases, the potential of the gate of the driving transistor M0 also decreases under the action of the first capacitor C1, so that the voltage of the gate of the driving transistor M0 is equal to the voltage of the drain of the driving transistor M0, and thus the potential difference between the gate and the drain of the driving transistor M0 is reduced, and the current I of the light-emitting period T02 increases, thereby compensating the driving current of the driving module 1 and improving the problem of poor brightness maintenance of the light-emitting period T02.
In some alternative embodiments, with continued reference to fig. 5, the other of the first pole or the second pole of the second transistor M2 is connected to the drain of the driving transistor M0, and the second pole of the first capacitor C1 is connected to the gate of the driving transistor M0.
In fig. 5, the first electrode 31 of the second transistor M2 is electrically connected to the first plate 41 of the first capacitor C1, the second electrode 32 of the second transistor M2 is electrically connected to the drain of the driving transistor M0, the second plate of the first capacitor C1 is electrically connected to the gate of the driving transistor M0, thus, when the second transistor M2 is turned on and the first plate 41 of the first capacitor C1 is changed in potential, the second plate of the first capacitor C1 is also changed correspondingly, therefore, when the drain potential of the driving transistor M0 drops, the potential of the gate of the driving transistor M0 also drops under the action of the first capacitor C1, so that the voltage of the gate of the driving transistor M0 is equal to the voltage of the drain of the driving transistor M0, thus, by reducing the potential difference between the gate and the drain of the driving transistor M0, the current I during the light emitting period T02 increases, thereby compensating the driving current of the driving module 1 and improving the problem that the brightness is kept poor in the lighting period T02.
In some alternative embodiments, referring to fig. 7 and 8, fig. 7 is a further enlarged view of the pixel unit in fig. 2, fig. 8 is a timing diagram of the pixel circuit in fig. 7, the pixel circuit 10 further includes a light-emitting control module 4, the light-emitting control module 4 is configured to selectively allow the light-emitting element 200 to enter a light-emitting phase T02, and a control terminal of the light-emitting control module 4 receives the light-emitting control signal; wherein the content of the first and second substances,
the gate of the second transistor M2 receives the light emission control signal.
It is understood that the first compensation module 21 and the second compensation module 22 in the present embodiment are applicable to any one of the above embodiments, and are not limited specifically here.
In fig. 7, the light-emitting control module 4 is provided between the first power signal PVDD and the source of the driving transistor M0, but the light-emitting control module 4 may be provided between the drain of the driving transistor M0 and the light-emitting element 200, and the light-emitting element 200 is allowed to enter the light-emitting phase T02 when the light-emitting control module 4 is turned on under the control of the light-emitting control signal, and the light-emitting element 200 does not emit light when the light-emitting control module 4 is turned off under the control of the light-emitting control signal. Alternatively, a transistor may be provided in the light emission control module 4, a source of the transistor being connected to the first power signal PVDD, and a drain of the transistor being connected to the source of the driving transistor M0.
In this embodiment, the gate of the second transistor M2 receives the light-emitting control signal, so when the light-emitting device 200 enters the light-emitting period T02, the light-emitting control signal simultaneously controls the second transistor M2 to be turned on, and the second compensation module 22 simultaneously adjusts the potential difference between the gate and the drain of the driving transistor M0, so that the voltage of the gate of the driving transistor M0 is equal to the voltage of the drain of the driving transistor M0, and thus the current I in the light-emitting period T02 is increased, thereby compensating the driving current of the driving module 1 and improving the problem of poor brightness maintenance in the light-emitting period T02.
In some alternative embodiments, referring to fig. 9 and 10, fig. 9 is a further enlarged view of the pixel unit in fig. 2, fig. 10 is a timing diagram of the pixel circuit in fig. 9, and the light-emitting control module 4 includes a first light-emitting control module 41 and a second light-emitting control module 42;
the first light emission control module 41 is connected between the first power signal PVDD and the source of the driving transistor M0, and the second light emission control module 42 is connected between the drain of the driving transistor M0 and the light emitting element 200; wherein the content of the first and second substances,
a control end of the first light emitting control module 41 receives the first light emitting control signal, and a control end of the second light emitting control module 42 receives the second light emitting control signal;
the gate of the second transistor M2 receives the shorter time length of the active pulse signal of the first and second light-emitting control signals.
It is to be understood that the first compensation module 21 and the second compensation module 22 in this embodiment may adopt the structure in any one of the above embodiments, and are not limited herein.
In the present embodiment, the first light emission control module 41 is connected between the first power signal PVDD and the source of the driving transistor M0, the second light emission control module 42 is connected between the drain of the driving transistor M0 and the light emitting device 200, the first light emission control signal controls the first light emission control module 41 to be turned on, the second light emission control signal controls the second light emission control module 42 to be turned on, the gate of the second transistor M2 receives one of the first light emission control signal and the second light emission control signal, which has a shorter effective pulse signal time length, and fig. 9 illustrates only the second light emission control signal, which has a shorter effective pulse signal time length, received by the gate of the second transistor M2, but of course, the light emission control signal having a shorter effective pulse signal time length determines the light emission time, so the gate of the second transistor M2 receives the one of the first light emission control signal and the second light emission control signal, which has a shorter effective pulse signal time length, therefore, it can be ensured that the current can be compensated when the light emitting element 200 is in the light emitting period T02, on the contrary, if the gate of the second transistor M2 receives the longer one of the effective pulse signal time lengths in the first light emitting control signal and the second light emitting control signal, the part of the light emitting element 200 with the time difference between the effective pulse signals in the first light emitting control signal and the second light emitting control signal is not light emitting, and the current is not adjusted when the second transistor M2 is turned on.
In some alternative embodiments, with continuing reference to fig. 4, fig. 5, fig. 7, fig. 8, fig. 6, and fig. 11, fig. 11 is a timing diagram of the pixel circuit in fig. 6, and the first transistor M1 and the second transistor M2 are both PMOS type transistors or both NMOS type transistors, wherein the control signal of the first transistor M1 and the control signal of the second transistor M2 are reverse timing signals; alternatively, the first and second electrodes may be,
one of the first transistor M1 and the second transistor M2 is a PMOS transistor, and the other is an NMOS transistor, wherein the control signal of the first transistor M1 and the control signal of the second transistor M2 are signals with the same timing.
Fig. 5 shows that the first transistor M1 and the second transistor M2 are both NMOS type transistors, fig. 7 shows that the first transistor M1 and the second transistor M2 are both PMOS type transistors, and fig. 4 and 8 show that the control signal of the first transistor M1 and the control signal of the second transistor M2 are reverse timing signals, so that the second transistor M2 is turned on when the first transistor M1 is turned off, and the second transistor M2 is turned off when the first transistor M1 is turned on; in fig. 6, the first transistor M1 is an NMOS transistor, the second transistor M2 is a PMOS transistor, and certainly, the first transistor M1 may also be a PMOS transistor and the second transistor M2 is an NMOS transistor, which is not limited herein specifically, when one of the first transistor M1 and the second transistor M2 is a PMOS transistor and the other is an NMOS transistor, the control signal of the first transistor M1 and the control signal of the second transistor M2 are signals of the same timing sequence, so that the second transistor M2 is turned on when the first transistor M1 is turned off, and the second transistor M2 is turned off when the first transistor M1 is turned on.
In some alternative embodiments, referring to fig. 12, fig. 12 is a further enlarged view of the pixel unit in fig. 2, the pixel circuit 10 is connected to a first power signal line (not shown) for transmitting a first power signal PVDD at a high level;
the pixel circuit 10 includes a second capacitor C2, the second capacitor C2 is connected between the first power supply signal line and the gate of the driving transistor M0; wherein the content of the first and second substances,
the capacitance value C1 of the first capacitor C1 is smaller than the capacitance value C2 of the second capacitor C2.
It can be understood that the second capacitor C2 is connected between the first power signal line and the gate of the driving transistor M0, the second capacitor C2 is a storage capacitor for maintaining the potential of the gate of the driving transistor M0, the storage capacitor needs to be large enough to maintain the potential of the gate of the driving transistor M0, the first capacitor C1 is used for pulling down the gate of the driving transistor M0 in the lighting phase T02, so that the gate potential of the driving transistor M0 is equal to the drain potential of the driving transistor M0, and a larger capacitance value is not needed for fine tuning, the capacitance value C1 of the first capacitor C1 is smaller than the capacitance value C2 of the second capacitor C2, so that it is ensured that the potential of the gate of the driving transistor M0 is maintained, and the gate potential of the driving transistor M0 and the drain potential of the driving transistor M0 are adjusted in the lighting phase T02.
In some alternative embodiments, referring to fig. 13, fig. 13 is a further enlarged view of the pixel unit in fig. 2, the second compensation module 22 further includes a third transistor M3, one of the first pole 51 or the second pole of the third transistor M3 is connected to the second plate of the first capacitor C1;
the other of the first electrode 31 or the second electrode 32 of the second transistor M2 is connected to the gate of the driving transistor M0, and the other of the first electrode 51 or the second electrode 51 of the third transistor M3 is connected to the drain of the driving transistor M0; alternatively, the first and second electrodes may be,
the other of the first electrode 31 or the second electrode 32 of the second transistor M2 is connected to the drain of the driving transistor M0, and the other of the first electrode 51 or the second electrode 51 of the third transistor M3 is connected to the gate of the driving transistor M0.
In fig. 13, only the first pole 51 of the third transistor M3 is connected to the second pole plate of the first capacitor C1, the first pole 31 of the second transistor M2 is connected to the gate of the driving transistor M0, the second pole 52 of the third transistor M3 is connected to the drain of the driving transistor M0, but it is needless to say that the first pole 51 of the third transistor M3 is connected to the first pole plate 41 of the first capacitor C1, the first pole 51 of the third transistor M3 is connected to the gate of the driving transistor M0, the first pole 31 of the second transistor M2 is connected to the second pole plate of the first capacitor C1, and the second pole 32 of the second transistor M2 is connected to the drain of the driving transistor M0, which is not particularly limited herein.
It can be understood that the second transistor M2 and the third transistor M3 are connected to both sides of the first capacitor C1, so that the problem that when the second transistor M2 is turned off, the potential at one end of the first capacitor C1 floats and the other end floats to cause instability of the circuit can be prevented.
In this embodiment, the two sides of the first capacitor C1 are connected to the second transistor M2 and the third transistor M3, so that when the second transistor M2 and the third transistor M3 are turned on simultaneously, the gate potential of the driving transistor M0 and the drain potential of the driving transistor M0 are adjusted, the second transistor M2 and the third transistor M3 are turned off simultaneously, and the two sides of the first capacitor C1 do not have the problem of floating, which is favorable for improving the stability of the circuit.
In some alternative embodiments, with continued reference to fig. 13, the gate of the second transistor M2 is connected to the same signal as the gate of the third transistor M3.
In this embodiment, referring to fig. 13, the gates of the second transistor M2 and the third transistor M3 are connected to the same signal S2, so that it can be ensured that the second transistor M2 and the third transistor M3 are turned off or turned on simultaneously, when the second transistor M2 and the third transistor M3 are turned on simultaneously, the gate potential of the driving transistor M0 and the drain potential of the driving transistor M0 are adjusted, the second transistor M2 and the third transistor M3 are turned off simultaneously, and both sides of the first capacitor C1 do not have the problem of floating, which is favorable for improving the stability of the circuit.
In some alternative embodiments, referring to fig. 14, fig. 14 is a cross-sectional view taken along line a-a' of fig. 2, only the first capacitor C1 and the second transistor M2 of the pixel circuit 10 are shown in fig. 14, and for other elements of the pixel circuit 10 not shown in fig. 14, the pixel circuit 10 is located on a substrate, and the first capacitor C1 at least partially overlaps the second transistor M2 in a direction perpendicular to the substrate.
Referring to fig. 14, the display panel 1000 includes a substrate base plate 60, a buffer layer 61 on a side of the substrate base plate 60, an active layer 29 on a side of the buffer layer 61 away from the substrate base plate 60, a first metal layer 65 on a side of the active layer 29 away from the substrate base plate 60, a second metal layer 66 on a side of the first metal layer 65 away from the substrate base plate 60, a third metal layer 67 on a side of the second metal layer 66 away from the substrate base plate, a gate of a second transistor M2 is located at the first metal layer 65, a first electrode 31 of the second transistor M2 and a second electrode 32 of the second transistor M2 are located at the third metal layer, in a direction perpendicular to the substrate base plate, the first capacitor C1 and the second transistor M2 at least partially overlap, a portion of the first electrode 31 of the second transistor M2 is reused as a first plate 41 of a first capacitor C1, a second electrode of the first capacitor C1 is located at the second metal layer, and a portion of the first electrode 31 of the second transistor M2 is reused as a first plate 41 of a first capacitor C1, a metal layer is not required to be arranged as the first plate 41 of the first capacitor C1, which is beneficial to realizing the lightness and thinness of the display panel 1000.
Based on the same inventive concept, the present application further provides a display device, and fig. 15 is a schematic diagram of a display device provided in an embodiment of the present application, where the display device 2000 includes a display panel provided in any one of the above embodiments of the present application. When the display device in the present application includes the display panel provided by the above embodiment, the display device has the beneficial effects of the display panel. It should be noted that, for the embodiments of the display device 2000 provided in the embodiments of the present application, reference may be made to the above embodiments of the display panel, and repeated descriptions are omitted. The display device 2000 provided by the present application may be: any product or component with practical functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:
the display panel of the present invention includes: a pixel circuit and a light emitting element; the pixel circuit comprises a driving module, a compensation module and a data writing module; the driving module is used for providing driving current for the light-emitting element and comprises a driving transistor; the data writing module is connected to the source electrode of the driving transistor; the compensation module is connected between the grid electrode and the drain electrode of the driving transistor and comprises a first compensation module and a second compensation module, the first compensation module is connected between the grid electrode and the drain electrode of the driving transistor, and the second compensation module is also connected between the grid electrode and the drain electrode of the driving transistor; the working process of the pixel circuit comprises a data writing frame, the data writing frame comprises a data writing stage and a light emitting stage, in the data writing stage, the driving transistor is conducted, the first compensation module is conducted, data voltage passes through the source electrode, the drain electrode and the first compensation module of the driving transistor, data are written into the grid electrode of the driving transistor, and data compensation is conducted on the grid electrode potential of the driving transistor; in at least partial time period of the light-emitting stage, the first compensation module is closed and the second compensation module is opened, the second compensation module is used for adjusting the potential difference between the grid electrode and the drain electrode of the driving transistor and pulling down the potential of the grid electrode of the driving transistor to the potential of the drain electrode of the driving transistor, so that Vdata' is a value smaller than the preset Vdata, the current I in the light-emitting stage is increased, the driving current of the driving module is compensated, and the problem of poor brightness maintenance in the light-emitting stage is solved.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (14)
1. A display panel, comprising:
a pixel circuit and a light emitting element;
the pixel circuit comprises a driving module, a compensation module and a data writing module;
the driving module is used for providing driving current for the light-emitting element and comprises a driving transistor;
the data writing module is connected to the source electrode of the driving transistor;
the compensation module is connected between the grid electrode and the drain electrode of the driving transistor and comprises a first compensation module and a second compensation module, the first compensation module is connected between the grid electrode and the drain electrode of the driving transistor, and the second compensation module is also connected between the grid electrode and the drain electrode of the driving transistor; wherein the content of the first and second substances,
the working process of the pixel circuit comprises a data writing frame, the data writing frame comprises a data writing stage and a light-emitting stage, in the data writing stage, the first compensation module is started, the second compensation module is closed, and the data writing module writes a data signal into the grid electrode of the driving transistor; and during at least part of the light-emitting period, the first compensation module is switched off and the second compensation module is switched on, and the second compensation module is used for adjusting the potential difference between the grid electrode and the drain electrode of the driving transistor.
2. The display panel according to claim 1,
in one data writing frame, the time length of the first compensation module is shorter than the time length of the second compensation module.
3. The display panel according to claim 1,
the first compensation module comprises a first transistor, the second compensation module comprises a second transistor and a first capacitor, and one of a first pole or a second pole of the second transistor is connected to a first pole plate of the first capacitor.
4. The display panel according to claim 3,
the gate potential of the driving transistor is Vg, the drain potential of the driving transistor is Vd, and the potential difference between the gate potential and the drain potential of the driving transistor is DeltaV |, Vg-Vd |;
when the delta V is larger than or equal to V0, the second compensation module is started;
when Δ V < V0, the second compensation module is closed;
v0 is a preset threshold greater than 0.
5. The display panel according to claim 3,
the other of the first pole or the second pole of the second transistor is connected to the gate of the driving transistor, and the second plate of the first capacitor is connected to the drain of the driving transistor.
6. The display panel according to claim 3,
the other of the first pole or the second pole of the second transistor is connected to the drain of the driving transistor, and the second pole of the first capacitor is connected to the gate of the driving transistor.
7. The display panel according to claim 3,
the pixel circuit further comprises a light-emitting control module, wherein the light-emitting control module is used for selectively allowing the light-emitting element to enter a light-emitting stage, and a control end of the light-emitting control module receives and transmits a light-emitting control signal; wherein the content of the first and second substances,
the gate of the second transistor receives the light emission control signal.
8. The display panel according to claim 7,
the light-emitting control module comprises a first light-emitting control module and a second light-emitting control module;
the first light-emitting control module is connected between a first power signal and the source electrode of the driving transistor, and the second light-emitting control module is connected between the drain electrode of the driving transistor and the light-emitting element; wherein the content of the first and second substances,
the control end of the first light-emitting control module receives a first light-emitting control signal, and the control end of the second light-emitting control module receives a second light-emitting control signal;
the gate of the second transistor receives one of the first and second light emission control signals, which has a shorter effective pulse signal time length.
9. The display panel according to claim 3,
the first transistor and the second transistor are both PMOS type transistors or both NMOS type transistors, wherein a control signal of the first transistor and a control signal of the second transistor are reverse time sequence signals; alternatively, the first and second electrodes may be,
one of the first transistor and the second transistor is a PMOS type transistor, and the other is an NMOS type transistor, wherein a control signal of the first transistor and a control signal of the second transistor are signals of the same timing sequence.
10. The display panel according to claim 3,
the pixel circuit is connected to a first power supply signal line for transmitting a first power supply signal of a high level;
the pixel circuit includes a second capacitance connected between the first power supply signal line and the gate of the driving transistor; wherein the content of the first and second substances,
the capacitance value C1 of the first capacitor is less than the capacitance value C2 of the second capacitor.
11. The display panel according to claim 3,
the second compensation module further comprises a third transistor, and one of a first pole or a second pole of the third transistor is connected to the second plate of the first capacitor;
the other of the first pole or the second pole of the second transistor is connected to the grid electrode of the driving transistor, and the other of the first pole or the second pole of the third transistor is connected to the drain electrode of the driving transistor; alternatively, the first and second electrodes may be,
the other of the first pole or the second pole of the second transistor is connected to the drain of the driving transistor, and the other of the first pole or the second pole of the third transistor is connected to the gate of the driving transistor.
12. The display panel according to claim 11,
the gate of the second transistor and the gate of the third transistor are connected to the same signal.
13. The display panel according to claim 3,
the pixel circuit is located on the substrate base plate, and the first capacitor and the second transistor at least partially overlap in a direction perpendicular to the substrate base plate.
14. A display device characterized by comprising the display panel according to any one of claims 1 to 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111362006.XA CN114023261B (en) | 2021-11-17 | 2021-11-17 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111362006.XA CN114023261B (en) | 2021-11-17 | 2021-11-17 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114023261A true CN114023261A (en) | 2022-02-08 |
| CN114023261B CN114023261B (en) | 2023-01-31 |
Family
ID=80064681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111362006.XA Active CN114023261B (en) | 2021-11-17 | 2021-11-17 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114023261B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023231130A1 (en) * | 2022-05-31 | 2023-12-07 | Tcl华星光电技术有限公司 | Pixel drive circuit and display panel |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009210993A (en) * | 2008-03-06 | 2009-09-17 | Toshiba Mobile Display Co Ltd | El display device |
| KR20170007574A (en) * | 2015-07-08 | 2017-01-19 | 엘지디스플레이 주식회사 | OLED driving current compensation circuit and Organic Light Emitting Display device comprising the same |
| CN110610683A (en) * | 2019-09-27 | 2019-12-24 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| CN111048041A (en) * | 2020-01-02 | 2020-04-21 | 武汉天马微电子有限公司 | Pixel circuit, driving method thereof, display panel and display device |
| CN111640397A (en) * | 2020-05-29 | 2020-09-08 | 昆山国显光电有限公司 | Pixel circuit, display panel and display device |
| CN112133242A (en) * | 2020-10-15 | 2020-12-25 | 厦门天马微电子有限公司 | Display panel, driving method thereof and display device |
| CN112331134A (en) * | 2020-10-23 | 2021-02-05 | 厦门天马微电子有限公司 | Display panel and display device |
| US20210183310A1 (en) * | 2019-03-11 | 2021-06-17 | Hefei Boe Display Technology Co., Ltd. | Pixel circuit, display panel, display device and pixel driving method |
| US11087685B1 (en) * | 2020-07-10 | 2021-08-10 | Sharp Kabushiki Kaisha | Fast data programming TFT pixel threshold voltage compensation circuit with two phase threshold compensation |
-
2021
- 2021-11-17 CN CN202111362006.XA patent/CN114023261B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009210993A (en) * | 2008-03-06 | 2009-09-17 | Toshiba Mobile Display Co Ltd | El display device |
| KR20170007574A (en) * | 2015-07-08 | 2017-01-19 | 엘지디스플레이 주식회사 | OLED driving current compensation circuit and Organic Light Emitting Display device comprising the same |
| US20210183310A1 (en) * | 2019-03-11 | 2021-06-17 | Hefei Boe Display Technology Co., Ltd. | Pixel circuit, display panel, display device and pixel driving method |
| CN110610683A (en) * | 2019-09-27 | 2019-12-24 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| CN111048041A (en) * | 2020-01-02 | 2020-04-21 | 武汉天马微电子有限公司 | Pixel circuit, driving method thereof, display panel and display device |
| CN111640397A (en) * | 2020-05-29 | 2020-09-08 | 昆山国显光电有限公司 | Pixel circuit, display panel and display device |
| US11087685B1 (en) * | 2020-07-10 | 2021-08-10 | Sharp Kabushiki Kaisha | Fast data programming TFT pixel threshold voltage compensation circuit with two phase threshold compensation |
| CN112133242A (en) * | 2020-10-15 | 2020-12-25 | 厦门天马微电子有限公司 | Display panel, driving method thereof and display device |
| CN112331134A (en) * | 2020-10-23 | 2021-02-05 | 厦门天马微电子有限公司 | Display panel and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023231130A1 (en) * | 2022-05-31 | 2023-12-07 | Tcl华星光电技术有限公司 | Pixel drive circuit and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114023261B (en) | 2023-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108206008B (en) | Pixel circuit, driving method, electroluminescent display panel and display device | |
| US11887533B2 (en) | Display panel, integrated chip and display device | |
| US20230178018A1 (en) | Display device, driving method for display device and electronic apparatus | |
| CN104871233B (en) | Display device, method for driving the same, and electronic apparatus | |
| US10984711B2 (en) | Pixel driving circuit, display panel and driving method | |
| US20100141626A1 (en) | Display device, driving method for display device, and electronic apparatus | |
| US8207918B2 (en) | Image display device having a set period during which a step signal is supplied at different levels to provide a uniform display | |
| TWI389081B (en) | Display device, driving method of the same and electronic equipment having the same | |
| US11568815B2 (en) | Pixel driving circuit, manufacturing method thereof, and display device | |
| WO2023093103A1 (en) | Pixel circuit and driving method thereof, and display panel | |
| WO2020100616A1 (en) | Pixel circuit, display device, drive method for pixel circuit, and electronic device | |
| US20230230547A1 (en) | Display panel and display device | |
| JP7090412B2 (en) | Pixel circuits, display devices, pixel circuit drive methods and electronic devices | |
| JPWO2019159651A1 (en) | Pixel circuits, display devices, pixel circuit drive methods and electronic devices | |
| CN114627817A (en) | Pixel circuit, pixel driving method and display device | |
| CN114093319A (en) | Pixel compensation circuit, pixel driving method and display device | |
| CN114023261B (en) | Display panel and display device | |
| CN113192458B (en) | Pixel circuit, driving method thereof and display panel | |
| WO2020173003A1 (en) | Display driving circuit and display driving method | |
| CN115294940A (en) | Pixel circuit, driving method thereof and display panel | |
| US11688338B2 (en) | Display device, luminance compensation circuit thereof and luminance compensation method | |
| CN114203109A (en) | Pixel driving circuit, compensation method thereof and display panel | |
| WO2022124165A1 (en) | Display device | |
| JP5342193B2 (en) | Image display device | |
| US20140218270A1 (en) | Display device, driving method of display device, and electronic apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |