WO2022124165A1 - Display device - Google Patents

Display device Download PDF

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Publication number
WO2022124165A1
WO2022124165A1 PCT/JP2021/044153 JP2021044153W WO2022124165A1 WO 2022124165 A1 WO2022124165 A1 WO 2022124165A1 JP 2021044153 W JP2021044153 W JP 2021044153W WO 2022124165 A1 WO2022124165 A1 WO 2022124165A1
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WO
WIPO (PCT)
Prior art keywords
voltage
transistor
display device
signal
light emitting
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Application number
PCT/JP2021/044153
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French (fr)
Japanese (ja)
Inventor
尚司 豊田
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
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Priority to JP2022568219A priority Critical patent/JPWO2022124165A1/ja
Publication of WO2022124165A1 publication Critical patent/WO2022124165A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the embodiment according to the present disclosure relates to a display device.
  • the voltage of the main power supply is being lowered for the purpose of lowering power consumption.
  • the amplitude of the signal voltage Vsig cannot be sufficiently increased, and the maximum brightness of the light emitting unit may be limited.
  • a display device capable of improving the brightness is provided.
  • the pixel array section where the pixel circuit is arranged and A drive circuit for driving the pixel array unit is provided.
  • the pixel circuit is A light emitting element that emits light with brightness according to the current flowing from the anode to the cathode, A drive transistor that drives the light emitting element based on the written signal voltage, A sampling transistor that samples the signal voltage written to the drive transistor, It has an anode voltage control unit that makes the anode voltage of the light emitting element higher than the cathode voltage of the light emitting element during the signal voltage writing period in which the sampling transistor is turned on and the signal voltage is written to the drive transistor.
  • a display device is provided.
  • the anode voltage control unit has a first switching transistor that is turned on within the signal voltage writing period to set the anode voltage of the light emitting element to a reference voltage.
  • the reference voltage may transition from the first voltage to a second voltage higher than the cathode voltage in accordance with the timing at which the sampling transistor is turned on.
  • the drive circuit may have a reference voltage control unit that controls the voltage value of the reference voltage so that the voltage value of the reference voltage becomes higher than the cathode voltage at least during the signal voltage writing period.
  • the reference voltage control unit may generate a pulse voltage whose voltage level is higher than the cathode voltage during the signal voltage writing period and output it to the reference voltage.
  • the reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then from the second voltage at the timing when the sampling transistor is turned off. It may transition to the first voltage.
  • the reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then the second voltage at the timing when the light emitting of the light emitting element is stopped. May transition to the first voltage.
  • the drive transistor, the sampling transistor, and the first switching transistor may be P-channel type transistors.
  • the drive transistor, the sampling transistor, and the first switching transistor may be N-channel type transistors.
  • the anode voltage control unit may make the anode voltage substantially the same as the cathode voltage during a predetermined period before the signal voltage writing period is started.
  • the pixel circuit may further include a second switching transistor for diode-connecting the drive transistor in a predetermined period before the signal voltage writing period is started.
  • the predetermined period may be a period in which the gate-source voltage of the drive transistor is set to a voltage corresponding to the threshold voltage of the drive transistor.
  • the light emitting element may emit light with a brightness corresponding to the current flowing through the drive transistor based on the signal voltage.
  • the display device of the present disclosure is a flat panel type display device in which a sampling transistor and a pixel circuit having a holding capacity are arranged in addition to a drive transistor for driving a light emitting unit.
  • the flat display device include an organic EL display device, a liquid crystal display device, and a plasma display device.
  • the organic EL display device uses electroluminescence of an organic material and uses an organic EL element that emits light when an electric field is applied to an organic thin film as a pixel light emitting element (electro-optical element). ing.
  • An organic EL display device that uses an organic EL element as the light emitting part of a pixel has the following features. Since the organic EL element is a self-luminous element, the organic EL display device has higher image visibility than the liquid crystal display device, which is the same flat display device, and is a lighting member such as a backlight. It is easy to reduce the weight and thickness because it does not require. Further, since the response speed of the organic EL element is as high as several microseconds, the organic EL display device does not generate an afterimage when displaying a moving image.
  • the organic EL element is a self-luminous element and a current-driven electro-optical element.
  • Examples of the current-driven electro-optical element include an inorganic EL element, an LED element, a semiconductor laser element, and the like, in addition to the organic EL element.
  • a flat display device such as an organic EL display device can be used as a display unit (display device) in various electronic devices provided with a display unit.
  • Various electronic devices include television systems, head-mounted displays, digital cameras, video cameras, game machines, notebook personal computers, mobile information devices such as electronic books, PDA (Personal Digital Assistant), mobile phones, etc.
  • a mobile communication device or the like can be exemplified.
  • the drive unit may be configured so that the gate node of the drive transistor is in a floating state and then the source node is in a floating state. Further, the drive unit may be configured to write the signal voltage by the sampling transistor while keeping the source node of the drive transistor in the floating state.
  • the initialization voltage may be supplied to the signal line at a timing different from the signal voltage, and may be written from the signal line to the gate node of the drive transistor by sampling by the sampling transistor.
  • the pixel circuit can be configured to be formed on a semiconductor such as silicon.
  • the drive transistor may be configured to consist of a P-channel type transistor. The reason why the P-channel type transistor is used as the drive transistor instead of the N-channel type transistor is as follows.
  • the transistor When a transistor is formed on a semiconductor such as silicon rather than on an insulator such as a glass substrate, the transistor is not a source / gate / drain terminal but a source / gate / drain / backgate (base). It has 4 terminals.
  • the back gate (board) voltage becomes 0 V, which adversely affects the operation of correcting the variation of the threshold voltage of the drive transistor for each pixel.
  • the variation in the characteristics of the transistor is smaller in the P-channel type transistor having no LDD region than in the N-channel type transistor having the LDD (Lightly Doped Drain) region, and the pixel miniaturization and eventually the display device. It is advantageous for achieving high definition. For this reason, when it is assumed that the transistor is formed on a semiconductor such as silicon, it is preferable to use a P-channel transistor instead of an N-channel transistor as the drive transistor.
  • the sampling transistor may also be configured to include a P-channel type transistor.
  • the pixel circuit may be configured to have a light emission control transistor for controlling light emission / non-light emission of the light emitting unit.
  • the light emission control transistor may also be configured to consist of a P-channel type transistor.
  • the holding capacity may be configured to be connected between the gate node and the source node of the drive transistor.
  • the pixel circuit can be configured to have an auxiliary capacitance connected between the source node of the drive transistor and the node of the fixed potential.
  • the pixel circuit may have a configuration having a switching transistor connected between the drain node of the drive transistor and the anode node of the light emitting unit.
  • the switching transistor may also be configured to consist of a P-channel type transistor.
  • the drive unit may be configured to have the switching transistor in a conductive state during the non-light emission period of the light emitting unit.
  • the drive unit activates the signal for driving the switching transistor before the sampling timing of the initialization voltage by the sampling transistor. Then, the signal for driving the light emission control transistor can be activated and then inactive. At this time, the drive unit may be configured to complete the sampling of the initialization voltage by the sampling transistor before the signal for driving the light emission control transistor is inactive.
  • FIG. 1 is an explanatory diagram showing an example of the configuration of the display device 100 according to the first embodiment of the present disclosure.
  • FIG. 1 is an explanatory diagram showing an example of the configuration of the display device 100 according to the first embodiment of the present disclosure.
  • an example of the configuration of the display device 100 according to the first embodiment of the present disclosure will be described with reference to FIG.
  • the pixel unit 110 has a configuration in which pixels provided with organic EL elements and other self-luminous elements are arranged in a matrix.
  • the pixel unit 110 is provided with scanning lines in the horizontal direction in line units with respect to the pixels arranged in a matrix, and signal lines SL are provided for each row so as to be orthogonal to the scanning lines.
  • the horizontal selector 120 sequentially transfers a predetermined sampling pulse, and sequentially latches the image data with this sampling pulse, thereby distributing the image data to each signal line SL. Further, the horizontal selector 120 performs analog digital conversion processing on the image data distributed to each signal line SL, thereby generating a drive signal indicating the emission luminance of each pixel connected to each signal line SL by time division. The horizontal selector 120 outputs this drive signal to the corresponding signal line SL.
  • the vertical scanner 130 responds to the driving of the signal line SL by the horizontal selector 120, generates a driving signal for each pixel, and outputs the driving signal to the scanning line SCN.
  • the display device 100 sequentially drives each pixel arranged in the pixel unit 110 by the vertical scanner 130, causes each pixel to emit light at the signal level of each signal line SL set by the horizontal selector 120, and produces a desired image. It is displayed by the pixel unit 110.
  • FIG. 2 is an explanatory diagram showing an example of a more detailed configuration of the display device 100 according to the first embodiment of the present disclosure.
  • FIG. 2 is an explanatory diagram showing an example of a more detailed configuration of the display device 100 according to the first embodiment of the present disclosure.
  • an example of the configuration of the display device 100 according to the first embodiment of the present disclosure will be described with reference to FIG.
  • a pixel 111R displaying red, a pixel 111G displaying green, and a pixel 111B displaying blue are arranged in a matrix.
  • the vertical scanner 130 includes an auto-zero scanner 131, a drive scanner 132, and a write scanner 133. By supplying a signal from each scanner to the pixels arranged in a matrix in the pixel unit 110, the TFTs provided in the respective pixels are turned on and off.
  • the vertical scanner 130 further has a VSS2 scanner (reference voltage control unit) 134.
  • the VSS2 scanner 134 generates, for example, a control voltage signal and supplies the control voltage signal to the pixels arranged in a matrix in the pixel unit 110. More specifically, the VSS2 scanner 134 supplies the control voltage signal to the feeder line of the reference voltage. That is, the VSS2 scanner 134 outputs a control voltage signal in the same manner as the signal outputs of the auto zero scanner 131, the drive scanner 132, and the write scanner 133.
  • the anode potential (anode voltage) of the organic EL element is controlled when the signal voltage Vsig is written, as will be described later. Can be done. As a result, the emission brightness of the organic EL element EL can be improved.
  • FIG. 3 is an explanatory diagram showing an example of a more detailed configuration of the display device 100 according to the first embodiment of the present disclosure.
  • FIG. 3 is an explanatory diagram showing an example of a more detailed configuration of the display device 100 according to the first embodiment of the present disclosure.
  • an example of the configuration of the display device 100 according to the first embodiment of the present disclosure will be described with reference to FIG.
  • FIG. 3 illustrates a pixel circuit for one pixel arranged in a matrix in the pixel unit 110.
  • the pixel circuit includes transistors T1 to T3, an anode potential control unit (anode voltage control unit) 112, capacitors C1 and C2, and an organic EL element EL.
  • the anode potential control unit 112 includes, for example, the transistor T4.
  • FIG. 4 is an explanatory diagram showing the pixel circuit shown in FIG. 3 extracted.
  • Transistor T1 is a light emission control transistor that controls light emission of the organic EL element EL.
  • the transistor T1 is connected between the power supply node of the power supply voltage VCCP and the source node (source electrode) of the transistor T2, and is driven by a light emission control signal (signal DS) output from the drive scanner 132, and is an organic EL. Controls the light emission / non-light emission of the element EL.
  • the transistor T2 is a drive transistor that drives the organic EL element EL by passing a drive current corresponding to the holding voltage of the capacitor C2 through the organic EL element EL.
  • the transistor T2 is connected between the anode of the organic EL element EL and the power supply node of the power supply voltage VCCP, and controls the current flowing through the organic EL element EL based on the signal voltage Vsig. Further, the organic EL element EL emits light with brightness corresponding to the current flowing from the anode to the cathode. More specifically, the organic EL element EL emits light with a brightness corresponding to the current flowing through the transistor T2 based on the signal voltage Vsig. As shown in FIG. 4, the transistor T2 has a parasitic capacitance Cp between the gate and the drain.
  • the transistor T3 is a sampling transistor that writes the signal voltage Vsig to the gate node (gate electrode) of the transistor T2 by sampling the signal voltage Vsig under the drive by the drive signal (signal WS) supplied from the write scanner 133. be.
  • the transistor T3 is connected between the gate of the transistor T2 and the signal line SL.
  • the transistor T4 is a first switching transistor connected between the drain node (drain electrode) of the transistor T2 and the current discharge destination node (for example, the power supply VSS2).
  • the transistor T4 is controlled so that the organic EL element EL does not emit light during the non-emission period of the organic EL element EL under the drive by the drive signal (signal AZ) from the auto-zero scanner 131.
  • the control voltage generated by the VSS2 scanner 134 is supplied to the feeder line of the power supply VSS2.
  • the transistors T1 to T4 can all be configured to be composed of P-channel type transistors.
  • the capacitor C2 is connected between the gate node and the source node of the transistor T2, and holds the signal voltage Vsig written by sampling by the transistor T3.
  • the capacitor C1 is connected between the source node of the transistor T2 and the node of a fixed potential (for example, the power supply node of the power supply voltage VCCP).
  • the capacitor C1 suppresses the fluctuation of the source voltage of the transistor T2 when the signal voltage Vsig is written, and also acts to change the gate-source voltage Vgs of the transistor T2 to the threshold voltage Vth of the transistor T2.
  • a pixel portion 110, a horizontal selector 120, a vertical scanner 130, and the like are collectively formed on a transparent insulating substrate made of a glass substrate or the like using a polysilicon TFT.
  • Polysilicon TFTs cannot avoid variations in threshold voltage or mobility, and in display devices using organic EL elements, there is a problem that image quality deteriorates due to these variations.
  • the anode potential control unit 112 having the transistor T4 makes the anode potential Band of the organic EL element EL substantially the same as the cathode potential Vcat in a predetermined period before the signal voltage writing period is started.
  • the predetermined period is a period for correcting variations in the threshold voltage and mobility of the drive transistor.
  • the anode potential control unit 112 sets the anode potential Vand of the organic EL element EL higher than the cathode potential Vcat of the organic EL element EL during the signal voltage writing period in which the transistor T3 is turned on and the signal voltage Vsig is written to the transistor T2. do.
  • the transistor T4 is turned on, for example, within the signal voltage writing period, and the anode potential Band of the organic EL element EL is set to the power supply VSS2.
  • the VSS2 scanner 134 controls the voltage value of the power supply VSS2 so that the voltage value of the power supply VSS2 becomes higher than the cathode potential Vcat at least during the signal voltage writing period. As a result, as described with reference to FIG. 5, the emission brightness of the organic EL element EL can be improved.
  • the correction of the characteristic variation of the driving transistor and the operation of writing the signal voltage Vsig will be described.
  • the operation of changing the voltage value of the power supply VSS2 by the VSS2 scanner 134 will also be described.
  • FIG. 5 is an explanatory diagram showing an example of a driving method of the display device 100 according to the first embodiment of the present disclosure.
  • FIG. 5 shows the temporal transition of the source potential Vs, the gate potential Vg and the drain potential Vd of the transistor T2, and the anode potential Vand and the cathode potential (cathode voltage) Vcat of the organic EL element EL.
  • the anode potential Vand is substantially the same as the drain potential Vd.
  • FIG. 5 also shows the temporal transition of the control signal voltage supplied from the VSS2 scanner 134 to the power supply VSS2, the signal DS from the drive scanner 132, the signal WS from the write scanner 133, and the signal AZ from the auto-zero scanner 131. Has been done.
  • time t1 is, for example, the timing at which the quenching period ends and the writing period of one horizontal line (1H) begins.
  • the signal AZ is low and the transistor T4 is on. This is to prevent the organic EL element EL from emitting light due to a current flowing into the organic EL element EL during the Vth correction period described later.
  • the transistors T1 and T3 are turned on by changing the signals WS and DS from high to low.
  • the preparation period for correcting the threshold voltage Vth of the transistor T2 is entered.
  • the gate potential Vg of the transistor T2 drops to the offset voltage Vofs.
  • the transistor T3 is turned off when the signal WS changes from low to high.
  • the transistor T1 is turned off when the signal DS changes from low to high.
  • the Vth correction period is entered.
  • the gate-source voltage Vgs of the transistor T2 is set to the threshold voltage Vth.
  • the transistor T3 is turned on by changing the signal WS from high to low.
  • the writing period of the signal voltage Vsig to the transistor T2 is set.
  • the gate potential Vg of the transistor T2 becomes Vsig.
  • the voltage value of the power supply VSS2 becomes large. More specifically, the voltage value of the power supply VSS2 before the time t5 is substantially the same as, for example, the cathode potential Vcat. Therefore, it is possible to suppress the flow of unnecessary current during the Vth correction period or the like.
  • the voltage value of the power supply VSS2 becomes larger than, for example, the cathode potential Vcat. As a result, the drain potential Vd increases via the transistor T4 in the on state.
  • the VSS2 scanner 134 generates, for example, a pulse voltage whose voltage level increases during the period from time t5 to time t7 as a control voltage signal, and outputs the pulse voltage to the power supply VSS2 for each horizontal line (1H).
  • the voltage value of the power supply VSS2 transitions from the first voltage to the second voltage higher than the cathode potential Vcat at the timing when the transistor T3 is turned on.
  • the transistor T3 is turned off when the signal WS changes from low to high.
  • the writing period of the signal voltage Vsig to the transistor T2 ends.
  • the transistor T4 is turned off when the signal AZ changes from low to high between the time t6 and the time t7.
  • the transistor T1 is turned on by changing the signal DS from high to low.
  • the organic EL element EL emits light.
  • the source potential Vs of the transistor T2 becomes the power supply voltage VCCP.
  • the voltage value of the power supply VSS2 becomes smaller.
  • the voltage value of the power supply VSS2 at time t7 is a voltage value before time t5, and is substantially the same as, for example, the cathode potential Vcat. That is, the voltage value of the power supply VSS2 transitions from the second voltage to the first voltage at time t7.
  • the period from time t8 to time t9 is a light emission transition period.
  • a current flows through the organic EL element EL, and the potential difference Vold between the anode potential Vand and the cathode potential Vcat gradually widens due to the IV characteristics of the organic EL element EL. Since the cathode potential Vcat is fixed, the anode potential Vand and the drain potential Vd substantially the same as the anode potential Vd gradually increase. After that, at time t9, the drain potential Vd stabilizes.
  • the gate potential Vg also increases as the drain potential Vd increases from time t8 to time t9.
  • the source potential Vs is fixed to the power supply voltage VCCP. Therefore, from time t8 to time t9, the gate-source voltage Vgs is gradually compressed.
  • the gate potential Vg is set to the signal voltage Vsig. Therefore, even if the drain potential Vd rises due to the increase in the voltage value of the power supply VSS2, the influence on the gate potential Vg via the parasitic capacitance Cp is small.
  • the drain potential Vd can be increased by increasing the voltage value of the power supply VSS2 during the writing period of the signal voltage Vsig from the time t5 to the time t6.
  • the compression amount of the gate-source voltage Vgs in the period from the time t8 to the time t9 can be suppressed. That is, the gate-source voltage Vgs at the time of light emission after the time t9 can be increased, and the current flowing through the transistor T2 can be increased.
  • the emission brightness of the organic EL element EL can be improved.
  • FIG. 6 is an explanatory diagram showing an example of a more detailed configuration of the display device 100 according to the comparative example of the present disclosure.
  • the comparative example is different from the first embodiment in that the VSS2 scanner 134 is not provided and the fixed voltage power supply VSS is connected to the drain of the transistor T4 instead of the power supply VSS2 having a variable voltage value. ing.
  • FIG. 7 is an explanatory diagram showing an example of a driving method of the display device 100 according to the comparative example of the present disclosure.
  • the voltage value of the power supply VSS is substantially constant (DC (Direct Current)). Therefore, the drain potential Vd is substantially constant during the writing period of the signal voltage Vsig from the time t5 to the time t6.
  • the voltage value of the power supply VSS is, for example, substantially the same as the cathode potential Vcat of the organic EL element EL.
  • the drain potential Vd shown in FIG. 7 of the comparative example is smaller than the drain potential Vd shown in FIG. 5 of the first embodiment in which the voltage value of the power supply VSS2 fluctuates (AC (Alternating Current)). Therefore, in the period from time t8 to time t9, the increase value of the drain potential Vd in the comparative example is larger than the increase value of the drain potential Vd in the first embodiment. That is, in the comparative example, the increase value of the gate potential Vg via the parasitic capacitance Cp is large, and the compression amount of the gate-source voltage Vgs is large. As a result, at time t9, the gate-source voltage Vgs shown in FIG. 7 of the comparative example is smaller than the gate-source voltage Vgs shown in FIG. 5 of the first embodiment.
  • the voltage of the main power supply has been reduced for the purpose of reducing power consumption.
  • the amplitude of the signal voltage Vsig cannot be sufficiently increased, and the maximum brightness may be limited.
  • the parasitic capacitance Cp compresses the gate-source voltage Vgs at the time of light emission at time t9. The smaller the amplitude of the signal voltage Vsig, the greater the effect of compression of the gate-source voltage Vgs. As a result, the maximum brightness may be further limited.
  • the amount of increase in the anode potential Vand due to the parasitic capacitance Cp during the light emission transition period is suppressed. can do. That is, it is possible to suppress the amount of compression of the gate-source voltage Vgs due to the parasitic capacitance Cp during the light emission transition period.
  • the gate-source voltage Vgs at the time of light emission can be increased, and the light emission brightness can be improved.
  • the emission brightness can be improved without increasing the amplitude of the signal voltage Vsig. That is, it is possible to suppress the limitation of the maximum luminance due to the small amplitude of the signal voltage Vsig.
  • FIG. 8 is an explanatory diagram showing a first modification of the driving method of the display device 100 according to the first embodiment of the present disclosure.
  • the first modification is different from the first embodiment in that the timing at which the voltage value of the power supply VSS2 becomes small is before the time t7.
  • the voltage value of the power supply VSS2 becomes smaller at time t6, and becomes substantially the same as, for example, the cathode potential Vcat. Therefore, the width of the pulse voltage of the power supply VSS2 is the period from the time t5 to the time t6.
  • the width of the pulse voltage of the power supply VSS corresponds to, for example, the period during which the signal WS becomes low due to the writing of the signal voltage Vsig. That is, the voltage value of the power supply VSS2 transitions from the first voltage to the second voltage according to the timing when the transistor T3 is turned on, and then from the second voltage to the first voltage according to the timing when the transistor T3 is turned off. Transition to the voltage of.
  • the voltage value of the power supply VSS2 is preferably larger than the cathode potential Vcat, at least during the period when the signal WS is low.
  • FIG. 9 is an explanatory diagram showing a second modification of the driving method of the display device 100 according to the first embodiment of the present disclosure.
  • the second modification is different from the first embodiment in that the timing at which the voltage value of the power supply VSS2 becomes small is after the time t7.
  • the voltage value of the power supply VSS2 becomes smaller at time t10, and becomes substantially the same as, for example, the cathode potential Vcat.
  • Time t10 is the timing at which the light emission period ends and the quenching period begins. That is, the voltage value of the power supply VSS2 transitions from the first voltage to the second voltage according to the timing when the transistor T3 is turned on, and then the second voltage is matched with the timing when the light emission of the organic EL element EL is stopped. The transition from the voltage to the first voltage.
  • the timing at which the voltage value of the power supply VSS2 becomes small is not limited to the solid line shown in FIG. 9, and may be within the period from time t9 to time t10, for example, as shown by the broken line.
  • the timing at which the voltage value of the power supply VSS2 decreases is, for example, any of the time t6 from the time when the signal WS becomes high to t10 which is the start of the quenching period.
  • the timing is fine.
  • FIG. 10 is an explanatory diagram showing an example of the configuration of the pixel circuit according to the second embodiment of the present disclosure.
  • the pixel circuit has a so-called "4Tr1C" configuration as compared with FIG.
  • the capacitor C1 is not provided.
  • the transistors T1 to T4 shown in FIG. 11 are N-channel type transistors.
  • the voltage value of the power supply VSS2 becomes higher than the cathode potential Vcat during the writing period of the signal voltage Vsig. Therefore, the emission brightness can be improved as in the first embodiment.
  • FIG. 11 is an explanatory diagram showing an example of the configuration of the pixel circuit according to the third embodiment of the present disclosure.
  • the pixel circuit has a so-called “5Tr” configuration as compared with FIG.
  • the capacitor C1 is not provided.
  • the transistor T1 which is a light emission control transistor is connected not between the power supply voltage VCCP and the source of the transistor T2 but between the drain of the transistor T2 and the anode of the organic EL element EL.
  • the pixel circuit further has a transistor T5.
  • the transistor T5 is connected between the drain and the gate of the transistor T2.
  • the transistor T5 is a threshold value compensating transistor that compensates for the threshold value of the transistor T2.
  • the transistor T5 is turned on in a predetermined period before the write period of the signal voltage Vsig. That is, the transistor T5 is a second switching transistor in which the gate and drain of the transistor T2 are connected and the transistor T2 is connected by a diode during the compensation period for compensating the threshold value of the transistor T2.
  • the capacitor C2 holds the threshold voltage of the transistor T2.
  • the voltage value of the power supply VSS2 becomes higher than the cathode potential Vcat during the writing period of the signal voltage Vsig. Therefore, the emission brightness can be improved as in the first embodiment.
  • FIG. 12 is an explanatory diagram showing an example of the configuration of the pixel circuit according to the fourth embodiment of the present disclosure.
  • the pixel circuit has a so-called "6Tr" configuration as compared with FIG.
  • the fourth embodiment shown in FIG. 12 is also a modification of the third embodiment shown in FIG.
  • the signal line SL shown in FIG. 12 has a signal line SL1 and a plurality of signal lines SL2 as compared with FIG. Further, the pixel circuit further includes a transistor T6 and capacitors C3 and C4.
  • a plurality of signal lines SL2 are provided for one signal line SL1.
  • Each of the plurality of signal lines SL2 is electrically connected to the signal line SL1.
  • Each of the plurality of signal lines SL2 is electrically connected to the plurality of pixels 111. That is, one signal line SL1 is shared by a plurality of signal lines SL2, and one signal line SL2 is shared by a plurality of pixels 111. Thereby, the signal line SL2 can be made shorter than the signal line when connected to all the pixels 111.
  • the compensation operation for compensating for the threshold value of the transistor T2 the time required for charging or discharging the parasitic capacitance of the signal line SL2 can be shortened. Therefore, in the fourth embodiment, the compensation period for compensating the threshold value of the transistor T2 can be shortened as compared with the third embodiment.
  • a plurality of transistors T6 are provided for each signal line SL2 corresponding to the signal line SL2.
  • the plurality of transistors T6 are connected between the signal line SL1 and each of the plurality of signal lines SL2.
  • the transistor T6 is a switching transistor that controls the connection between the signal line SL1 and the signal line SL2.
  • a plurality of capacitors C3 are provided for each signal line SL2 corresponding to the signal line SL2.
  • the plurality of capacitors C3 are connected between the signal line SL1 and each of the plurality of signal lines SL2.
  • the capacitor C4 is connected between the signal line SL1 and the power supply VSS2.
  • the capacitor C4 holds the potential of the signal line SL1.
  • the capacitor C4 is formed, for example, by a parasitic capacitance between a signal line SL1 adjacent to each other and a feeder line of the power supply VSS2.
  • the voltage value of the power supply VSS2 becomes higher than the cathode potential Vcat during the writing period of the signal voltage Vsig. Therefore, the emission brightness can be improved as in the first embodiment.
  • the present technology can have the following configurations.
  • a pixel array unit in which a pixel circuit is arranged and A drive circuit for driving the pixel array unit is provided.
  • the pixel circuit is A light emitting element that emits light with brightness according to the current flowing from the anode to the cathode, A drive transistor that drives the light emitting element based on the written signal voltage, A sampling transistor that samples the signal voltage written to the drive transistor, It has an anode voltage control unit that makes the anode voltage of the light emitting element higher than the cathode voltage of the light emitting element during the signal voltage writing period in which the sampling transistor is turned on and the signal voltage is written to the drive transistor. , Display device.
  • the anode voltage control unit has a first switching transistor that is turned on within the signal voltage writing period to set the anode voltage of the light emitting element to the reference voltage.
  • the drive circuit has a reference voltage control unit that controls the voltage value of the reference voltage so that the voltage value of the reference voltage becomes higher than the cathode voltage at least during the signal voltage writing period (2). ).
  • the display device (4) The display device according to (3), wherein the reference voltage control unit generates a pulse voltage whose voltage level is higher than the cathode voltage during the signal voltage writing period and outputs the pulse voltage to the reference voltage.
  • the reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then at the timing when the sampling transistor is turned off, the second voltage.
  • the display device according to any one of (2) to (4), which transitions from a voltage to the first voltage.
  • the reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then at the timing when the light emitting of the light emitting element is stopped, the first voltage.
  • the display device according to any one of (2) to (4), which transitions from the voltage of 2 to the first voltage.
  • the anode voltage control unit makes the anode voltage substantially the same as the cathode voltage during a predetermined period before the signal voltage writing period is started, any one of (1) to (8).
  • the pixel circuit further includes a second switching transistor for diode-connecting the drive transistor in a predetermined period before the signal voltage writing period is started.
  • the predetermined period is a period in which the gate-source voltage of the drive transistor is set to a voltage corresponding to the threshold voltage of the drive transistor.
  • the light emitting element emits light with brightness corresponding to the current flowing through the drive transistor based on the signal voltage.
  • 100 display device 110 pixel unit, 111R pixel, 111G pixel, 111B pixel, 112 anode potential control unit, 120 horizontal selector, 130 vertical scanner, 134 VSS2 scanner, EL organic EL element, SL signal line, T1 to T6 transistor, Band Anode potential, Vcat cathode potential, Vsig signal voltage

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Abstract

[Problem] To improve brightness. [Solution] This display device is provided with a pixel array unit in which a pixel circuit is arranged, and a drive circuit for driving the pixel array unit, wherein the pixel circuit includes: a light emitting element which emits light having a brightness corresponding to a current flowing from an anode to a cathode; a drive transistor for driving the light emitting element on the basis of a written signal voltage; a sampling transistor for sampling the signal voltage written to the drive transistor; and an anode voltage control unit for making the anode voltage of the light emitting element higher than the cathode voltage of the light emitting element during a signal voltage writing period in which the sampling transistor is turned on and the signal voltage is written to the drive transistor.

Description

表示装置Display device
　本開示による実施形態は、表示装置に関する。 The embodiment according to the present disclosure relates to a display device.
　近年、表示装置の分野では、発光部を含む画素が行列状（マトリクス状）に配置された平面型（フラットパネル型）の表示装置が主流となっている。平面型の表示装置の一つとして、発光部に流れる電流値に応じて発光輝度が変化する、所謂、電流駆動型の電気光学素子、例えば、有機エレクトロルミネッセンス（Ｅｌｅｃｔｒｏ　Ｌｕｍｉｎｅｓｃｅｎｃｅ：ＥＬ）素子を用いる有機ＥＬ表示装置がある。 In recent years, in the field of display devices, flat type (flat panel type) display devices in which pixels including light emitting parts are arranged in a matrix shape have become mainstream. Organic using a so-called current-driven electroluminescence element, for example, an organic electroluminescence (EL) element, in which the emission brightness changes according to the current value flowing through the light emitting unit as one of the planar display devices. There is an EL display device.
　この有機ＥＬ表示装置に代表される平面型の表示装置にあっては、発光部に流れる電流値、すなわち、発光輝度は、画素回路に供給される信号電圧Ｖｓｉｇの大きさに応じて変化する（特許文献１参照）。 In a planar display device typified by this organic EL display device, the current value flowing through the light emitting unit, that is, the light emission luminance, changes according to the magnitude of the signal voltage Vsig supplied to the pixel circuit ( See Patent Document 1).
特開２０１９－８２５４８号公報Japanese Unexamined Patent Publication No. 2019-82548
　しかし、低消費電力化を目的として、主電源の低電圧化が進んでいる。この結果、信号電圧Ｖｓｉｇの振幅を十分大きくすることができず、発光部の最大輝度が制限される可能性がある。 However, the voltage of the main power supply is being lowered for the purpose of lowering power consumption. As a result, the amplitude of the signal voltage Vsig cannot be sufficiently increased, and the maximum brightness of the light emitting unit may be limited.
　そこで、本開示では、輝度を向上させることができる表示装置を提供するものである。 Therefore, in the present disclosure, a display device capable of improving the brightness is provided.
　上記の課題を解決するために、本開示によれば、
　画素回路が配置される画素アレイ部と、
　前記画素アレイ部を駆動させる駆動回路と、を備え、
　前記画素回路は、
　アノードからカソードに流れる電流に応じた輝度で発光する発光素子と、
　書き込まれた信号電圧に基づいて、前記発光素子を駆動する駆動トランジスタと、
　前記駆動トランジスタへ書き込まれる前記信号電圧をサンプリングするサンプリングトランジスタと、
　前記サンプリングトランジスタをオンにして前記駆動トランジスタへの前記信号電圧の書き込みを行う信号電圧書き込み期間に、前記発光素子のアノード電圧を前記発光素子のカソード電圧よりも高くするアノード電圧制御部と、を有する、表示装置が提供される。 In order to solve the above problems, according to this disclosure,
The pixel array section where the pixel circuit is arranged and
A drive circuit for driving the pixel array unit is provided.
The pixel circuit is
A light emitting element that emits light with brightness according to the current flowing from the anode to the cathode,
A drive transistor that drives the light emitting element based on the written signal voltage,
A sampling transistor that samples the signal voltage written to the drive transistor,
It has an anode voltage control unit that makes the anode voltage of the light emitting element higher than the cathode voltage of the light emitting element during the signal voltage writing period in which the sampling transistor is turned on and the signal voltage is written to the drive transistor. , A display device is provided.
　前記アノード電圧制御部は、前記信号電圧書き込み期間内にオンして、前記発光素子のアノード電圧を基準電圧に設定する第１スイッチングトランジスタを有し、
　前記基準電圧は、前記サンプリングトランジスタがオンするタイミングに合わせて、第１の電圧から、前記カソード電圧より高い第２の電圧に遷移してもよい。 The anode voltage control unit has a first switching transistor that is turned on within the signal voltage writing period to set the anode voltage of the light emitting element to a reference voltage.
The reference voltage may transition from the first voltage to a second voltage higher than the cathode voltage in accordance with the timing at which the sampling transistor is turned on.
　前記駆動回路は、少なくとも前記信号電圧書き込み期間に前記基準電圧の電圧値が前記カソード電圧よりも高くなるように、前記基準電圧の電圧値を制御する基準電圧制御部を有してもよい。 The drive circuit may have a reference voltage control unit that controls the voltage value of the reference voltage so that the voltage value of the reference voltage becomes higher than the cathode voltage at least during the signal voltage writing period.
　前記基準電圧制御部は、前記信号電圧書き込み期間に電圧レベルが前記カソード電圧よりも高くなるパルス電圧を生成して前記基準電圧に出力してもよい。 The reference voltage control unit may generate a pulse voltage whose voltage level is higher than the cathode voltage during the signal voltage writing period and output it to the reference voltage.
　前記基準電圧は、前記サンプリングトランジスタがオンするタイミングに合わせて前記第１の電圧から前記第２の電圧に遷移し、その後、前記サンプリングトランジスタがオフするタイミングに合わせて、前記第２の電圧から前記第１の電圧に遷移してもよい。 The reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then from the second voltage at the timing when the sampling transistor is turned off. It may transition to the first voltage.
　前記基準電圧は、前記サンプリングトランジスタがオンするタイミングに合わせて前記第１の電圧から前記第２の電圧に遷移し、その後、前記発光素子の発光が停止するタイミングに合わせて、前記第２の電圧から前記第１の電圧に遷移してもよい。 The reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then the second voltage at the timing when the light emitting of the light emitting element is stopped. May transition to the first voltage.
　前記駆動トランジスタ、前記サンプリングトランジスタ及び前記第１スイッチングトランジスタは、Ｐチャネル型のトランジスタであってもよい。 The drive transistor, the sampling transistor, and the first switching transistor may be P-channel type transistors.
　前記駆動トランジスタ、前記サンプリングトランジスタ及び前記第１スイッチングトランジスタは、Ｎチャネル型のトランジスタであってもよい。 The drive transistor, the sampling transistor, and the first switching transistor may be N-channel type transistors.
　前記アノード電圧制御部は、前記信号電圧書き込み期間が開始される前の所定の期間に、前記アノード電圧を前記カソード電圧と略同じにしてもよい。 The anode voltage control unit may make the anode voltage substantially the same as the cathode voltage during a predetermined period before the signal voltage writing period is started.
　前記画素回路は、前記信号電圧書き込み期間が開始される前の所定の期間に、前記駆動トランジスタをダイオード接続させる第２スイッチングトランジスタをさらに有してもよい。 The pixel circuit may further include a second switching transistor for diode-connecting the drive transistor in a predetermined period before the signal voltage writing period is started.
　前記所定の期間は、前記駆動トランジスタのゲート及びソース間電圧を、前記駆動トランジスタの閾値電圧に応じた電圧にする期間であってもよい。 The predetermined period may be a period in which the gate-source voltage of the drive transistor is set to a voltage corresponding to the threshold voltage of the drive transistor.
　前記発光素子は、前記信号電圧に基づいて前記駆動トランジスタを流れる電流に応じた輝度で発光してもよい。 The light emitting element may emit light with a brightness corresponding to the current flowing through the drive transistor based on the signal voltage.
本開示の第１実施形態に係る表示装置の構成の一例を示す説明図である。It is explanatory drawing which shows an example of the structure of the display device which concerns on 1st Embodiment of this disclosure. 本開示の第１実施形態に係る表示装置のより詳細な構成の一例を示す説明図である。It is explanatory drawing which shows an example of the more detailed structure of the display device which concerns on 1st Embodiment of this disclosure. 本開示の第１実施形態に係る表示装置のより詳細な構成の一例を示す説明図である。It is explanatory drawing which shows an example of the more detailed structure of the display device which concerns on 1st Embodiment of this disclosure. 図３に示した画素回路を抜き出して示した説明図である。It is explanatory drawing which took out and showed the pixel circuit shown in FIG. 本開示の第１実施形態に係る表示装置の駆動方法の一例を示す説明図である。It is explanatory drawing which shows an example of the driving method of the display device which concerns on 1st Embodiment of this disclosure. 本開示の比較例に係る表示装置のより詳細な構成の一例を示す説明図である。It is explanatory drawing which shows an example of the more detailed structure of the display device which concerns on the comparative example of this disclosure. 本開示の比較例に係る表示装置の駆動方法の一例を示す説明図である。It is explanatory drawing which shows an example of the driving method of the display device which concerns on the comparative example of this disclosure. 本開示の第１実施形態に係る表示装置の駆動方法の第１変形例を示す説明図である。It is explanatory drawing which shows the 1st modification of the driving method of the display device which concerns on 1st Embodiment of this disclosure. 本開示の第１実施形態に係る表示装置の駆動方法の第２変形例を示す説明図である。It is explanatory drawing which shows the 2nd modification of the driving method of the display device which concerns on 1st Embodiment of this disclosure. 本開示の第２実施形態に係る画素回路の構成の一例を示す説明図である。It is explanatory drawing which shows an example of the structure of the pixel circuit which concerns on 2nd Embodiment of this disclosure. 本開示の第３実施形態に係る画素回路の構成の一例を示す説明図である。It is explanatory drawing which shows an example of the structure of the pixel circuit which concerns on 3rd Embodiment of this disclosure. 本開示の第４実施形態に係る画素回路の構成の一例を示す説明図である。It is explanatory drawing which shows an example of the structure of the pixel circuit which concerns on 4th Embodiment of this disclosure.
　以下、図面を参照して、表示装置の実施形態について説明する。以下では、表示装置の主要な構成部分を中心に説明するが、表示装置には、図示又は説明されていない構成部分や機能が存在しうる。以下の説明は、図示又は説明されていない構成部分や機能を除外するものではない。 Hereinafter, embodiments of the display device will be described with reference to the drawings. In the following, the main components of the display device will be mainly described, but the display device may have components and functions not shown or described. The following description does not exclude components or functions not shown or described.
＜第１実施形態＞
　［本開示の表示装置全般に関する説明］
　本開示の表示装置は、発光部を駆動する駆動トランジスタの他に、サンプリングトランジスタ及び保持容量を有する画素回路が配置されて成る平面型（フラットパネル型）の表示装置である。平面型の表示装置としては、有機ＥＬ表示装置、液晶表示装置、プラズマ表示装置などを例示することができる。これらの表示装置のうち、有機ＥＬ表示装置は、有機材料のエレクトロルミネッセンスを利用し、有機薄膜に電界をかけると発光する現象を用いた有機ＥＬ素子を画素の発光素子（電気光学素子）として用いている。 <First Embodiment>
[Explanation of the display device in general in the present disclosure]
The display device of the present disclosure is a flat panel type display device in which a sampling transistor and a pixel circuit having a holding capacity are arranged in addition to a drive transistor for driving a light emitting unit. Examples of the flat display device include an organic EL display device, a liquid crystal display device, and a plasma display device. Among these display devices, the organic EL display device uses electroluminescence of an organic material and uses an organic EL element that emits light when an electric field is applied to an organic thin film as a pixel light emitting element (electro-optical element). ing.
　画素の発光部として有機ＥＬ素子を用いた有機ＥＬ表示装置は次のような特長を持っている。有機ＥＬ素子が自発光型の素子であるために、有機ＥＬ表示装置は、同じ平面型の表示装置である液晶表示装置に比べて、画像の視認性が高く、しかも、バックライト等の照明部材を必要としないために軽量化及び薄型化が容易である。更に、有機ＥＬ素子の応答速度が数マイクロ秒程度と非常に高速であるために、有機ＥＬ表示装置は動画表示時の残像が発生しない。 An organic EL display device that uses an organic EL element as the light emitting part of a pixel has the following features. Since the organic EL element is a self-luminous element, the organic EL display device has higher image visibility than the liquid crystal display device, which is the same flat display device, and is a lighting member such as a backlight. It is easy to reduce the weight and thickness because it does not require. Further, since the response speed of the organic EL element is as high as several microseconds, the organic EL display device does not generate an afterimage when displaying a moving image.
　有機ＥＬ素子は、自発光型の素子であるとともに、電流駆動型の電気光学素子である。電流駆動型の電気光学素子としては、有機ＥＬ素子の他に、無機ＥＬ素子、ＬＥＤ素子、半導体レーザー素子などを例示することができる。 The organic EL element is a self-luminous element and a current-driven electro-optical element. Examples of the current-driven electro-optical element include an inorganic EL element, an LED element, a semiconductor laser element, and the like, in addition to the organic EL element.
　有機ＥＬ表示装置等の平面型の表示装置は、表示部を備える各種の電子機器において、その表示部（表示装置）として用いることができる。各種の電子機器としては、テレビジョンシステムの他、ヘッドマウントディスプレイ、デジタルカメラ、ビデオカメラ、ゲーム機、ノート型パーソナルコンピュータ、電子書籍等の携帯情報機器、ＰＤＡ（Ｐｅｒｓｏｎａｌ　Ｄｉｇｉｔａｌ　Ａｓｓｉｓｔａｎｔ）や携帯電話機等の携帯通信機器などを例示することができる。 A flat display device such as an organic EL display device can be used as a display unit (display device) in various electronic devices provided with a display unit. Various electronic devices include television systems, head-mounted displays, digital cameras, video cameras, game machines, notebook personal computers, mobile information devices such as electronic books, PDA (Personal Digital Assistant), mobile phones, etc. A mobile communication device or the like can be exemplified.
　本開示の表示装置にあっては、駆動部について、駆動トランジスタのゲートノードをフローティング状態にした後ソースノードをフローティング状態にする構成とすることができる。また、駆動部について、駆動トランジスタのソースノードをフローティング状態にしたままサンプリングトランジスタによる信号電圧の書込みを行う構成とすることができる。初期化電圧については、信号電圧と異なるタイミングで信号線に供給され、信号線からサンプリングトランジスタによるサンプリングによって駆動トランジスタのゲートノードに書き込まれる構成とすることができる。 In the display device of the present disclosure, the drive unit may be configured so that the gate node of the drive transistor is in a floating state and then the source node is in a floating state. Further, the drive unit may be configured to write the signal voltage by the sampling transistor while keeping the source node of the drive transistor in the floating state. The initialization voltage may be supplied to the signal line at a timing different from the signal voltage, and may be written from the signal line to the gate node of the drive transistor by sampling by the sampling transistor.
　上述した好ましい構成を含む本開示の表示装置にあっては、画素回路について、シリコンのような半導体上に形成する構成とすることができる。また、駆動トランジスタについて、Ｐチャネル型のトランジスタから成る構成とすることができる。駆動トランジスタとして、Ｎチャネル型のトランジスタではなく、Ｐチャネル型のトランジスタを用いるのは次の理由による。 In the display device of the present disclosure including the above-mentioned preferable configuration, the pixel circuit can be configured to be formed on a semiconductor such as silicon. Further, the drive transistor may be configured to consist of a P-channel type transistor. The reason why the P-channel type transistor is used as the drive transistor instead of the N-channel type transistor is as follows.
　トランジスタをガラス基板のような絶縁体上ではなく、シリコンのような半導体上に形成する場合、トランジスタは、ソース／ゲート／ドレインの３端子ではなく、ソース／ゲート／ドレイン／バックゲート（ベース）の４端子となる。そして、駆動トランジスタとしてＮチャネル型のトランジスタを用いた場合、バックゲート（基板）電圧が０Ｖとなり、駆動トランジスタの閾値電圧の画素毎のばらつきを補正する動作などに悪影響を及ぼすことになる。 When a transistor is formed on a semiconductor such as silicon rather than on an insulator such as a glass substrate, the transistor is not a source / gate / drain terminal but a source / gate / drain / backgate (base). It has 4 terminals. When an N-channel type transistor is used as the drive transistor, the back gate (board) voltage becomes 0 V, which adversely affects the operation of correcting the variation of the threshold voltage of the drive transistor for each pixel.
　また、トランジスタの特性ばらつきは、ＬＤＤ（Ｌｉｇｈｔｌｙ　Ｄｏｐｅｄ　Ｄｒａｉｎ）領域を持つＮチャネル型のトランジスタに比べて、ＬＤＤ領域を持たないＰチャネル型のトランジスタの方が小さく、画素の微細化、ひいては、表示装置の高精細化を図る上で有利である。このような理由などから、シリコンのような半導体上への形成を想定した場合、駆動トランジスタとして、Ｎチャネル型のトランジスタではなく、Ｐチャネル型のトランジスタを用いるのが好ましい。 Further, the variation in the characteristics of the transistor is smaller in the P-channel type transistor having no LDD region than in the N-channel type transistor having the LDD (Lightly Doped Drain) region, and the pixel miniaturization and eventually the display device. It is advantageous for achieving high definition. For this reason, when it is assumed that the transistor is formed on a semiconductor such as silicon, it is preferable to use a P-channel transistor instead of an N-channel transistor as the drive transistor.
　上述した好ましい構成を含む本開示の表示装置にあっては、サンプリングトランジスタについても、Ｐチャネル型のトランジスタから成る構成とすることができる。 In the display device of the present disclosure including the above-mentioned preferable configuration, the sampling transistor may also be configured to include a P-channel type transistor.
　あるいは又、上述した好ましい構成を含む本開示の表示装置にあっては、画素回路について、発光部の発光／非発光を制御する発光制御トランジスタを有する構成とすることができる。このとき、発光制御トランジスタについても、Ｐチャネル型のトランジスタから成る構成とすることができる。 Alternatively, in the display device of the present disclosure including the above-mentioned preferable configuration, the pixel circuit may be configured to have a light emission control transistor for controlling light emission / non-light emission of the light emitting unit. At this time, the light emission control transistor may also be configured to consist of a P-channel type transistor.
　あるいは又、上述した好ましい構成を含む本開示の表示装置にあっては、保持容量について、駆動トランジスタのゲートノードとソースノードとの間に接続された構成とすることができる。また、画素回路について、駆動トランジスタのソースノードと固定電位のノードとの間に接続された補助容量を有する構成とすることができる。 Alternatively, in the display device of the present disclosure including the above-mentioned preferable configuration, the holding capacity may be configured to be connected between the gate node and the source node of the drive transistor. Further, the pixel circuit can be configured to have an auxiliary capacitance connected between the source node of the drive transistor and the node of the fixed potential.
　あるいは又、上述した好ましい構成を含む本開示の表示装置にあっては、画素回路について、駆動トランジスタのドレインノードと発光部のアノードノードとの間に接続されたスイッチングトランジスタを有する構成とすることができる。このとき、スイッチングトランジスタについても、Ｐチャネル型のトランジスタから成る構成とすることができる。また、駆動部について、発光部の非発光期間にスイッチングトランジスタを導通状態にする構成とすることができる。 Alternatively, in the display device of the present disclosure including the above-mentioned preferable configuration, the pixel circuit may have a configuration having a switching transistor connected between the drain node of the drive transistor and the anode node of the light emitting unit. can. At this time, the switching transistor may also be configured to consist of a P-channel type transistor. Further, the drive unit may be configured to have the switching transistor in a conductive state during the non-light emission period of the light emitting unit.
　あるいは又、上述した好ましい構成を含む本開示の表示装置にあっては、駆動部は、スイッチングトランジスタを駆動する信号を、サンプリングトランジスタによる初期化電圧のサンプリングタイミングよりも前にアクティブ状態にする。そして、発光制御トランジスタを駆動する信号をアクティブ状態にした後に非アクティブ状態にする構成とすることができる。このとき、駆動部について、発光制御トランジスタを駆動する信号を非アクティブ状態にする前に、サンプリングトランジスタによる初期化電圧のサンプリングを完了する構成とすることができる。 Alternatively, in the display device of the present disclosure including the above-mentioned preferable configuration, the drive unit activates the signal for driving the switching transistor before the sampling timing of the initialization voltage by the sampling transistor. Then, the signal for driving the light emission control transistor can be activated and then inactive. At this time, the drive unit may be configured to complete the sampling of the initialization voltage by the sampling transistor before the signal for driving the light emission control transistor is inactive.
　［構成例および動作例］
　続いて、本開示の実施の形態に係る表示装置の構成例を説明する。図１は、本開示の第１実施形態に係る表示装置１００の構成の一例を示す説明図である。以下、図１を用いて本開示の第１実施形態に係る表示装置１００の構成の一例を説明する。 [Configuration example and operation example]
Subsequently, a configuration example of the display device according to the embodiment of the present disclosure will be described. FIG. 1 is an explanatory diagram showing an example of the configuration of the display device 100 according to the first embodiment of the present disclosure. Hereinafter, an example of the configuration of the display device 100 according to the first embodiment of the present disclosure will be described with reference to FIG.
　画素部１１０は、有機ＥＬ素子その他の自発光素子がそれぞれ設けられた画素がマトリクス状に配置された構成を有する。画素部１１０は、マトリックス状に配置した画素に対して、走査線がライン単位で水平方向に設けられ、また走査線と直交するように信号線ＳＬが列毎に設けられる。 The pixel unit 110 has a configuration in which pixels provided with organic EL elements and other self-luminous elements are arranged in a matrix. The pixel unit 110 is provided with scanning lines in the horizontal direction in line units with respect to the pixels arranged in a matrix, and signal lines SL are provided for each row so as to be orthogonal to the scanning lines.
　水平セレクタ１２０は、所定のサンプリングパルスを順次転送し、このサンプリングパルスで画像データを順次ラッチすることにより、この画像データを各信号線ＳＬに振り分ける。また水平セレクタ１２０は、各信号線ＳＬに振り分けた画像データをそれぞれアナログディジタル変換処理し、これにより各信号線ＳＬに接続された各画素の発光輝度を時分割により示す駆動信号を生成する。水平セレクタ１２０は、この駆動信号を対応する信号線ＳＬに出力する。 The horizontal selector 120 sequentially transfers a predetermined sampling pulse, and sequentially latches the image data with this sampling pulse, thereby distributing the image data to each signal line SL. Further, the horizontal selector 120 performs analog digital conversion processing on the image data distributed to each signal line SL, thereby generating a drive signal indicating the emission luminance of each pixel connected to each signal line SL by time division. The horizontal selector 120 outputs this drive signal to the corresponding signal line SL.
　垂直スキャナ１３０は、この水平セレクタ１２０による信号線ＳＬの駆動に応動して、各画素の駆動信号を生成して走査線ＳＣＮに出力する。これにより表示装置１００は、垂直スキャナ１３０により画素部１１０に配置された各画素を順次駆動し、水平セレクタ１２０より設定される各信号線ＳＬの信号レベルで各画素を発光させ、所望の画像を画素部１１０で表示する。 The vertical scanner 130 responds to the driving of the signal line SL by the horizontal selector 120, generates a driving signal for each pixel, and outputs the driving signal to the scanning line SCN. As a result, the display device 100 sequentially drives each pixel arranged in the pixel unit 110 by the vertical scanner 130, causes each pixel to emit light at the signal level of each signal line SL set by the horizontal selector 120, and produces a desired image. It is displayed by the pixel unit 110.
　図２は、本開示の第１実施形態に係る表示装置１００のより詳細な構成の一例を示す説明図である。以下、図２を用いて本開示の第１実施形態に係る表示装置１００の構成の一例を説明する。 FIG. 2 is an explanatory diagram showing an example of a more detailed configuration of the display device 100 according to the first embodiment of the present disclosure. Hereinafter, an example of the configuration of the display device 100 according to the first embodiment of the present disclosure will be described with reference to FIG.
　画素部１１０には、赤色を表示する画素１１１Ｒ、緑色を表示する画素１１１Ｇ、青色を表示する画素１１１Ｂがマトリクス状に配置されている。 In the pixel unit 110, a pixel 111R displaying red, a pixel 111G displaying green, and a pixel 111B displaying blue are arranged in a matrix.
　そして垂直スキャナ１３０は、オートゼロスキャナ１３１、駆動スキャナ１３２及び書き込みスキャナ１３３を有する。それぞれのスキャナから信号が画素部１１０にマトリクス状に配置された画素に供給されることで、それぞれの画素に設けられるＴＦＴのオン、オフ動作が行われる。 The vertical scanner 130 includes an auto-zero scanner 131, a drive scanner 132, and a write scanner 133. By supplying a signal from each scanner to the pixels arranged in a matrix in the pixel unit 110, the TFTs provided in the respective pixels are turned on and off.
　また、垂直スキャナ１３０は、ＶＳＳ２スキャナ（基準電圧制御部）１３４をさらに有する。ＶＳＳ２スキャナ１３４は、例えば、制御電圧信号を生成し、画素部１１０にマトリクス状に配置された画素に供給する。より詳細には、ＶＳＳ２スキャナ１３４は、制御電圧信号を基準電圧の給電線に供給する。すなわち、ＶＳＳ２スキャナ１３４は、オートゼロスキャナ１３１、駆動スキャナ１３２、書き込みスキャナ１３３の信号出力と同様に、制御電圧信号を出力する。電圧レベルが時間変化する制御電圧信号を画素内の基準電圧に供給することにより、後で説明するように、信号電圧Ｖｓｉｇの書き込みの際に有機ＥＬ素子のアノード電位（アノード電圧）を制御することができる。この結果、有機ＥＬ素子ＥＬの発光輝度を向上させることができる。 Further, the vertical scanner 130 further has a VSS2 scanner (reference voltage control unit) 134. The VSS2 scanner 134 generates, for example, a control voltage signal and supplies the control voltage signal to the pixels arranged in a matrix in the pixel unit 110. More specifically, the VSS2 scanner 134 supplies the control voltage signal to the feeder line of the reference voltage. That is, the VSS2 scanner 134 outputs a control voltage signal in the same manner as the signal outputs of the auto zero scanner 131, the drive scanner 132, and the write scanner 133. By supplying a control voltage signal whose voltage level changes with time to a reference voltage in the pixel, the anode potential (anode voltage) of the organic EL element is controlled when the signal voltage Vsig is written, as will be described later. Can be done. As a result, the emission brightness of the organic EL element EL can be improved.
　図３は、本開示の第１実施形態に係る表示装置１００のより詳細な構成の一例を示す説明図である。以下、図３を用いて本開示の第１実施形態に係る表示装置１００の構成の一例を説明する。 FIG. 3 is an explanatory diagram showing an example of a more detailed configuration of the display device 100 according to the first embodiment of the present disclosure. Hereinafter, an example of the configuration of the display device 100 according to the first embodiment of the present disclosure will be described with reference to FIG.
　図３には、画素部１１０にマトリクス状に配置された１つの画素に対する画素回路を図示している。画素回路は、トランジスタＴ１～Ｔ３と、アノード電位制御部（アノード電圧制御部）１１２と、キャパシタＣ１、Ｃ２と、有機ＥＬ素子ＥＬと、を含んで構成される。なお、アノード電位制御部１１２は、例えば、トランジスタＴ４を有する。図４は、図３に示した画素回路を抜き出して示した説明図である。 FIG. 3 illustrates a pixel circuit for one pixel arranged in a matrix in the pixel unit 110. The pixel circuit includes transistors T1 to T3, an anode potential control unit (anode voltage control unit) 112, capacitors C1 and C2, and an organic EL element EL. The anode potential control unit 112 includes, for example, the transistor T4. FIG. 4 is an explanatory diagram showing the pixel circuit shown in FIG. 3 extracted.
　トランジスタＴ１は有機ＥＬ素子ＥＬの発光を制御する発光制御トランジスタである。トランジスタＴ１は、電源電圧ＶＣＣＰの電源ノードと、トランジスタＴ２のソースノード（ソース電極）との間に接続され、駆動スキャナ１３２から出力される発光制御信号（信号ＤＳ）による駆動の下に、有機ＥＬ素子ＥＬの発光／非発光を制御する。 Transistor T1 is a light emission control transistor that controls light emission of the organic EL element EL. The transistor T1 is connected between the power supply node of the power supply voltage VCCP and the source node (source electrode) of the transistor T2, and is driven by a light emission control signal (signal DS) output from the drive scanner 132, and is an organic EL. Controls the light emission / non-light emission of the element EL.
　トランジスタＴ２は、キャパシタＣ２の保持電圧に応じた駆動電流を有機ＥＬ素子ＥＬに流すことによって有機ＥＬ素子ＥＬを駆動する駆動トランジスタである。トランジスタＴ２は、有機ＥＬ素子ＥＬのアノードと電源電圧ＶＣＣＰの電源ノードとの間に接続され、有機ＥＬ素子ＥＬに流れる電流を信号電圧Ｖｓｉｇに基づいて制御する。また、有機ＥＬ素子ＥＬは、アノードからカソードに流れる電流に応じた輝度で発光する。より詳細には、有機ＥＬ素子ＥＬは、信号電圧Ｖｓｉｇに基づいてトランジスタＴ２を流れる電流に応じた輝度で発光する。なお、図４に示すように、トランジスタＴ２は、ゲートとドレインとの間に寄生容量Ｃｐを有する。 The transistor T2 is a drive transistor that drives the organic EL element EL by passing a drive current corresponding to the holding voltage of the capacitor C2 through the organic EL element EL. The transistor T2 is connected between the anode of the organic EL element EL and the power supply node of the power supply voltage VCCP, and controls the current flowing through the organic EL element EL based on the signal voltage Vsig. Further, the organic EL element EL emits light with brightness corresponding to the current flowing from the anode to the cathode. More specifically, the organic EL element EL emits light with a brightness corresponding to the current flowing through the transistor T2 based on the signal voltage Vsig. As shown in FIG. 4, the transistor T2 has a parasitic capacitance Cp between the gate and the drain.
　トランジスタＴ３は、書き込みスキャナ１３３から供給される駆動信号（信号ＷＳ）による駆動の下に、信号電圧Ｖｓｉｇをサンプリングすることによって、トランジスタＴ２のゲートノード（ゲート電極）に信号電圧Ｖｓｉｇを書き込むサンプリングトランジスタである。トランジスタＴ３は、トランジスタＴ２のゲートと信号線ＳＬとの間に接続される。 The transistor T3 is a sampling transistor that writes the signal voltage Vsig to the gate node (gate electrode) of the transistor T2 by sampling the signal voltage Vsig under the drive by the drive signal (signal WS) supplied from the write scanner 133. be. The transistor T3 is connected between the gate of the transistor T2 and the signal line SL.
　トランジスタＴ４は、トランジスタＴ２のドレインノード（ドレイン電極）と電流排出先ノード（例えば、電源ＶＳＳ２）との間に接続される第１スイッチングトランジスタである。トランジスタＴ４は、オートゼロスキャナ１３１からの駆動信号（信号ＡＺ）による駆動の下に、有機ＥＬ素子ＥＬの非発光期間に有機ＥＬ素子ＥＬが発光しないように制御する。電源ＶＳＳ２の給電線には、例えば、ＶＳＳ２スキャナ１３４で生成された制御電圧が供給される。 The transistor T4 is a first switching transistor connected between the drain node (drain electrode) of the transistor T2 and the current discharge destination node (for example, the power supply VSS2). The transistor T4 is controlled so that the organic EL element EL does not emit light during the non-emission period of the organic EL element EL under the drive by the drive signal (signal AZ) from the auto-zero scanner 131. For example, the control voltage generated by the VSS2 scanner 134 is supplied to the feeder line of the power supply VSS2.
　トランジスタＴ１～Ｔ４は、いずれもＰチャネル型のトランジスタから成る構成とすることができる。 The transistors T1 to T4 can all be configured to be composed of P-channel type transistors.
　キャパシタＣ２は、トランジスタＴ２のゲートノードとソースノードとの間に接続されており、トランジスタＴ３によるサンプリングによって書き込まれた信号電圧Ｖｓｉｇを保持する。キャパシタＣ１は、トランジスタＴ２のソースノードと、固定電位のノード（例えば、電源電圧ＶＣＣＰの電源ノード）との間に接続されている。このキャパシタＣ１は、信号電圧Ｖｓｉｇを書き込んだときにトランジスタＴ２のソース電圧が変動するのを抑制するとともに、トランジスタＴ２のゲートソース間電圧ＶｇｓをトランジスタＴ２の閾値電圧Ｖthにする作用をなす。 The capacitor C2 is connected between the gate node and the source node of the transistor T2, and holds the signal voltage Vsig written by sampling by the transistor T3. The capacitor C1 is connected between the source node of the transistor T2 and the node of a fixed potential (for example, the power supply node of the power supply voltage VCCP). The capacitor C1 suppresses the fluctuation of the source voltage of the transistor T2 when the signal voltage Vsig is written, and also acts to change the gate-source voltage Vgs of the transistor T2 to the threshold voltage Vth of the transistor T2.
　この種の表示装置１００では、ポリシリコンＴＦＴを用いてガラス基板等による透明絶縁基板上に画素部１１０、水平セレクタ１２０、垂直スキャナ１３０等がまとめて形成される。ポリシリコンＴＦＴは、しきい値電圧または移動度にばらつきを避け得ず、有機ＥＬ素子を用いたディスプレイ装置では、これらのばらつきにより画質が劣化する問題がある。 In this type of display device 100, a pixel portion 110, a horizontal selector 120, a vertical scanner 130, and the like are collectively formed on a transparent insulating substrate made of a glass substrate or the like using a polysilicon TFT. Polysilicon TFTs cannot avoid variations in threshold voltage or mobility, and in display devices using organic EL elements, there is a problem that image quality deteriorates due to these variations.
　そこで、例えば図４に示す回路構成により画素回路を構成し、信号電圧Ｖｓｉｇの書き込みの前に、駆動用トランジスタのしきい値電圧または移動度のばらつきを補正することが考えられる。 Therefore, for example, it is conceivable to configure a pixel circuit with the circuit configuration shown in FIG. 4 and correct variations in the threshold voltage or mobility of the drive transistor before writing the signal voltage Vsig.
　また、トランジスタＴ４を有するアノード電位制御部１１２は、信号電圧書き込み期間が開始される前の所定の期間に、有機ＥＬ素子ＥＬのアノード電位Ｖａｎｄをカソード電位Ｖｃａｔｈと略同じにする。所定の期間は、駆動用トランジスタのしきい値電圧、移動度のばらつきを補正するための期間である。 Further, the anode potential control unit 112 having the transistor T4 makes the anode potential Band of the organic EL element EL substantially the same as the cathode potential Vcat in a predetermined period before the signal voltage writing period is started. The predetermined period is a period for correcting variations in the threshold voltage and mobility of the drive transistor.
　アノード電位制御部１１２は、トランジスタＴ３をオンにしてトランジスタＴ２への信号電圧Ｖｓｉｇの書き込みを行う信号電圧書き込み期間に、有機ＥＬ素子ＥＬのアノード電位Ｖａｎｄを有機ＥＬ素子ＥＬのカソード電位Ｖｃａｔｈよりも高くする。トランジスタＴ４は、例えば、信号電圧書き込み期間内にオンして、有機ＥＬ素子ＥＬのアノード電位Ｖａｎｄを電源ＶＳＳ２に設定する。ＶＳＳ２スキャナ１３４は、例えば、少なくとも信号電圧書き込み期間に電源ＶＳＳ２の電圧値がカソード電位Ｖｃａｔｈよりも高くなるように、電源ＶＳＳ２の電圧値を制御する。この結果、図５を参照して説明するように、有機ＥＬ素子ＥＬの発光輝度を向上させることができる。 The anode potential control unit 112 sets the anode potential Vand of the organic EL element EL higher than the cathode potential Vcat of the organic EL element EL during the signal voltage writing period in which the transistor T3 is turned on and the signal voltage Vsig is written to the transistor T2. do. The transistor T4 is turned on, for example, within the signal voltage writing period, and the anode potential Band of the organic EL element EL is set to the power supply VSS2. The VSS2 scanner 134 controls the voltage value of the power supply VSS2 so that the voltage value of the power supply VSS2 becomes higher than the cathode potential Vcat at least during the signal voltage writing period. As a result, as described with reference to FIG. 5, the emission brightness of the organic EL element EL can be improved.
　上記の構成の表示装置１００の駆動方法に関して、駆動用トランジスタの特性ばらつきの補正、及び、信号電圧Ｖｓｉｇの書き込みの動作について説明する。なお、信号電圧Ｖｓｉｇの書き込みにおいて、ＶＳＳ２スキャナ１３４による電源ＶＳＳ２の電圧値の変更動作についても説明する。 Regarding the driving method of the display device 100 having the above configuration, the correction of the characteristic variation of the driving transistor and the operation of writing the signal voltage Vsig will be described. In writing the signal voltage Vsig, the operation of changing the voltage value of the power supply VSS2 by the VSS2 scanner 134 will also be described.
　図５は、本開示の第１実施形態に係る表示装置１００の駆動方法の一例を示す説明図である。図５には、トランジスタＴ２のソース電位Ｖｓ、ゲート電位Ｖｇ及びドレイン電位Ｖｄ、並びに、有機ＥＬ素子ＥＬのアノード電位Ｖａｎｄ及びカソード電位（カソード電圧）Ｖｃａｔｈの時間的推移が示されている。なお、図５に示す例では、アノード電位Ｖａｎｄは、ドレイン電位Ｖｄと略同じである。また、図５には、ＶＳＳ２スキャナ１３４から電源ＶＳＳ２に供給される制御信号電圧、駆動スキャナ１３２からの信号ＤＳ、書き込みスキャナ１３３からの信号ＷＳ及びオートゼロスキャナ１３１からの信号ＡＺの時間的推移も示されている。 FIG. 5 is an explanatory diagram showing an example of a driving method of the display device 100 according to the first embodiment of the present disclosure. FIG. 5 shows the temporal transition of the source potential Vs, the gate potential Vg and the drain potential Vd of the transistor T2, and the anode potential Vand and the cathode potential (cathode voltage) Vcat of the organic EL element EL. In the example shown in FIG. 5, the anode potential Vand is substantially the same as the drain potential Vd. Further, FIG. 5 also shows the temporal transition of the control signal voltage supplied from the VSS2 scanner 134 to the power supply VSS2, the signal DS from the drive scanner 132, the signal WS from the write scanner 133, and the signal AZ from the auto-zero scanner 131. Has been done.
　まず、時刻ｔ１は、例えば、消光期間が終了し、１水平ライン（１Ｈ）の書き込み期間が開始するタイミングである。時刻ｔ１において、信号ＡＺはローであり、トランジスタＴ４はオンである。これは、後述のＶｔｈ補正期間中に有機ＥＬ素子ＥＬに電流が流れ込み、有機ＥＬ素子ＥＬが発光することを防ぐためである。 First, time t1 is, for example, the timing at which the quenching period ends and the writing period of one horizontal line (1H) begins. At time t1, the signal AZ is low and the transistor T4 is on. This is to prevent the organic EL element EL from emitting light due to a current flowing into the organic EL element EL during the Vth correction period described later.
　次に、時刻ｔ２において、信号ＷＳ、ＤＳがハイからローになることにより、トランジスタＴ１、Ｔ３がオンする。これにより、トランジスタＴ２の閾値電圧Ｖｔｈの補正の準備期間に入る。ここでトランジスタＴ２のゲート電位Ｖｇがオフセット電圧Ｖｏｆｓまで低下する。 Next, at time t2, the transistors T1 and T3 are turned on by changing the signals WS and DS from high to low. As a result, the preparation period for correcting the threshold voltage Vth of the transistor T2 is entered. Here, the gate potential Vg of the transistor T2 drops to the offset voltage Vofs.
　次に、時刻ｔ３において、信号ＷＳがローからハイになることにより、トランジスタＴ３がオフする。 Next, at time t3, the transistor T3 is turned off when the signal WS changes from low to high.
　次に、時刻ｔ４において、信号ＤＳがローからハイになることにより、トランジスタＴ１がオフする。これにより、Ｖｔｈ補正期間に入る。Ｖｔｈ補正期間において、トランジスタＴ２のゲートソース間電圧Ｖｇｓが閾値電圧Ｖｔｈに設定される。 Next, at time t4, the transistor T1 is turned off when the signal DS changes from low to high. As a result, the Vth correction period is entered. In the Vth correction period, the gate-source voltage Vgs of the transistor T2 is set to the threshold voltage Vth.
　次に、時刻ｔ５において、信号ＷＳがハイからローになることにより、トランジスタＴ３がオンする。これにより、トランジスタＴ２への信号電圧Ｖｓｉｇの書き込み期間となる。この書き込み期間において、トランジスタＴ２のゲート電位ＶｇがＶｓｉｇになる。 Next, at time t5, the transistor T3 is turned on by changing the signal WS from high to low. As a result, the writing period of the signal voltage Vsig to the transistor T2 is set. During this writing period, the gate potential Vg of the transistor T2 becomes Vsig.
　また、時刻ｔ５において、電源ＶＳＳ２の電圧値が大きくなる。より詳細には、時刻ｔ５よりも前の電源ＶＳＳ２の電圧値は、例えば、カソード電位Ｖｃａｔｈと略同じである。従って、Ｖｔｈ補正期間等において無駄な電流が流れることを抑制することができる。時刻ｔ５において、電源ＶＳＳ２の電圧値は、例えば、カソード電位Ｖｃａｔｈよりも大きくなる。これにより、オン状態のトランジスタＴ４を介して、ドレイン電位Ｖｄが大きくなる。ＶＳＳ２スキャナ１３４は、例えば、時刻ｔ５から時刻ｔ７までの期間に電圧レベルが高くなるパルス電圧を制御電圧信号として生成し、１水平ライン（１Ｈ）ごとに電源ＶＳＳ２に出力する。電源ＶＳＳ２の電圧値は、トランジスタＴ３がオンするタイミングに合わせて、第１の電圧から、カソード電位Ｖｃａｔｈより高い第２の電圧に遷移する。 Also, at time t5, the voltage value of the power supply VSS2 becomes large. More specifically, the voltage value of the power supply VSS2 before the time t5 is substantially the same as, for example, the cathode potential Vcat. Therefore, it is possible to suppress the flow of unnecessary current during the Vth correction period or the like. At time t5, the voltage value of the power supply VSS2 becomes larger than, for example, the cathode potential Vcat. As a result, the drain potential Vd increases via the transistor T4 in the on state. The VSS2 scanner 134 generates, for example, a pulse voltage whose voltage level increases during the period from time t5 to time t7 as a control voltage signal, and outputs the pulse voltage to the power supply VSS2 for each horizontal line (1H). The voltage value of the power supply VSS2 transitions from the first voltage to the second voltage higher than the cathode potential Vcat at the timing when the transistor T3 is turned on.
　次に、時刻ｔ６において、信号ＷＳがローからハイになることにより、トランジスタＴ３がオフする。これにより、トランジスタＴ２への信号電圧Ｖｓｉｇの書き込み期間が終了する。なお、時刻ｔ６と時刻ｔ７との間において、信号ＡＺがローからハイになることにより、トランジスタＴ４がオフする。 Next, at time t6, the transistor T3 is turned off when the signal WS changes from low to high. As a result, the writing period of the signal voltage Vsig to the transistor T2 ends. The transistor T4 is turned off when the signal AZ changes from low to high between the time t6 and the time t7.
　次に、時刻ｔ７において、信号ＤＳがハイからローになることにより、トランジスタＴ１がオンする。これにより、有機ＥＬ素子ＥＬが発光する。トランジスタＴ２のソース電位Ｖｓは電源電圧ＶＣＣＰとなる。 Next, at time t7, the transistor T1 is turned on by changing the signal DS from high to low. As a result, the organic EL element EL emits light. The source potential Vs of the transistor T2 becomes the power supply voltage VCCP.
　また、時刻ｔ７において、電源ＶＳＳ２の電圧値が小さくなる。時刻ｔ７における電源ＶＳＳ２の電圧値は、時刻ｔ５以前の電圧値であり、例えば、カソード電位Ｖｃａｔｈと略同じである。すなわち、電源ＶＳＳ２の電圧値は、時刻ｔ７において、第２の電圧から第１の電圧に遷移する。 Also, at time t7, the voltage value of the power supply VSS2 becomes smaller. The voltage value of the power supply VSS2 at time t7 is a voltage value before time t5, and is substantially the same as, for example, the cathode potential Vcat. That is, the voltage value of the power supply VSS2 transitions from the second voltage to the first voltage at time t7.
　次に、時刻ｔ８において、有機ＥＬ素子ＥＬが発光する発光期間となる。より詳細には、時刻ｔ８から時刻ｔ９までの期間は、発光遷移期間である。時刻ｔ８から時刻ｔ９までの期間では、有機ＥＬ素子ＥＬに電流が流れ、有機ＥＬ素子ＥＬのＩ－Ｖ特性によって、アノード電位Ｖａｎｄとカソード電位Ｖｃａｔｈとの間の電位差Ｖｏｌｅｄが徐々に広がる。カソード電位Ｖｃａｔｈは固定されているため、アノード電位Ｖａｎｄ、及び、アノード電位Ｖａｎｄと略同じドレイン電位Ｖｄが徐々に大きくなる。その後、時刻ｔ９において、ドレイン電位Ｖｄは安定する。 Next, at time t8, it becomes a light emitting period in which the organic EL element EL emits light. More specifically, the period from time t8 to time t9 is a light emission transition period. In the period from time t8 to time t9, a current flows through the organic EL element EL, and the potential difference Vold between the anode potential Vand and the cathode potential Vcat gradually widens due to the IV characteristics of the organic EL element EL. Since the cathode potential Vcat is fixed, the anode potential Vand and the drain potential Vd substantially the same as the anode potential Vd gradually increase. After that, at time t9, the drain potential Vd stabilizes.
　ここで、トランジスタＴ２のゲートとドレインとの間の寄生容量Ｃｐ（図４を参照）により、時刻ｔ８から時刻ｔ９にかけてドレイン電位Ｖｄが大きくなるに伴って、ゲート電位Ｖｇも大きくなる。一方、ソース電位Ｖｓは電源電圧ＶＣＣＰに固定されている。従って、時刻ｔ８から時刻ｔ９にかけて、ゲートソース間電圧Ｖｇｓは徐々に圧縮される。 Here, due to the parasitic capacitance Cp between the gate and drain of the transistor T2 (see FIG. 4), the gate potential Vg also increases as the drain potential Vd increases from time t8 to time t9. On the other hand, the source potential Vs is fixed to the power supply voltage VCCP. Therefore, from time t8 to time t9, the gate-source voltage Vgs is gradually compressed.
　なお、時刻ｔ５から時刻ｔ６までの信号電圧Ｖｓｉｇの書き込み期間では、ゲート電位Ｖｇは信号電圧Ｖｓｉｇに設定される。従って、電源ＶＳＳ２の電圧値が大きくなることによりドレイン電位Ｖｄが上昇しても、寄生容量Ｃｐを介したゲート電位Ｖｇへの影響は小さい。 In the writing period of the signal voltage Vsig from the time t5 to the time t6, the gate potential Vg is set to the signal voltage Vsig. Therefore, even if the drain potential Vd rises due to the increase in the voltage value of the power supply VSS2, the influence on the gate potential Vg via the parasitic capacitance Cp is small.
　第１実施形態では、時刻ｔ５から時刻ｔ６までにおける信号電圧Ｖｓｉｇの書き込み期間に、電源ＶＳＳ２の電圧値を大きくすることにより、ドレイン電位Ｖｄを大きくすることができる。これにより、時刻ｔ８から時刻ｔ９までの期間におけるゲートソース間電圧Ｖｇｓの圧縮量を抑制することができる。すなわち、時刻ｔ９以降の発光時のゲートソース間電圧Ｖｇｓを大きくすることができ、トランジスタＴ２に流れる電流を大きくすることができる。この結果、有機ＥＬ素子ＥＬの発光輝度を向上させることができる。 In the first embodiment, the drain potential Vd can be increased by increasing the voltage value of the power supply VSS2 during the writing period of the signal voltage Vsig from the time t5 to the time t6. Thereby, the compression amount of the gate-source voltage Vgs in the period from the time t8 to the time t9 can be suppressed. That is, the gate-source voltage Vgs at the time of light emission after the time t9 can be increased, and the current flowing through the transistor T2 can be increased. As a result, the emission brightness of the organic EL element EL can be improved.
　［比較例］
　図６は、本開示の比較例に係る表示装置１００のより詳細な構成の一例を示す説明図である。比較例は、ＶＳＳ２スキャナ１３４が設けられず、また、電圧値が可変である電源ＶＳＳ２に代えて、固定電圧の電源ＶＳＳがトランジスタＴ４のドレインと接続される点で、第１実施形態とは異なっている。 [Comparison example]
FIG. 6 is an explanatory diagram showing an example of a more detailed configuration of the display device 100 according to the comparative example of the present disclosure. The comparative example is different from the first embodiment in that the VSS2 scanner 134 is not provided and the fixed voltage power supply VSS is connected to the drain of the transistor T4 instead of the power supply VSS2 having a variable voltage value. ing.
　図７は、本開示の比較例に係る表示装置１００の駆動方法の一例を示す説明図である。 FIG. 7 is an explanatory diagram showing an example of a driving method of the display device 100 according to the comparative example of the present disclosure.
　図７に示すように、電源ＶＳＳの電圧値は、略一定（ＤＣ（Direct Current））である。従って、時刻ｔ５から時刻ｔ６までにおける信号電圧Ｖｓｉｇの書き込み期間において、ドレイン電位Ｖｄは略一定である。電源ＶＳＳの電圧値は、例えば、有機ＥＬ素子ＥＬのカソード電位Ｖｃａｔｈと略同じである。 As shown in FIG. 7, the voltage value of the power supply VSS is substantially constant (DC (Direct Current)). Therefore, the drain potential Vd is substantially constant during the writing period of the signal voltage Vsig from the time t5 to the time t6. The voltage value of the power supply VSS is, for example, substantially the same as the cathode potential Vcat of the organic EL element EL.
　時刻ｔ８において、比較例の図７に示すドレイン電位Ｖｄは、電源ＶＳＳ２の電圧値が変動する（ＡＣ（Alternating Current））第１実施形態の図５に示すドレイン電位Ｖｄよりも小さい。従って、時刻ｔ８から時刻ｔ９までの期間において、比較例におけるドレイン電位Ｖｄの上昇値は、第１実施形態におけるドレイン電位Ｖｄの上昇値よりも大きい。すなわち、比較例では、寄生容量Ｃｐを介したゲート電位Ｖｇの上昇値が大きく、ゲートソース間電圧Ｖｇｓの圧縮量が大きい。この結果、時刻ｔ９において、比較例の図７に示すゲートソース間電圧Ｖｇｓは、第１実施形態の図５に示すゲートソース間電圧Ｖｇｓよりも小さい。 At time t8, the drain potential Vd shown in FIG. 7 of the comparative example is smaller than the drain potential Vd shown in FIG. 5 of the first embodiment in which the voltage value of the power supply VSS2 fluctuates (AC (Alternating Current)). Therefore, in the period from time t8 to time t9, the increase value of the drain potential Vd in the comparative example is larger than the increase value of the drain potential Vd in the first embodiment. That is, in the comparative example, the increase value of the gate potential Vg via the parasitic capacitance Cp is large, and the compression amount of the gate-source voltage Vgs is large. As a result, at time t9, the gate-source voltage Vgs shown in FIG. 7 of the comparative example is smaller than the gate-source voltage Vgs shown in FIG. 5 of the first embodiment.
　近年、低消費電力化を目的として、主電源の低電圧化が進んでいる。この結果、信号電圧Ｖｓｉｇの振幅を十分大きくすることができず、最大輝度が制限される可能性がある。また、上記のように、寄生容量Ｃｐによって、時刻ｔ９の発光時におけるゲートソース間電圧Ｖｇｓが圧縮されてしまう。信号電圧Ｖｓｉｇの振幅が小さくなるほど、ゲートソース間電圧Ｖｇｓの圧縮の影響が大きくなる。この結果、最大輝度がさらに制限される可能性がある。 In recent years, the voltage of the main power supply has been reduced for the purpose of reducing power consumption. As a result, the amplitude of the signal voltage Vsig cannot be sufficiently increased, and the maximum brightness may be limited. Further, as described above, the parasitic capacitance Cp compresses the gate-source voltage Vgs at the time of light emission at time t9. The smaller the amplitude of the signal voltage Vsig, the greater the effect of compression of the gate-source voltage Vgs. As a result, the maximum brightness may be further limited.
　これに対して、第１実施形態では、信号電圧Ｖｓｉｇの書き込み期間においてドレイン電位Ｖｄを上昇させることにより、発光遷移期間（時刻ｔ８～時刻ｔ９）における寄生容量Ｃｐによるアノード電位Ｖａｎｄの上昇量を抑制することができる。すなわち、発光遷移期間における寄生容量Ｃｐによるゲートソース間電圧Ｖｇｓの圧縮量を抑制することができる。これにより、発光時（時刻ｔ９以降）におけるゲートソース間電圧Ｖｇｓを大きくすることができ、発光輝度を向上させることができる。この結果、信号電圧Ｖｓｉｇの振幅を増加させることなく、発光輝度を向上させることができる。すなわち、信号電圧Ｖｓｉｇの振幅が小さくなることによる最大輝度の制限を抑制することができる。 On the other hand, in the first embodiment, by increasing the drain potential Vd during the writing period of the signal voltage Vsig, the amount of increase in the anode potential Vand due to the parasitic capacitance Cp during the light emission transition period (time t8 to time t9) is suppressed. can do. That is, it is possible to suppress the amount of compression of the gate-source voltage Vgs due to the parasitic capacitance Cp during the light emission transition period. As a result, the gate-source voltage Vgs at the time of light emission (time t9 or later) can be increased, and the light emission brightness can be improved. As a result, the emission brightness can be improved without increasing the amplitude of the signal voltage Vsig. That is, it is possible to suppress the limitation of the maximum luminance due to the small amplitude of the signal voltage Vsig.
　［動作方法の変形例］
　次に、表示装置１００の動作方法の変形例について説明する。 [Modification example of operation method]
Next, a modified example of the operation method of the display device 100 will be described.
　図８は、本開示の第１実施形態に係る表示装置１００の駆動方法の第１変形例を示す説明図である。第１変形例は、電源ＶＳＳ２の電圧値が小さくなるタイミングが時刻ｔ７より前である点で、第１実施形態とは異なっている。 FIG. 8 is an explanatory diagram showing a first modification of the driving method of the display device 100 according to the first embodiment of the present disclosure. The first modification is different from the first embodiment in that the timing at which the voltage value of the power supply VSS2 becomes small is before the time t7.
　図８に示す例では、時刻ｔ６において、電源ＶＳＳ２の電圧値が小さくなり、例えば、カソード電位Ｖｃａｔｈと略同じになる。従って、電源ＶＳＳ２のパルス電圧の幅は、時刻ｔ５から時刻ｔ６までの期間である。 In the example shown in FIG. 8, the voltage value of the power supply VSS2 becomes smaller at time t6, and becomes substantially the same as, for example, the cathode potential Vcat. Therefore, the width of the pulse voltage of the power supply VSS2 is the period from the time t5 to the time t6.
　また、電源ＶＳＳのパルス電圧の幅は、例えば、信号電圧Ｖｓｉｇの書き込みのために信号ＷＳがローになる期間と対応する。すなわち、電源ＶＳＳ２の電圧値は、トランジスタＴ３がオンするタイミングに合わせて第１の電圧から第２の電圧に遷移し、その後、トランジスタＴ３がオフするタイミングに合わせて、第２の電圧から第１の電圧に遷移する。アノード電位Ｖａｎｄを大きくするために、電源ＶＳＳ２の電圧値は、少なくとも信号ＷＳがローである期間に、カソード電位Ｖｃａｔｈよりも大きいことが好ましい。 Further, the width of the pulse voltage of the power supply VSS corresponds to, for example, the period during which the signal WS becomes low due to the writing of the signal voltage Vsig. That is, the voltage value of the power supply VSS2 transitions from the first voltage to the second voltage according to the timing when the transistor T3 is turned on, and then from the second voltage to the first voltage according to the timing when the transistor T3 is turned off. Transition to the voltage of. In order to increase the anode potential Band, the voltage value of the power supply VSS2 is preferably larger than the cathode potential Vcat, at least during the period when the signal WS is low.
　図９は、本開示の第１実施形態に係る表示装置１００の駆動方法の第２変形例を示す説明図である。第２変形例は、電源ＶＳＳ２の電圧値が小さくなるタイミングが時刻ｔ７より後である点で、第１実施形態とは異なっている。 FIG. 9 is an explanatory diagram showing a second modification of the driving method of the display device 100 according to the first embodiment of the present disclosure. The second modification is different from the first embodiment in that the timing at which the voltage value of the power supply VSS2 becomes small is after the time t7.
　図９に示す例では、時刻ｔ１０において、電源ＶＳＳ２の電圧値が小さくなり、例えば、カソード電位Ｖｃａｔｈと略同じになる。時刻ｔ１０は、発光期間が終了し消光期間が開始するタイミングである。すなわち、電源ＶＳＳ２の電圧値は、トランジスタＴ３がオンするタイミングに合わせて第１の電圧から第２の電圧に遷移し、その後、有機ＥＬ素子ＥＬの発光が停止するタイミングに合わせて、第２の電圧から第１の電圧に遷移する。 In the example shown in FIG. 9, the voltage value of the power supply VSS2 becomes smaller at time t10, and becomes substantially the same as, for example, the cathode potential Vcat. Time t10 is the timing at which the light emission period ends and the quenching period begins. That is, the voltage value of the power supply VSS2 transitions from the first voltage to the second voltage according to the timing when the transistor T3 is turned on, and then the second voltage is matched with the timing when the light emission of the organic EL element EL is stopped. The transition from the voltage to the first voltage.
　なお、電源ＶＳＳ２の電圧値が小さくなるタイミングは、図９に示す実線に限られず、例えば、破線で示すように、時刻ｔ９から時刻ｔ１０までの期間内であってもよい。 The timing at which the voltage value of the power supply VSS2 becomes small is not limited to the solid line shown in FIG. 9, and may be within the period from time t9 to time t10, for example, as shown by the broken line.
　上記の変形例１及び変形例２に基づいて、電源ＶＳＳ２の電圧値が小さくなるタイミングは、例えば、信号ＷＳがハイになる時刻ｔ６から、消光期間の開始時であるｔ１０までの間のいずれかのタイミングでよい。 Based on the above modification 1 and modification 2, the timing at which the voltage value of the power supply VSS2 decreases is, for example, any of the time t6 from the time when the signal WS becomes high to t10 which is the start of the quenching period. The timing is fine.
　次に、表示装置１００のうち画素回路の構成の変形例として、第２実施形態～第４実施形態について説明する。 Next, the second to fourth embodiments will be described as a modification of the configuration of the pixel circuit in the display device 100.
＜第２実施形態＞
　図１０は、本開示の第２実施形態に係る画素回路の構成の一例を示す説明図である。 <Second Embodiment>
FIG. 10 is an explanatory diagram showing an example of the configuration of the pixel circuit according to the second embodiment of the present disclosure.
　図１０に示す例では、図４と比較して、画素回路はいわゆる「４Ｔｒ１Ｃ」の構成を有する。図１０に示す例では、キャパシタＣ１が設けられていない。また、図１１に示すトランジスタＴ１～Ｔ４は、Ｎチャネル型のトランジスタである。 In the example shown in FIG. 10, the pixel circuit has a so-called "4Tr1C" configuration as compared with FIG. In the example shown in FIG. 10, the capacitor C1 is not provided. Further, the transistors T1 to T4 shown in FIG. 11 are N-channel type transistors.
　第２実施形態においても、信号電圧Ｖｓｉｇの書き込み期間に、電源ＶＳＳ２の電圧値はカソード電位Ｖｃａｔｈよりも高くなる。これにより、第１実施形態と同様に、発光輝度を向上させることができる。 Also in the second embodiment, the voltage value of the power supply VSS2 becomes higher than the cathode potential Vcat during the writing period of the signal voltage Vsig. Thereby, the emission brightness can be improved as in the first embodiment.
＜第３実施形態＞
　図１１は、本開示の第３実施形態に係る画素回路の構成の一例を示す説明図である。 <Third Embodiment>
FIG. 11 is an explanatory diagram showing an example of the configuration of the pixel circuit according to the third embodiment of the present disclosure.
　図１１に示す例では、図４と比較して、画素回路はいわゆる「５Ｔｒ」の構成を有する。図１１に示す例では、キャパシタＣ１が設けられていない。また、発光制御トランジスタであるトランジスタＴ１は、電源電圧ＶＣＣＰとトランジスタＴ２のソースとの間ではなく、トランジスタＴ２のドレインと有機ＥＬ素子ＥＬのアノードとの間に接続されている。 In the example shown in FIG. 11, the pixel circuit has a so-called “5Tr” configuration as compared with FIG. In the example shown in FIG. 11, the capacitor C1 is not provided. Further, the transistor T1 which is a light emission control transistor is connected not between the power supply voltage VCCP and the source of the transistor T2 but between the drain of the transistor T2 and the anode of the organic EL element EL.
　画素回路は、トランジスタＴ５をさらに有する。トランジスタＴ５は、トランジスタＴ２のドレインとゲートとの間に接続される。トランジスタＴ５は、トランジスタＴ２の閾値を補償する閾値補償トランジスタである。トランジスタＴ５は、信号電圧Ｖｓｉｇの書き込み期間の前の所定の期間にオンする。すなわち、トランジスタＴ５は、トランジスタＴ２の閾値を補償する補償期間にトランジスタＴ２のゲートとドレインとを接続させ、トランジスタＴ２をダイオード接続させる第２スイッチングトランジスタである。補償期間の終了時、すなわち、信号電圧Ｖｓｉｇの書き込み期間の開始時に、キャパシタＣ２には、トランジスタＴ２の閾値電圧が保持される。この結果、画素回路ごとのトランジスタの閾値等の特性ばらつきの影響を抑制し、表示特性を向上させることができる。 The pixel circuit further has a transistor T5. The transistor T5 is connected between the drain and the gate of the transistor T2. The transistor T5 is a threshold value compensating transistor that compensates for the threshold value of the transistor T2. The transistor T5 is turned on in a predetermined period before the write period of the signal voltage Vsig. That is, the transistor T5 is a second switching transistor in which the gate and drain of the transistor T2 are connected and the transistor T2 is connected by a diode during the compensation period for compensating the threshold value of the transistor T2. At the end of the compensation period, that is, at the beginning of the write period of the signal voltage Vsig, the capacitor C2 holds the threshold voltage of the transistor T2. As a result, it is possible to suppress the influence of characteristic variations such as the threshold value of the transistor for each pixel circuit and improve the display characteristics.
　第３実施形態においても、信号電圧Ｖｓｉｇの書き込み期間に、電源ＶＳＳ２の電圧値はカソード電位Ｖｃａｔｈよりも高くなる。これにより、第１実施形態と同様に、発光輝度を向上させることができる。 Also in the third embodiment, the voltage value of the power supply VSS2 becomes higher than the cathode potential Vcat during the writing period of the signal voltage Vsig. Thereby, the emission brightness can be improved as in the first embodiment.
＜第４実施形態＞
　図１２は、本開示の第４実施形態に係る画素回路の構成の一例を示す説明図である。 <Fourth Embodiment>
FIG. 12 is an explanatory diagram showing an example of the configuration of the pixel circuit according to the fourth embodiment of the present disclosure.
　図１２に示す例では、図４と比較して、画素回路はいわゆる「６Ｔｒ」の構成を有する。図１２に示す第４実施形態は、図１１に示す第３実施形態の変形例でもある。 In the example shown in FIG. 12, the pixel circuit has a so-called "6Tr" configuration as compared with FIG. The fourth embodiment shown in FIG. 12 is also a modification of the third embodiment shown in FIG.
　図１２に示す信号線ＳＬは、図１１と比較して、信号線ＳＬ１と、複数の信号線ＳＬ２と、を有する。また、画素回路は、トランジスタＴ６と、キャパシタＣ３、Ｃ４と、をさらに有する。 The signal line SL shown in FIG. 12 has a signal line SL1 and a plurality of signal lines SL2 as compared with FIG. Further, the pixel circuit further includes a transistor T6 and capacitors C3 and C4.
　信号線ＳＬ２は、１つの信号線ＳＬ１に対して複数設けられる。複数の信号線ＳＬ２のそれぞれは、信号線ＳＬ１と電気的に接続される。複数の信号線ＳＬ２のそれぞれは、複数の画素１１１と電気的に接続される。すなわち、１つの信号線ＳＬ１は複数の信号線ＳＬ２に共有され、かつ、１つの信号線ＳＬ２は複数の画素１１１に共有される。これにより、信号線ＳＬ２を、全ての画素１１１と接続される場合の信号線よりも短くすることができる。この結果、トランジスタＴ２の閾値を補償する補償動作において、信号線ＳＬ２の寄生容量への充電又は放電に要する時間を短くすることができる。従って、第４実施形態では、第３実施形態と比較して、トランジスタＴ２の閾値を補償する補償期間を短くすることができる。 A plurality of signal lines SL2 are provided for one signal line SL1. Each of the plurality of signal lines SL2 is electrically connected to the signal line SL1. Each of the plurality of signal lines SL2 is electrically connected to the plurality of pixels 111. That is, one signal line SL1 is shared by a plurality of signal lines SL2, and one signal line SL2 is shared by a plurality of pixels 111. Thereby, the signal line SL2 can be made shorter than the signal line when connected to all the pixels 111. As a result, in the compensation operation for compensating for the threshold value of the transistor T2, the time required for charging or discharging the parasitic capacitance of the signal line SL2 can be shortened. Therefore, in the fourth embodiment, the compensation period for compensating the threshold value of the transistor T2 can be shortened as compared with the third embodiment.
　トランジスタＴ６は、信号線ＳＬ２に対応して、信号線ＳＬ２ごとに複数設けられる。複数のトランジスタＴ６は、信号線ＳＬ１と複数の信号線ＳＬ２のそれぞれとの間に接続される。トランジスタＴ６は、信号線ＳＬ１と信号線ＳＬ２との間の接続を制御するスイッチングトランジスタである。 A plurality of transistors T6 are provided for each signal line SL2 corresponding to the signal line SL2. The plurality of transistors T6 are connected between the signal line SL1 and each of the plurality of signal lines SL2. The transistor T6 is a switching transistor that controls the connection between the signal line SL1 and the signal line SL2.
　キャパシタＣ３は、信号線ＳＬ２に対応して、信号線ＳＬ２ごとに複数設けられる。複数のキャパシタＣ３は、信号線ＳＬ１と複数の信号線ＳＬ２のそれぞれとの間に接続される。 A plurality of capacitors C3 are provided for each signal line SL2 corresponding to the signal line SL2. The plurality of capacitors C3 are connected between the signal line SL1 and each of the plurality of signal lines SL2.
　キャパシタＣ４は、信号線ＳＬ１と電源ＶＳＳ２との間に接続される。キャパシタＣ４は、信号線ＳＬ１の電位を保持する。キャパシタＣ４は、例えば、互いに隣り合う信号線ＳＬ１と電源ＶＳＳ２の給電線との寄生容量により形成される。 The capacitor C4 is connected between the signal line SL1 and the power supply VSS2. The capacitor C4 holds the potential of the signal line SL1. The capacitor C4 is formed, for example, by a parasitic capacitance between a signal line SL1 adjacent to each other and a feeder line of the power supply VSS2.
　第４実施形態においても、信号電圧Ｖｓｉｇの書き込み期間に、電源ＶＳＳ２の電圧値はカソード電位Ｖｃａｔｈよりも高くなる。これにより、第１実施形態と同様に、発光輝度を向上させることができる。 Also in the fourth embodiment, the voltage value of the power supply VSS2 becomes higher than the cathode potential Vcat during the writing period of the signal voltage Vsig. Thereby, the emission brightness can be improved as in the first embodiment.
　なお、本技術は以下のような構成を取ることができる。
　（１）画素回路が配置される画素アレイ部と、
　前記画素アレイ部を駆動させる駆動回路と、を備え、
　前記画素回路は、
　アノードからカソードに流れる電流に応じた輝度で発光する発光素子と、
　書き込まれた信号電圧に基づいて、前記発光素子を駆動する駆動トランジスタと、
　前記駆動トランジスタへ書き込まれる前記信号電圧をサンプリングするサンプリングトランジスタと、
　前記サンプリングトランジスタをオンにして前記駆動トランジスタへの前記信号電圧の書き込みを行う信号電圧書き込み期間に、前記発光素子のアノード電圧を前記発光素子のカソード電圧よりも高くするアノード電圧制御部と、を有する、表示装置。
　（２）前記アノード電圧制御部は、前記信号電圧書き込み期間内にオンして、前記発光素子のアノード電圧を基準電圧に設定する第１スイッチングトランジスタを有し、
　前記基準電圧は、前記サンプリングトランジスタがオンするタイミングに合わせて、第１の電圧から、前記カソード電圧より高い第２の電圧に遷移する、（１）に記載の表示装置。
　（３）前記駆動回路は、少なくとも前記信号電圧書き込み期間に前記基準電圧の電圧値が前記カソード電圧よりも高くなるように、前記基準電圧の電圧値を制御する基準電圧制御部を有する、（２）に記載の表示装置。
　（４）前記基準電圧制御部は、前記信号電圧書き込み期間に電圧レベルが前記カソード電圧よりも高くなるパルス電圧を生成して前記基準電圧に出力する、（３）に記載の表示装置。
　（５）前記基準電圧は、前記サンプリングトランジスタがオンするタイミングに合わせて前記第１の電圧から前記第２の電圧に遷移し、その後、前記サンプリングトランジスタがオフするタイミングに合わせて、前記第２の電圧から前記第１の電圧に遷移する、（２）乃至（４）のいずれか一項に記載の表示装置。
　（６）前記基準電圧は、前記サンプリングトランジスタがオンするタイミングに合わせて前記第１の電圧から前記第２の電圧に遷移し、その後、前記発光素子の発光が停止するタイミングに合わせて、前記第２の電圧から前記第１の電圧に遷移する、（２）乃至（４）のいずれか一項に記載の表示装置。
　（７）前記駆動トランジスタ、前記サンプリングトランジスタ及び前記第１スイッチングトランジスタは、Ｐチャネル型のトランジスタである、（２）乃至（６）のいずれか一項に記載の表示装置。
　（８）前記駆動トランジスタ、前記サンプリングトランジスタ及び前記第１スイッチングトランジスタは、Ｎチャネル型のトランジスタである、（２）乃至（６）のいずれか一項に記載の表示装置。
　（９）前記アノード電圧制御部は、前記信号電圧書き込み期間が開始される前の所定の期間に、前記アノード電圧を前記カソード電圧と略同じにする、（１）乃至（８）のいずれか一項に記載の表示装置。
　（１０）前記画素回路は、前記信号電圧書き込み期間が開始される前の所定の期間に、前記駆動トランジスタをダイオード接続させる第２スイッチングトランジスタをさらに有する、（１）乃至（９）のいずれか一項に記載の表示装置。
　（１１）前記所定の期間は、前記駆動トランジスタのゲート及びソース間電圧を、前記駆動トランジスタの閾値電圧に応じた電圧にする期間である、（９）又は（１０）に記載の表示装置。
　（１２）前記発光素子は、前記信号電圧に基づいて前記駆動トランジスタを流れる電流に応じた輝度で発光する、（１）乃至（１１）のいずれか一項に記載の表示装置。 The present technology can have the following configurations.
(1) A pixel array unit in which a pixel circuit is arranged and
A drive circuit for driving the pixel array unit is provided.
The pixel circuit is
A light emitting element that emits light with brightness according to the current flowing from the anode to the cathode,
A drive transistor that drives the light emitting element based on the written signal voltage,
A sampling transistor that samples the signal voltage written to the drive transistor,
It has an anode voltage control unit that makes the anode voltage of the light emitting element higher than the cathode voltage of the light emitting element during the signal voltage writing period in which the sampling transistor is turned on and the signal voltage is written to the drive transistor. , Display device.
(2) The anode voltage control unit has a first switching transistor that is turned on within the signal voltage writing period to set the anode voltage of the light emitting element to the reference voltage.
The display device according to (1), wherein the reference voltage changes from a first voltage to a second voltage higher than the cathode voltage in accordance with the timing at which the sampling transistor is turned on.
(3) The drive circuit has a reference voltage control unit that controls the voltage value of the reference voltage so that the voltage value of the reference voltage becomes higher than the cathode voltage at least during the signal voltage writing period (2). ). The display device.
(4) The display device according to (3), wherein the reference voltage control unit generates a pulse voltage whose voltage level is higher than the cathode voltage during the signal voltage writing period and outputs the pulse voltage to the reference voltage.
(5) The reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then at the timing when the sampling transistor is turned off, the second voltage. The display device according to any one of (2) to (4), which transitions from a voltage to the first voltage.
(6) The reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then at the timing when the light emitting of the light emitting element is stopped, the first voltage. The display device according to any one of (2) to (4), which transitions from the voltage of 2 to the first voltage.
(7) The display device according to any one of (2) to (6), wherein the drive transistor, the sampling transistor, and the first switching transistor are P-channel type transistors.
(8) The display device according to any one of (2) to (6), wherein the drive transistor, the sampling transistor, and the first switching transistor are N-channel type transistors.
(9) The anode voltage control unit makes the anode voltage substantially the same as the cathode voltage during a predetermined period before the signal voltage writing period is started, any one of (1) to (8). The display device described in the section.
(10) Any one of (1) to (9), wherein the pixel circuit further includes a second switching transistor for diode-connecting the drive transistor in a predetermined period before the signal voltage writing period is started. The display device described in the section.
(11) The display device according to (9) or (10), wherein the predetermined period is a period in which the gate-source voltage of the drive transistor is set to a voltage corresponding to the threshold voltage of the drive transistor.
(12) The display device according to any one of (1) to (11), wherein the light emitting element emits light with brightness corresponding to the current flowing through the drive transistor based on the signal voltage.
　本開示の態様は、上述した個々の実施形態に限定されるものではなく、当業者が想到しうる種々の変形も含むものであり、本開示の効果も上述した内容に限定されない。すなわち、特許請求の範囲に規定された内容およびその均等物から導き出される本開示の概念的な思想と趣旨を逸脱しない範囲で種々の追加、変更および部分的削除が可能である。 The aspects of the present disclosure are not limited to the individual embodiments described above, but also include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. That is, various additions, changes and partial deletions are possible without departing from the conceptual idea and purpose of the present disclosure derived from the contents specified in the claims and their equivalents.
１００　表示装置、１１０　画素部、１１１Ｒ　画素、１１１Ｇ　画素、１１１Ｂ　画素、１１２　アノード電位制御部、１２０　水平セレクタ、１３０　垂直スキャナ、１３４　ＶＳＳ２スキャナ、ＥＬ　有機ＥＬ素子、ＳＬ　信号線、Ｔ１～Ｔ６　トランジスタ、Ｖａｎｄ　アノード電位、Ｖｃａｔｈ　カソード電位、Ｖｓｉｇ　信号電圧 100 display device, 110 pixel unit, 111R pixel, 111G pixel, 111B pixel, 112 anode potential control unit, 120 horizontal selector, 130 vertical scanner, 134 VSS2 scanner, EL organic EL element, SL signal line, T1 to T6 transistor, Band Anode potential, Vcat cathode potential, Vsig signal voltage

Claims (12)

  1. 　画素回路が配置される画素アレイ部と、
    　前記画素アレイ部を駆動させる駆動回路と、を備え、
    　前記画素回路は、
    　アノードからカソードに流れる電流に応じた輝度で発光する発光素子と、
    　書き込まれた信号電圧に基づいて、前記発光素子を駆動する駆動トランジスタと、
    　前記駆動トランジスタへ書き込まれる前記信号電圧をサンプリングするサンプリングトランジスタと、
    　前記サンプリングトランジスタをオンにして前記駆動トランジスタへの前記信号電圧の書き込みを行う信号電圧書き込み期間に、前記発光素子のアノード電圧を前記発光素子のカソード電圧よりも高くするアノード電圧制御部と、を有する、表示装置。     The pixel array section where the pixel circuit is arranged and
    A drive circuit for driving the pixel array unit is provided.
    The pixel circuit is
    A light emitting element that emits light with brightness according to the current flowing from the anode to the cathode,
    A drive transistor that drives the light emitting element based on the written signal voltage,
    A sampling transistor that samples the signal voltage written to the drive transistor,
    It has an anode voltage control unit that makes the anode voltage of the light emitting element higher than the cathode voltage of the light emitting element during the signal voltage writing period in which the sampling transistor is turned on and the signal voltage is written to the drive transistor. , Display device.
  2. 　前記アノード電圧制御部は、前記信号電圧書き込み期間内にオンして、前記発光素子のアノード電圧を基準電圧に設定する第１スイッチングトランジスタを有し、
    　前記基準電圧は、前記サンプリングトランジスタがオンするタイミングに合わせて、第１の電圧から、前記カソード電圧より高い第２の電圧に遷移する、請求項１に記載の表示装置。     The anode voltage control unit has a first switching transistor that is turned on within the signal voltage writing period to set the anode voltage of the light emitting element to a reference voltage.
    The display device according to claim 1, wherein the reference voltage changes from a first voltage to a second voltage higher than the cathode voltage in accordance with the timing at which the sampling transistor is turned on.
  3. 　前記駆動回路は、少なくとも前記信号電圧書き込み期間に前記基準電圧の電圧値が前記カソード電圧よりも高くなるように、前記基準電圧の電圧値を制御する基準電圧制御部を有する、請求項２に記載の表示装置。 2. The drive circuit has a reference voltage control unit that controls the voltage value of the reference voltage so that the voltage value of the reference voltage becomes higher than the cathode voltage at least during the signal voltage writing period. Display device.
  4. 　前記基準電圧制御部は、前記信号電圧書き込み期間に電圧レベルが前記カソード電圧よりも高くなるパルス電圧を生成して前記基準電圧に出力する、請求項３に記載の表示装置。 The display device according to claim 3, wherein the reference voltage control unit generates a pulse voltage whose voltage level is higher than the cathode voltage during the signal voltage writing period and outputs the pulse voltage to the reference voltage.
  5. 　前記基準電圧は、前記サンプリングトランジスタがオンするタイミングに合わせて前記第１の電圧から前記第２の電圧に遷移し、その後、前記サンプリングトランジスタがオフするタイミングに合わせて、前記第２の電圧から前記第１の電圧に遷移する、請求項２に記載の表示装置。 The reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then from the second voltage at the timing when the sampling transistor is turned off. The display device according to claim 2, which transitions to the first voltage.
  6. 　前記基準電圧は、前記サンプリングトランジスタがオンするタイミングに合わせて前記第１の電圧から前記第２の電圧に遷移し、その後、前記発光素子の発光が停止するタイミングに合わせて、前記第２の電圧から前記第１の電圧に遷移する、請求項２に記載の表示装置。 The reference voltage transitions from the first voltage to the second voltage at the timing when the sampling transistor is turned on, and then the second voltage at the timing when the light emitting of the light emitting element is stopped. The display device according to claim 2, wherein the voltage transitions from the first voltage to the first voltage.
  7. 　前記駆動トランジスタ、前記サンプリングトランジスタ及び前記第１スイッチングトランジスタは、Ｐチャネル型のトランジスタである、請求項２に記載の表示装置。 The display device according to claim 2, wherein the drive transistor, the sampling transistor, and the first switching transistor are P-channel type transistors.
  8. 　前記駆動トランジスタ、前記サンプリングトランジスタ及び前記第１スイッチングトランジスタは、Ｎチャネル型のトランジスタである、請求項２に記載の表示装置。 The display device according to claim 2, wherein the drive transistor, the sampling transistor, and the first switching transistor are N-channel type transistors.
  9. 　前記アノード電圧制御部は、前記信号電圧書き込み期間が開始される前の所定の期間に、前記アノード電圧を前記カソード電圧と略同じにする、請求項１に記載の表示装置。 The display device according to claim 1, wherein the anode voltage control unit makes the anode voltage substantially the same as the cathode voltage in a predetermined period before the signal voltage writing period is started.
  10. 　前記画素回路は、前記信号電圧書き込み期間が開始される前の所定の期間に、前記駆動トランジスタをダイオード接続させる第２スイッチングトランジスタをさらに有する、請求項１に記載の表示装置。 The display device according to claim 1, wherein the pixel circuit further includes a second switching transistor for diode-connecting the drive transistor in a predetermined period before the signal voltage writing period is started.
  11. 　前記所定の期間は、前記駆動トランジスタのゲート及びソース間電圧を、前記駆動トランジスタの閾値電圧に応じた電圧にする期間である、請求項９に記載の表示装置。 The display device according to claim 9, wherein the predetermined period is a period in which the gate-source voltage of the drive transistor is set to a voltage corresponding to the threshold voltage of the drive transistor.
  12. 　前記発光素子は、前記信号電圧に基づいて前記駆動トランジスタを流れる電流に応じた輝度で発光する、請求項１に記載の表示装置。 The display device according to claim 1, wherein the light emitting element emits light with a brightness corresponding to a current flowing through the drive transistor based on the signal voltage.
PCT/JP2021/044153 2020-12-10 2021-12-01 Display device WO2022124165A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018200441A (en) * 2017-05-29 2018-12-20 キヤノン株式会社 Light-emitting device and imaging apparatus
JP2019082548A (en) * 2017-10-30 2019-05-30 ソニーセミコンダクタソリューションズ株式会社 Pixel circuit, display device, driving method of pixel circuit, and electronic apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018200441A (en) * 2017-05-29 2018-12-20 キヤノン株式会社 Light-emitting device and imaging apparatus
JP2019082548A (en) * 2017-10-30 2019-05-30 ソニーセミコンダクタソリューションズ株式会社 Pixel circuit, display device, driving method of pixel circuit, and electronic apparatus

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