CN111862890B

CN111862890B - Display panel, driving method thereof and display device

Info

Publication number: CN111862890B
Application number: CN202010887320.9A
Authority: CN
Inventors: 张蒙蒙; 高娅娜; 周星耀
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2022-05-24
Anticipated expiration: 2040-08-28
Also published as: CN114999396A; CN111862890A

Abstract

The application discloses a display panel, which comprises a pixel and a driving circuit for driving the pixel; the driving circuit comprises a driving transistor, wherein the grid electrode of the driving transistor is a first node; the scanning lines and the data lines are arranged in a crossed manner; the scanning lines and the data lines are connected with a driving circuit; a first parasitic capacitor is included between the data line and the first node; the anti-flicker module is used for providing a coupling signal to the data line in a holding stage in the first display mode; the first display mode comprises refresh phases and said holding phases between adjacent refresh phases. The display panel can reduce leakage current and prevent the display panel from flickering under low-frequency driving.

Description

Display panel, driving method thereof and display device

Technical Field

The present disclosure generally relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.

Background

With the development of display technology, wearable devices increasingly employ Organic Light Emitting (OLED) display panels. Wearable devices, such as watches, do not have high requirements for display effects, but have a need for low power consumption. However, the organic light emitting display panel is driven by current, and the driving current of the pixel driving circuit generating the driving circuit is determined by the voltage difference between the source and the gate of the driving transistor. The source of the driving transistor receives a power supply voltage, and the gate of the driving transistor receives a data signal voltage and stores the data signal voltage in the storage capacitor. The channel leakage and the film leakage cause the voltage of the data signal stored in the grid electrode of the driving transistor to change, thereby causing the brightness jump and the phenomenon of flicker.

Disclosure of Invention

In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a display panel and a display device, which are intended to solve the technical problems in the prior art.

In one aspect, the present application discloses a display panel, a pixel, and a driving circuit driving the pixel; the driving circuit comprises a driving transistor, wherein the grid electrode of the driving transistor is a first node;

the scanning lines and the data lines are arranged in a crossed manner; the scanning lines and the data lines are connected with the driving circuit; a first parasitic capacitance is included between the data line and the first node;

the anti-flicker module is used for providing a coupling signal to the data line in a holding stage in a first display mode; the first display mode includes refresh phases and the hold phases between adjacent ones of the refresh phases.

In another aspect, the present application discloses a method of driving a display panel, the display panel including: a pixel, and a driving circuit that drives the pixel; the driving circuit comprises a driving transistor, wherein the grid electrode of the driving transistor is a first node;

The driving method includes: the display driving method comprises a first display driving mode and a second display driving mode, wherein the display refresh rate of the first display driving mode is smaller than that of the second display driving mode;

in a first display mode, the display device comprises a refreshing stage and a maintaining stage, wherein the maintaining stage is positioned between adjacent refreshing stages; providing a coupling signal to the data line during the hold phase.

In another aspect, the present application provides a display device including the display panel as described above.

According to the display panel and the display device, leakage current can be reduced, and the phenomenon that the display panel flickers under low-frequency driving is prevented.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a diagram illustrating the variation of the gate potential of a driving transistor in the prior art;

FIG. 2 shows a schematic view of a display panel in an embodiment of the present application;

FIG. 3 shows an equivalent circuit schematic of the drive circuit at X in FIG. 2;

fig. 4 shows a schematic diagram of the layout of the drive circuit at X in fig. 2 as viewed from the light exit surface;

FIG. 5 shows a schematic diagram of the layout of the drive circuit at X in FIG. 2 as viewed from the non-light-exiting face;

FIG. 6 illustrates a cross-sectional view of a display panel of an embodiment of the present application;

FIG. 7 shows a timing diagram for a display panel of 60Hz according to one embodiment of the present application;

FIG. 8 shows a timing diagram for a display panel 15Hz according to one embodiment of the present application;

FIG. 9 shows a timing diagram for a display panel 15Hz according to another embodiment of the present application;

FIG. 10 is a timing diagram of a display panel in another embodiment of the present application;

fig. 11 shows a schematic view of a display device in an embodiment of the present application.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Wearable devices, such as watches, do not have high requirements for display effects, but have a need for low power consumption. Therefore, in order to reduce power consumption, products such as watches and the like generally adopt a low-frequency driving mode to reduce power consumption, but unlike the low-frequency driving of the liquid crystal display panel, the low-frequency driving of the OLED display panel has a problem of flickering. As a result of the analysis by the inventors, it was found that, since the organic light emitting display panel is driven by a current, the driving current of the pixel driving circuit generating the driving circuit is determined by the voltage difference (Vgs) between the source and the gate of the driving transistor. The source of the driving transistor receives a power supply voltage, and the gate of the driving transistor receives a data signal voltage and stores the data signal voltage in the storage capacitor. The power supply voltage is an active signal, and the data signal voltage is stored in the storage capacitor. But the voltage of the data signal stored at the gate of the driving transistor varies due to channel leakage and film leakage. And the Vgs changes when the point Vg of the grid electrode of the driving transistor changes, so that the brightness jumps and the phenomenon of flicker occurs. In the normal driving frequency, for example, in the 60Hz mode, the time of one frame is 16.67ms, the potential change of the driving transistor gate (N1) is as shown in fig. 1, the potential of the N1 node is reduced a little at 60Hz, the luminance change is small, and the human eye can not easily recognize the change. However, at 30Hz, the time of one frame becomes 33.33ms, the drop value of the potential at the N1 node is relatively large, and the frequency is reduced, so that human eyes can observe flicker. Further, the time of the next frame at 15Hz becomes 66.67ms, the drop value of the potential of the N1 node is larger, and the frequency is reduced more, so that the human eye can observe flicker significantly. Resulting in the unavailability of low frequency driving, limiting the reduction of power consumption of the OLED display panel.

In an embodiment of the present application, please refer to fig. 2 to 8, fig. 2 is a schematic diagram of a display panel in an embodiment of the present application; FIG. 3 shows an equivalent circuit schematic of the drive circuit at X in FIG. 2; fig. 4 shows a schematic diagram of the layout of the driving circuit at X in fig. 2 as viewed from the light exit surface; FIG. 5 shows a schematic diagram of the layout of the drive circuit at X in FIG. 2 as viewed from the non-light-exiting face; FIG. 6 illustrates a cross-sectional view of a display panel of an embodiment of the present application; FIG. 7 shows a timing diagram for a display panel of 60Hz according to one embodiment of the present application; FIG. 8 shows a timing diagram for a display panel 15Hz according to one embodiment of the present application;

the display panel of the present application includes: a pixel P, and a drive circuit PC that drives the pixel P; the driving circuit PC comprises a driving transistor M3, wherein the gate of the driving transistor M3 is a first node N1; the scanning lines 100 and the data lines 200 are arranged in a crossed manner; the scanning lines 100 and the data lines 200 are connected with the driving circuit PC;

here, the driving circuit of fig. 3 is explained as an example. The present embodiment further includes a first light emission controlling transistor M1 in addition to the driving transistor M3, the first light emission controlling transistor M1 is controlled by a light emission control signal Emit to provide a first power voltage signal PVDD to the driving transistor M3; and a second light emission control transistor connected in series between the driving transistor M3 and the light emitting element, and controlled by the light emission control signal Emit to control whether or not the driving current passes through the light emitting element. A data write transistor M2, the data write transistor M2 controlled by a second scan signal S2 to transmit a data signal Vdata to the driving transistor M3; the compensation transistor M4 is controlled by the second scan signal S2 for detecting and self-compensating the deviation of the threshold voltage of the driving transistor M3; the first initialization transistor M5 provides an initialization signal to the gate of the driving transistor under the control of a first scan signal S1; the second initialization transistor M7 supplies an initialization signal to the organic light emitting element under the control of the first scan signal S1 or the second scan signal S2. The scan line 100 supplies the first scan signal S1, the second scan signal S2, and the emission control signal Emit to the driving circuit. The data line 200 supplies a data signal voltage Vdata to the pixel circuit.

In the initialization phase: the first scan signal S1 provides an active level, the second scan signal and the light emission control signal provide an off level; the first initialization transistor M5 is turned on, the initialization signal Vref is transmitted to the gate of the driving transistor M3, and initialization is performed on the driving transistor M3, at this time, the potential of the node N1 of the gate of the driving transistor M3 is Vref;

in the compensation stage: the first scan signal S1 provides an off level, the second scan signal provides an active level, and the light emission control signal provides an off level; the data writing transistor M2 and the compensation transistor M4 are turned on, the data signal voltage Vdata is transmitted from the data writing transistor to the first pole of the driving transistor M3, at this time, the driving transistor M3 meets the condition of being turned on, so that the driving transistor M3 is turned on, the data signal voltage is transmitted to the N1 node through the driving transistor M3 and the compensation transistor M4, the potential of the N1 node is raised, until the potential difference between the gate of the driving transistor and the first pole is the threshold voltage Vth of the driving transistor M3, the driving transistor M3 is turned off, the potential of the N1 node cannot be raised continuously, and at this time, the potential of the N1 node is vd- | Vth |.

In the light emitting stage: the first and second scan signals S1 and S2 provide off levels, and the light emission control signal provides an active level; the first and second light emission control transistors M1 and M2 are turned on, the first light emission control transistor M1 transmits the first power voltage PVDD to the source of the driving transistor, and the light emission current is Ids ═ k ═ Vgs-Vth ^2 ═ k ^ (PVDD-Vdata) ^ 2. Therefore, the light emission current is independent of the threshold voltage, so that the driving transistor compensates for the deviation of the threshold voltage.

Referring to the layout in fig. 4 and fig. 5 and the film structure diagram in fig. 6, the initialization signal line 110 transmits an initialization signal Vref, the first scan signal line 101 transmits a scan signal S1, and the second scan signal line 102 transmits a second scan signal S2; the light emission signal line 103 supplies a light emission control signal Emit; the power signal line 210 transmits the power signal PVDD, and the lateral power signal line 120 is connected to the power signal line 210 through a via hole, transmits the power signal PVDD, and serves as one pole of the storage capacitor. Referring to fig. 6, the semiconductor layer in the pixel driving circuit is made of poly, and the first scanning signal line 101, the second scanning signal line 102 and the light emitting signal line 103 are located on the gate metal layer M1 to serve as the gate of the transistor. The signal line 110 is initialized, the lateral power signal line 120 is located at the capacitance metal layer Mc, and the power signal line 210 and the data line 200 are located at the source-drain metal layer M2. Meanwhile, the pixel P includes a light emitting element including an anode 500, a cathode 700, and an organic light emitting material 600 between the cathode and the anode, and the anode 500 is connected to the drain M2 of the transistor through a via hole.

In low-frequency driving, the potential of the gate N1 node of the driving transistor M3 needs to be held for too long, and the leakage current causes the potential of the N1 node to continuously change, for example: the leakage of the M5 transistor causes the N1 node potential to be continuously pulled down by Vref, so the light emitting current Ids continuously increases, and the brightness rise occurs. Alternatively, the potential at the node N1 is pulled low by interlayer leakage. And the brightness is rapidly reduced after the data signal voltage is written in the next frame, so that the human eye observes the phenomenon of flickering.

The invention is arranged in the layout of a driving circuit PC, and a first parasitic capacitor Ca is arranged between a data line 200 and the first node N1; referring to fig. 4, 5 and 6, a portion of the C1 of the data line 200 and a portion of the N1 node are close to each other, i.e., C2, resulting in a parasitic capacitance therebetween. Therefore, in the present application, the anti-flicker module 30 is disposed on the display panel, and in the first display mode, the anti-flicker module 30 is configured to provide the coupling signal to the data line in the hold phase; the coupling signal on the data line is transmitted to the gate first node N1 of the driving transistor through the parasitic capacitance Ca, and the potential variation of the N1 node is offset, thereby improving or even eliminating the flicker phenomenon. In this application, the coupled signal refers to a difference from a signal at a previous time. For example: when the signal on the data line is 1v and the coupling signal is 2v at the previous time, 3v of signal needs to be provided to the data line.

The first display mode comprises a refresh phase and the hold phase between adjacent ones of the refresh phases; the display panel also comprises a second display mode, and the display refresh rate of the second display mode is greater than that of the first display mode; the display refresh rate of the first display mode is 30Hz or less. Referring to fig. 7 and 8, fig. 7 shows a second display mode (normal driving mode), and fig. 8 shows a first display mode (low frequency driving mode). In the first display mode, although the time per frame is increased, the time for refreshing data is not increased in the present application. For example: under the condition that the second display mode is 60Hz and the first display mode is 15Hz, the time of one frame in the second display mode is 16.67ms, and the time of the refreshing stage is equal to 16.67 ms; the first display mode has a frame time of 66.67ms, wherein the time of the refresh phase is 16.67ms, and the time of three hold phases of the hold phases between two adjacent refresh phases is 16.67ms each. In the first display mode, in the holding phase, the anti-flicker module 30 provides a coupling signal to the data line; the coupling signal on the data line is transmitted to the gate first node N1 of the driving transistor through the parasitic capacitance Ca, and the potential variation of the N1 node is offset, thereby improving or even eliminating the flicker phenomenon.

The application also provides a driving method of the display panel, which is used for driving the display panel. The display panel includes pixels P, and a driving circuit PC that drives the pixels P; the driving circuit comprises a driving transistor M3, wherein the gate of the driving transistor M3 is a first node N1; the scanning lines 100 and the data lines 200 are arranged in a crossed manner; the scanning lines 100 and the data lines 200 are connected with a driving circuit PC; a first parasitic capacitance Ca is included between the data line 200 and the first node N1; the driving method includes: the display driving method comprises a first display driving mode and a second display driving mode, wherein the display refresh rate of the first display driving mode is smaller than that of the second display driving mode;

in a first display mode, the display device comprises a refreshing stage and a maintaining stage, wherein the maintaining stage is positioned between adjacent refreshing stages; in the hold phase, a coupling signal is provided to the data line 200. The coupling signal on the data line is transmitted to the gate first node N1 of the driving transistor through the parasitic capacitance Ca, and the potential variation of the N1 node is offset, thereby improving or even eliminating the flicker phenomenon.

Further, the anti-flicker module 30 further comprises a multiplexer 40, wherein the multiplexer 40 comprises a plurality of multiplexer units 41, each of which comprises 1 input terminal 411, N output terminals 412 and N control terminals; each output end 412 is correspondingly connected with the data line 200; n is an integer not less than 2; taking N-2 as an example in fig. 2, each multiplexer unit 41 includes 1

input terminal

411 and 2 output terminal 412 and two control terminals CKH1 and CKH2, and when CKH1 is active, the data signal is transmitted to the data line corresponding to CKH1 through input terminal 411, and when CKH2 is active, the data signal is transmitted to the data line corresponding to CKH2 through input terminal 411.

In the first display mode, N control terminals turn on alternately, and the input terminal 411 outputs data signals to the output terminal 412 in turn; referring to fig. 7, CKH1 and CKH2 are alternately turned on before the active pulse of SCAN1, and data signals are written to the data lines 200 of the odd and even columns, respectively, and are stored in the parasitic capacitances of the data lines, respectively. When the SCAN1 outputs an active level, a data signal is written to the gate of the driving transistor M3. After the active pulse of SCAN1, before the active pulse of SCAN2, CKH1 and CKH2 turn on again alternately, and data signals are written again to the data lines 200 of the odd and even columns, respectively, and are stored in parasitic capacitances storing the data lines, respectively. When the SCAN2 outputs an active level, a data signal is written to the gate of the driving transistor M3. And so on. It should be noted that SCAN1 represents the second SCAN signal S2 of the first row, SCAN2 represents the second SCAN signal S2 of the second row, and so on. EMIT1 represents the light emission control signal EMIT of the first row. Here, fig. 7 shows only the light emission control signal of the first row.

In an embodiment of the present application, referring to fig. 8, in the second display mode, in the refresh phase, N controlled terminal streams are turned on, and the input terminal stream outputs a data signal to the output terminal; in the holding stage, each control terminal is started at least once, and the output terminal transmits a coupling signal to the data line. Specifically, in the refresh phase, CKH1 and CKH2 are alternately turned on before the active pulse of SCAN1, and data signals are written to the data lines 200 of the odd and even columns, respectively, and are stored in the parasitic capacitances of the data lines, respectively. When the SCAN1 outputs an active level, a data signal is written to the gate of the driving transistor M3. After the active pulse of SCAN1, before the active pulse of SCAN2, CKH1 and CKH2 turn on again alternately, and data signals are written again to the data lines 200 of the odd and even columns, respectively, and are stored in parasitic capacitances storing the data lines, respectively. When the SCAN2 outputs an active level, a data signal is written to the gate of the driving transistor M3. In the hold phase, CKH1 and CKH2 are turned on at least once, and a coupling signal is provided to the data line 200 through the input terminal 411 and coupled to the gate N1 of the driving transistor through the voltage difference of the data line to compensate for the leakage of N1, thereby preventing flicker.

Further, referring to fig. 8, CKH1 and CKH2 are turned on alternately, the output terminal 412 sequentially transmits a coupling signal to the data line 200, the voltage of the first node N1 is changed by the first parasitic capacitor Ca, CKH1 and CKH2 are turned on sequentially, the coupling signal is provided to the data line 200 through the input terminal 411, and the coupling signal is coupled to the gate N1 of the driving transistor through the voltage difference of the data line to compensate for the leakage of N1, thereby preventing flicker. The current efficiency of different sub-pixels is different, for example, the driving current of the blue sub-pixel is higher than that of the red and green sub-pixels, so that the coupling signal of the blue sub-pixel is larger when the same brightness needs to be compensated. Therefore, the present embodiment can adopt a single data line for the blue sub-pixel, and different potentials can be coupled to the N1 nodes corresponding to the sub-pixels of different colors by turning on the CKH1 and the CKH2 in turn. For example: a greater coupled signal is coupled to the blue subpixel. Specifically, further, the display panel includes: red pixel R, green pixel G, and blue pixel B; the anti-flicker module 30 provides a first coupling signal to the data lines corresponding to the red pixel R and the green pixel G, and provides a second coupling signal to the data lines corresponding to the blue pixel B, where the second coupling signal is greater than the first coupling signal.

Alternatively, referring to fig. 9, the output terminal 412 simultaneously transmits the coupling signal to the data line 200, the voltage of the first node N1 is changed by the first parasitic capacitor Ca, the CKH1 and the CKH2 are simultaneously turned on, the coupling signal is provided to the data line 200 through the input terminal 411, and the coupling signal is coupled to the gate N1 of the driving transistor through the voltage difference of the data line to compensate the leakage of the N1, thereby avoiding the flicker. In this way, the time for coupling can be saved, and all the sub-pixels of the display panel are coupled at the same time without being coupled in columns, thereby avoiding the leakage of the N1 node at different times caused by the coupling in columns, for example, the N1 node is compensated in the odd-numbered rows, but the N1 node is not compensated in the even-numbered rows, so that the strong contrast can be perceived by human eyes, and the coupling at the same time can avoid the problem.

Further, since the voltage of the data signal written into the data line 200 at the end of the refresh period depends on the luminance information of the sub-pixels in the last row, this luminance information is different in each column. The coupling signal is the target potential newly written into the data line minus the residual potential of the data line at the previous moment. If the residual potential of each column at the previous time is different, the target potential to be written needs to be calculated from the residual potential at the previous time, which increases the load on the IC. Thus, in this embodiment, an initialization signal is provided to the data lines after the refresh phase and before the hold phase. Therefore, the residual potential of each column is the same, so that the difference value of the target potential and the initialization signal is the coupling signal, the calculation difficulty of the coupling signal is greatly reduced, the burden of an IC is reduced, and the power consumption of the display panel is reduced.

Referring further to fig. 8 and 9, the display panel further includes a second display mode; the display refresh rate of the first display mode is Q, and the display refresh rate of the second display mode is P; the first display mode comprises a refresh phase and M maintaining phases which are circularly set; wherein the M holding phases include a first holding phase to an Mth holding phase; m is an integer greater than or equal to 2;

for example, when the second display mode is 60Hz, and the first display mode is 15Hz, the time of one frame in the second display mode is 16.67ms, and the time of the refresh phase is equal to 16.67 ms; the time of one frame of the first display mode is 66.67ms, wherein the time of the refresh phase is 16.67ms, and the time of 3 holding phases of the holding phases between two adjacent refresh phases is 16.67ms each. In the first display mode, in the holding phase, the anti-flicker module 30 provides a coupling signal to the data line; the coupling signal on the data line is transmitted to the gate first node N1 of the driving transistor through the parasitic capacitance Ca, and the potential variation of the N1 node is offset, thereby improving or even eliminating the flicker phenomenon. The anti-flicker module 30 sequentially provides a 1 st coupled signal to a 3 rd coupled signal to the data line in a 1 st holding stage to a 3 rd holding stage; the first coupled signal is less than the second coupled signal, and the second coupled signal is equal to the mth coupled signal. Since the data signals are alternately written from the first row to the last row at the first coupling of the first holding period, the parasitic capacitances are present between the data lines and the first nodes N1 of all rows, and thus, are coupled to the N1 node at the same time. However, according to the foregoing, the leakage time from the first row to the last row is different, the leakage time from the first row is the longest, and the leakage time from the last row is the shortest, so that in the embodiment, the first-time coupling signal is calculated based on the leakage time substantially in the middle row, and therefore, the leakage time involved in the calculation is relatively short, and the first-time coupling signal is relatively idle. After the first coupling, all rows are drained for a hold period, so the second to mth coupled signals are all the same and all are larger than the first coupled signal. The arrangement according to this embodiment can avoid first-time overcompensation.

In another embodiment of the present application, the first node N1 is coupled by the parasitic capacitance of the data line to compensate the leakage current. When the multiplexer writes the coupling signal into the data line, the parasitic capacitance on the data line is charged essentially. When the parasitic capacitor is charged, the potential on the data line cannot jump to the target potential immediately, but a rising edge or a falling edge occurs, and when the coupling signal is larger, the time for rising or falling to the target potential is longer, so in this embodiment, the on-duration of the control signal is proportional to the absolute value of the coupling signal. So that, even if the coupling signal is relatively large, there is sufficient charging time at the target potential. Specifically, for example: at the end of the refresh period, the potential of the data line is 1V, the coupling signals are 1V and 5V, respectively, when the coupling signal is 1V, the target potential is 2V, and writing the 2V potential into the data line only needs to raise the potential by 1V, so that the duration of the rising edge is relatively short, for example, 0.5 μ s, and the on time of the control signal can be 2 μ s, thus having a charging time of 1.5 μ s at the target potential. When the coupling signal is 5V, the target potential is 6V, and writing the potential of 6V to the data line requires raising the potential by 5V, so that the duration of the rising edge is longer, for example, 1 μ s, and the on time of the control signal can be 2.5 μ s, so that there is still a charging time of 1.5 μ s at the target potential. Therefore, the on-time of the control signal can be set according to the size of the coupling signal, and the phenomenon that insufficient charging occurs when the absolute value of the coupling signal is too large is avoided, so that insufficient compensation is caused.

Further, in order to avoid the transition of brightness in a short time when the coupling signal is written into the data line, the first node N1 will transition in a short time, and in this embodiment, the method further includes: a light emission control signal EMIT and front and rear porches; the light emission control signal EMIT is a PWM modulation signal; when the control terminal is turned on, the light emission control signal EMIT is a valid signal in both the front and rear lanes. Referring to fig. 10, fig. 10 is a schematic diagram of a display panel according to another embodiment of the present application; pulse Width Modulation (PWM) is implemented by using Pulse trains with equal Pulse widths as PWM waveforms, changing the period of the Pulse trains to adjust frequency, changing the width or duty ratio of the pulses to adjust brightness, and adopting a proper control method to coordinate and change voltage and frequency. The purpose of controlling the brightness can be achieved by adjusting the period of the PWM and the duty ratio of the PWM. In the figure, it1 denotes a light emission control signal of the first row, it2 denotes a light emission control signal of the second row, and so on, and it12 denotes a light emission control signal of the 12 th row. In the present embodiment, 12 behavior examples are used, but the present application does not limit this. The light emission control signal of the present embodiment may be to control the first light emission control transistor M1 and the second light emission control transistor M6 in fig. 3 to control whether or not a current flows through the light emitting element. When the light-emitting control signal is at the cut-off level, the pixels in the current row do not emit light; when the light-emitting control signal is at the on level, the pixels in the current row emit light. The light emission control signal is transmitted stage by stage through the shift register circuit, and as indicated by the arrows in the figure, the light emission control signal is "scrolling" and the display panel is also "scrolling" displaying. Therefore, at a certain time t1, the light emission control signals of some pixel rows are active level, the pixels of these rows emit light, and these pixel rows form a bright band. The light emission control signals of the other pixel rows are at the off level, the pixels of the rows do not emit light, and the pixel rows form dark bands. Further, the display panel preferably includes front and rear porches, which do not correspond to actual pixels and are virtual lines, in addition to the display lines, and the front and rear porches are waiting stages for loading data signals. In this embodiment, the light emission control signals in the front and rear porches are both active levels, so that the bright band is located in the front and rear porches, but the front and rear porches are not light-emitting, and therefore, the number of lines of the bright band in the actual display area is the minimum, and the number of lines displayed by the change of the coupling signal is the minimum, thereby avoiding the perception of human eyes.

On the other hand, the inventors have studied to find that the sensitivity of human eyes to luminance is related to the luminance value before the change. When the brightness value is low, a momentary brightness increase or brightness decrease can be perceived clearly. When the brightness is relatively high, the brightness is raised or lowered instantly and is hardly perceived.

In this embodiment, the first display mode includes a low gray scale mode and a high gray scale mode, and in the high gray scale mode, the anti-flicker module 30 provides the third coupling signal to the data line 200; in the low gray scale mode, the anti-flicker module 30 provides the fourth coupling signal to the data line 200; the fourth coupled signal is less than the third coupled signal. Therefore, the phenomenon that the coupling signal is too large to cause flicker under the low gray scale can be avoided, and the condition that the compensation value is insufficient under the high gray scale is also avoided.

The display device of the present application may be any device including the driving unit as described above, including but not limited to a cellular phone 1000, a tablet computer, a display of a computer, a display applied to a smart wearable device, a display applied to a vehicle such as an automobile, and the like as shown in fig. 11. The display device is considered to fall within the scope of protection of the present application as long as the display device includes the driving unit included in the display device disclosed in the present application.

According to the foldable display panel and the display device, the risk of wire breakage can be reduced, the driving capability is improved, and the display effect and the display stability are enhanced.

It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A display panel, comprising,

a pixel, and a driving circuit that drives the pixel; the driving circuit comprises a driving transistor, wherein the grid electrode of the driving transistor is a first node;

the anti-flicker module is used for providing a coupling signal to the data line in a holding stage in a first display mode; the first display mode comprises a refresh phase and the hold phase between adjacent ones of the refresh phases;

The display panel further comprises a second display mode; the display refresh rate of the first display mode is Q, and the display refresh rate of the second display mode is P;

the first display mode comprises a refresh phase and M maintaining phases which are circularly set; wherein the M holding phases include a first holding phase to an Mth holding phase; m is an integer greater than or equal to 2;

the anti-flicker module provides a first coupling signal to an Mth coupling signal to the data line in the first holding stage to the Mth holding stage in sequence;

the first coupling signal is smaller than the second coupling signal, and the second coupling signal is equal to the Mth coupling signal.

2. The display panel according to claim 1,

the display refresh rate of the first display mode is less than or equal to 30 Hz.

3. The display panel according to claim 1,

the anti-flicker module comprises a multiplexer, the multiplexer comprises a plurality of multiplexer units, and each multiplexer unit comprises 1 input end, N output ends and N control ends; each output end is correspondingly connected with the data line; n is an integer not less than 2;

the display panel also comprises a second display mode, and the display refresh rate of the second display mode is greater than that of the first display mode;

In a first display mode, the N control ends are turned on in turn, and the input end turns to output data signals to the output end;

in a second display mode, in a refreshing stage, N control ends are turned on in turn, and the input end turns to output data signals to the output end; in the holding stage, each control terminal is turned on at least once, and the output terminal transmits a coupling signal to the data line.

4. The display panel according to claim 3,

in a second display mode, in a refreshing stage, N control ends are turned on in turn, and the input end turns to output data signals to the output end;

in the maintenance phase, the temperature of the substrate is maintained,

the control terminals are sequentially turned on, the output terminal sequentially transmits a coupling signal to the data line, and the first node voltage is changed by the first parasitic capacitance, or

The control ends are simultaneously started, the output end simultaneously transmits coupling signals to the data lines, and the first node voltage is changed through the first parasitic capacitance.

5. The display panel according to claim 3, comprising:

in the hold phase, the on-duration of the control terminal is proportional to the absolute value of the coupling signal.

6. The display panel according to claim 3, characterized by further comprising: a lighting control signal and front and rear lanes; the light-emitting control signal is a PWM modulation signal;

when the control end is started, the light-emitting control signals are all effective signals in the front corridor and the rear corridor;

the front and back porches do not correspond to the pixels, the front and back porches do not scan the pixels, and the front and back porches are waiting stages for loading the data signals.

7. The display panel according to claim 1,

after the refresh phase, and before the hold phase, an initialization signal is provided to the data lines.

8. The display panel according to claim 1, comprising:

red, green and blue pixels; the anti-flicker module provides a first coupling signal to the data lines corresponding to the red pixel and the green pixel, and provides a second coupling signal to the data lines corresponding to the blue pixel, wherein the second coupling signal is greater than the first coupling signal.

9. The display panel according to claim 1,

the first display mode comprises a low gray scale mode and a high gray scale mode, and in the high gray scale mode, the anti-flicker module provides a third coupling signal for the data line; in the low gray scale mode, the anti-flicker module provides a fourth coupling signal to the data line; the fourth coupled signal is less than the third coupled signal.

10. A method for driving a display panel is characterized in that,

the display panel includes: a pixel, and a driving circuit that drives the pixel; the driving circuit comprises a driving transistor, wherein the grid electrode of the driving transistor is a first node;

the driving method includes: the display device comprises a first display mode and a second display mode, wherein the display refresh rate of the first display mode is smaller than that of the second display mode;

in a first display mode, the display device comprises a refreshing stage and a maintaining stage, wherein the maintaining stage is positioned between adjacent refreshing stages; providing a coupling signal to the data line during the hold phase;

the display refresh rate of the first display mode is Q, and the display refresh rate of the second display mode is P;

Providing a first coupling signal to an Mth coupling signal to the data line in the first to Mth holding phases;

11. A display device comprising the display panel according to any one of claims 1 to 9.