CN113903307B - Signal providing method, signal providing module and display device - Google Patents
Signal providing method, signal providing module and display device Download PDFInfo
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- CN113903307B CN113903307B CN202111228557.7A CN202111228557A CN113903307B CN 113903307 B CN113903307 B CN 113903307B CN 202111228557 A CN202111228557 A CN 202111228557A CN 113903307 B CN113903307 B CN 113903307B
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- 230000007423 decrease Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000011664 signaling Effects 0.000 description 3
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- 230000005669 field effect Effects 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a signal providing method, a signal providing module and a display device. The signal providing method is applied to a driving circuit in a display device, the driving circuit is electrically connected with a clock signal end and is used for providing a driving signal, when the display device works in a low-frequency driving mode, a display period comprises a refreshing stage and a holding stage, and the signal providing method comprises the following steps: and in the holding stage, controlling the duty ratio of the signal provided by the clock signal terminal to be smaller than or equal to a duty ratio threshold value. The invention can realize low-frequency driving and reduce power consumption.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a signal providing method, a signal providing module, and a display device.
Background
In the related art, LTPO (low temperature poly oxide) technology is used to realize low refresh frequency display, and when the display device operates in a low frequency driving mode, one frame time may include a refresh stage and a hold stage, which are disposed sequentially, for example. The transistors of the LTPO pixel circuit may be electrically connected to a plurality of scan lines, at least one of the scan lines is not turned on in the hold phase, that is, the potential of the scan signal provided by the at least one scan line is an inactive voltage, but in the related art, the clock signal terminal connected to the driving circuit for generating the scan signal still outputs the clock signal normally in the hold phase, so that the power consumption is high.
Disclosure of Invention
The invention mainly aims to provide a signal providing method, a signal providing module and a display device, which solve the problem that the existing display device can not realize low-frequency driving and reduce power consumption.
In order to achieve the above object, an embodiment of the present invention provides a signal providing method applied to a driving circuit in a display device, the driving circuit being electrically connected to a clock signal terminal and configured to provide a driving signal, a display period including a refresh phase and a hold phase when the display device is operated in a low frequency driving mode, the signal providing method including:
and in the holding stage, controlling the duty ratio of the signal provided by the clock signal terminal to be smaller than or equal to a duty ratio threshold value.
Optionally, the duty cycle threshold is greater than or equal to 5% and less than or equal to 45%.
Optionally, the driving circuit is electrically connected to a first node, a second node, a first voltage end, a second voltage end and a driving signal output end, and is configured to control, under control of a potential of the second node, communication between the driving signal output end and the first voltage end, and control, under control of a potential of the first node, communication between the driving signal output end and the second voltage end, where the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage end is an ineffective voltage signal; the signal providing method includes:
Controlling the first voltage terminal to provide a first voltage signal in the refreshing stage;
and in the holding stage, controlling the clock signal terminal to output a direct-current voltage signal and controlling the first voltage terminal to provide a second voltage signal.
Optionally, the display device includes a display panel, the display panel includes a plurality of pixel circuits, and the driving circuit is configured to provide the driving signals for the pixel circuits; the pixel circuit is electrically connected with the data line and receives the data voltage from the data line; the holding stage includes a plurality of holding periods, and an output period disposed between adjacent two-dimensional holding periods;
the signal providing method includes:
in the maintaining time period, controlling the clock signal end to output a direct-current voltage signal;
in the output time period, the clock signal terminal is controlled to output a corresponding clock signal;
the duration of the sustain period is an interval time.
Optionally, a sampling phase is further included before the display period; the signal providing method further includes:
in the sampling stage, controlling the clock signal end to output the direct-current voltage signal, controlling the data line to provide unchanged data voltage, detecting the display brightness of the display panel, and recording corresponding change time when detecting that the brightness change reaches a brightness change value threshold;
The interval time is greater than a preset threshold time and less than or equal to the change time.
Optionally, the dc voltage signal is a high voltage signal, and in the output period, when the potential of the clock signal is a low voltage, a difference between the voltage value of the high voltage signal and the voltage value of the clock signal is unchanged.
Optionally, the display panel displays a low-brightness picture, the direct-current voltage signal is a high-voltage signal, and in the output time periods, when the potential of the clock signal is a low voltage, the difference between the voltage value of the high-voltage signal and the voltage value of the clock signal gradually decreases.
Optionally, the display panel displays a high brightness picture, the direct current voltage signal is a high voltage signal, and in the output time periods, when the potential of the clock signal is a low voltage, the difference between the voltage value of the high voltage signal and the voltage value of the clock signal is gradually increased.
Optionally, the clock signal terminal includes a first clock signal terminal and a second clock signal terminal.
The embodiment of the invention also provides a signal providing module, which is applied to a driving circuit in a display device, wherein the driving circuit is electrically connected with a clock signal end and is used for providing a driving signal, and the signal providing module is characterized in that when the refresh frequency of the display device is smaller than a preset frequency, a display period comprises a refresh stage and a holding stage, and the signal providing module comprises:
And the first signal providing circuit is used for controlling the duty ratio of the signal provided by the clock signal terminal to be smaller than or equal to a duty ratio threshold value in the holding stage.
Optionally, the driving circuit is electrically connected to a first node, a second node, a first voltage end, a second voltage end and a driving signal output end, and is configured to control, under control of a potential of the second node, communication between the driving signal output end and the first voltage end, and control, under control of a potential of the first node, communication between the driving signal output end and the second voltage end, where the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage end is an ineffective voltage signal; the signal providing module further comprises a second signal providing circuit;
the first signal providing circuit is used for controlling the clock signal end to output a direct-current voltage signal in the holding stage;
the second signal providing circuit is used for controlling the first voltage terminal to provide a first voltage signal in the refreshing stage and controlling the first voltage terminal to provide a second voltage signal in the maintaining stage.
Optionally, the second signal providing circuit includes a control circuit and a control switch circuit; the control switch circuit comprises a first control transistor and a second control transistor;
The control electrode of the first control transistor is electrically connected with a first control line, the first electrode of the first control transistor is electrically connected with a second voltage line, and the second electrode of the first control transistor is electrically connected with the first voltage end; the second voltage line is used for providing a second voltage signal;
the control electrode of the second control transistor is electrically connected with a second control line, the first electrode of the second control transistor is electrically connected with a first voltage line, and the second electrode of the second control transistor is electrically connected with the first voltage end; the first voltage line is used for providing a first voltage signal;
the control circuit is configured to provide an inactive first control signal to the first control line to turn off the first control transistor, an active second control signal to the second control line to turn on the second control transistor during the refresh phase, and to provide an active first control signal to the first control line to turn on the first control transistor and an inactive second control signal to the second control line to turn off the second control transistor during the hold phase.
Optionally, the display device includes a display panel, the display panel includes a plurality of pixel circuits, and the driving circuit is configured to provide the driving signals for the pixel circuits; the pixel circuit is electrically connected with the data line and receives the data voltage from the data line; the holding stage includes a plurality of holding periods, and an output period disposed between adjacent two-dimensional holding periods;
The first signal providing circuit is used for controlling the clock signal terminal to output a direct-current voltage signal in the maintaining time period, and controlling the clock signal terminal to output a corresponding clock signal in the output time period;
the duration of the sustain period is an interval time.
Optionally, the display panel displays a low-brightness picture, the direct-current voltage signal is a high-voltage signal, and the first signal providing circuit is configured to gradually decrease, in a plurality of output periods, a difference between a voltage value of the high-voltage signal and a voltage value of the clock signal when the potential of the clock signal is a low voltage.
Optionally, the display panel displays a high brightness picture, the direct current voltage signal is a high voltage signal, and the first signal providing circuit is configured to gradually increase a difference between a voltage value of the high voltage signal and a voltage value of the clock signal when the potential of the clock signal is a low voltage in a plurality of output time periods.
The embodiment of the invention also provides a display device which comprises the signal providing module.
Optionally, the display device includes a display panel and a driving integrated circuit; the signal providing module further comprises a second signal providing circuit, wherein the second signal providing circuit comprises a control circuit and a control switch circuit;
The control circuit and a first signal providing circuit in the signal providing module are arranged in the driving integrated circuit;
the control switch circuit is integrated on the display panel.
According to the signal providing method, the signal providing module and the display device, when the display device works in the low-frequency driving mode, the duty ratio of the signal provided by the clock signal end is controlled to be smaller than or equal to the duty ratio threshold value in the holding stage, so that the power consumption is reduced while the low-frequency driving is realized.
Drawings
FIG. 1 is a schematic diagram of the connection relationship of a driving circuit;
FIG. 2 is a circuit diagram of an embodiment of the drive circuit;
FIG. 3 is a circuit diagram of an embodiment of a pixel circuit in a display device according to an embodiment of the invention;
FIG. 4 is a timing diagram of the operation of the embodiment of the pixel circuit shown in FIG. 3;
fig. 5 is a schematic diagram showing that the potential of the driving signal outputted from the driving circuit is gradually increased by the leakage action in the related art;
fig. 6 is a waveform diagram of a signal provided from the high voltage terminal VGH, a signal provided from the first clock signal terminal CK, and a signal provided from the second clock signal terminal CB in at least one embodiment of the present invention;
FIG. 7 is a schematic diagram of the potential of the drive circuit output by the drive circuit after the signals shown in FIG. 6 are applied;
FIG. 8 is a waveform diagram of a signal provided from a first clock signal terminal S1_CK electrically connected to a driving circuit providing a first scan signal, a signal provided from a first second clock signal terminal S1_CB electrically connected to a driving circuit providing a first scan signal, a signal provided from a second first clock signal terminal S2_CK electrically connected to a driving circuit providing a second scan signal, and a signal provided from a second clock signal terminal S2_CB electrically connected to a driving circuit providing a second scan signal, according to at least one embodiment of the present invention;
fig. 9 is a waveform diagram of a signal provided from the first clock signal terminal CK and a signal provided from the second clock signal terminal CB in at least one embodiment of the present invention;
fig. 10 is a waveform of a signal output from the driving circuit in the output-off hold stage by employing the operation timing shown in fig. 9;
fig. 11 is a waveform diagram of a signal provided from the first clock signal terminal CK and a signal provided from the second clock signal terminal CB in at least one embodiment of the present invention;
fig. 12 is a waveform diagram of a signal provided from the first clock signal terminal CK and a signal provided from the second clock signal terminal CB in at least one embodiment of the present invention;
FIG. 13 is a circuit diagram of an embodiment of a second signal providing circuit in a signal providing module according to an embodiment of the present invention;
FIG. 14 is a timing diagram of the operation of an embodiment of the second signal providing circuit;
fig. 15 is a schematic structural view of a display device according to an embodiment of the present invention;
fig. 16 is a schematic diagram of a driving circuit according to an embodiment.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.
The signal providing method of the embodiment of the invention is applied to a driving circuit in a display device, the driving circuit is electrically connected with a clock signal end and is used for providing a driving signal, when the display device works in a low-frequency driving mode, a display period comprises a refreshing stage and a holding stage, and the signal providing method comprises the following steps:
and in the holding stage, controlling the duty ratio of the signal provided by the clock signal terminal to be smaller than or equal to a duty ratio threshold value.
In the signal providing method according to the embodiment of the present invention, when the display device is operated in the low frequency driving mode, the duty ratio of the signal provided by the clock signal terminal is controlled to be less than or equal to the duty ratio threshold value in the hold stage, so as to reduce the power consumption while implementing the low frequency driving.
In at least one embodiment of the present invention, when the refresh frequency of the display device is less than or equal to the common refresh frequency, the display device operates in a low frequency driving mode.
Optionally, the common refresh frequency may be 60Hz, and when the refresh frequency of the display device is less than or equal to 60Hz, the display device operates in a low-frequency driving mode, but not limited to this. For example, when the refresh frequency of the display device is 50Hz, 40Hz, 30Hz, 20Hz, 10Hz, or 1Hz, the display device operates in a low frequency driving mode.
Optionally, the duty cycle threshold is greater than or equal to 5% and less than or equal to 45%. For example, the duty cycle threshold may be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, or 45%, but is not limited thereto.
According to a specific embodiment, the driving circuit is electrically connected to a first node, a second node, a first voltage end, a second voltage end and a driving signal output end, and is configured to control, under the control of the potential of the second node, communication between the driving signal output end and the first voltage end, and control, under the control of the potential of the first node, communication between the driving signal output end and the second voltage end, where the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage end is an ineffective voltage signal; the signal providing method includes:
controlling the first voltage terminal to provide a first voltage signal in the refreshing stage;
and in the holding stage, controlling the clock signal terminal to output a direct-current voltage signal and controlling the first voltage terminal to provide a second voltage signal.
In the implementation, when the driving signal provided by the driving signal output end is connected to the gate of the n-type transistor, the effective voltage signal is a high voltage signal, and the ineffective voltage signal is a low voltage signal;
When the driving signal provided by the driving signal output end is connected to the grid electrode of the p-type transistor, the effective voltage signal is a low voltage signal, and the ineffective voltage signal is a high voltage signal.
At least one embodiment of the present invention is illustrated with the active voltage signal being a high voltage signal and the inactive voltage signal being a low voltage signal.
As shown in fig. 1, the driving circuit 10 is electrically connected to a first node N1, a second node N2, a first voltage terminal V1, a second voltage terminal V2, and a driving signal output terminal OUT, and is configured to control communication between the driving signal output terminal OUT and the first voltage terminal V1 under control of a potential of the second node N2, and control communication between the driving signal output terminal OUT and the second voltage terminal V2 under control of a potential of the first node N1.
In at least one embodiment of the present invention, the first voltage terminal V1 may be a high voltage terminal, and the second voltage terminal V2 may be a low voltage terminal.
As shown in fig. 2, an embodiment of the driving circuit 10 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3;
The grid electrode of the T1 is electrically connected with the first clock signal end CK, the source electrode of the T1 is electrically connected with the starting voltage end STV, and the drain electrode of the T1 is electrically connected with the first node N1;
the grid electrode of the T2 is electrically connected with the first node N1, the source electrode of the T2 is electrically connected with the grid electrode of the T6, and the drain electrode of the T2 is electrically connected with the first clock signal end CK;
the grid electrode of the T3 is electrically connected with the first clock signal end CK, the source electrode of the T3 is electrically connected with the low voltage end VGL, and the drain electrode of the T3 is electrically connected with the grid electrode of the T6;
the grid electrode of the T4 is electrically connected with the second clock signal end CB, the source electrode of the T4 is electrically connected with the first node N1, and the drain electrode of the T4 is electrically connected with the source electrode of the T5;
the grid of the T5 is electrically connected with the grid of the T6, and the drain electrode of the T5 is electrically connected with the high voltage end VGH;
the source electrode of the T6 is electrically connected with the second clock signal end CB, and the drain electrode of the T6 is electrically connected with the source electrode of the T7;
the grid electrode of the T7 is electrically connected with the second clock signal end CB, and the drain electrode of the T7 is electrically connected with the second node N2;
the grid electrode of the T8 is electrically connected with the first node N1, the source electrode of the T8 is electrically connected with the high voltage end VGH, and the drain electrode of the T8 is electrically connected with the second node N2;
the grid electrode of the T9 is electrically connected with the second node N2, the source electrode of the T9 is electrically connected with the high voltage end VGH, and the drain electrode of the T9 is electrically connected with the driving signal output end OUT;
The grid electrode of the T10 is electrically connected with the first node N1, the source electrode of the T10 is electrically connected with the low voltage end VGL, and the drain electrode of the T10 is electrically connected with the driving signal output end OUT;
the first end of C1 is electrically connected with the first node, and the second end of C1 is electrically connected with the second clock signal end CB;
the first end of C2 is electrically connected with the grid electrode of T6, and the second end of C2 is electrically connected with the drain electrode of T6;
the first end of C3 is electrically connected to the second node N2, and the second end of C3 is electrically connected to the high voltage terminal VGH.
In at least one embodiment of the present invention, the clock signal terminal may include the first clock signal terminal CK and the second clock signal terminal CB.
As shown in fig. 3, an embodiment of a pixel circuit included in a display panel in the display device may include an organic light emitting diode O1, a first initialization transistor M1, a compensation control transistor M2, a second initialization transistor M3, a driving transistor M0, a data writing transistor M4, a first light emitting control transistor M5 and a second light emitting control transistor M6, and a storage capacitor Cst;
the grid electrode of M1 is electrically connected with the first scanning line S1, the source electrode of M1 is electrically connected with the first initial voltage end VIN1, and the drain electrode of M1 is electrically connected with the driving node N0;
The grid electrode of the M2 is electrically connected with the second scanning line S2, the source electrode of the M2 is electrically connected with the driving node N0, and the drain electrode of the M2 is electrically connected with the drain electrode of the M0;
the grid electrode of M3 is electrically connected with the third scanning line S3, the source electrode of M3 is electrically connected with the second initial voltage end VIN2, and the drain electrode of M3 is electrically connected with the anode electrode of O1;
the grid electrode of M4 is electrically connected with the fourth scanning line S4, the source electrode of M4 is electrically connected with the Data line Data, and the drain electrode of M4 is electrically connected with the source electrode of M0;
the grid electrode of M5 is electrically connected with the light-emitting control line EM, the source electrode of M5 is electrically connected with the power supply voltage end ELVDD, and the drain electrode of M5 is electrically connected with the source electrode of M0;
the grid electrode of M6 is electrically connected with the light-emitting control line EM, the source electrode of M6 is electrically connected with the drain electrode of M0, and the drain electrode of M6 is electrically connected with the anode of O1;
the cathode of O1 is electrically connected to the low voltage line ELVSS.
In the embodiment of the pixel circuit shown in fig. 3, M1 and M2 are oxide thin film transistors, and M3, M4, M5, M6 and M0 are low temperature polysilicon thin film transistors;
m1 and M2 are n-type transistors, and M3, M4, M5, M6 and M0 are p-type transistors.
The embodiment of the pixel circuit shown in fig. 3 may be an LTPO (low temperature poly oxide) pixel circuit.
In at least one embodiment of the present invention, the driving circuit may provide the first scan signal to S1 through its driving signal output terminal, and the other driving circuit may provide the second scan signal to S2 through its driving signal output terminal.
In the related art, the LTPO technology is used to realize low refresh rate display, and when the refresh rate is 1Hz, a frame time (i.e. a display period) may include a refresh stage and a hold stage that are sequentially arranged, where the duration of the refresh stage may be 1s/120, and the duration of the hold stage may be 119s/120; the holding phase may include 119 holding periods, each holding period may last for 1s/120; but not limited thereto;
in the refresh stage, the initialization and data writing of the pixel circuit are performed, the number writing is not performed in the hold stage, and the initialization of the pixel anode is performed by controlling the EM and S3 to be turned on only in each hold period, so as to improve the flicker phenomenon. In the hold phase, the first scan line S1 and the second scan line S2 are not turned on, that is, the potential of the first scan signal provided by S1 and the potential of the second scan signal provided by S2 are both low voltages, but in the related art, the first clock signal terminal CK and the second clock signal terminal CB still normally output clock signals in the hold phase, so that power consumption is high.
As shown in fig. 4, in operation, the embodiment of the pixel circuit shown in fig. 2 may include an output stage t1, a reset stage t2, and an output off-hold stage t3, which are sequentially arranged;
In the output stage T1, T9 is turned on under the control of the potential of the second node N2 to control OUT to output a high voltage signal; t10 is turned off under control of the potential of the first node N1;
in the reset phase T1, T9 is turned off under the control of the potential of the second node N2, and T10 is turned on under the control of the potential of the first node N1 to control OUT to output a low voltage signal;
in the output cut-off stage T2, when the second clock signal terminal CB normally outputs a clock signal, the potential of the second clock signal provided by the second clock signal terminal CB jumps from high voltage to low voltage at regular intervals, so that the potential of N1 can be pulled down, ensuring that T10 is better turned on to output a low voltage signal, ensuring that the low voltage signal output by OUT is stable, if the second clock signal terminal CB outputs a dc voltage signal, the potential of N1 cannot be pulled down through coupling of C1, and a good turn-on state of T10 cannot be ensured, and as a result, as shown in fig. 5, the potential of the driving signal output by OUT is gradually increased due to the leakage effect of T9.
In fig. 5, the vertical axis is Vout in V (volts), the horizontal axis is time t in s (seconds); where Vout is the potential of the driving signal output from OUT.
Based on the above problems, the signal providing method according to at least one embodiment of the present invention may include:
controlling the first voltage terminal to provide a first voltage signal in the refreshing stage;
and in the holding stage, controlling the clock signal terminal to output a direct-current voltage signal and controlling the first voltage terminal to provide a second voltage signal.
At least one embodiment of the invention controls the first voltage terminal to provide the second voltage signal by controlling in the holding stage, wherein the second voltage signal can be a low voltage signal, so that even if T9 leaks electricity, the potential of the driving signal output by OUT can not be pulled up, the problem that the potential of the driving signal output by OUT gradually rises in the output cut-off holding stage is avoided, and the fact that OUT continuously outputs the low voltage signal in the output cut-off stage is ensured.
In at least one embodiment of the present invention, the dc voltage signal may be a high voltage signal, but is not limited thereto.
As shown in fig. 6, in at least one embodiment of the present invention, during the refresh phase P1, CK and CB are controlled to normally output clock signals, and during the hold phase P2, CK and CB are controlled to output high voltage signals;
in the refresh stage P1, controlling VGH to normally output a high voltage signal;
In the hold phase P2, VGH is controlled to output a low voltage signal.
As shown in fig. 7, by adopting the operation timing shown in fig. 6, OUT continuously outputs a low voltage signal in the output off-hold stage. In fig. 7, the vertical axis is Vout in V (volts), the horizontal axis is time t in s (seconds); where Vout is the potential of the driving signal output from OUT.
In fig. 8, a first clock signal terminal denoted by s1_ck and electrically connected to a driving circuit for supplying a first scan signal, a first second clock signal terminal denoted by s1_cb and electrically connected to a driving circuit for supplying a first scan signal, a second first clock signal terminal denoted by s2_ck and electrically connected to a driving circuit for supplying a second scan signal, and a second clock signal terminal denoted by s2_cb and electrically connected to a driving circuit for supplying a second scan signal;
as shown in fig. 8, in the refresh stage P1, s1_ck and s2_ck provide the first clock signal, and s1_cb and s2_cb provide the second clock signal;
in fig. 8, a first holding period denoted by P21 and included in the holding stage P2, a second holding period denoted by P22 and included in the holding stage P2, a third holding period denoted by P23 and included in the holding stage P2, a fourth holding period denoted by P24 and included in the holding stage P2, a first hundred and sixteen holding periods denoted by P2116 and included in the holding stage P2, a first hundred and seventeen holding periods denoted by P2117 and included in the holding stage P2, a first hundred and eighteen holding periods denoted by P2118 and included in the holding stage P2, and a first hundred and nineteen holding periods denoted by P2119 and included in the holding stage P2.
As shown in fig. 8, in the hold phase P2, s1_ck, s2_ck, s1_cb, and s2_cb all supply a high voltage signal.
According to another embodiment, the display device includes a display panel including a plurality of pixel circuits, the driving circuit for supplying the driving signals to the pixel circuits; the pixel circuit is electrically connected with the data line and receives the data voltage from the data line; the holding stage includes a plurality of holding periods, and an output period disposed between adjacent two-dimensional holding periods;
the signal providing method includes:
in the maintaining time period, controlling the clock signal end to output a direct-current voltage signal;
in the output time period, the clock signal terminal is controlled to output a corresponding clock signal;
the duration of the sustain period is an interval time.
In a specific implementation, the holding stage may include N holding periods and N-1 output periods, where N is an integer greater than 1, the output periods are disposed between two adjacent holding periods, the clock signal terminals are controlled to output a dc voltage signal in the holding periods, and the clock signal terminals are controlled to output a corresponding clock signal in the output periods, so that in a low-frequency driving mode, power consumption is saved and stability of a driving signal output by the driving signal output terminal is ensured.
Optionally, in the output period, the clock signal output by the clock signal terminal has at least one pulse, for example, the clock signal may have one pulse, but not limited to this.
In practice, the pulse may be a downward pulse, but is not limited thereto.
Alternatively, the interval time may be preset, or may be selected by detecting the brightness of the display panel during the sampling period.
In at least one embodiment of the present invention, a sampling phase may also be included prior to the display period; the signal providing method further includes:
in the sampling stage, controlling the clock signal end to output the direct-current voltage signal, controlling the data line to provide unchanged data voltage, detecting the display brightness of the display panel, and recording corresponding change time when detecting that the brightness change reaches a brightness change value threshold;
the interval time is greater than a preset threshold time and less than or equal to the change time.
After the display panel module is finished, adjusting the time sequence, controlling the clock signal end to output a high-voltage signal in a holding stage, shooting the brightness change of the display panel by using a high-precision camera, recording corresponding time when the brightness change reaches a certain degree (for example, the change amount reaches 2%), and recording the corresponding time in a storage unit (the storage unit can be a newly added storage unit or can be integrated in a time control module in a drive IC (integrated circuit)), and sampling and storing each display panel for use when the display panel works normally. When the screen is normally turned on, the brightness of the display panel can be reduced to a critical value every time the corresponding time is needed in the holding stage, and at the moment, the clock signal end can be controlled to output a pulse from high voltage to low voltage once so as to pull down the potential of a first node in the driving circuit, so that the driving circuit outputs a low voltage signal again, and the normal operation of the screen body is maintained.
Alternatively, the dc voltage signal is a high voltage signal, and in the output period, when the potential of the clock signal is a low voltage, a difference between the voltage value of the high voltage signal and the voltage value of the clock signal is unchanged, for example, the difference may be greater than or equal to 1mV and less than or equal to 5mV.
As shown in fig. 9, in the refresh stage P1, the first clock signal terminal CK is controlled to output the first clock signal, and the second clock signal terminal CB is controlled to output the second clock signal;
in fig. 9, a first holding period denoted by P31 and included in the holding period P2, a second holding period denoted by P32 and included in the holding period P2, a first output period denoted by P41, and P41 disposed between P31 and P32;
a third duration, denoted P33, which is comprised by the hold phase P2, a second output duration, denoted P42, P42 being arranged between P32 and P33;
the third output period is denoted by reference numeral P43;
the N-3 output period, denoted by P4N-3, is comprised by the hold phase P2;
an N-2 sustain period denoted by P3N-2 and included in the hold stage P2, an N-2 output period denoted by P4N-2 and included in the hold stage P2, and an N-1 sustain period denoted by P3N-1 and included in the hold stage P2; P4N-2 is arranged between P3N-2 and P3N-1;
The N-th maintaining period denoted by P3N and included in the maintaining period P2, the N-1-th output period denoted by P4N-1, and P4N-1 disposed between P3N-1 and P3N;
outputting high voltage signals at P31, P32, P33, P3N-2, P3N-1 and P3N, CK and CB;
outputting clock signals at P41, P42, P43, P4N-3, P4N-2, P4N-1 and P4N, CK and CB, the clock signals having a downward pulse; and when the potential of the clock signal is a low voltage, the difference between the voltage value of the high voltage signal output at P31, P32, P33, P34, P3N-1 and P3N, CK and CB and the voltage value of the clock signal is unchanged.
Fig. 10 is a waveform of a signal output from OUT in the output-off hold stage by adopting the operation timing shown in fig. 9. In fig. 5, the vertical axis is Vout in V (volts), the horizontal axis is time t in s (seconds); where Vout is the potential of the driving signal output from OUT.
In at least one embodiment of the present invention, when the display panel displays a low brightness image, the dc voltage signal is a high voltage signal, and in a plurality of output periods, when the potential of the clock signal is a low voltage, the difference between the voltage value of the high voltage signal and the voltage value of the clock signal may be gradually reduced to compensate for the brightness attenuation;
When the display panel displays a high-brightness picture, the direct-current voltage signal is a high-voltage signal, and in a plurality of output time periods, when the potential of the clock signal is a low voltage, the difference between the voltage value of the high-voltage signal and the voltage value of the clock signal is gradually increased so as to weaken the increase of brightness.
In a specific implementation, the voltage difference between the high voltage and the low voltage output by the clock signal terminal determines the coupling effect, for example, in the hold phase, the signal jump output by the clock signal terminal affects the driving signal output by the driving signal output terminal. The larger the voltage difference is, the stronger the coupling effect is, the smaller the voltage value of the low-voltage signal output by the driving signal output end is, otherwise, the smaller the voltage difference is, and the higher the voltage value of the low-voltage signal output by the driving signal output end is relatively. At the time of low frequency driving, the brightness of the display panel varies between different sustain phases. For example, the brightness of the display panel may be lower and lower in a high brightness screen, and the brightness of the display panel may be slowly increased in a low brightness screen. According to at least one embodiment of the invention, the clock signal end is intermittently controlled to output the clock signal in the holding stage, the clock signal can comprise at least one downward pulse, the voltage difference between the high voltage and the low voltage of the clock signal is changed in the holding stage, the voltage value of the driving signal output by the driving circuit can be influenced, and finally the change of the luminescence of the pixel circuit is influenced, so that the compensation process is realized, the uniformity of the low-frequency display brightness is improved, and the flicker phenomenon of the low-frequency display is improved.
In fig. 11, a first clock signal terminal denoted by CK, and a second clock signal terminal denoted by CB;
as shown in fig. 11, in the refresh phase P1, CK provides a first clock signal and CB provides a second clock signal;
in fig. 11, a first holding period denoted by P21 and included in the holding stage P2, a second holding period denoted by P22 and included in the holding stage P2, a third holding period denoted by P23 and included in the holding stage P2, a fourth holding period denoted by P24 and included in the holding stage P2, a first hundred and sixteen holding periods denoted by P2116 and included in the holding stage P2, a first hundred and seventeen holding periods denoted by P2117 and included in the holding stage P2, a first hundred and eighteen holding periods denoted by P2118 and included in the holding stage P2, and a first hundred and nineteen holding periods denoted by P2119 and included in the holding stage P2.
As shown in fig. 11, in the output period in each holding period, CK and CB output respective clock signals having one downward pulse;
in the output period in the first holding period P21, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv1;
In the output period in the second holding period P22, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv2;
in the output period in the third holding period P23, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv3;
in the output period in the second holding period P24, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv4;
in the output period in the first holding period P2116, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv116;
in the output period in the second holding period P2117, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv117;
in the output period in the third holding period P2118, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv118;
in the output period in the second holding period P2119, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv119;
Δv1, Δv2, Δv3, Δv4, …, Δv116, Δv117, Δv118, and Δv119 decrease gradually, stepwise;
the operation timing shown in fig. 11 can be applied when a high-luminance screen is displayed. For example, when the brightness of the frame is greater than 800nit, the frame may be a high brightness frame, but not limited thereto.
In fig. 12, CK is a first clock signal terminal, and CB is a second clock signal terminal;
as shown in fig. 12, in the refresh phase P1, CK provides a first clock signal and CB provides a second clock signal;
in fig. 12, a first holding period denoted by P21 and included in the holding stage P2, a second holding period denoted by P22 and included in the holding stage P2, a third holding period denoted by P23 and included in the holding stage P2, a fourth holding period denoted by P24 and included in the holding stage P2, a first hundred and sixteen holding periods denoted by P2116 and included in the holding stage P2, a first hundred and seventeen holding periods denoted by P2117 and included in the holding stage P2, a first hundred and eighteen holding periods denoted by P2118 and included in the holding stage P2, and a first hundred and nineteen holding periods denoted by P2119 and included in the holding stage P2.
As shown in fig. 12, in the output period in each holding period, CK and CB output respective clock signals having one downward pulse;
in the output period in the first holding period P21, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv1;
in the output period in the second holding period P22, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv2;
in the output period in the third holding period P23, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv3;
in the output period in the second holding period P24, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv4;
in the output period in the first holding period P2116, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv116;
in the output period in the second holding period P2117, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv117;
In the output period in the third holding period P2118, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv118;
in the output period in the second holding period P2119, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δv119;
Δv1, Δv2, Δv3, Δv4, …, Δv116, Δv117, Δv118, and Δv119 are gradually increased, stepwise;
the operation sequence shown in fig. 12 can be applied when a low-luminance screen is displayed. For example, when the brightness of the frame is less than 4nit, the frame may be a low brightness frame, but not limited thereto.
In at least one embodiment corresponding to fig. 11 and 12, an output period is provided in each holding period, but not limited to this.
In an implementation, the clock signal terminals may include a first clock signal terminal and a second clock signal terminal, but are not limited thereto.
The signal providing module according to the embodiment of the present invention is applied to a driving circuit in a display device, where the driving circuit is electrically connected to a clock signal terminal and is configured to provide a driving signal, and when a refresh frequency of the display device is less than a predetermined frequency, a display period includes a refresh phase and a hold phase, where the signal providing module may include:
And the first signal providing circuit is used for controlling the duty ratio of the signal provided by the clock signal terminal to be smaller than or equal to a duty ratio threshold value in the holding stage.
When the signal providing module of the embodiment of the invention works, when the display device works in a low-frequency driving mode, the signal providing circuit controls the duty ratio of the signal provided by the clock signal end to be smaller than or equal to the duty ratio threshold value in a holding stage so as to reduce the power consumption while realizing low-frequency driving.
According to a specific embodiment, the driving circuit is electrically connected to a first node, a second node, a first voltage end, a second voltage end and a driving signal output end, and is configured to control, under the control of the potential of the second node, communication between the driving signal output end and the first voltage end, and control, under the control of the potential of the first node, communication between the driving signal output end and the second voltage end, where the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage end is an ineffective voltage signal; the signal providing module further comprises a second signal providing circuit;
the first signal providing circuit is used for controlling the clock signal end to output a direct-current voltage signal in the holding stage;
The second signal providing circuit is used for controlling the first voltage terminal to provide a first voltage signal in the refreshing stage and controlling the first voltage terminal to provide a second voltage signal in the maintaining stage.
Optionally, the second signal providing circuit may include a control circuit and a control switching circuit; the control switch circuit comprises a first control transistor and a second control transistor;
the control electrode of the first control transistor is electrically connected with a first control line, the first electrode of the first control transistor is electrically connected with a second voltage line, and the second electrode of the first control transistor is electrically connected with the first voltage end; the second voltage line is used for providing a second voltage signal;
the control electrode of the second control transistor is electrically connected with a second control line, the first electrode of the second control transistor is electrically connected with a first voltage line, and the second electrode of the second control transistor is electrically connected with the first voltage end; the first voltage line is used for providing a first voltage signal;
the control circuit is configured to provide an inactive first control signal to the first control line to turn off the first control transistor, an active second control signal to the second control line to turn on the second control transistor during the refresh phase, and to provide an active first control signal to the first control line to turn on the first control transistor and an inactive second control signal to the second control line to turn off the second control transistor during the hold phase.
In the implementation, the control circuit can control the on-off of the first control transistor and the second control transistor so as to control the first voltage terminal to provide different voltage signals in different time periods.
In at least one embodiment of the present invention, the first voltage signal may be a high voltage signal, and the second voltage signal may be a low voltage signal, but not limited thereto.
In at least one embodiment of the present invention, when the first control transistor and the second control transistor are n-type transistors, the potential of the effective control signal may be a high voltage, and the potential of the ineffective control signal may be a low voltage; when the first control transistor and the second control transistor are p-type transistors, the potential of the effective control signal may be a low voltage and the potential of the ineffective control signal may be a high voltage.
As shown in fig. 13, the second signal providing circuit may include a control circuit 130, a first control transistor Tc1, and a second control transistor Tc2;
the gate of the first control transistor Tc1 is electrically connected to a first control line SW1, the source of the first control transistor Tc1 is electrically connected to a low voltage line, and the drain of the first control transistor Tc1 is electrically connected to the first voltage terminal V1; the low voltage line is used for providing a low voltage signal Vgl;
The gate of the second control transistor Tc2 is electrically connected to a second control line SW2, the source of the second control transistor Tc2 is electrically connected to a high voltage line, and the drain of the second control transistor Tc2 is electrically connected to the first voltage terminal V1; the high voltage line is used for providing a high voltage signal Vgh;
the control circuit 130 is configured to provide an inactive first control signal to the first control line SW1 to turn off the first control transistor Tc1, an active second control signal to the second control line SW2 to turn on the second control transistor Tc2 during the refresh period, and to provide an active first control signal to the first control line SW1 to turn on the first control transistor Tc1 and an inactive second control signal to the second control line SW2 to turn off the second control transistor Tc2 during the hold period.
In the embodiment of the second signal providing circuit shown in fig. 13, tc1 and Tc2 are both p-type transistors.
In implementation, tc1 and Tc2 may be disposed on the display panel, and the control circuit 130 may be disposed in the driving IC.
Fig. 14 is a timing chart of the first control signal on SW1 and the second control signal on SW 2.
As shown in fig. 14, in the refresh stage P1, the potential of the first control signal on SW1 is high voltage, and the potential of the second control signal on SW2 is low voltage; in the hold phase P2, the potential of the first control signal on SW1 is low and the potential of the second control signal on SW2 is high.
According to another embodiment, the display device includes a display panel including a plurality of pixel circuits, the driving circuit for supplying the driving signals to the pixel circuits; the pixel circuit is electrically connected with the data line and receives the data voltage from the data line; the holding stage includes a plurality of holding periods, and an output period disposed between adjacent two-dimensional holding periods;
the first signal providing circuit is used for controlling the clock signal terminal to output a direct-current voltage signal in the maintaining time period, and controlling the clock signal terminal to output a corresponding clock signal in the output time period;
the duration of the sustain period is an interval time.
In at least one embodiment of the present invention, when the display panel displays a low brightness picture, the dc voltage signal is a high voltage signal, and the first signal providing circuit is configured to gradually decrease a difference between a voltage value of the high voltage signal and a voltage value of the clock signal when the potential of the clock signal is a low voltage in a plurality of output periods.
In at least one embodiment of the present invention, when the display panel displays a high brightness picture, the dc voltage signal is a high voltage signal, and the first signal providing circuit is configured to gradually increase a difference between a voltage value of the high voltage signal and a voltage value of the clock signal when the potential of the clock signal is a low voltage in a plurality of output periods.
The display device provided by the embodiment of the invention comprises the signal providing module.
In an implementation, the display device may include a driving integrated circuit and a display panel; the signal providing module further comprises a second signal providing circuit, wherein the second signal providing circuit comprises a control switch circuit and a control circuit;
the control circuit and the first signal providing circuit in the signal providing module may be disposed in the driving integrated circuit;
the first control transistor and the second control transistor are integrated on the display panel.
As shown in fig. 15, the display device according to the embodiment of the present invention includes a display panel 150, a driving circuit 151, and a display integrated circuit 152;
the driving circuit 151 is disposed at a left side of the display panel 150 and a right side of the display panel 150;
The display panel 150 includes a plurality of rows and columns of pixel circuits 153 disposed in an effective display area A0;
the display device according to an embodiment of the present invention may include a second signal providing circuit including a control switch circuit 154 and a control circuit;
the display integrated circuit 152 is attached to the lower side of the display panel 150, and the control circuit may be disposed in the display integrated circuit 152.
As shown in fig. 16, the driving circuit 151 may include a first driving circuit 161, a second driving circuit 162, and a third driving circuit 163; wherein,,
the first driving circuit 161 is for providing a p-type driving signal, the second driving circuit 162 is for providing an n-type driving signal, and the third driving circuit 163 is for providing a light emission control signal.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (8)
1. A signal providing method applied to a driving circuit in a display device, the driving circuit being electrically connected to a clock signal terminal for providing a driving signal, wherein a display period includes a refresh phase and a hold phase when the display device is operated in a low frequency driving mode, the signal providing method comprising:
in the holding stage, the duty ratio of the signal provided by the clock signal terminal is controlled to be smaller than or equal to a duty ratio threshold value;
the display device comprises a display panel, wherein the display panel comprises a plurality of pixel circuits, and the driving circuit is used for providing the driving signals for the pixel circuits; the pixel circuit is electrically connected with the data line and receives the data voltage from the data line; the holding stage includes a plurality of holding periods, and an output period disposed between adjacent two-dimensional holding periods;
the signal providing method includes:
in the maintaining time period, controlling the clock signal end to output a direct-current voltage signal;
in the output time period, the clock signal terminal is controlled to output a corresponding clock signal;
the duration of the maintenance time period is interval time;
The driving circuit is respectively and electrically connected with a first node, a second node, a first voltage end, a second voltage end and a driving signal output end, and is used for controlling the communication between the driving signal output end and the first voltage end under the control of the potential of the second node, controlling the communication between the driving signal output end and the second voltage end under the control of the potential of the first node, wherein the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage end is an ineffective voltage signal; the signal providing method includes:
controlling the first voltage terminal to provide a first voltage signal in the refreshing stage;
in the holding stage, the clock signal terminal is controlled to output a direct-current voltage signal, and the first voltage terminal is controlled to provide a second voltage signal;
the display panel displays a low-brightness picture, the direct-current voltage signal is a high-voltage signal, and in a plurality of output time periods, when the potential of the clock signal is low voltage, the difference value between the voltage value of the high-voltage signal and the voltage value of the clock signal is gradually reduced; or the display panel displays a high-brightness picture, the direct-current voltage signal is a high-voltage signal, and when the potential of the clock signal is low in a plurality of output time periods, the difference value between the voltage value of the high-voltage signal and the voltage value of the clock signal is gradually increased.
2. The signal providing method of claim 1, wherein the duty cycle threshold is greater than or equal to 5% and less than or equal to 45%.
3. The signal providing method of claim 1, further comprising a sampling phase prior to the display period; the signal providing method further includes:
in the sampling stage, controlling the clock signal end to output the direct-current voltage signal, controlling the data line to provide unchanged data voltage, detecting the display brightness of the display panel, and recording corresponding change time when detecting that the brightness change reaches a brightness change value threshold;
the interval time is greater than a preset threshold time and less than or equal to the change time.
4. A signal providing method according to any one of claims 1 to 3, wherein the clock signal terminals comprise a first clock signal terminal and a second clock signal terminal.
5. A signal providing module, characterized in that it is applied to a driving circuit in a display device, the driving circuit is electrically connected to a clock signal terminal and is used for providing a driving signal, and when a refresh frequency of the display device is less than a predetermined frequency, a display period includes a refresh phase and a hold phase, the signal providing module includes:
The first signal providing circuit is used for controlling the duty ratio of the signal provided by the clock signal terminal to be smaller than or equal to a duty ratio threshold value in a holding stage;
the display device comprises a display panel, wherein the display panel comprises a plurality of pixel circuits, and the driving circuit is used for providing the driving signals for the pixel circuits; the pixel circuit is electrically connected with the data line and receives the data voltage from the data line; the holding stage includes a plurality of holding periods, and an output period disposed between adjacent two-dimensional holding periods;
the first signal providing circuit is used for controlling the clock signal terminal to output a direct-current voltage signal in the maintaining time period, and controlling the clock signal terminal to output a corresponding clock signal in the output time period;
the duration of the maintenance time period is interval time;
the driving circuit is respectively and electrically connected with a first node, a second node, a first voltage end, a second voltage end and a driving signal output end, and is used for controlling the communication between the driving signal output end and the first voltage end under the control of the potential of the second node, controlling the communication between the driving signal output end and the second voltage end under the control of the potential of the first node, wherein the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage end is an ineffective voltage signal; the signal providing module further comprises a second signal providing circuit;
The first signal providing circuit is used for controlling the clock signal end to output a direct-current voltage signal in the holding stage;
the second signal providing circuit is used for controlling the first voltage terminal to provide a first voltage signal in the refreshing stage and controlling the first voltage terminal to provide a second voltage signal in the holding stage;
the display panel displays a low-brightness picture, the direct-current voltage signal is a high-voltage signal, the first signal providing circuit is used for gradually reducing the difference between the voltage value of the high-voltage signal and the voltage value of the clock signal or gradually increasing the difference between the voltage value of the high-voltage signal and the voltage value of the clock signal when the potential of the clock signal is a low voltage in a plurality of output time periods.
6. The signal providing module of claim 5, wherein the second signal providing circuit comprises a control circuit and a control switch circuit; the control switch circuit comprises a first control transistor and a second control transistor;
The control electrode of the first control transistor is electrically connected with a first control line, the first electrode of the first control transistor is electrically connected with a second voltage line, and the second electrode of the first control transistor is electrically connected with the first voltage end; the second voltage line is used for providing a second voltage signal;
the control electrode of the second control transistor is electrically connected with a second control line, the first electrode of the second control transistor is electrically connected with a first voltage line, and the second electrode of the second control transistor is electrically connected with the first voltage end; the first voltage line is used for providing a first voltage signal;
the control circuit is configured to provide an inactive first control signal to the first control line to turn off the first control transistor, an active second control signal to the second control line to turn on the second control transistor during the refresh phase, and to provide an active first control signal to the first control line to turn on the first control transistor and an inactive second control signal to the second control line to turn off the second control transistor during the hold phase.
7. A display device comprising a signal providing module according to claim 5 or 6.
8. The display device according to claim 7, wherein the display device comprises a display panel and a driver integrated circuit; the signal providing module further comprises a second signal providing circuit, wherein the second signal providing circuit comprises a control circuit and a control switch circuit;
the control circuit and a first signal providing circuit in the signal providing module are arranged in the driving integrated circuit;
the control switch circuit is integrated on the display panel.
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| CN114783348A (en) * | 2022-05-24 | 2022-07-22 | 武汉天马微电子有限公司 | Shift register circuit, driving method thereof and display device |
| CN114783379B (en) * | 2022-05-26 | 2024-02-09 | 云谷（固安）科技有限公司 | Pixel circuit, driving method thereof and display panel |
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