CN113903307A - Signal providing method, signal providing module and display device - Google Patents
Signal providing method, signal providing module and display device Download PDFInfo
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- CN113903307A CN113903307A CN202111228557.7A CN202111228557A CN113903307A CN 113903307 A CN113903307 A CN 113903307A CN 202111228557 A CN202111228557 A CN 202111228557A CN 113903307 A CN113903307 A CN 113903307A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a signal providing method, a signal providing module and a display device. The signal providing method is applied to a driving circuit in a display device, the driving circuit is electrically connected with a clock signal end and is used for providing a driving signal, when the display device works in a low-frequency driving mode, a display period comprises a refreshing stage and a holding stage, and the signal providing method comprises the following steps: and in the holding stage, controlling the duty ratio of a signal provided by the clock signal end to be less than or equal to a duty ratio threshold value. The invention can realize low-frequency driving and reduce power consumption.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a signal providing method, a signal providing module, and a display device.
Background
In the related art, a low refresh frequency display is realized by using an LTPO (low temperature poly oxide) technology, and when the display device operates in a low frequency driving mode, one frame time may include, for example, a refresh phase and a hold phase which are sequentially provided. The transistors of the LTPO pixel circuit may be electrically connected to a plurality of scan lines, and in the hold stage, at least one of the scan lines is not turned on, that is, the potential of the scan signal provided by the at least one scan line is an invalid voltage, but in the related art, the clock signal terminal connected to the driving circuit generating the scan signal still outputs the clock signal normally in the hold stage, so that power consumption is high.
Disclosure of Invention
The invention mainly aims to provide a signal providing method, a signal providing module and a display device, and solves the problem that the conventional display device cannot realize low-frequency driving and simultaneously reduce power consumption.
In order to achieve the above object, an embodiment of the present invention provides a signal providing method, applied to a driving circuit in a display device, where the driving circuit is electrically connected to a clock signal terminal and is used to provide a driving signal, and when the display device operates in a low frequency driving mode, a display period includes a refresh phase and a hold phase, and the signal providing method includes:
and in the holding stage, controlling the duty ratio of a signal provided by the clock signal end to be less than or equal to a duty ratio threshold value.
Optionally, the duty cycle threshold is greater than or equal to 5% and less than or equal to 45%.
Optionally, the driving circuit is electrically connected to the first node, the second node, the first voltage end, the second voltage end, and the driving signal output end, and is configured to control the connection between the driving signal output end and the first voltage end under the control of the potential of the second node, and control the connection between the driving signal output end and the second voltage end under the control of the potential of the first node, where the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage end is an invalid voltage signal; the signal providing method includes:
in the refreshing stage, controlling the first voltage end to provide a first voltage signal;
and in the holding stage, controlling the clock signal end to output a direct current voltage signal, and controlling the first voltage end to provide a second voltage signal.
Optionally, the display device includes a display panel, the display panel includes a plurality of pixel circuits, and the driving circuit is configured to provide the driving signals for the pixel circuits; the pixel circuit is electrically connected with the data line and receives data voltage from the data line; the holding phase comprises a plurality of holding time periods and output time periods arranged between two adjacent holding time periods;
the signal providing method includes:
controlling the clock signal end to output a direct current voltage signal in the maintaining time period;
controlling the clock signal end to output a corresponding clock signal in the output time period;
the duration of the maintaining period is an interval time.
Optionally, a sampling phase is further included before the display period; the signal providing method further includes:
in the sampling stage, controlling the clock signal end to output the direct-current voltage signal, controlling the data line to provide constant data voltage, detecting the display brightness of the display panel, and recording corresponding change time when detecting that the brightness change reaches a brightness change value threshold;
the interval time is greater than a preset threshold time and less than or equal to the change time.
Optionally, the dc voltage signal is a high voltage signal, and in the output time period, when the potential of the clock signal is a low voltage, a difference between a voltage value of the high voltage signal and a voltage value of the clock signal is not changed.
Optionally, the display panel displays a low-luminance picture, the dc voltage signal is a high voltage signal, and in a plurality of output time periods, when the potential of the clock signal is a low voltage, a difference between a voltage value of the high voltage signal and a voltage value of the clock signal is gradually decreased.
Optionally, the display panel displays a high-brightness picture, the dc voltage signal is a high voltage signal, and in a plurality of output time periods, when the potential of the clock signal is a low voltage, a difference between a voltage value of the high voltage signal and a voltage value of the clock signal gradually increases.
Optionally, the clock signal terminal includes a first clock signal terminal and a second clock signal terminal.
An embodiment of the present invention further provides a signal providing module, applied to a driving circuit in a display device, where the driving circuit is electrically connected to a clock signal terminal and is configured to provide a driving signal, where when a refresh frequency of the display device is less than a predetermined frequency, a display cycle includes a refresh phase and a hold phase, and the signal providing module includes:
and the first signal providing circuit is used for controlling the duty ratio of the signal provided by the clock signal end to be less than or equal to a duty ratio threshold value in a holding phase.
Optionally, the driving circuit is electrically connected to the first node, the second node, the first voltage end, the second voltage end, and the driving signal output end, and is configured to control the connection between the driving signal output end and the first voltage end under the control of the potential of the second node, and control the connection between the driving signal output end and the second voltage end under the control of the potential of the first node, where the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage end is an invalid voltage signal; the signal providing module also comprises a second signal providing circuit;
the first signal providing circuit is used for controlling the clock signal end to output a direct current voltage signal in the holding stage;
the second signal providing circuit is used for controlling the first voltage end to provide a first voltage signal in the refreshing stage and controlling the first voltage end to provide a second voltage signal in the maintaining stage.
Optionally, the second signal providing circuit includes a control circuit and a control switch circuit; the control switch circuit comprises a first control transistor and a second control transistor;
a control electrode of the first control transistor is electrically connected with a first control line, a first electrode of the first control transistor is electrically connected with a second voltage line, and a second electrode of the first control transistor is electrically connected with the first voltage end; the second voltage line is used for providing a second voltage signal;
a control electrode of the second control transistor is electrically connected with a second control line, a first electrode of the second control transistor is electrically connected with a first voltage line, and a second electrode of the second control transistor is electrically connected with the first voltage end; the first voltage line is used for providing a first voltage signal;
the control circuit is configured to provide an inactive first control signal to the first control line to turn off the first control transistor and an active second control signal to the second control line to turn on the second control transistor during the refresh phase, and is further configured to provide an active first control signal to the first control line to turn on the first control transistor and an inactive second control signal to the second control line to turn off the second control transistor during the hold phase.
Optionally, the display device includes a display panel, the display panel includes a plurality of pixel circuits, and the driving circuit is configured to provide the driving signals for the pixel circuits; the pixel circuit is electrically connected with the data line and receives data voltage from the data line; the holding phase comprises a plurality of holding time periods and output time periods arranged between two adjacent holding time periods;
the first signal providing circuit is used for controlling the clock signal end to output a direct current voltage signal in the maintaining time period and controlling the clock signal end to output a corresponding clock signal in the output time period;
the duration of the maintaining period is an interval time.
Optionally, the display panel displays a low-luminance picture, the dc voltage signal is a high voltage signal, and the first signal providing circuit is configured to gradually decrease a difference between a voltage value of the high voltage signal and a voltage value of the clock signal in a plurality of output time periods when the potential of the clock signal is a low voltage.
Optionally, the display panel displays a high-luminance picture, the dc voltage signal is a high voltage signal, and the first signal providing circuit is configured to gradually increase a difference between a voltage value of the high voltage signal and a voltage value of the clock signal in a plurality of output time periods when the potential of the clock signal is a low voltage.
The embodiment of the invention also provides a display device which comprises the signal providing module.
Optionally, the display device includes a display panel and a driving integrated circuit; the signal providing module also comprises a second signal providing circuit, and the second signal providing circuit comprises a control circuit and a control switch circuit;
the control circuit and a first signal providing circuit in the signal providing module are arranged in the driving integrated circuit;
the control switch circuit is integrated on the display panel.
According to the signal providing method, the signal providing module and the display device, when the display device works in a low-frequency driving mode, in a keeping stage, the duty ratio of a signal provided by the clock signal end is controlled to be smaller than or equal to a duty ratio threshold value, so that low-frequency driving is achieved, and meanwhile power consumption is reduced.
Drawings
FIG. 1 is a schematic diagram of the connection relationship of a driving circuit;
FIG. 2 is a circuit diagram of one embodiment of the drive circuit;
FIG. 3 is a circuit diagram of an embodiment of a pixel circuit in a display device according to the invention;
FIG. 4 is a timing diagram of the operation of the embodiment of the pixel circuit shown in FIG. 3;
fig. 5 is a schematic diagram illustrating that the potential of the driving signal output by the driving circuit gradually increases due to the leakage in the related art;
FIG. 6 is a waveform diagram of a signal provided by the high voltage terminal VGH, a signal provided by the first clock signal terminal CK, and a signal provided by the second clock signal terminal CB, in at least one embodiment of the present invention;
FIG. 7 is a schematic diagram of the drive circuit potential output by the drive circuit after the signals shown in FIG. 6 are applied;
FIG. 8 is a waveform diagram of a signal provided by a first clock signal terminal S1_ CK electrically connected to a driving circuit for providing a first scan signal, a signal provided by a first second clock signal terminal S1_ CB electrically connected to a driving circuit for providing a first scan signal, a signal provided by a second first clock signal terminal S2_ CK electrically connected to a driving circuit for providing a second scan signal, and a signal provided by a second clock signal terminal S2_ CB electrically connected to a driving circuit for providing a second scan signal, in accordance with at least one embodiment of the present invention;
FIG. 9 is a waveform diagram of a signal provided by the first clock signal terminal CK and a signal provided by the second clock signal terminal CB in at least one embodiment of the present invention;
FIG. 10 is a waveform of a signal output from the driving circuit in an output off hold stage by adopting the operation timing shown in FIG. 9;
FIG. 11 is a waveform diagram of a signal provided by the first clock signal terminal CK and a signal provided by the second clock signal terminal CB in at least one embodiment of the present invention;
FIG. 12 is a waveform diagram of a signal provided by the first clock signal terminal CK and a signal provided by the second clock signal terminal CB in at least one embodiment of the present invention;
FIG. 13 is a circuit diagram of an embodiment of a second signal providing circuit in the signal providing module according to the present invention;
FIG. 14 is a timing diagram of the operation of an embodiment of the second signal providing circuit;
fig. 15 is a schematic structural diagram of a display device according to an embodiment of the invention;
fig. 16 is a schematic structural diagram of an embodiment of a driving circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.
The signal providing method according to the embodiment of the present invention is applied to a driving circuit in a display device, wherein the driving circuit is electrically connected to a clock signal terminal and is configured to provide a driving signal, and when the display device operates in a low frequency driving mode, a display cycle includes a refresh phase and a hold phase, and the signal providing method includes:
and in the holding stage, controlling the duty ratio of a signal provided by the clock signal end to be less than or equal to a duty ratio threshold value.
In the signal providing method according to the embodiment of the present invention, when the display device operates in the low frequency driving mode, in the holding stage, the duty ratio of the signal provided by the clock signal terminal is controlled to be less than or equal to the duty ratio threshold, so as to reduce power consumption while realizing low frequency driving.
In at least one embodiment of the present invention, when the refresh rate of the display device is less than or equal to the common refresh rate, the display device operates in the low frequency driving mode.
Optionally, the common refresh frequency may be 60Hz, and when the refresh frequency of the display device is less than or equal to 60Hz, the display device operates in the low-frequency driving mode, but not limited thereto. For example, when the refresh frequency of the display device is 50Hz, 40Hz, 30Hz, 20Hz, 10Hz, or 1Hz, the display device operates in the low frequency driving mode.
Optionally, the duty cycle threshold is greater than or equal to 5% and less than or equal to 45%. For example, the duty cycle threshold may be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, or 45%, but is not limited thereto.
According to a specific embodiment, the driving circuit is electrically connected to a first node, a second node, a first voltage terminal, a second voltage terminal, and a driving signal output terminal, respectively, and is configured to control the connection between the driving signal output terminal and the first voltage terminal under the control of the potential of the second node, and control the connection between the driving signal output terminal and the second voltage terminal under the control of the potential of the first node, where the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage terminal is an invalid voltage signal; the signal providing method includes:
in the refreshing stage, controlling the first voltage end to provide a first voltage signal;
and in the holding stage, controlling the clock signal end to output a direct current voltage signal, and controlling the first voltage end to provide a second voltage signal.
In specific implementation, when a driving signal provided by the driving signal output end is connected to a grid electrode of the n-type transistor, the effective voltage signal is a high voltage signal, and the invalid voltage signal is a low voltage signal;
when the driving signal provided by the driving signal output end is connected to the grid electrode of the p-type transistor, the effective voltage signal is a low voltage signal, and the invalid voltage signal is a high voltage signal.
At least one embodiment of the present invention is described by taking the active voltage signal as the high voltage signal and the inactive voltage signal as the low voltage signal.
As shown in fig. 1, the driving circuit 10 is electrically connected to a first node N1, a second node N2, a first voltage terminal V1, a second voltage terminal V2 and a driving signal output terminal OUT, respectively, for controlling the communication between the driving signal output terminal OUT and the first voltage terminal V1 under the control of the potential of the second node N2, and controlling the communication between the driving signal output terminal OUT and the second voltage terminal V2 under the control of the potential of the first node N1.
In at least one embodiment of the present invention, the first voltage terminal V1 may be a high voltage terminal, and the second voltage terminal V2 may be a low voltage terminal.
As shown in fig. 2, an embodiment of the driving circuit 10 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3;
a gate of T1 is electrically connected to the first clock signal terminal CK, a source of T1 is electrically connected to the start voltage terminal STV, and a drain of T1 is electrically connected to the first node N1;
a gate of the T2 is electrically connected to the first node N1, a source of the T2 is electrically connected to the gate of the T6, and a drain of the T2 is electrically connected to the first clock signal terminal CK;
a gate of T3 is electrically connected to the first clock signal terminal CK, a source of T3 is electrically connected to a low voltage terminal VGL, and a drain of T3 is electrically connected to a gate of T6;
a gate of the T4 is electrically connected to the second clock signal terminal CB, a source of the T4 is electrically connected to the first node N1, and a drain of the T4 is electrically connected to a source of the T5;
the gate of T5 is electrically connected with the gate of T6, and the drain of T5 is electrically connected with the high voltage end VGH;
a source of the T6 is electrically connected to the second clock signal terminal CB, and a drain of the T6 is electrically connected to a source of the T7;
a gate of the T7 is electrically connected to the second clock signal terminal CB, and a drain of the T7 is electrically connected to the second node N2;
a gate of the T8 is electrically connected to the first node N1, a source of the T8 is electrically connected to the high voltage terminal VGH, and a drain of the T8 is electrically connected to the second node N2;
a gate of the T9 is electrically connected to the second node N2, a source of the T9 is electrically connected to the high voltage terminal VGH, and a drain of the T9 is electrically connected to the driving signal output terminal OUT;
a gate of the T10 is electrically connected to the first node N1, a source of the T10 is electrically connected to the low voltage terminal VGL, and a drain of the T10 is electrically connected to the driving signal output terminal OUT;
a first terminal of C1 is electrically connected to the first node, and a second terminal of C1 is electrically connected to the second clock signal terminal CB;
a first end of the C2 is electrically connected with the gate of the T6, and a second end of the C2 is electrically connected with the drain of the T6;
a first terminal of C3 is electrically connected to the second node N2, and a second terminal of C3 is electrically connected to the high voltage terminal VGH.
In at least one embodiment of the present invention, the clock signal terminal may include the first clock signal terminal CK and a second clock signal terminal CB.
As shown in fig. 3, an embodiment of a pixel circuit included in a display panel in the display device may include an organic light emitting diode O1, a first initialization transistor M1, a compensation control transistor M2, a second initialization transistor M3, a driving transistor M0, a data writing transistor M4, first and second light emission control transistors M5 and M6, and a storage capacitor Cst;
the gate of M1 is electrically connected to the first scan line S1, the source of M1 is electrically connected to the first initial voltage terminal VIN1, and the drain of M1 is electrically connected to the driving node N0;
the gate of M2 is electrically connected to the second scan line S2, the source of M2 is electrically connected to the driving node N0, and the drain of M2 is electrically connected to the drain of M0;
the gate of M3 is electrically connected to the third scan line S3, the source of M3 is electrically connected to the second initial voltage terminal VIN2, and the drain of M3 is electrically connected to the anode of O1;
the gate of M4 is electrically connected with the fourth scanning line S4, the source of M4 is electrically connected with the Data line Data, and the drain of M4 is electrically connected with the source of M0;
a gate of M5 is electrically connected to the emission control line EM, a source of M5 is electrically connected to the power voltage terminal ELVDD, and a drain of M5 is electrically connected to the source of M0;
a gate of M6 is electrically connected to the emission control line EM, a source of M6 is electrically connected to a drain of M0, and a drain of M6 is electrically connected to an anode of O1;
the cathode of O1 is electrically connected to the low voltage line ELVSS.
In the embodiment of the pixel circuit shown in fig. 3, M1 and M2 are oxide thin film transistors, and M3, M4, M5, M6 and M0 are all low temperature polysilicon thin film transistors;
m1 and M2 are n-type transistors, and M3, M4, M5, M6, and M0 are all p-type transistors.
The embodiment of the pixel circuit shown in fig. 3 may be an LTPO (low temperature poly oxide) pixel circuit.
In at least one embodiment of the present invention, the driving circuit may provide the first scan signal to the S1 through the driving signal output terminal thereof, and the other driving circuit may provide the second scan signal to the S2 through the driving signal output terminal thereof.
In the related art, LTPO technology is adopted to realize low refresh frequency display, when the refresh frequency is 1Hz, one frame time (i.e. one display period) may include, for example, a refresh phase and a hold phase that are set in sequence, the duration of the refresh phase may be 1s/120, and the duration of the hold phase may be 119 s/120; the holding phase may include 119 holding periods, and the duration of each holding period may be 1 s/120; but not limited thereto;
in the refresh phase, initialization and data writing operations of the pixel circuit are performed, and in the hold phase, no data writing is performed, and only in each hold period, the EM and S3 are controlled to be turned on to perform initialization of the pixel anode, so as to improve the flicker phenomenon. In the hold phase, the first scan line S1 and the second scan line S2 are not turned on, that is, the potential of the first scan signal provided in S1 and the potential of the second scan signal provided in S2 are both low voltages, but in the related art, the first clock signal terminal CK and the second clock signal terminal CB still normally output clock signals in the hold phase, so that power consumption is high.
As shown in fig. 4, in operation of the embodiment of the pixel circuit shown in fig. 2, the driving period may include an output phase t1, a reset phase t2, and an output off-hold phase t3, which are sequentially arranged;
in the output phase T1, T9 is turned on under the control of the potential of the second node N2 to control OUT to output a high voltage signal; t10 is turned off under the control of the potential of the first node N1;
in the reset phase T1, T9 is turned off under the control of the potential of the second node N2, and T10 is turned on under the control of the potential of the first node N1 to control OUT to output a low voltage signal;
in the output off stage T2, when the second clock signal terminal CB normally outputs the clock signal, the potential of the second clock signal provided by the second clock signal terminal CB jumps from the high voltage to the low voltage at regular intervals, so as to pull down the potential of N1, ensure that T10 is turned on well, output the low voltage signal, and ensure that the low voltage signal output by OUT is stable, and if the second clock signal terminal CB outputs the dc voltage signal, the potential of N1 cannot be pulled down through the coupling of C1, and the good on state of T10 cannot be ensured, as a result, as shown in fig. 5, the potential of the driving signal output by OUT is gradually increased by the leakage of T9.
In fig. 5, the vertical axis is Vout in units of V (volts), and the horizontal axis is time t in units of s (seconds); here, Vout is a potential of a drive signal output from OUT.
Based on the above problem, a signal providing method according to at least one embodiment of the present invention may include:
in the refreshing stage, controlling the first voltage end to provide a first voltage signal;
and in the holding stage, controlling the clock signal end to output a direct current voltage signal, and controlling the first voltage end to provide a second voltage signal.
At least one embodiment of the present invention controls the first voltage terminal to provide the second voltage signal in the holding phase by controlling, wherein the second voltage signal may be a low voltage signal, so that even if T9 leaks, the potential of the driving signal output by OUT is not pulled high, thereby avoiding the problem that the potential of the driving signal output by OUT gradually rises in the output-off holding phase, and ensuring that OUT continuously outputs the low voltage signal in the output-off phase.
In at least one embodiment of the present invention, the dc voltage signal may be a high voltage signal, but not limited thereto.
As shown in FIG. 6, in at least one embodiment of the present invention, the CK and CB are controlled to normally output clock signals during the refresh phase P1, and to output high voltage signals during the hold phase P2;
controlling the VGH to normally output a high voltage signal during a refresh period P1;
in the hold period P2, the VGH is controlled to output a low voltage signal.
As shown in fig. 7, by adopting the operation timing shown in fig. 6, the OUT continues to output the low voltage signal in the output off hold stage. In fig. 7, the vertical axis is Vout in units of V (volts), and the horizontal axis is time t in units of s (seconds); here, Vout is a potential of a drive signal output from OUT.
In fig. 8, a first clock signal terminal electrically connected to the driving circuit for supplying the first scan signal is denoted by S1_ CK, a first second clock signal terminal electrically connected to the driving circuit for supplying the first scan signal is denoted by S1_ CB, a second first clock signal terminal electrically connected to the driving circuit for supplying the second scan signal is denoted by S2_ CK, and a second clock signal terminal electrically connected to the driving circuit for supplying the second scan signal is denoted by S2_ CB;
as shown in fig. 8, in the refresh phase P1, S1_ CK and S2_ CK provide a first clock signal, and S1_ CB and S2_ CB provide a second clock signal;
in fig. 8, a first holding period denoted P21 and included for the holding phase P2, a second holding period denoted P22 and included for the holding phase P2, a third holding period denoted P23 and included for the holding phase P2, a fourth holding period denoted P24 and included for the holding phase P2, a one hundred sixteenth holding period denoted P2116 and included for the holding phase P2, a one hundred seventeenth holding period denoted P2117 and included for the holding phase P2, a one hundred eighteenth holding period denoted P2118 and included for the holding phase P2, and a one hundred nineteen holding period denoted P2119 and included for the holding phase P2.
As shown in fig. 8, in the holding phase P2, S1_ CK, S2_ CK, S1_ CB, and S2_ CB all provide a high voltage signal.
According to another specific embodiment, the display device includes a display panel including a plurality of pixel circuits, the driving circuit for providing the pixel circuits with the driving signals; the pixel circuit is electrically connected with the data line and receives data voltage from the data line; the holding phase comprises a plurality of holding time periods and output time periods arranged between two adjacent holding time periods;
the signal providing method includes:
controlling the clock signal end to output a direct current voltage signal in the maintaining time period;
controlling the clock signal end to output a corresponding clock signal in the output time period;
the duration of the maintaining period is an interval time.
In a specific implementation, the holding phase may include N sustain time periods and N-1 output time periods, where N is an integer greater than 1, the output time period is set between two adjacent sustain time periods, the clock signal terminal is controlled to output a dc voltage signal in the sustain time period, and the clock signal terminal is controlled to output a corresponding clock signal in the output time period, so as to ensure that the driving signal output by the driving signal output terminal is stable while saving power consumption in the low frequency driving mode.
Optionally, in the output time period, the clock signal output by the clock signal terminal has at least one pulse, for example, the clock signal may have one pulse, but is not limited thereto.
In specific implementation, the pulse may be a downward pulse, but is not limited thereto.
Alternatively, the interval time may be set in advance, or may be selected by detecting the brightness of the display panel in the sampling phase.
In at least one embodiment of the present invention, a sampling phase may be further included before the display period; the signal providing method further includes:
in the sampling stage, controlling the clock signal end to output the direct-current voltage signal, controlling the data line to provide constant data voltage, detecting the display brightness of the display panel, and recording corresponding change time when detecting that the brightness change reaches a brightness change value threshold;
the interval time is greater than a preset threshold time and less than or equal to the change time.
After the display panel module is made, adjusting the time sequence, controlling the clock signal end to output a high voltage signal in the holding stage, shooting the brightness change of the display panel by using a high-precision camera, recording corresponding time when the brightness changes to a certain degree (for example, the change reaches 2%), recording the corresponding time in a storage unit (the storage unit can be a newly-added storage unit, and can also be integrated in a time control module in a drive IC (integrated circuit)), sampling and storing each display panel, and using the display panel when the display panel normally works. When the screen is normally lighted, in the holding stage, the brightness of the display panel can be reduced to the critical value at each corresponding time interval, and at the moment, the clock signal end can be controlled to output a pulse which is jumped from a high voltage to a low voltage once so as to pull down the potential of the first node in the driving circuit, so that the driving circuit outputs a low voltage signal again, and the normal work of the screen body is maintained.
Optionally, the dc voltage signal is a high voltage signal, and in the output period, when the potential of the clock signal is a low voltage, a difference between a voltage value of the high voltage signal and a voltage value of the clock signal is not changed, for example, the difference may be greater than or equal to 1mV and less than or equal to 5 mV.
As shown in fig. 9, in the refresh phase P1, the first clock signal terminal CK is controlled to output the first clock signal, and the second clock signal terminal CB is controlled to output the second clock signal;
in fig. 9, a first holding period denoted by P31 and included for the holding phase P2, a second holding period denoted by P32 and included for the holding phase P2, a first output period denoted by P41, and P41 disposed between P31 and P32;
a third holding period, denoted P33, comprised by the holding phase P2, a second output period, denoted P42, P42 being arranged between P32 and P33;
reference numeral P43 is a third output period;
an N-3 th output period denoted by P4N-3 and included in the hold phase P2;
an N-2 th sustain period, denoted P3N-2, included for the hold phase P2, an N-2 th output period, denoted P4N-2, included for the hold phase P2, and an N-1 th sustain period, denoted P3N-1, included for the hold phase P2; P4N-2 is disposed between P3N-2 and P3N-1;
an Nth sustain period, denoted by P3N, included in the hold phase P2, an N-1 th output period, denoted by P4N-1, P4N-1 being disposed between P3N-1 and P3N;
high voltage signals are output at P31, P32, P33, P3N-2, P3N-1 and P3N, CK and CB;
at P41, P42, P43, P4N-3, P4N-2, P4N-1 and P4N, CK and CB output clock signals having one pulse down; and when the potential of the clock signal is a low voltage, the difference between the voltage value of the high voltage signal output by CK and CB and the voltage value of the clock signal is not changed at P31, P32, P33, P34, P3N-1 and P3N.
Fig. 10 is a waveform of a signal output from OUT in the output off hold phase by adopting the operation timing shown in fig. 9. In fig. 5, the vertical axis is Vout in units of V (volts), and the horizontal axis is time t in units of s (seconds); here, Vout is a potential of a drive signal output from OUT.
In at least one embodiment of the present invention, when the display panel displays a low-luminance image, the dc voltage signal is a high voltage signal, and in a plurality of output time periods, when the potential of the clock signal is a low voltage, a difference between a voltage value of the high voltage signal and a voltage value of the clock signal may be gradually decreased to compensate for the attenuation of luminance;
when the display panel displays a high-brightness image, the direct-current voltage signal is a high-voltage signal, and in a plurality of output time periods, when the potential of the clock signal is a low voltage, the difference between the voltage value of the high-voltage signal and the voltage value of the clock signal is gradually increased to weaken the increase of brightness.
In an implementation, the voltage difference between the high voltage and the low voltage outputted by the clock signal terminal determines the strength of the coupling, for example, during the hold phase, the transition of the signal outputted by the clock signal terminal affects the driving signal outputted by the driving signal output terminal. The larger the voltage difference is, the stronger the coupling action is, the smaller the voltage value of the low-voltage signal output by the driving signal output terminal is, and conversely, the smaller the voltage difference is, the higher the voltage value of the low-voltage signal output by the driving signal output terminal is. At low frequency driving, the brightness of the display panel differs between different hold periods. For example, in a high-luminance screen, the luminance of the display panel is gradually decreased, and in a low-luminance screen, the luminance of the display panel is gradually increased. In at least one embodiment of the present invention, the clock signal end is intermittently controlled to output a clock signal in the holding stage, the clock signal may include at least one downward pulse, and the voltage difference between the high voltage and the low voltage of the clock signal may be changed in the holding stage, so as to affect the voltage value of the driving signal output by the driving circuit, and finally affect the change of light emission of the pixel circuit, thereby implementing a compensation process, improving the uniformity of low-frequency display brightness, and improving the phenomenon of low-frequency display flicker.
In fig. 11, the first clock terminal labeled CK and the second clock terminal labeled CB;
as shown in fig. 11, CK provides a first clock signal and CB provides a second clock signal during a refresh phase P1;
in fig. 11, a first holding period denoted P21 and included for the holding phase P2, a second holding period denoted P22 and included for the holding phase P2, a third holding period denoted P23 and included for the holding phase P2, a fourth holding period denoted P24 and included for the holding phase P2, a one hundred sixteenth holding period denoted P2116 and included for the holding phase P2, a one hundred seventeenth holding period denoted P2117 and included for the holding phase P2, a one hundred eighteenth holding period denoted P2118 and included for the holding phase P2, and a one hundred nineteen holding period denoted P2119 and included for the holding phase P2.
As shown in fig. 11, in the output period in each holding period, CK and CB output the corresponding clock signals, respectively, having one pulse downward;
in an output period in the first holding period P21, a voltage difference value between a high voltage value of the clock signal and a low voltage value of the clock signal is Δ V1;
in an output period in the second holding period P22, a voltage difference value between a high voltage value of the clock signal and a low voltage value of the clock signal is Δ V2;
in an output period in the third holding period P23, a voltage difference value between a high voltage value of the clock signal and a low voltage value of the clock signal is Δ V3;
in an output period in the second holding period P24, a voltage difference value between a high voltage value of the clock signal and a low voltage value of the clock signal is Δ V4;
in the output period in the first holding period P2116, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δ V116;
in the output period in the second holding period P2117, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δ V117;
in the output period in the third holding period P2118, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δ V118;
in the output period in the second holding period P2119, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δ V119;
Δ V1, Δ V2, Δ V3, Δ V4, …, Δ V116, Δ V117, Δ V118, and Δ V119 are gradually reduced and changed in a stepwise manner;
the operation timing shown in fig. 11 can be applied to displaying a high-luminance screen. For example, when the brightness of the picture is greater than 800nit, the picture may be a high-brightness picture, but not limited thereto.
In fig. 12, reference numeral CK denotes a first clock signal terminal, and reference numeral CB denotes a second clock signal terminal;
as shown in fig. 12, CK provides a first clock signal and CB provides a second clock signal during the refresh phase P1;
in fig. 12, a first holding period denoted P21 and included for the holding phase P2, a second holding period denoted P22 and included for the holding phase P2, a third holding period denoted P23 and included for the holding phase P2, a fourth holding period denoted P24 and included for the holding phase P2, a one hundred sixteenth holding period denoted P2116 and included for the holding phase P2, a one hundred seventeenth holding period denoted P2117 and included for the holding phase P2, a one hundred eighteenth holding period denoted P2118 and included for the holding phase P2, and a one hundred nineteen holding period denoted P2119 and included for the holding phase P2.
As shown in fig. 12, in the output period in each holding period, CK and CB output the corresponding clock signals, respectively, having one pulse downward;
in an output period in the first holding period P21, a voltage difference value between a high voltage value of the clock signal and a low voltage value of the clock signal is Δ V1;
in an output period in the second holding period P22, a voltage difference value between a high voltage value of the clock signal and a low voltage value of the clock signal is Δ V2;
in an output period in the third holding period P23, a voltage difference value between a high voltage value of the clock signal and a low voltage value of the clock signal is Δ V3;
in an output period in the second holding period P24, a voltage difference value between a high voltage value of the clock signal and a low voltage value of the clock signal is Δ V4;
in the output period in the first holding period P2116, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δ V116;
in the output period in the second holding period P2117, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δ V117;
in the output period in the third holding period P2118, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δ V118;
in the output period in the second holding period P2119, the voltage difference between the high voltage value of the clock signal and the low voltage value of the clock signal is Δ V119;
Δ V1, Δ V2, Δ V3, Δ V4, …, Δ V116, Δ V117, Δ V118, and Δ V119 are gradually increased and changed in a stepwise manner;
the operation timing shown in fig. 12 can be applied to displaying a low-luminance screen. For example, when the brightness of the frame is less than 4nit, the frame may be a low-brightness frame, but not limited thereto.
In at least one embodiment corresponding to fig. 11 and 12, an output period is set in each holding period, but not limited thereto.
In a specific implementation, the clock signal terminal may include a first clock signal terminal and a second clock signal terminal, but is not limited thereto.
The signal providing module according to an embodiment of the present invention is applied to a driving circuit in a display device, wherein the driving circuit is electrically connected to a clock signal terminal and configured to provide a driving signal, when a refresh frequency of the display device is less than a predetermined frequency, a display cycle includes a refresh stage and a hold stage, and the signal providing module may include:
and the first signal providing circuit is used for controlling the duty ratio of the signal provided by the clock signal end to be less than or equal to a duty ratio threshold value in a holding phase.
When the signal providing module disclosed by the embodiment of the invention works, when the display device works in a low-frequency driving mode, the signal providing circuit controls the duty ratio of a signal provided by the clock signal end to be smaller than or equal to a duty ratio threshold value in a holding stage so as to realize low-frequency driving and reduce power consumption.
According to a specific embodiment, the driving circuit is electrically connected to a first node, a second node, a first voltage terminal, a second voltage terminal, and a driving signal output terminal, respectively, and is configured to control the connection between the driving signal output terminal and the first voltage terminal under the control of the potential of the second node, and control the connection between the driving signal output terminal and the second voltage terminal under the control of the potential of the first node, where the first voltage signal is an effective voltage signal, and the second voltage signal provided by the second voltage terminal is an invalid voltage signal; the signal providing module also comprises a second signal providing circuit;
the first signal providing circuit is used for controlling the clock signal end to output a direct current voltage signal in the holding stage;
the second signal providing circuit is used for controlling the first voltage end to provide a first voltage signal in the refreshing stage and controlling the first voltage end to provide a second voltage signal in the maintaining stage.
Optionally, the second signal providing circuit may include a control circuit and a control switch circuit; the control switch circuit comprises a first control transistor and a second control transistor;
a control electrode of the first control transistor is electrically connected with a first control line, a first electrode of the first control transistor is electrically connected with a second voltage line, and a second electrode of the first control transistor is electrically connected with the first voltage end; the second voltage line is used for providing a second voltage signal;
a control electrode of the second control transistor is electrically connected with a second control line, a first electrode of the second control transistor is electrically connected with a first voltage line, and a second electrode of the second control transistor is electrically connected with the first voltage end; the first voltage line is used for providing a first voltage signal;
the control circuit is configured to provide an inactive first control signal to the first control line to turn off the first control transistor and an active second control signal to the second control line to turn on the second control transistor during the refresh phase, and is further configured to provide an active first control signal to the first control line to turn on the first control transistor and an inactive second control signal to the second control line to turn off the second control transistor during the hold phase.
In specific implementation, the on-off of the first control transistor and the second control transistor can be controlled through the control circuit so as to control the first voltage end to provide different voltage signals in different time periods.
In at least one embodiment of the present invention, the first voltage signal may be a high voltage signal, and the second voltage signal may be a low voltage signal, but not limited thereto.
In at least one embodiment of the present invention, when the first control transistor and the second control transistor are n-type transistors, the potential of the active control signal may be a high voltage, and the potential of the inactive control signal may be a low voltage; when the first control transistor and the second control transistor are p-type transistors, the potential of the active control signal may be a low voltage, and the potential of the inactive control signal may be a high voltage.
As shown in fig. 13, the second signal supply circuit may include a control circuit 130, a first control transistor Tc1, and a second control transistor Tc 2;
the gate of the first control transistor Tc1 is electrically connected to a first control line SW1, the source of the first control transistor Tc1 is electrically connected to a low voltage line, and the drain of the first control transistor Tc1 is electrically connected to the first voltage terminal V1; the low voltage line is used for providing a low voltage signal Vgl;
the gate of the second control transistor Tc2 is electrically connected to a second control line SW2, the source of the second control transistor Tc2 is electrically connected to a high voltage line, and the drain of the second control transistor Tc2 is electrically connected to the first voltage terminal V1; the high voltage line is used for providing a high voltage signal Vgh;
the control circuit 130 is configured to provide an inactive first control signal to the first control line SW1 to turn off the first control transistor Tc1 during the refresh period, provide an active second control signal to the second control line SW2 to turn on the second control transistor Tc2, and provide an active first control signal to the first control line SW1 to turn on the first control transistor Tc1 and provide an inactive second control signal to the second control line SW2 to turn off the second control transistor Tc2 during the hold period.
In the embodiment of the second signal supply circuit shown in fig. 13, Tc1 and Tc2 are both p-type transistors.
In practical implementation, Tc1 and Tc2 may be disposed on the display panel, and the control circuit 130 may be disposed in the driving IC.
FIG. 14 is a timing diagram of the first control signal on SW1 and the second control signal on SW 2.
As shown in fig. 14, during the refresh period P1, the potential of the first control signal on SW1 is high voltage, and the potential of the second control signal on SW2 is low voltage; in the hold phase P2, the potential of the first control signal in SW1 is low, and the potential of the second control signal in SW2 is high.
According to another specific embodiment, the display device includes a display panel including a plurality of pixel circuits, the driving circuit for providing the pixel circuits with the driving signals; the pixel circuit is electrically connected with the data line and receives data voltage from the data line; the holding phase comprises a plurality of holding time periods and output time periods arranged between two adjacent holding time periods;
the first signal providing circuit is used for controlling the clock signal end to output a direct current voltage signal in the maintaining time period and controlling the clock signal end to output a corresponding clock signal in the output time period;
the duration of the maintaining period is an interval time.
In at least one embodiment of the present invention, when the display panel displays a low-luminance image, the dc voltage signal is a high voltage signal, and the first signal providing circuit is configured to gradually decrease a difference between a voltage value of the high voltage signal and a voltage value of the clock signal when the potential of the clock signal is a low voltage in a plurality of the output periods.
In at least one embodiment of the present invention, when the display panel displays a high-luminance image, the dc voltage signal is a high voltage signal, and the first signal providing circuit is configured to gradually increase a difference between a voltage value of the high voltage signal and a voltage value of the clock signal when the potential of the clock signal is a low voltage in a plurality of the output periods.
The display device provided by the embodiment of the invention comprises the signal providing module.
In particular implementation, the display device may include a driving integrated circuit and a display panel; the signal providing module also comprises a second signal providing circuit, and the second signal providing circuit comprises a control switch circuit and a control circuit;
the control circuit and a first signal providing circuit in the signal providing module can be arranged in the driving integrated circuit;
the first control transistor and the second control transistor are integrated on the display panel.
As shown in fig. 15, the display device according to the embodiment of the present invention includes a display panel 150, a driving circuit 151, and a display integrated circuit 152;
the driving circuit 151 is disposed at a left side of the display panel 150 and a right side of the display panel 150;
the display panel 150 includes a plurality of rows and columns of pixel circuits 153 disposed in an effective display area a 0;
the display device according to the embodiment of the present invention may include a second signal supply circuit including a control switch circuit 154 and a control circuit;
the display integrated circuit 152 is attached to the lower side of the display panel 150, and the control circuit may be disposed in the display integrated circuit 152.
As shown in fig. 16, the driving circuit 151 may include a first driving circuit 161, a second driving circuit 162, and a third driving circuit 163; wherein the content of the first and second substances,
the first driving circuit 161 is configured to provide a p-type driving signal, the second driving circuit 162 is configured to provide an n-type driving signal, and the third driving circuit 163 is configured to provide a light emission control signal.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A signal providing method applied to a driving circuit in a display device, wherein the driving circuit is electrically connected to a clock signal terminal and is used for providing a driving signal, and when the display device operates in a low frequency driving mode, a display period comprises a refresh phase and a hold phase, and the signal providing method comprises:
and in the holding stage, controlling the duty ratio of a signal provided by the clock signal end to be less than or equal to a duty ratio threshold value.
2. The signal providing method of claim 1, wherein the duty cycle threshold is greater than or equal to 5% and less than or equal to 45%.
3. The signal providing method according to claim 1, wherein the driving circuit is electrically connected to a first node, a second node, a first voltage terminal, a second voltage terminal and a driving signal output terminal, respectively, for controlling the connection between the driving signal output terminal and the first voltage terminal under the control of the potential of the second node, and controlling the connection between the driving signal output terminal and the second voltage terminal under the control of the potential of the first node, the first voltage signal is an active voltage signal, and the second voltage signal provided by the second voltage terminal is an inactive voltage signal; the signal providing method includes:
in the refreshing stage, controlling the first voltage end to provide a first voltage signal;
and in the holding stage, controlling the clock signal end to output a direct current voltage signal, and controlling the first voltage end to provide a second voltage signal.
4. The signal supplying method according to claim 1, wherein the display device includes a display panel including a plurality of pixel circuits, the driving circuit being configured to supply the driving signal to the pixel circuits; the pixel circuit is electrically connected with the data line and receives data voltage from the data line; the holding phase comprises a plurality of holding time periods and output time periods arranged between two adjacent holding time periods;
the signal providing method includes:
controlling the clock signal end to output a direct current voltage signal in the maintaining time period;
controlling the clock signal end to output a corresponding clock signal in the output time period;
the duration of the maintaining period is an interval time.
5. The signal providing method of claim 4, further comprising a sampling phase before the display period; the signal providing method further includes:
in the sampling stage, controlling the clock signal end to output the direct-current voltage signal, controlling the data line to provide constant data voltage, detecting the display brightness of the display panel, and recording corresponding change time when detecting that the brightness change reaches a brightness change value threshold;
the interval time is greater than a preset threshold time and less than or equal to the change time.
6. The signal supplying method according to claim 4 or 5, wherein the direct-current voltage signal is a high-voltage signal, and a difference between a voltage value of the high-voltage signal and a voltage value of the clock signal is constant when the potential of the clock signal is a low voltage in the output period.
7. The signal providing method according to claim 4 or 5, wherein the display panel displays a low-luminance picture, the DC voltage signal is a high voltage signal, and a difference between a voltage value of the high voltage signal and a voltage value of the clock signal is gradually decreased when the potential of the clock signal is a low voltage in a plurality of the output periods.
8. The signal providing method according to claim 4 or 5, wherein the display panel displays a high-luminance picture, the direct-current voltage signal is a high-voltage signal, and a difference between a voltage value of the high-voltage signal and a voltage value of the clock signal gradually increases when a potential of the clock signal is a low voltage in a plurality of the output periods.
9. The signal providing method according to any one of claims 1 to 5, wherein the clock signal terminal includes a first clock signal terminal and a second clock signal terminal.
10. A signal providing module, applied to a driving circuit in a display device, wherein the driving circuit is electrically connected to a clock signal terminal and is configured to provide a driving signal, wherein when a refresh frequency of the display device is less than a predetermined frequency, a display cycle includes a refresh phase and a hold phase, and the signal providing module includes:
and the first signal providing circuit is used for controlling the duty ratio of the signal provided by the clock signal end to be less than or equal to a duty ratio threshold value in a holding phase.
11. The signal providing module of claim 10, wherein the driving circuit is electrically connected to a first node, a second node, a first voltage terminal, a second voltage terminal, and a driving signal output terminal, respectively, for controlling the connection between the driving signal output terminal and the first voltage terminal under the control of the potential of the second node, and controlling the connection between the driving signal output terminal and the second voltage terminal under the control of the potential of the first node, the first voltage signal being an active voltage signal, and the second voltage signal provided by the second voltage terminal being an inactive voltage signal; the signal providing module also comprises a second signal providing circuit;
the first signal providing circuit is used for controlling the clock signal end to output a direct current voltage signal in the holding stage;
the second signal providing circuit is used for controlling the first voltage end to provide a first voltage signal in the refreshing stage and controlling the first voltage end to provide a second voltage signal in the maintaining stage.
12. The signal providing module of claim 11 wherein the second signal providing circuit comprises a control circuit and a control switch circuit; the control switch circuit comprises a first control transistor and a second control transistor;
a control electrode of the first control transistor is electrically connected with a first control line, a first electrode of the first control transistor is electrically connected with a second voltage line, and a second electrode of the first control transistor is electrically connected with the first voltage end; the second voltage line is used for providing a second voltage signal;
a control electrode of the second control transistor is electrically connected with a second control line, a first electrode of the second control transistor is electrically connected with a first voltage line, and a second electrode of the second control transistor is electrically connected with the first voltage end; the first voltage line is used for providing a first voltage signal;
the control circuit is configured to provide an inactive first control signal to the first control line to turn off the first control transistor and an active second control signal to the second control line to turn on the second control transistor during the refresh phase, and is further configured to provide an active first control signal to the first control line to turn on the first control transistor and an inactive second control signal to the second control line to turn off the second control transistor during the hold phase.
13. The signal providing module of claim 11, wherein the display device comprises a display panel comprising a plurality of pixel circuits, the driving circuit for providing the driving signals to the pixel circuits; the pixel circuit is electrically connected with the data line and receives data voltage from the data line; the holding phase comprises a plurality of holding time periods and output time periods arranged between two adjacent holding time periods;
the first signal providing circuit is used for controlling the clock signal end to output a direct current voltage signal in the maintaining time period and controlling the clock signal end to output a corresponding clock signal in the output time period;
the duration of the maintaining period is an interval time.
14. The signal providing module of claim 13, wherein the display panel displays a low brightness image, the dc voltage signal is a high voltage signal, and the first signal providing circuit is configured to gradually decrease a difference between a voltage value of the high voltage signal and a voltage value of the clock signal in a plurality of the output periods when the potential of the clock signal is a low voltage.
15. The signal providing module of claim 13, wherein the display panel displays a high brightness image, the dc voltage signal is a high voltage signal, and the first signal providing circuit is configured to gradually increase a difference between a voltage value of the high voltage signal and a voltage value of the clock signal when the potential of the clock signal is a low voltage during a plurality of the output periods.
16. A display device comprising a signal providing module according to any one of claims 10 to 15.
17. The display device according to claim 16, wherein the display device comprises a display panel and a driver integrated circuit; the signal providing module also comprises a second signal providing circuit, and the second signal providing circuit comprises a control circuit and a control switch circuit;
the control circuit and a first signal providing circuit in the signal providing module are arranged in the driving integrated circuit;
the control switch circuit is integrated on the display panel.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114783379A (en) * | 2022-05-26 | 2022-07-22 | 云谷（固安）科技有限公司 | Pixel circuit, driving method thereof and display panel |
| WO2023216175A1 (en) * | 2022-05-12 | 2023-11-16 | 京东方科技集团股份有限公司 | Display substrate and driving method therefor, and display apparatus |
Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100134399A1 (en) * | 2008-11-28 | 2010-06-03 | Samsung Electronics Co., Ltd. | Method of driving a gate line, gate drive circuit and display apparatus having the gate drive circuit |
| CN102723064A (en) * | 2012-03-28 | 2012-10-10 | 北京大学深圳研究生院 | Driving circuit unit, gate driving circuit and display device |
| US20150138176A1 (en) * | 2012-05-11 | 2015-05-21 | Sharp Kabushiki Kaisha | Scanning signal line drive circuit and display device provided with same |
| CN108766383A (en) * | 2018-06-12 | 2018-11-06 | 京东方科技集团股份有限公司 | Shift register cell and shift-register circuit, display device |
| EP3444804A1 (en) * | 2017-08-16 | 2019-02-20 | LG Display Co., Ltd. | Gate driver circuit and display device using the same |
| CN110322851A (en) * | 2019-05-21 | 2019-10-11 | 合肥维信诺科技有限公司 | A kind of scan drive circuit and display panel |
| US20190348007A1 (en) * | 2018-05-09 | 2019-11-14 | Samsung Display Co., Ltd. | Gate driver and display device having the same |
| US20190378463A1 (en) * | 2018-06-08 | 2019-12-12 | Samsung Display Co., Ltd. | Scan driver and display device having the same |
| US20200058259A1 (en) * | 2017-05-09 | 2020-02-20 | HKC Corporation Limited | Display device, driving circuit and driving method for the same |
| CN111326109A (en) * | 2018-05-07 | 2020-06-23 | 上海天马微电子有限公司 | Light emission control signal generation circuit, display panel, and display device |
| CN111445866A (en) * | 2020-05-08 | 2020-07-24 | 京东方科技集团股份有限公司 | Shift register, driving method, driving control circuit and display device |
| CN111489701A (en) * | 2020-05-29 | 2020-08-04 | 上海天马有机发光显示技术有限公司 | Array substrate, driving method thereof, display panel and display device |
| CN111489674A (en) * | 2019-01-28 | 2020-08-04 | 三星显示有限公司 | Display device |
| CN111862890A (en) * | 2020-08-28 | 2020-10-30 | 上海天马有机发光显示技术有限公司 | Display panel, driving method thereof and display device |
| CN112017595A (en) * | 2020-09-02 | 2020-12-01 | Tcl华星光电技术有限公司 | Display panel and electronic device |
| CN112771602A (en) * | 2018-09-20 | 2021-05-07 | 三星显示有限公司 | Display device |
| CN112951308A (en) * | 2021-02-22 | 2021-06-11 | 京东方科技集团股份有限公司 | Shift register unit, driving method, driving circuit and display device |
| CN113409874A (en) * | 2021-06-16 | 2021-09-17 | 京东方科技集团股份有限公司 | Shift register, display panel and display device |
| CN113450709A (en) * | 2020-03-24 | 2021-09-28 | 三星显示有限公司 | Display device and method of driving display panel using the same |
-
2021
- 2021-10-21 CN CN202111228557.7A patent/CN113903307B/en active Active
Patent Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100134399A1 (en) * | 2008-11-28 | 2010-06-03 | Samsung Electronics Co., Ltd. | Method of driving a gate line, gate drive circuit and display apparatus having the gate drive circuit |
| CN102723064A (en) * | 2012-03-28 | 2012-10-10 | 北京大学深圳研究生院 | Driving circuit unit, gate driving circuit and display device |
| US20150138176A1 (en) * | 2012-05-11 | 2015-05-21 | Sharp Kabushiki Kaisha | Scanning signal line drive circuit and display device provided with same |
| US20200058259A1 (en) * | 2017-05-09 | 2020-02-20 | HKC Corporation Limited | Display device, driving circuit and driving method for the same |
| EP3444804A1 (en) * | 2017-08-16 | 2019-02-20 | LG Display Co., Ltd. | Gate driver circuit and display device using the same |
| CN111326109A (en) * | 2018-05-07 | 2020-06-23 | 上海天马微电子有限公司 | Light emission control signal generation circuit, display panel, and display device |
| US20190348007A1 (en) * | 2018-05-09 | 2019-11-14 | Samsung Display Co., Ltd. | Gate driver and display device having the same |
| US20190378463A1 (en) * | 2018-06-08 | 2019-12-12 | Samsung Display Co., Ltd. | Scan driver and display device having the same |
| CN108766383A (en) * | 2018-06-12 | 2018-11-06 | 京东方科技集团股份有限公司 | Shift register cell and shift-register circuit, display device |
| CN112771602A (en) * | 2018-09-20 | 2021-05-07 | 三星显示有限公司 | Display device |
| CN111489674A (en) * | 2019-01-28 | 2020-08-04 | 三星显示有限公司 | Display device |
| CN110322851A (en) * | 2019-05-21 | 2019-10-11 | 合肥维信诺科技有限公司 | A kind of scan drive circuit and display panel |
| CN113450709A (en) * | 2020-03-24 | 2021-09-28 | 三星显示有限公司 | Display device and method of driving display panel using the same |
| CN111445866A (en) * | 2020-05-08 | 2020-07-24 | 京东方科技集团股份有限公司 | Shift register, driving method, driving control circuit and display device |
| CN111489701A (en) * | 2020-05-29 | 2020-08-04 | 上海天马有机发光显示技术有限公司 | Array substrate, driving method thereof, display panel and display device |
| CN111862890A (en) * | 2020-08-28 | 2020-10-30 | 上海天马有机发光显示技术有限公司 | Display panel, driving method thereof and display device |
| CN112017595A (en) * | 2020-09-02 | 2020-12-01 | Tcl华星光电技术有限公司 | Display panel and electronic device |
| CN112951308A (en) * | 2021-02-22 | 2021-06-11 | 京东方科技集团股份有限公司 | Shift register unit, driving method, driving circuit and display device |
| CN113409874A (en) * | 2021-06-16 | 2021-09-17 | 京东方科技集团股份有限公司 | Shift register, display panel and display device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023216175A1 (en) * | 2022-05-12 | 2023-11-16 | 京东方科技集团股份有限公司 | Display substrate and driving method therefor, and display apparatus |
| CN114783379A (en) * | 2022-05-26 | 2022-07-22 | 云谷（固安）科技有限公司 | Pixel circuit, driving method thereof and display panel |
| CN114783379B (en) * | 2022-05-26 | 2024-02-09 | 云谷（固安）科技有限公司 | Pixel circuit, driving method thereof and display panel |
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