KR20150053475A - The Method for Driving of Organic Light Emitting diode Display - Google Patents

Abstract

The present invention relates to a method for driving an organic light emitting diode. The method for driving the organic light emitting diode according to the present invention includes an initialization step of initializing a potential between a gate and a source of a driving transistor by applying a reference voltage to a first node between a gate electrode and a drain line in a (n-2)-th horizontal period for scanning a (n-2)-th horizontal line and applying an initialization voltage to a second node between a source electrode and the organic light emitting diode, a first sampling step of raising the potential of the source electrode of the driving transistor by supplying a driving voltage to the second node when the second node is floated in a (n-1) horizontal period, a second sampling step of saturating the potential of the source electrode which firstly rises in the first sampling step to a voltage corresponding to a difference between a reference voltage and the threshold voltage of the driving transistor, in a n-th horizontal period, and a step of emitting light from the organic light emitting diode in the n-th horizontal period while compensating a data voltage according to a light emission control signal regardless of the threshold voltage of the driving transistor in the n-th horizontal period.

Description

[0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to a driving method of an organic light emitting diode display.

2. Description of the Related Art Flat panel displays (FPDs) are widely used not only for monitors of desktop computers but also for portable computers such as notebook computers and PDAs, as well as mobile phone terminals, because they are advantageous in downsizing and light weight. Such a flat panel display device includes a liquid crystal display (LCD) (LCD), a plasma display panel (PDP), a field emission display (FED) and an organic light emitting diode display (OLED).

Among these organic light emitting diode display devices, the organic light emitting diode display device has a high response speed, high luminance efficiency, and a large viewing angle. In general, an organic light emitting diode display device applies a data voltage to a gate electrode of a driving transistor by using a switch transistor turned on by a scan signal, and emits an organic light emitting diode by using a data voltage supplied to the driving transistor . That is, the current supplied to the organic light emitting diode is controlled by the data voltage applied to the gate electrode of the driving transistor. However, due to the characteristics of the manufacturing process, each of the driving transistors formed in the pixels deviates from the threshold voltage (Vth). The current supplied to the organic light emitting diode may be different from the designed value due to the deviation of the threshold voltage of the driving transistor, and accordingly, the luminance to emit light may be different from the desired value.

Recently, a lot of methods for compensating the threshold voltage of a driving transistor have been studied. For example, the 'organic light emitting device and its driving method' disclosed in Japanese Laid-Open Patent Application No. 10-2011-0078387, So that the deterioration of image quality caused by the device variation can be improved.

In addition to the aforementioned prior arts, many prior art methods are a method of compensating for a threshold voltage, in which, before an emission period of an organic light emitting diode, an initialization period for initializing a driving transistor to a specific voltage, Is adopted as the driving method. In this method, the sampling period is for making the voltage deviation between the gate and source electrodes of the driving transistor close to the threshold voltage, and the more the time is enough, the more efficient the deviation of the threshold voltage can be. However, since one horizontal period (H) is limited in the driving waveform applied to one scan line, it is difficult to secure sufficient time in the sampling period. In particular, since the 1H period becomes shorter as the resolution is increased, there is a difficulty in securing a further sampling period.

Accordingly, the present invention provides a method of driving an organic light emitting diode display device for sufficiently compensating a variation in threshold voltage of a driving transistor by sufficiently ensuring a sampling period.

A driving method of an organic light emitting diode according to the present invention is characterized in that a reference voltage is applied to a first node between the gate electrode and the data line in an (n-2) horizontal period for scanning the (n-2) An initialization step of initializing a potential between a gate and a source of the driving transistor by applying an initialization voltage to a second node between the source electrode and the organic light emitting diode; A first sampling step of raising the potential of the source electrode of the driving transistor by providing the driving voltage to the second node while floating the second node within the (n-1) horizontal period; The voltage of the source electrode that has risen primarily in the first sampling step may be set to a voltage corresponding to a difference between the reference voltage and the threshold voltage of the driving transistor by performing the same process as the first sampling step in the n- A second sampling step of saturating with the second sampling step; And emitting the organic light emitting diode to the nth horizontal line while compensating the data voltage in accordance with the emission control signal regardless of the threshold voltage of the driving transistor in the nth horizontal period, .

The driving method of the organic light emitting diode display according to the present invention can secure a sufficient scan time because the sampling period is performed over two scan periods. Therefore, the present invention can effectively improve the picture quality deterioration due to the threshold voltage deviation of the driving transistor. Particularly, the present invention divides the sampling for the current single light emission into the previous scan period and the current scan period, so that the limited scan period can be efficiently used. Accordingly, even in a high-quality display device having a short scan period, .

1 is a view showing an organic light emitting diode display device according to the present invention.
2 is a view showing an embodiment of a pixel included in an organic light emitting diode display device according to the present invention.
3 is a timing diagram for driving an organic light emitting diode display device according to the present invention.
4A to 4E are views illustrating a method of driving an organic light emitting diode display according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 1 shows an organic light emitting diode display device according to the present invention.

1, an organic light emitting diode display device according to the present invention includes a display panel 10, a data driving circuit 12, a gate driving circuit 13, and a timing controller (not shown) in which pixels P are arranged in a matrix 11).

The display panel 10 includes a plurality of pixels P and is for displaying an image based on the gradation displayed by each of the pixels P. [ The pixels P are arranged in a matrix form in the display panel 10 by arranging a plurality of first to m-th horizontal lines HL1 to HL [m] at regular intervals.

At this time, each of the pixels P is arranged in a region where the data line portion 14 and the plurality of gate line portions 15 intersect at right angles. The data line section 14 connected to each pixel P includes an initialization line 14a and a data line 14b and the gate line section 15 includes a previous stage scan line 15a, 15b and an emission line 15c.

Each of the pixels P includes an organic light emitting diode OLED, a driving transistor DT and first through third transistors T1, T2 and T3, a storage capacitor Cs and an auxiliary capacitor C1. The driving transistor DT and the first to third transistors T1, T2 and T3 may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor layer. The oxide TFT is advantageous for large-sized display panel 10 when considering both electron mobility and process variations. However, the present invention is not limited to this, and the semiconductor layer of the TFT may be formed of amorphous silicon, polysilicon, or the like.

The timing controller 11 is for controlling the driving timings of the data driving circuit 12 and the gate driving circuit 13. To this end, the timing controller 11 rearranges the digital video data RGB input from the outside in accordance with the resolution of the display panel 10 and supplies the digital video data RGB to the data driving circuit 12. The timing controller 11 is also connected to the data driving circuit 12 based on timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK and a data enable signal DE, A data control signal DDC for controlling the operation timing of the gate driving circuit 13 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13. [

The data driving circuit 12 is for driving the data line unit 14. [ To this end, the data driving circuit 12 converts the digital video data RGB input from the timing controller 11 based on the data control signal DDC into an analog data voltage and supplies it to the data lines 14.

The gate drive circuit 13 is for driving the gate line portion 15. To this end, the gate drive circuit 13 generates a scan signal, a light emission control signal, and an initialization signal based on the gate control signal GDC. The gate drive circuit 13 supplies the scan signal to the scan line 15a in a line sequential manner, supplies the emission control signal to the emission line 15b in a line sequential manner, (15c).

Fig. 3 shows one example of the pixel P shown in Fig. 2, and shows one of the pixels P in the nth horizontal line. At this time, the nth horizontal line belongs to the range within the m horizontal line in the third horizontal line.

3, a pixel P according to an exemplary embodiment of the present invention includes an organic light emitting diode (OLED), a driving transistor DT, first to third transistors ST1 to ST3, first and second capacitors (C1, C2).

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). The anode electrode of the organic light emitting diode (OLED) is connected to the source electrode of the driving transistor DT, and the cathode electrode is connected to the ground terminal (VSS).

The driving transistor DT controls a driving current applied to the organic light emitting diode OLED by a voltage between its gate and source. To this end, the gate electrode of the driving transistor DT is connected to the input terminal of the data voltage Vdata, the drain electrode thereof is connected to the input terminal of the driving voltage VDD, and the source electrode thereof is connected to the low voltage driving voltage VSS.

The first transistor ST1 controls the current path between the driving voltage VDD input terminal and the driving transistor DT in response to the emission control signal EM. To this end, the gate electrode of the first transistor ST1 is connected to the emission control signal line 15c, the drain electrode thereof is connected to the driving voltage VDD input terminal, and the source electrode thereof is connected to the driving transistor DT.

The second transistor T2 provides the initialization voltage Vini provided from the initialization line 14a to the second node n2 in response to the (n-1) th scan signal Scan [n-1] . To this end, the gate electrode of the second transistor T2 is connected to the (n-1) th scan line 15a, the drain electrode of the second transistor T2 is connected to the initialization line 14a, and the source electrode thereof is connected to the second node n2.

The third transistor ST3 provides the reference voltage Vref and the data voltage Vdata provided from the data line 14c to the driving transistor DT in response to the n-th scan signal Scan [n]. To this end, the gate electrode of the third transistor T3 is connected to the scan line, the drain electrode thereof is connected to the data line 14c, and the source electrode thereof is connected to the driving transistor DT.

The storage capacitor Cs holds the data voltage Vdata supplied from the data line 14c for one frame so that the driving transistor DT maintains a constant voltage. To this end, the storage capacitor Cs is connected to the gate electrode and the source electrode of the driving transistor DT.

The auxiliary capacitor C1 is connected in series with the storage capacitor Cs at the second node n2 to increase the efficiency of the driving voltage Vdata.

The operation of the pixel P having the above-described structure will now be described. 3 is a waveform diagram showing signals (EM, SCAN, INIT, DATA) applied to the pixel P in FIG. 2 and the potential change of the gate electrode and the source electrode of the driving transistor DT accordingly.

In the figure, the horizontal period H is a scan period for driving pixels arranged in one horizontal line. That is, the n-th horizontal period ([n] H) is a scan period for driving the pixels of the n-th horizontal line, and the (n-1) N-2] horizontal period ([n-2] H) is a period for scanning pixels of the [n-2] horizontal line, which is the front end.

4A to 4E show equivalent circuits of the pixel P in the setup period Ti, the sampling period Ts, the lighting period Tw, and the light emission period Te, respectively. At this time, FIGS. 4A to 4E show that the devices are activated and the devices are inactivated by a dotted line.

4, the operation of the pixel P according to the present invention includes an initialization period Ti for initializing nodes A, B and C to a specific voltage, a first period T1 for detecting and storing a threshold voltage of the driving transistor DT, And a second sampling period Ts1 and Ts2 and a writing period Tw for applying a data voltage Vdata and a driving voltage applied to the organic light emitting diode OLED using a threshold voltage and a data voltage Vdata, And a light emission period Te for emitting light by compensating irrespective of the light emission period.

3 and 4A, the initialization period T1 for the nth horizontal line is performed in the [n-2] horizontal period ([n-2] H).

During the initialization period Ti, the second transistor T2 responds to the (n-1) th scan signal Scan [n-1] by supplying the initialization voltage Vini provided from the initialization line 14a to the second node n2. Therefore, the source voltage Vs of the driving transistor DT, which is the voltage of the second node n2, has the potential of the initializing voltage Vini. The third transistor T3 applies a reference voltage Vref supplied from the data line 14c to the first node n1 of the gate electrode of the driving transistor DT in response to the nth scan signal Scan [n] . Therefore, the gate voltage Vg of the driving transistor DT, which is the voltage of the first node n1, has the potential of the reference voltage Vref.

The initialization voltage Vini supplied to the second node n2 in the initialization period Ti is used to initialize the pixel P to a predetermined level. Is set to a voltage value smaller than the operating voltage of the organic light emitting diode (OLED) so as not to emit light. For example, the initialization voltage Vini can be set to a voltage having a magnitude of -1 to +1 (V).

Since the (n-2) th horizontal period ([n-2] H) includes a writing period for driving the pixels of the (n-2) th horizontal line, For example, in a range of 40 to 60% of the time, for example, a half (H) time.

Subsequently, in the first transient period T1, the voltage of the first node n1 is maintained at the reference voltage Vref, and the voltage of the second node n2 is maintained at the initializing voltage Vini.

3 and 4B, the first sampling period Ts1 for the nth horizontal line is performed in the (n-1) horizontal period ([n-1] H).

At this time, the third transistor T3 supplies the reference voltage Vref received from the data line 14c to the first node n1 in response to the n-th scan signal Scan [n]. The first transistor T1 supplies a driving voltage VDD to the driving transistor DT in response to the emission control signal EM. At this time, the driving transistor gate electrode voltage Vg maintains the reference voltage Vref. And the second node n2 is in a floating state, the voltage of the second node n2 is set such that the current flowing through the first transistor T1 and the driving transistor DT at the driving voltage VDD is accumulated And increases from the initialization voltage to the first sampling voltage Vsam1.

Since the [n-1] horizontal period is a period including the application of the data voltage in the previous scan period, the first sampling period Ts1 is 40 to 60% of 1 horizontal period (1H) 2 (H) time range. As described above, the voltage gradually rises from the initializing voltage Vini to the second node n2 during the first sampling period of 1/2 (H).

In the second transient period T2, the first to third transistors T1, T2 and T3 are turned off. The reference voltage Vref is maintained at the first node n1 and the reference voltage Vref is maintained at the second node n2 The accumulated voltage during the first sampling period Ts1 is maintained.

Referring to Figs. 3 and 4C, the second sampling period Ts2 for the nth horizontal line is performed in the present short horizontal period ([n] H).

In the second sampling period Ts2, the third transistor T3 responds to the n-th scan signal Scan [n] and supplies the reference voltage Vref supplied from the data line 14c to the first node n1 Supply. The first transistor T1 supplies a driving voltage VDD to the driving transistor DT in response to the emission control signal EM.

At this time, the driving transistor gate electrode voltage Vg maintains the reference potential Vref. Since the second node n2 is in a floating state, the voltage of the second node n2 is set such that the current flowing through the first transistor T1 and the driving transistor DT at the driving voltage VDD is accumulated So that the voltage rises again from the voltage increased in the first sampling period. At this time, the voltage increased through the second sampling period Ts2 is saturated with a voltage having a magnitude corresponding to the difference between the reference voltage Vref and the threshold voltage Vth of the driving transistor DT. That is, the potential difference between the gate and source of the driving transistor DT becomes the magnitude of the threshold voltage Vth through the first and second sampling periods Ts1 and Ts2.

That is, the potentials accumulated in the source electrode of the driving transistor DT through the second sampling period Ts2 are respectively applied to the scanning period of two horizontal periods (H), that is, the scanning periods of the previous stage horizontal period and the current stage horizontal period And are accumulated through the first and second sampling periods (Ts1, Ts2). As described above, according to the present invention, since the threshold voltage can be detected with a sufficient time margin, the image quality degradation due to the deviation of the threshold voltage can be effectively improved.

Referring to FIGS. 3 and 4D, the lighting period Tw for the current short horizontal line is made at the present short horizontal period ([n] H).

In the lighting period Tw, the first and second transistors T1 and T2 are turned off. The third transistor T3 is turned on and supplies the data voltage Vdata supplied from the data line 14c to the first node n1. At this time, the voltage of the second node n2 in a floating state is coupled or coupled by the ratio of the storage capacitor Cs and the auxiliary capacitor Cl.

3 and 4E, the light emission period Te for the nth horizontal line is performed at the nth horizontal period ([n] H).

In the light emission period Te, the second and third transistors T2 and T3 are turned off and the first transistor T1 is turned on. The data voltage Vdata stored in the storage capacitor Cs is supplied to the organic light emitting diode OLED so that the organic light emitting diode OLED emits light with a brightness proportional to the data voltage Vdata. At this time, a current flows to the driving transistor DT by the voltages of the first node n1 and the second node 2 determined in the lighting period Tw and a desired current is supplied to the organic light emitting diode OLED, Therefore, the organic light emitting diode OLED can adjust the brightness by the data voltage Vdata.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
14: data line section 15: gate line section

Claims (4)

And a driving transistor, which receives a reference voltage and a driving voltage from a data line through a gate electrode, receives a driving voltage through a drain electrode, and a source electrode connected to the organic light emitting diode,
A reference voltage is applied to a first node between the gate electrode and the data line in an (n-2) horizontal period for scanning the (n-2) th horizontal line and a reference voltage is applied between the source electrode and the organic light emitting diode An initialization step of initializing a potential between a gate and a source of the driving transistor by applying an initialization voltage to a second node of the driving transistor;
A first sampling step of raising the potential of the source electrode of the driving transistor by providing the driving voltage to the second node while floating the second node within the (n-1) horizontal period;
The voltage of the source electrode that has risen primarily in the first sampling step may be set to a voltage corresponding to a difference between the reference voltage and the threshold voltage of the driving transistor by performing the same process as the first sampling step in the n- A second sampling step of saturating with the second sampling step; And
And emitting the organic light emitting diode to the nth horizontal line while compensating the data voltage in the nth horizontal period according to the emission control signal irrespective of the threshold voltage of the driving transistor. Driving method.
The method according to claim 1,
The organic light emitting diode display includes a second transistor for switching a current path between an initialization line for providing the initialization voltage and the second node; And a third transistor for switching a current path between the data line and the first node,
In the initialization step,
Providing the reference voltage provided from the data line to the first node in response to the n-th scan signal; And
And supplying the initialization voltage supplied from the initialization line to the second node in response to the (n-1) th scan signal.
3. The method of claim 2,
Wherein the first and second sampling steps comprise:
Providing the reference voltage to the first node, wherein the third transistor is provided from the data line in response to the nth scan signal; And
And the second transistor applies the driving voltage to a source electrode of the driving transistor in response to a light emission control signal.
4. The method according to any one of claims 1 to 3,
Wherein the initialization step and the first and second sampling steps are performed during a 1/2 horizontal period.

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