KR20110032937A - Organic light emitting diode display and driving method thereof - Google Patents

Abstract

PURPOSE: An organic light emitting diode display and a driving method thereof are provided to prevent the deterioration of image quality by compensating the deterioration deviation of an organic light-emitting diode between pixels. CONSTITUTION: In an organic light emitting diode display and a driving method thereof, a display panel comprises a plurality of pixels. The pixels have an organic light-emitting diode. A data driving circuit comprises a plurality of sensing and output unit(124) and an ADC(122) The sensing and output units are connected to data lines one-to-one. The ADC converts a sensing result into a sampling and a digital signal. The ADC generates sensing information. . A data processing circuit determines the deterioration compensation values of the organic light-emitting diode. The data processing circuit generates digital correction data.

Description

Organic Light Emitting Diode Display And Driving Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display, and more particularly, to an organic light emitting diode display and a driving method thereof which can reduce image sticking due to deterioration of an organic light emitting diode.

Recently, various flat panel displays (FPDs) that can reduce weight and volume, which are disadvantages of cathode ray tubes, have been developed. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs") and electric fields. Light emitting devices; and the like.

PDP is attracting attention as a display device that is light and small and is most advantageous for large screen because of its simple structure and manufacturing process. TFT LCDs with thin film transistors (hereinafter referred to as "TFTs") as switching devices are the most widely used flat panel display devices, but they have a narrow viewing angle and low response speed because they are non-light emitting devices. In contrast, electroluminescent devices are classified into inorganic light emitting diode display devices and organic light emitting diode display devices depending on the material of the light emitting layer. In particular, organic light emitting diode display devices use self-light emitting devices that emit light, and thus, the response speed is high and the light emitting efficiency, There is a great advantage in brightness and viewing angle.

The organic light emitting diode display device has an organic light emitting diode as shown in FIG. 1. The organic light emitting diode includes an organic compound layer (HIL, HTL, EML, ETL, EIL) formed between the anode electrode and the cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emission layer EML to form excitons, and as a result, the emission layer EML becomes Visible light is generated.

The organic light emitting diode display device arranges the pixels including the organic light emitting diode in a matrix form and controls the brightness of the pixels selected by the scan pulse according to the gray level of the video data.

2 shows equivalently one pixel in an organic light emitting diode display. Referring to FIG. 2, a pixel of an organic light emitting diode display of an active matrix type includes an organic light emitting diode OLED, a data line DL and a gate line GL, a switch TFT SW, and a driving TFT DR that cross each other. ), And a storage capacitor Cst. The switch TFT (SW) and the driving TFT (DR) are implemented with a P-type MOS-FET.

The switch TFT SW is turned on in response to a scan pulse from the gate line GL to conduct a current path between its source electrode and drain electrode. The switch TFT SW applies the data voltage from the data line DL to the gate electrode and the storage capacitor Cst of the driving TFT DR during the turn-on period. The driving TFT DR controls the current flowing through the organic light emitting diode OLED according to the difference voltage Vgs between its gate electrode and the source electrode. The storage capacitor Cst keeps the gate potential of the driving TFT DR constant for one frame. The organic light emitting diode OLED is implemented in the structure as shown in FIG. 1 and is connected between the drain electrode of the driving TFT DR and the ground voltage source GND.

In general, non-uniformity of luminance between pixels in an organic light emitting diode display device is due to various causes, for example, variations in electrical characteristics of driving TFTs, variations in high potential driving voltages according to positions, and degradation variations in organic light emitting diodes. In particular, the deterioration deviation of the organic light emitting diode is caused because the deterioration speed is different for each pixel during a long driving time, and when this is intensified, image sticking occurs, resulting in deterioration of image quality.

Accordingly, an object of the present invention is to provide an organic light emitting diode display device and a method of driving the same, which compensate for deterioration deviation of organic light emitting diodes between pixels to prevent image degradation.

Another object of the present invention is to provide an organic light emitting diode display and a method of driving the same, which compensate for variations in electrical characteristics of driving TFTs between pixels and variations in high potential driving voltages according to positions, thereby preventing image quality degradation. have.

In order to achieve the above object, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a plurality of pixels disposed in a matrix form at intersections of a plurality of gate lines and a plurality of data lines and each having a plurality of pixels having an organic light emitting diode. A display panel; A data driving circuit including a plurality of sensing & output units connected one-to-one to the data lines, and an ADC for sampling and analog-to-digital converting the sensing results from the sensing & output units to generate sensing information; And a data processing circuit configured to determine compensation values for compensating degradation of the organic light emitting diode based on the sensing information, and add the compensation values to input digital video data to generate digital correction data.

The organic light emitting diode display device further includes a plurality of DACs for converting the digital correction data into a data voltage and supplying the digital correction data to the sensing and output units.

Each of the sensing and output units may include: an OP-AMP having a first input terminal, a second input terminal, and an output terminal connected to the ADC; A feedback capacitor connected between the second input terminal and the output terminal; A first switch connected between the first input terminal and the DAC; A second switch connected between the first input terminal and an initialization voltage supply source; A third switch connected in parallel with the feedback capacitor between the second input terminal and the output terminal; A fourth switch connected between the second input terminal and a reference current source; And a fifth switch connected between the second input terminal and the pixel.

Each of the sensing and output units functions as a current integrator through a first compensation driving to sense a degree of degradation of the organic light emitting diodes of the pixels.

The first compensation drive proceeds in a first period, a second period following the first period, and a third period following the second period; During the first period, the second, third, and fifth switches are turned on to reset the feedback capacitor, and apply an initialization voltage from the initialization voltage source to the organic light emitting diode to supply the organic light emitting diode. Flowing current; During the second period, the third switch is turned off and the second and fifth switches are continuously turned on to charge the feedback capacitor with current flowing through the organic light emitting diode; During the third period, the third and fifth switches are turned off and the second switches are continuously turned on, so that the voltage at the output terminal is sensed.

The ADC samples the voltage level of the output stage at a certain point in time, or samples the time taken for the voltage of the output stage to reach a predetermined target voltage.

Each of the sensing & output units functions as a current integrator through a second compensation drive to sense their feedback capacitor size; In the second compensation driving, the second and fourth switches are turned on for a predetermined time.

Each of the sensing & output units functions as a current integrator through a third compensation drive to sense a parasitic resistance value between itself and the organic light emitting diode; In the third compensation driving, the second and fifth switches are turned on for a predetermined time, and the initialization voltage supply source generates the initialization voltages of different levels twice.

Each of the sensing & output units functions as an output buffer through normal driving to supply a data voltage from the DAC to the data lines; In the normal driving, the first, third and fifth switches are turned on.

Each of the pixels may include an organic light emitting diode; A driving TFT connected between the high potential driving voltage source generating the high potential driving voltage and the organic light emitting diode, and controlling the amount of current flowing through the organic light emitting diode according to the voltage applied between the high potential driving voltage source and the first node; A first switch TFT connected between the high potential drive voltage source and the first node; A second switch TFT connected between the data line and a second node; A third switch TFT connected between the reference voltage source generating a reference voltage and the second node; A fourth switch TFT connected between the driving TFT and the organic light emitting diode; A fifth switch TFT connected between the data line and the organic light emitting diode; And a storage capacitor connected between the first node and the second node.

The normal driving proceeds in a first period and a second period following the first period; During the first period, the first and second switch TFTs are turned on and the third to fifth switch TFTs are turned off, and the first node is subtracted from the high potential driving voltage by the threshold voltage of the driving TFT. An intermediate compensation value is applied and a data voltage is applied to the second node; During the second period, the first, second and fifth switch TFTs are turned off and the third and fourth switch TFTs are turned on, so that the potential of the second node changes from the data voltage to the reference voltage. The potential of the first node is determined as the final compensation value obtained by subtracting the potential change amount of the second node from the intermediate compensation value due to the potential change effect of the second node.

According to an exemplary embodiment of the present invention, a method of driving an organic light emitting diode display device including a plurality of pixels disposed in a matrix form at intersections of a plurality of gate lines and a plurality of data lines and each having an organic light emitting diode may include the data. Sensing a degree of degradation of the organic light emitting diode by using a plurality of sensing & output units connected one-to-one to lines; Sampling and analog-to-digital converting the sensing results from the sensing and output units to generate sensing information; And determining compensation values for compensating for degradation of the organic light emitting diode based on the sensing information, and adding the compensation values to input digital video data to generate digital correction data.

The organic light emitting diode display and the driving method thereof according to the present invention can improve image quality by compensating for deterioration deviation of the organic light emitting diode between pixels to prevent image fixation.

Furthermore, the organic light emitting diode display and the driving method thereof according to the present invention can greatly improve the image quality by compensating for variations in electrical characteristics of driving TFTs between pixels and variations in high potential driving voltages according to positions.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 17B.

FIG. 3 is a block diagram illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIG. 4 illustrates a detailed configuration of a timing controller, a data driving circuit, and a memory of FIG. 3.

3 and 4, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 10 in which pixels P are arranged in a matrix, and data for driving the data lines 14. A timing controller 11 for controlling driving timing of the driving circuit 12, the gate driving circuit 13 for driving the gate line portions 15, and the data driving circuit 12 and the gate driving circuit 13; And a memory 15.

In the display panel 10, a plurality of data lines 14 and a plurality of gate line units 15 intersect each other, and pixels P are arranged in a matrix form at each of the crossing regions. The gate line unit 15 includes a scan line 15a, a sensing line 15b, and an emission line 15c. Each pixel P is connected to one data line 14 and three signal lines constituting the gate line part 15. The pixels P are commonly supplied with a high potential driving voltage Vdd and a reference voltage Vref. The high potential drive voltage Vdd is generated at a constant level by the high potential drive voltage source, and the reference voltage Vref is generated at a constant level by the reference voltage source. The reference voltage Vref may be determined as a voltage level between the base voltage and the high potential driving voltage Vdd, and may generally be set at the same level as the lowest data voltage. Each of the pixels P includes an organic light emitting diode, a driving TFT, and a plurality of switch TFTs. The configuration of the pixel P will be described later in detail with reference to FIG. 6.

The timing controller 11 includes a control signal generation circuit 111 and a data processing circuit 112.

The control signal generation circuit 111 includes timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE input from a system board (not shown). Based on the data control signal DDC and the switch control signals φ1 to φ5 for controlling the operation timing of the data driving circuit 12, and the gate control signal for controlling the operation timing of the gate driving circuit 13. (GDC) occurs.

The data processing circuit 112 stores, in the memory 15, compensation values CD determined based on the sensing information together with the sensing information input from the data driving circuit 12. The digital correction data R'G'B 'is generated by adding the compensation values CD to the digital video data RGB input from the system board with reference to the memory 15. R'G'B ') is supplied to the data driving circuit 12. Here, the compensation value CD depends on the degree of degradation of the organic light emitting diodes of the pixels P, the size of the feedback capacitor constituting the current integrator of the data driving circuit 12, and the parasitic resistance value between the current integrator and the organic light emitting diode. It is determined differently.

The data processing circuit 112 includes first to third compensation units 112A to 112C, a compensation value determiner 112D, and a data modulator 112E. The memory 15 includes first to fourth lookup tables LUT1 to LUT4. The first compensator 112A extracts the size of the feedback capacitors based on the first sensing information SD1 from the data driving circuit 12 and stores the result in the first lookup table LUT1. 7 and 8) The second compensator 112B extracts the parasitic resistance values by applying the second sensing information SD2 from the data driving circuit 12 to the built-in algorithm (Equation 1 to be described later). The result is stored in the second lookup table LUT2 (refer to FIGS. 9 and 10). The third compensator 112C may use the organic light emitting diode based on the third sensing information SD3 from the data driving circuit 12. After the current-voltage characteristic values are extracted, the result is stored in the third lookup table LUT3 (see FIGS. 11 and 12C). The compensation value determiner 112D performs the first to third lookup tables LUT3. After determining compensation values (CDs) for compensating deterioration of organic light emitting diodes by location based on the values stored in Stored in the fourth lookup table LUT4. The data modulator 112E adds the compensation values CD for each position stored in the fourth lookup table LUT4 to the input digital video data RGB of each corresponding position, thereby providing digital correction data R'G'B '. Is generated, and the digital correction data R'G'B 'is supplied to the data driving circuit 12. The luminance non-uniformity between the pixels P due to the deterioration deviation of the organic light emitting diode may be eliminated by the digital correction data R'G'B '.

The data driving circuit 12 generates the first to third sensing information SD1 to SD3 under the control of the timing controller 11 and supplies it to the timing controller 11. The digital correction data R'G'B 'input under the control of the timing controller 11 is converted into an analog data voltage (hereinafter, referred to as a data voltage) and supplied to the data lines 14. To this end, the data driving circuit 12 includes a shift register 121, an analog-to-digital converter (hereinafter referred to as "ADC") 122, a plurality of digital-to-analog converters (hereinafter referred to as "DAC") ( 123, and a plurality of sensing & output units 124.

The sensing & output units 124 are connected one-to-one to the data lines 14, respectively, and are operated in response to the switch control signals phi 1 to phi 5 from the timing controller 11, so as to operate as current integrators during compensation driving. It functions as an output buffer during normal driving. Here, the compensation driving means driving for determining the compensation values CD, and the normal driving means driving for displaying the digital correction data R'G'B 'on the display panel 10. The detailed configuration of the sensing & output unit 124 will be described later in detail with reference to FIG. 5.

The ADC 122 is commonly connected to the sensing & output units 124 to sample sensing voltages, and converts the sampled sensing voltages into first to third sensing information SD1 to SD3, which are digital signals, and then timings. Supply to the controller 11. The ADC 122 may be implemented with a known Pipe-Line type, SAR type, Single-Slope type, and the like.

The shift register 121 sequentially shifts the sampling signal for the digital correction data R'G'B 'in response to the data control signal DDC from the timing controller 11.

The DACs 123 are connected one-to-one to the sensing & output units 124, respectively, and convert the digital correction data R'G'B 'input from the timing controller 11 into data voltages in accordance with the sampling signal. . The data voltage is supplied to the data lines 14 via the sensing & output units 124.

The gate driving circuit 13 generates a scan signal SCAN, a sensing signal SEN, and an emission signal EM under the control of the timing controller 11. The scan signal SCAN is supplied to the scan line 15a and the sensing signal SEN is supplied to the sensing line 15b. The emission signal EM is supplied to the emission line 15c. The shift register array constituting the gate driving circuit 13 may be directly formed on the display panel 10 by a gate in panel (GIP) method.

5 illustrates the sensing & output unit 124 of FIG. 4 in detail.

Referring to FIG. 5, the sensing & output unit 124 includes an op amp (hereinafter referred to as “OP-AMP”), an initialization voltage supply source VCM, a feedback capacitor Cfb, and a plurality of switches SW1 to SW. SW5). The switches SW1 to SW5 may be implemented with N-type MOSFETs.

The OP-AMP has a first input terminal (+), a second input terminal (−), and an output terminal. The feedback capacitor Cfb is connected between the second input terminal (−) and the output terminal of the OP-AMP. The first switch SW1 is connected between the first input terminal (+) of the OP-AMP and the DAC 123 and is switched in response to the first switch control signal φ1. The second switch SW2 is connected between the first input terminal (+) of the OP-AMP and the initialization voltage supply source VCM, and is switched in response to the second switch control signal φ2. The third switch SW3 is connected between the second input terminal (−) and the output terminal of the OP-AMP and is switched in response to the third switch control signal φ3. The fourth switch SW4 is connected between the second input terminal (−) of the OP-AMP and the reference current source IREF, and is switched in response to the fourth switch control signal φ4. The fifth switch SW5 is connected between the second input terminal (−) of the OP-AMP and the pixel P, and is switched in response to the fifth switch control signal φ5. The reference current source IREF is commonly connected to all the sensing & output units 124. The initialization voltage source VCM generates an initialization voltage Vcm, and the reference current source IREF generates a reference current Iref that sinks toward the base voltage source GND.

FIG. 6 shows the pixel P shown in FIG. 3 in detail.

Referring to FIG. 6, the pixel P includes an organic light emitting diode OLED, a driving TFT DR, a plurality of switch TFTs ST1 to ST5, and a storage capacitor Cst. The driving TFT DR and the switch TFTs ST1 to ST5 may be implemented as P-type MOSFETs.

The organic light emitting diode OLED is connected between the third node N3 and the ground voltage source GND, and emits light by a current flowing between the high potential driving voltage source VDD and the ground voltage source GND.

The driving TFT DR is connected between the high potential driving voltage source VDD generating the high potential driving voltage Vdd and the organic light emitting diode OLED, and has a source-gate voltage, that is, a high potential driving voltage source VDD. ) And the amount of current flowing through the organic light emitting diode OLED according to the voltage applied between the first node N1 and the first node N1.

The first switch TFT ST1 is connected between the high potential drive voltage source VDD and the first node N1 and is switched in response to the scan signal SCAN from the scan line 15a. The second switch TFT ST2 is connected between the data line 14 and the second node N2 and is switched in response to the scan signal SCAN from the scan line 15a. The third switch TFT ST3 is connected between the reference voltage source VREF generating the reference voltage Vref and the second node N2 and in response to the emission signal EM from the emission line 15b. Switching. The fourth switch TFT ST4 is connected between the driving TFT DR and the third node N3, and is switched in response to the emission signal EM from the emission line 15b. The fifth switch TFT ST5 is connected between the data line 14 and the third node N3 and switched in response to the sensing signal SEN from the sensing line 15c.

The storage capacitor Cst is connected between the first node N1 and the second node N2.

The organic light emitting diode display device is largely operated by compensation driving and normal driving. The compensation drive is a drive for determining compensation values (CDs), the first compensation drive for deriving the first sensing information (SD1) to find the deviation of the feedback capacitor (Cfb), and the first compensation drive to determine the parasitic resistance values The second compensation driving to derive the second sensing information SD2 is divided into a third compensation driving to derive the third sensing information SD2 to find current-voltage characteristic values of the organic light emitting diodes. The normal driving means driving for displaying the digital correction data R'G'B 'reflecting the compensation values CD on the display panel 10. The first and second compensation driving are performed once in the initial setting of the display device, and the third compensation driving is performed a plurality of times in accordance with deterioration of the organic light emitting diodes by the normal driving after the initial setting of the display device.

Hereinafter, the circuit operation in compensation driving and the circuit operation in normal driving will be described sequentially.

FIG. 7 is a waveform diagram illustrating application of control signals for the first compensation driving, and FIG. 8 illustrates an operation state of the display device during the first compensation driving.

7 and 8, in the first compensation driving, the scan signal SCAN, the emission signal EM, and the sensing signal SEN are maintained at the high logic level H so that all the switch TFTs of the pixel P are held. Turn them off (ST1 to ST5). In addition, the first, third, and fifth switch control signals φ1, φ3, and φ5 are maintained at the low logic level L so that the first, third, and fifth switches SW1 in the data driving circuit 12 are maintained. Turn off (SW3, SW5). On the other hand, the second and fourth switch control signals φ2 and φ4 are maintained at the high logic level H and then inverted to the low logic level L in synchronization with the sensing timing.

As a result, the sensing & output units 124 function as current integrators, and the current integrators are commonly connected to the reference current source IREF through the fourth switch SW4, respectively. Due to the sink current Iref generated from the reference current source IREF, the sensing voltages Vout1 applied to the output terminals of the current integrators gradually increase. The sensing voltages Vout1 are sampled at the logic level inversion of the second and fourth switch control signals φ2 and φ4. The level of the sensing voltage Vout1 depends on the size of the feedback capacitor Cfb constituting the current integrator. In order to compensate the organic light emitting diode degradation of all the pixels P with the same condition, the size of the feedback capacitors Cfb should be uniform, but it is very difficult to realize the same size of the feedback capacitors Cfb due to the process variation. . As a result, even if the same sink current Iref is applied to each current integrator by the reference current source IREF, the levels of the sensing voltages Vout1 may vary. For example, the sensing voltage Vout1 from the current integrator with a relatively large feedback capacitor Cfb is at a lower level than the sensing voltage Vout1 from the current integrator with a relatively small feedback capacitor Cfb. Will have Therefore, in order to accurately compensate for deterioration of the organic light emitting diodes, the size of the feedback capacitors Cfb should be reflected in the compensation value CD. To this end, the sampled sensing voltages Vout1 are converted into the first sensing information SD1 through the ADC 122 and then stored in the first lookup table LUT1 via the first compensation unit 112A. (CD) is used for the determination.

Since the first compensation driving is performed once in the initial setting process of the display device, the information stored in the first lookup table LUT1 is fixed.

FIG. 9 is a waveform diagram illustrating application of control signals for the second compensation driving, and FIG. 10 illustrates an operation state of the display device during the second compensation driving.

9 and 10, in the second compensation driving, the scan signal SCAN and the emission signal EM are maintained at the high logic level H, so that the first to fourth switch TFTs of the pixel P ( Turn off ST1 to ST4). The first, third, and fourth switch control signals φ1, φ3, and φ4 are maintained at the low logic level L so that the first, third, and fourth switches SW1, SW3 in the data driving circuit 12 are maintained. Turn SW4) off.

On the other hand, during the second compensation driving, the sensing signal SEN is maintained at the low logic level L to turn on the fifth switch TFT ST5 of the pixel P. After the second and fifth switch control signals φ2 and φ5 are maintained at the high logic level H, they are inverted to the low logic level L in synchronization with the sensing timing.

As a result, the sensing & output unit 124 functions as a current integrator, and the current integrator is electrically connected to the organic light emitting diode OLED through the fifth switch SW5. The current Ioled flows through the organic light emitting diode OLED by the initialization voltage Vcm applied to the input terminal (+) of the current integrator. Due to the current Ioled flowing in the organic light emitting diode OLED, the sensing voltage Vout2 applied to the output terminal of the current integrator gradually increases. The sensing voltage Vout2 is sampled at the logic level inversion of the second and fifth switch control signals φ2 and φ5.

However, when a current Ioled flows through the organic light emitting diode OLED, IR drops due to the parasitic resistance value Rload present in the data line 14 and the parasitic resistance value Rsw of the fifth switch TFT ST5. This causes the voltage applied to the organic light emitting diode OLED to be lower than the initialization voltage Vcm. Since the parasitic resistance value Rload increases in proportion to the length of the data line 14, the parasitic resistance value Rload is applied to the organic light emitting diode OLED according to the position of the pixel P even when the same initialization voltage Vcm is applied using a current integrator. The voltages will be different from each other. Therefore, in order to accurately compensate for deterioration of the organic light emitting diodes, parasitic resistance values Rload and Rsw should be extracted and reflected in the compensation value CD. To this end, the initialization voltage Vcm is applied twice to the first level Vcm1 and the second level Vcm2 higher than the first level Vcm1. The sensing voltage Vout2 of the first level sampled by the initialization voltage of the first level Vcm1 and the sensing voltage Vout2 of the second level sampled by the initialization voltage of the second level Vcm2 are the ADC 122. ) Is converted into second sensing information SD2 and applied to the second compensation unit 112B. The second compensator 112B applies the second sensing information SD2 to an algorithm represented by Equation 2 below to extract the entire parasitic resistance value Rload + Rsw.

In Equation 1, "Ioled1" represents a current flowing through the organic light emitting diode when applying the initialization voltage of the first level (Vcm1), "Ioled2" represents a current flowing through the organic light emitting diode when applying the initialization voltage of the second level (Vcm2). , "Is" is the saturation current of the organic light emitting diode, "Va1" is the voltage actually applied to the organic light emitting diode when applying the initialization voltage of the first level (Vcm1), "Va2" is the initialization of the second level (Vcm2) The voltage actually applied to the organic light emitting diode when voltage is applied, “V _T ” represents a thermal voltage constant of the organic light emitting diode, and “n” represents an emission coefficient of the organic light emitting diode, respectively.

"Ioled1" and "Ioled2" in Equation 1 can be easily understood through Equation 2 below.

In Equation 2, "Cf" represents the capacitance of the feedback capacitor Cfb, and "Vcf" represents the voltage across the feedback capacitor Cfb, respectively.

The extracted parasitic resistance value Rload + Rsw is stored in the second lookup table LUT2 by the second compensation unit 112A and then used to determine the compensation value CD. The parasitic resistance value Rload + Rsw extraction process is performed for all the pixels P. FIG.

Since the second compensation driving is performed once in the initial setting process of the display device, the information stored in the second lookup table LUT2 is fixed.

FIG. 11 is a waveform diagram illustrating application of control signals for the third compensation driving, and FIGS. 12A to 12C sequentially show an operating state of the display device during the second compensation driving. The third compensation driving is sequentially performed in the first period CT1 for applying the initialization voltage, the second period CT2 for charging the feedback capacitor, and the third period CT3 for generating the sensing voltage. Such third compensation driving may be performed for all the pixels P for at least one frame synchronized with the on timing of the driving power supply or at least one frame synchronized with the off timing of the driving power supply. In addition, the third compensation driving may be performed on the pixels P by one horizontal line for each blank period between adjacent frames in the process of normal driving.

11 and 12A, during the first period CT1, the scan signal SCAN and the emission signal EM are generated at the high logic level H to generate the first to fourth switch TFTs of the pixel P. Referring to FIGS. Turn them off (ST1 to ST4). The sensing signal SEN is generated at the low logic level L during the first period CT1 to turn on the fifth switch TFT ST5 of the pixel P. During the first period CT1, the first and fourth switch control signals φ1 and φ4 are generated at the low logic level L to switch the first and fourth switches SW1 and SW4 in the data driving circuit 12. The second, third and fifth switch control signals φ2, φ3, and φ5 are generated at the high logic level H so that the second, third and fifth switches SW2 in the data driving circuit 12 are turned off. Turn on (SW3, SW5).

Accordingly, the first input terminal (+) of the OP-AMP constituting the sensing & output unit 124 is connected to the initialization voltage source VCM, and the second input terminal (-) and the output terminal of the OP-AMP are shorted to each other. The second input terminal (-) of the OP-AMP is connected to the organic light emitting diode OLED of the pixel P. The short circuit resets the feedback capacitor Cfb. Due to the virtual ground characteristic of the OP-AMP, the potential of the second input terminal (−) of the OP-AMP is maintained at the initialization voltage Vcm. The output terminal potential of the OP-AMP is also maintained at the initialization voltage (Vcm). The initialization voltage Vcm is applied to the anode electrode of the organic light emitting diode OLED while charging the data line 14 at a high speed. As a result, a current flows through the organic light emitting diode OLED. The magnitude of the current flowing through the organic light emitting diode OLED depends on the degree of deterioration of the organic light emitting diode OLED. For example, even when the same level of initialization voltage Vcm is applied to the two organic light emitting diodes OLED as shown in FIG. 13, the current Ib flowing to the organic light emitting diode OLED_B having a relatively high degree of deterioration is relatively high. The deterioration degree is lower than the current Ia flowing in the organic light emitting diode OLED_A.

11 and 12B, during the second period CT2, the scan signal SCAN and the emission signal EM are maintained at the high logic level H so that the first to fourth switch TFTs of the pixel P are held. The fields ST1 to ST4 continue to be turned off. During the second period CT2, the sensing signal SEN is maintained at the low logic level L to continuously turn on the fifth switch TFT ST5 of the pixel P. During the second period CT2, the first and fourth switch control signals φ1 and φ4 are maintained at the low logic level L to operate the first and fourth switches SW1 and SW4 in the data driving circuit 12. Subsequently, the third switch control signal φ3 is inverted to the low logic level L to turn off the third switch SW3 in the data driving circuit 12, and the second and fifth switch control signals are turned off. φ2 and φ5 are maintained at the high logic level H to continuously turn on the second and fifth switches SW2 and SW5 in the data driving circuit 12.

Accordingly, the first input terminal (+) of the OP-AMP constituting the sensing & output unit 124 is continuously connected to the initialization voltage source VCM, and the short between the second input terminal (-) and the output terminal of the OP-AMP is short. Is released, and the second input terminal (−) of the OP-AMP is continuously connected to the organic light emitting diode OLED of the pixel P. By the short release, the sensing & output unit 124 functions as an integrator. Since the current flowing through the organic light emitting diode OLED charges the feedback capacitor Cfb, the output terminal potential Vo of the OP-AMP increases linearly at the initialization voltage Vcm.

11 and 12C, during the third period CT3, the scan signal SCAN and the emission signal EM are maintained at the high logic level H so that the first to fourth switch TFTs of the pixel P are held. The fields ST1 to ST4 continue to be turned off. During the third period CT3, the sensing signal SEN is maintained at the low logic level L to continuously turn on the fifth switch TFT ST5 of the pixel P. During the third period CT3, the first and fourth switch control signals φ1 and φ4 are maintained at the low logic level L to switch the first and fourth switches SW1 and SW4 in the data driving circuit 12. The third switch control signal φ3 is kept at the low logic level L to continuously turn off the third switch SW3 in the data driving circuit 12, and the second switch control signal φ2 is maintained at the high logic level H to continuously turn on the second switch SW2 in the data driving circuit 12. The fifth switch control signal φ5 is inverted to the low logic level L to turn off the fifth switch SW5 in the data driving circuit 12.

Accordingly, the voltage stored at the output terminal of the OP-AMP until just before the fifth switch SW5 is turned off is sampled as the sensing voltage Vout3. When the sampling point is made constant, the level of the sensing voltages Vout3 to be sampled depends on the degree of deterioration of the organic light emitting diode OLED. For example, when sampling at a predetermined time Ts as shown in FIG. 14, the sensing voltage Vout3 level Vb when the degradation is large is smaller than the sensing voltage Vout3 level Va when the degradation is small. . This is a method of making the time constant and sampling the voltage obtained at that time, and may be implemented through the ADC 122 such as a pipe-line type or a SAR type. The magnitude of the sampled sensing voltage Vout3 is inversely proportional to the degree of degradation of the organic light emitting diode OLED.

Another way to predict the degree of degradation of an organic light emitting diode (OLED) is to use a constant voltage and the amount of time it takes to reach this voltage. Similar to the above method, this method uses a method in which the increase slope of the output terminal voltage of the OP-AMP varies according to the amount of current flowing through the organic light emitting diode (OLED). For example, as shown in FIG. 15, the target voltage Vc is predetermined, and the time taken for the level of the sensing voltage Vout3 to reach the target voltage Vc can be sampled. In FIG. 15, the sizes of the sampled times Ts1 and Ts2 are proportional to the degree of deterioration of the organic light emitting diode OLED. This method may be implemented through an ADC 122 such as a single-slope type.

The sampled sensing voltages Vout3 (or sampled times) are converted into the third sensing information SD3 through the ADC 122 and then passed to the third lookup table LUT3 through the third compensation unit 112C. It is then stored and used to determine the compensation value (CD).

Since this third compensation drive is repeatedly executed, the information stored in the third lookup table LUT3 is continuously updated.

FIG. 16 is a waveform diagram illustrating application of control signals for normal driving, and FIGS. 17A and 17B sequentially show an operating state of a display device during normal driving. The normal driving proceeds sequentially into the first period DT1 for compensating the driving TFT deviation and the high potential driving voltage deviation, and the second period DT2 for programming and light emission.

16 and 17A, during the first period DT1, the scan signal SCAN is generated at the low logic level L to turn on the first and second switch TFTs ST1 and ST2 of the pixel P. On, the emission signal EM is generated at the high logic level H to turn off the third and fourth switches TFTs ST3 and ST4 of the pixel P, and the sensing signal SEN is at the high logic level. Generated by (H) to turn off the fifth switch TFT ST5 of the pixel P. FIG. During the first period DT1, the first, third and fifth switch control signals φ1, φ3, and φ5 are generated at the high logic level H, so that the first, third and fifth in the data driving circuit 12 are generated. The fifth switch SW1, SW3, SW5 is turned on, and the second and fourth switch control signals φ2 and φ4 are generated at the low logic level L so that the second and fourth switches in the data driving circuit 12 are generated. Turn off (SW2, SW4).

As a result, the sensing & output unit 124 functions as an output buffer and buffers the data voltage Vdata input from the DAC 123 to supply the data line 14 to the data line 14. In the pixel P, the intermediate compensation value Vdd-Vth is applied to the first node N1 by the diode connection of the driving TFT DR (the gate electrode and the drain electrode of the driving TFT DR are shorted). The intermediate compensation value Vdd-Vth is determined by subtracting the high potential driving voltage Vdd from the threshold voltage Vth of the driving TFT DR. The data voltage Vdata is applied to the second node N2. The storage capacitor Cst maintains the potential of the first node N1 as the intermediate compensation value Vdd-Vth and the potential of the second node N2 as the data voltage Vdata.

16 and 17B, during the second period DT2, the scan signal SCAN is inverted to the high logic level H to turn on the first and second switches TFTs ST1 and ST2 of the pixel P. The emission signal EM is inverted to the low logic level L to turn on the third and fourth switches TFTs ST3 and ST4 of the pixel P, and the sensing signal SEN to the high logic level. It is held at (H) to continuously turn off the fifth switch TFT ST5 of the pixel P. During the second period DT2, the logic level states of the switch control signals φ1 to φ5 are kept the same as the first period DT1.

Accordingly, the reference voltage Vref is applied to the second node N2 of the pixel P, and the potential of the second node N2 is changed from the data voltage Vdata to the reference voltage Vref. Since the first node N1 is connected to the second node N2 with the storage capacitor Cst interposed therebetween, the potential change amount Vdata-Vref of the second node is not changed by the capacitor coupling phenomenon. It is reflected in the potential of N1). As a result, the potential of the first node N1 is the final compensation value {(Vdd-Vth)-(Vdata-Vref)} obtained by subtracting the potential change amount Vdata-Vref of the second node from the intermediate compensation value Vdd-Vth. Is determined.

At this time, the driving current Ioled flowing through the organic light emitting diode OLED is expressed by Equation 3 below.

In Equation 3, "k" denotes a constant determined for mobility, parasitic capacitance and channel size, and "Vsg" denotes a source-gate voltage of the driving TFT DR, respectively.

As can be easily seen through Equation 3, the driving current (Ioled) according to the present invention depends on the data voltage (Vdata) and the reference voltage (Vref) that can be controlled by the user, the threshold voltage of the driving TFT (DR) It is independent of the level of Vth and the high potential driving voltage Vdd applied to the driving TFT DR. Therefore, even if the threshold voltage Vth and the high potential driving voltage Vdd of the driving TFT DR vary from pixel to pixel P, the luminance non-uniformity between the pixels P can be varied by selecting the appropriate voltage Vdata-Vref. Can be solved.

As described above, the organic light emitting diode display and the driving method thereof according to the present invention can improve image quality by compensating for deterioration variation of the organic light emitting diode between pixels to prevent image fixation.

Furthermore, the organic light emitting diode display and the driving method thereof according to the present invention can greatly improve the image quality by compensating for variations in electrical characteristics of driving TFTs between pixels and variations in high potential driving voltages according to positions.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a view illustrating a light emission principle of a general organic light emitting diode display.

2 is an equivalent view of one pixel in an organic light emitting diode display having a conventional 2T1C structure.

3 illustrates an organic light emitting diode display device according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a detailed configuration of a timing controller, a data driving circuit, and a memory of FIG. 3.

5 is a view illustrating in detail the sensing & output unit of FIG.

FIG. 6 is a detailed view of the pixel illustrated in FIG. 3. FIG.

7 is a diagram illustrating an application waveform of control signals for first compensation driving;

8 is a view showing an operating state of the display device in the first compensation driving;

9 is a diagram illustrating an application waveform of control signals for a second compensation driving;

FIG. 10 is a view showing an operating state of a display device in a second compensation drive; FIG.

FIG. 11 is a diagram illustrating an application waveform of control signals for a third compensation driving; FIG.

12A through 12C are diagrams sequentially illustrating an operating state of a display device during a second compensation driving.

13 is a view showing a relationship between a current flowing through an organic light emitting diode and a degree of deterioration of the organic light emitting diode.

14 and 15 are diagrams for explaining a sampling method.

FIG. 16 is a diagram showing an application waveform of control signals for normal driving; FIG.

17A and 17B are diagrams sequentially showing an operating state of a display device during normal driving;

<Description of Symbols for Main Parts of Drawings>

10: display panel 11: timing controller

12: data driving circuit 13: gate driving circuit

14 data line 15 gate line

16 memory 111 control signal generating circuit

112: data processing circuit 121: shift register

122: analog-to-digital converter 123: digital-to-analog converter

124 Sensing & Output

Claims (14)

A display panel including a plurality of pixels disposed in a matrix form at intersections of a plurality of gate lines and a plurality of data lines, each pixel having an organic light emitting diode; A data driving circuit including a plurality of sensing & output units connected one-to-one to the data lines, and an ADC for sampling and analog-to-digital converting the sensing results from the sensing & output units to generate sensing information; And And a data processing circuit configured to determine compensation values for compensating degradation of the organic light emitting diode based on the sensing information, and add the compensation values to input digital video data to generate digital correction data. Light emitting diode display device. The method of claim 1, And the data driving circuit further comprises a plurality of DACs for converting the digital correction data into a data voltage and supplying the digital correction data to the sensing and output units. The method of claim 2, Each of the sensing & output unit, An OP-AMP having a first input, a second input, and an output connected to the ADC; A feedback capacitor connected between the second input terminal and the output terminal; A first switch connected between the first input terminal and the DAC; A second switch connected between the first input terminal and an initialization voltage supply source; A third switch connected in parallel with the feedback capacitor between the second input terminal and the output terminal; A fourth switch connected between the second input terminal and a reference current source; And And a fifth switch connected between the second input terminal and the pixel. The method of claim 3, wherein And each of the sensing and output units functions as a current integrator through a first compensation driving to sense a degree of degradation of the organic light emitting diodes of the pixels. The method of claim 4, wherein The first compensation drive proceeds in a first period, a second period following the first period, and a third period following the second period; During the first period, the second, third, and fifth switches are turned on to reset the feedback capacitor, and apply an initialization voltage from the initialization voltage source to the organic light emitting diode to supply the organic light emitting diode. Flowing current; During the second period, the third switch is turned off and the second and fifth switches are continuously turned on to charge the feedback capacitor with current flowing through the organic light emitting diode; And the third and fifth switches are turned off and the second switch is continuously turned on during the third period, such that the voltage at the output terminal is sensed. The method of claim 5, And the ADC samples the voltage level of the output terminal at a certain point of time, or samples the time taken for the voltage of the output terminal to reach a predetermined target voltage. The method of claim 3, wherein Each of the sensing & output units functions as a current integrator through a second compensation drive to sense their feedback capacitor size; And the second and fourth switches are turned on for a predetermined time during the second compensation driving. The method of claim 3, wherein Each of the sensing & output units functions as a current integrator through a third compensation drive to sense a parasitic resistance value between itself and the organic light emitting diode; In the third compensation driving, the second and fifth switches are turned on for a predetermined time, and the initialization voltage supply source generates an initialization voltage of different levels twice. The method of claim 3, wherein Each of the sensing & output units functions as an output buffer through normal driving to supply a data voltage from the DAC to the data lines; And the first, third, and fifth switches are turned on during the normal driving. The method of claim 9, Each of the pixels, Organic light emitting diodes; A driving TFT connected between the high potential driving voltage source generating the high potential driving voltage and the organic light emitting diode, and controlling the amount of current flowing through the organic light emitting diode according to the voltage applied between the high potential driving voltage source and the first node; A first switch TFT connected between the high potential drive voltage source and the first node; A second switch TFT connected between the data line and a second node; A third switch TFT connected between the reference voltage source generating a reference voltage and the second node; A fourth switch TFT connected between the driving TFT and the organic light emitting diode; A fifth switch TFT connected between the data line and the organic light emitting diode; And And a storage capacitor connected between the first node and the second node. 11. The method of claim 10, The normal driving proceeds in a first period and a second period following the first period; During the first period, the first and second switch TFTs are turned on and the third to fifth switch TFTs are turned off, and the first node is subtracted from the high potential driving voltage by the threshold voltage of the driving TFT. An intermediate compensation value is applied and a data voltage is applied to the second node; During the second period, the first, second and fifth switch TFTs are turned off and the third and fourth switch TFTs are turned on, so that the potential of the second node changes from the data voltage to the reference voltage. And the potential of the first node is determined as a final compensation value obtained by subtracting the potential change amount of the second node from the intermediate compensation value due to the influence of the potential change of the second node. A driving method of an organic light emitting diode display device including a plurality of pixels disposed in a matrix form at intersections of a plurality of gate lines and a plurality of data lines and each having an organic light emitting diode, Sensing a degree of degradation of the organic light emitting diode by using a plurality of sensing & output units connected one-to-one to the data lines; Sampling and analog-to-digital converting the sensing results from the sensing and output units to generate sensing information; And Determining compensation values for compensating degradation of the organic light emitting diode based on the sensing information, and adding the compensation values to input digital video data to generate digital correction data. Method of driving display device. 13. The method of claim 12, Sensing the deterioration degree, Applying an initialization voltage generated through the sensing and output unit to the organic light emitting diode to pass a current through the organic light emitting diode; Charging a feedback capacitor in the sensing and output unit with a current flowing through the organic light emitting diode; And And sensing a charging voltage of the feedback capacitor applied to an output terminal of the sensing & output unit. 13. The method of claim 12, And the sampling step samples the voltage level of the output terminal at a predetermined time point or samples the time taken for the voltage of the output terminal to reach a predetermined target voltage.

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