KR101450919B1 - Organic Light Emitting Diode Display And Driving Method Thereof - Google Patents

Abstract

The present invention relates to an organic light emitting diode (OLED) display device and a driving method thereof that can reduce image sticking due to deterioration of an organic light emitting diode.

The organic light emitting diode display device includes a display panel including a plurality of pixels each having an organic light emitting diode arranged in a matrix form at intersecting regions of a plurality of gate lines and a plurality of data lines; A data driving circuit including a plurality of sensing and output units connected to the data lines on a one-to-one basis, and an ADC for generating sensing information by sampling and analog-to-digital converting a sensing result from the sensing & And a data processing circuit for determining compensation values for compensating deterioration of the organic light emitting diode based on the sensing information and adding the compensation values to input digital video data to generate digital correction data, Each of the output units operates as a current integrator during compensation driving to determine the compensation values, while acting as an output buffer during normal driving to apply the digital correction data to the display panel.

Description

[0001] The present invention relates to an organic light emitting diode (OLED) display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display, and more particularly, to an organic light emitting diode (OLED) display device and a driving method thereof that can reduce image sticking due to deterioration of an organic light emitting diode.

2. Description of the Related Art In recent years, various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such a flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) And a light emitting device (Electroluminescence Device).

PDP has attracted attention as a display device that is most advantageous for large screen size but large screen size because of its simple structure and manufacturing process, but it has a problem of low luminous efficiency, low luminance, and large power consumption. A TFT LCD to which a thin film transistor (hereinafter referred to as "TFT") is applied as a switching element is the most widely used flat panel display device, but has a problem of a narrow viewing angle and a low response speed because it is a non-light emitting device. On the other hand, the electroluminescent device is divided into an inorganic light emitting diode display device and an organic light emitting diode display device according to the material of the light emitting layer. In particular, the organic light emitting diode display device uses self light emitting devices that emit self- Brightness and viewing angle are large.

The organic light emitting diode display device has an organic light emitting diode as shown in FIG. The organic light emitting diode has organic compound layers (HIL, HTL, EML, ETL, EIL) formed between the anode electrode and the cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The organic light emitting diode display device arranges the pixels including the organic light emitting diode in a matrix form and controls the brightness of the pixels selected by the scan pulse according to the gray level of the video data.

2 shows one pixel equivalently in an organic light emitting diode display. Referring to FIG. 2, the pixels of the active matrix type organic light emitting diode display include organic light emitting diodes (OLED), data lines DL and gate lines GL intersecting with each other, a switch TFT SW, a driving TFT DR ), And a storage capacitor (Cst). The switch TFT (SW) and the drive TFT (DR) are implemented as a P-type MOS-FET.

The switch TFT SW is turned on in response to a scan pulse from the gate line GL, thereby making the current path between the source electrode and the drain electrode conductive. The switch TFT SW applies a data voltage from the data line DL to the gate electrode of the drive TFT DR and the storage capacitor Cst during the turn-on period. The driving TFT DR controls the current flowing in the organic light emitting diode OLED according to the difference voltage Vgs between the gate electrode and the source electrode of the driving TFT DR. The storage capacitor Cst maintains the gate potential of the driving TFT DR constant for one frame. The organic light emitting diode OLED has a structure as shown in FIG. 1, and is connected between the drain electrode of the driving TFT DR and the ground voltage source GND.

In general, the non-uniformity of luminance between pixels in an organic light emitting diode display device is caused by various causes, for example, electric characteristic drift of a driving TFT, variation of a high potential driving voltage depending on a position, and deterioration of an organic light emitting diode. Particularly, the deterioration of the organic light emitting diode occurs because the deterioration rate of the organic light emitting diode varies for each pixel for a long period of time. When this deteriorates, an image sticking phenomenon occurs and the image quality deteriorates as a result.

Accordingly, it is an object of the present invention to provide an organic light emitting diode (OLED) display device and a method of driving the same that can compensate for a deterioration of an organic light emitting diode between pixels to prevent image quality degradation.

Another object of the present invention is to provide an organic light emitting diode display device and a method of driving the same that can compensate for a variation in electric characteristics of a driving TFT between pixels and a deviation of a high potential driving voltage according to a position, have.

According to an aspect of the present invention, there is provided an organic light emitting diode display device including a plurality of pixels arranged in a matrix in a crossing region of a plurality of gate lines and a plurality of data lines, Display panel including; A data driving circuit including a plurality of sensing and output units connected to the data lines on a one-to-one basis, and an ADC for generating sensing information by sampling and analog-to-digital converting a sensing result from the sensing & And a data processing circuit for determining compensation values for compensating deterioration of the organic light emitting diode based on the sensing information and adding the compensation values to input digital video data to generate digital correction data, Each of the output units operates as a current integrator during compensation driving to determine the compensation values, while acting as an output buffer during normal driving to apply the digital correction data to the display panel.

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

According to an embodiment of the present invention, a driving method of an organic light emitting diode display including a plurality of pixels arranged in a matrix form at intersecting regions of a plurality of gate lines and a plurality of data lines and each having an organic light emitting diode, Sensing a degree of deterioration of the organic light emitting diode using a plurality of sensing and output units connected in a one-to-one manner to the lines; Generating sensing information by sampling and analog-to-digital converting a sensing result from the sensing and outputting units; And determining compensation values for compensating deterioration of the organic light emitting diode based on the sensing information and adding the compensation values to input digital video data to generate digital correction data, Each operates as an output buffer in normal driving for applying the digital correction data to the display panel, while acting as a current integrator during compensation driving to determine the compensation values.

INDUSTRIAL APPLICABILITY The organic light emitting diode display device and the driving method thereof according to the present invention can significantly improve image quality by preventing image sticking phenomenon by compensating a deterioration deviation of the organic light emitting diode between pixels.

Furthermore, the organic light emitting diode display device and the driving method thereof according to the present invention can significantly improve the image quality by compensating for the deviation of the electric characteristics of the driving TFTs between the pixels and the deviation of the high-potential driving voltage according to the position.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 3 to 17B.

FIG. 3 is a block diagram showing an organic light emitting diode display according to an embodiment of the present invention, and FIG. 4 shows a specific configuration of the timing controller, the data driving circuit, and the memory of FIG.

3 and 4, an OLED display according to an embodiment of the present invention includes a display panel 10 in which pixels P are arranged in a matrix, data for driving the data lines 14 A gate drive circuit 13 for driving the gate line portions 15 and a timing controller 11 for controlling the drive timing of the data drive circuit 12 and the gate drive circuit 13, And a memory 15, as shown in Fig.

In the display panel 10, a plurality of data lines 14 and a plurality of gate line portions 15 cross each other, and the pixels P are arranged in a matrix form for each of the intersection regions. The gate line portion 15 is composed of a scan line 15a, a sensing line 15b, and an emission line 15c. Each pixel P is connected to one data line 14 and three signal lines constituting the gate line unit 15. [ The pixels P are commonly supplied with the high potential driving voltage Vdd and the reference voltage Vref. The high potential driving voltage Vdd is generated at a constant level by the high potential driving voltage source, and the reference voltage Vref is generated at a constant level by the reference voltage source. The reference voltage Vref may be defined as the voltage level between the base low voltage and the high potential driving voltage Vdd and may be generally set to the same level as the lowest data voltage. Each of the pixels P includes an organic light emitting diode, a driving TFT, and a plurality of switch TFTs. The configuration of the pixel P will be described later in detail with reference to Fig.

The timing controller 11 includes a control signal generating circuit 111 and a data processing circuit 112.

The control signal generating circuit 111 receives timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK and a data enable signal DE input from a system board A data control signal DDC and switch control signals phi 1 to phi 5 for controlling the operation timing of the data drive circuit 12 and a gate control signal for controlling the operation timing of the gate drive circuit 13, (GDC).

The data processing circuit 112 supplies the sensing information SD1 to SD3 input from the data driving circuit 12 and the compensation values CD determined based on the sensing information SD1 to SD3 to the memory 15 ). The digital correction data R'G'B 'is generated by adding the compensation values CD to the digital video data RGB inputted from the system board by referring to the memory 15, R'G'B ') to the data driving circuit 12. [ Here, the compensation value CD depends on the degree of deterioration of the organic light emitting diodes of the pixels P, the size of the feedback capacitor constituting the current integrator in the data driving circuit 12, and the parasitic resistance value between the current integrator and the organic light emitting diode It is determined differently.

The data processing circuit 112 includes first to third compensators 112A to 112C, a compensation value determiner 112D, and a data modulator 112E. The memory 15 includes first to fourth lookup tables LUT1 to LUT4. The first compensator 112A extracts the size of the feedback capacitor of each current integrator based on the first sensing information SD1 from the data driving circuit 12 and stores the result in the first lookup table LUT1 The second compensating unit 112B applies the second sensing information SD2 from the data driving circuit 12 to a built-in algorithm (Equation (1) to be described later) (See FIGS. 9 and 10). The third compensating unit 112C compensates the parasitic resistance values of the light emitting diodes from the data driving circuit 12 Voltage characteristic values of the organic light emitting diodes based on the sensing information SD3 and stores the result in the third lookup table LUT3 (see Figs. 11 and 12C). The compensation value determiner 112D ) Are calculated based on the values stored in the first through third lookup tables (LUT3) After determining the compensation values CD for compensating the distortion, the result is stored in the fourth lookup table LUT4. The data modulator 112E adds the position compensation values CD stored in the fourth lookup table LUT4 to the input digital video data RGB of the corresponding positions to output the digital correction data R'G'B ' And supplies this digital correction data R'G'B 'to the data driving circuit 12. The luminance nonuniformity between the pixels P due to the deterioration of the organic light emitting diode due to the digital correction data R'G'B 'can be solved.

The data driving circuit 12 generates the first to third sensing information SD1 to SD3 under the control of the timing controller 11 and supplies the first to third sensing information SD1 to SD3 to the timing controller 11. [ The digital correction data R'G'B 'input under the control of the timing controller 11 is converted into an analog data voltage (hereinafter referred to as a data voltage) and supplied to the data lines 14. To this end, the data driving circuit 12 includes a shift register 121, an analog-to-digital converter (ADC) 122, a plurality of digital-to-analog converters , And a plurality of sensing &

The sensing and outputting sections 124 are connected to the data lines 14 in a one-to-one manner and are operated in response to the switch control signals? 1 to? 5 from the timing controller 11, And functions as an output buffer at normal driving. Here, the compensation drive means a drive for determining the compensation values CD, and the normal drive means a drive for implementing a desired image by applying the digital correction data R'G'B 'to the display panel 10 it means. The detailed configuration of the sensing & output unit 124 will be described later in detail with reference to FIG.

The ADC 122 is commonly connected to the sensing and outputting units 124 to sample the sensing voltages, convert the sampled sensing voltages into first to third sensing information SD1 to SD3, which are digital signals, To the controller (11). The ADC 122 may be implemented as a known pipe-line type, SAR type, or single-slope type.

The shift register 121 sequentially shifts the sampling signal for the digital correction data R'G'B 'in response to the data control signal DDC from the timing controller 11. [

The DACs 123 are connected to the sensing and outputting units 124 on a one-to-one basis, respectively, and convert the digital correction data R'G'B 'input from the timing controller 11 into data voltages according to the sampling signals . The data voltage is supplied to the data lines 14 through the sensing &

The gate drive circuit 13 generates a scan signal SCAN, a sensing signal SEN and an emission signal EM under the control of the timing controller 11. [ The scan signal SCAN is supplied to the scan line 15a and the sensing signal SEN is supplied to the sensing line 15b. And the emission signal EM is supplied to the emission line 15c. The shift register array constituting the gate drive circuit 13 can be formed directly on the display panel 10 by a GIP (Gate In Panel) method.

FIG. 5 shows the sensing & output portion 124 of FIG. 4 in detail.

5, the sensing & output unit 124 includes an operational amplifier (hereinafter referred to as "OP-AMP"), an initialization voltage source VCM, a feedback capacitor Cfb, SW5. The switches SW1 to SW5 may be implemented as N-type MOSFETs.

OP-AMP has a first input terminal (+), a second input terminal (-), and an output terminal. The feedback capacitor Cfb is connected between the second input terminal (-) of the OP-AMP and the output terminal. The first switch SW1 is connected between the first input terminal (+) of the OP-AMP and the DAC 123, and is switched in response to the first switch control signal? 1. The second switch SW2 is connected between the first input terminal (+) of the OP-AMP and the initialization voltage supply source (VCM), and is switched in response to the second switch control signal? 2. The third switch SW3 is connected between the second input terminal (-) of the OP-AMP and the output terminal, and is switched in response to the third switch control signal? 3. The fourth switch SW4 is connected between the second input terminal (-) of the OP-AMP and the reference current source IREF, and is switched in response to the fourth switch control signal? 4. The fifth switch SW5 is connected between the second input terminal (-) of the OP-AMP and the pixel P, and is switched in response to the fifth switch control signal? 5. The reference current source IREF is commonly connected to all the sensing & The initialization voltage source VCM generates the initializing voltage Vcm and the reference current source IREF generates the reference current Iref that sinks toward the base voltage source GND.

Fig. 6 shows the pixel P shown in Fig. 3 in detail.

Referring to FIG. 6, the pixel P includes an organic light emitting diode OLED, a driving TFT DR, a plurality of switch TFTs ST1 to ST5, and a storage capacitor Cst. The driving TFT DR and the switch TFTs ST1 to ST5 may be implemented as a P-type MOSFET.

The organic light emitting diode OLED is connected between the third node N3 and the ground voltage source GND and emits light by a current flowing between the high potential driving voltage source VDD and the ground voltage source GND.

The driving TFT DR is connected between a high potential driving voltage source VDD for generating a high potential driving voltage Vdd and the organic light emitting diode OLED and has its source-gate voltage, that is, the high potential driving voltage source VDD And the first node N1, the amount of current flowing through the organic light emitting diode OLED is controlled.

The first switch TFT ST1 is connected between the high potential driving voltage source VDD and the first node N1 and is switched in response to the scan signal SCAN from the scan line 15a. The second switch TFT ST2 is connected between the data line 14 and the second node N2 and is switched in response to the scan signal SCAN from the scan line 15a. The third switch TFT ST3 is connected between the reference voltage source VREF for generating the reference voltage Vref and the second node N2 and is responsive to the emission signal EM from the emission line 15b Lt; / RTI > The fourth switch TFT (ST4) is connected between the drive TFT DR and the third node N3 and is switched in response to the emission signal EM from the emission line 15b. The fifth switch TFT ST5 is connected between the data line 14 and the third node N3 and is switched in response to the sensing signal SEN from the sensing line 15c.

The storage capacitor Cst is connected between the first node N1 and the second node N2.

Such organic light emitting diode display devices are largely operated by compensation driving and normal driving. The compensation drive is a drive for determining the compensation values CD and comprises a first compensation drive for deriving the first sensing information SD1 to determine the deviation of the feedback capacitors Cfb, The second compensation drive for deriving the second sensing information SD2 and the third compensation drive for deriving the third sensing information SD3 for determining the current-voltage characteristic values of the organic light emitting diodes. The normal driving means driving the display panel 10 to display the digital correction data R'G'B 'on which the compensation values CD are reflected. The first and second compensation driving are performed once at the initial setting of the display device, and the third compensation driving is performed a number of times in accordance with the deterioration of the organic light emitting diodes by the normal driving after the initial setting of the display device.

Hereinafter, the circuit operation in the compensation driving and the circuit operation in the normal driving will be sequentially described.

FIG. 7 is an application waveform diagram of control signals for the first compensation drive, and FIG. 8 shows an operation state of the display device at the same time as the first compensation operation.

7 and 8, the scan signal SCAN, the emission signal EM and the sensing signal SEN are maintained at the high logic level H during the first compensation operation, (ST1 to ST5). The first, third and fifth switch control signals phi 1, phi 3 and phi 5 are held at a low logic level L to be supplied to the first, third and fifth switches SW1 , SW3, and SW5 are turned off. On the other hand, the second and fourth switch control signals? 2 and? 4 are held at the high logic level (H) and then inverted to the low logic level (L) in synchronization with the sensing timing.

As a result, the sensing and outputting sections 124 function as current integrators, and the current integrators are connected in common to the reference current source IREF via the fourth switch SW4, respectively. Due to the sink current Iref generated in the reference current source IREF, the sensing voltage Vout1 applied to the output terminals of the current integrators gradually increases. These sensing voltages Vout1 are sampled at the logic level inversion of the second and fourth switch control signals? 2 and? 4. The level of the sensing voltage Vout1 depends on the size of the feedback capacitor Cfb constituting the current integrator. In order to compensate the deterioration of the organic light emitting diodes of all the pixels P under the same condition, the size of the feedback capacitors Cfb must be made uniform, but it is very difficult to realize the same size of the feedback capacitors Cfb due to the process variation . As a result, even if the same sink current Iref is applied to each current integrator by the reference current source IREF, the level of the sensing voltage Vout1 can be changed. For example, the sensing voltage Vout1 from the current integrator with the relatively large-sized feedback capacitor Cfb is lower than the sensing voltage Vout1 from the current integrator with the relatively small-sized feedback capacitor Cfb . Therefore, in order to accurately compensate the deterioration of the organic light emitting diodes, the size of the feedback capacitors Cfb must be reflected in the compensation value CD. To this end, the sampled sensing voltages Vout1 are converted into first sensing information SD1 through the ADC 122, stored in the first lookup table LUT1 via the first compensator 112A, (CD) crystal.

Since the first compensation drive is performed once in the initial setting process of the display device, the information stored in the first lookup table LUT1 is fixed.

FIG. 9 is an application waveform diagram of control signals for the second compensation drive, and FIG. 10 shows the operation state of the display device at the same time as the second compensation operation.

9 and 10, the scan signal SCAN and the emission signal EM during the second compensation operation are maintained at the high logic level H, and the first to fourth switch TFTs ST1 to ST4) are turned off. The first, third and fourth switch control signals? 1,? 3 and? 4 are held at the low logic level L and the first, third and fourth switches SW1 and SW3 , SW4 are turned off.

On the other hand, during the second compensation driving, the sensing signal SEN is held at the low logic level L to turn on the fifth switch TFT ST5 of the pixel P. [ The second and fifth switch control signals phi 2 and phi 5 are held at the high logic level H and then inverted to the low logic level L in synchronization with the sensing timing.

As a result, the sensing and outputting section 124 functions as a current integrator, and this current integrator is electrically connected to the organic light emitting diode OLED through the fifth switch SW5. The current Ioled flows through the organic light emitting diode OLED by the initializing voltage Vcm applied to the input terminal (+) of the current integrator. Due to the current Ioled flowing through the organic light emitting diode OLED, the sensing voltage Vout2 applied to the output terminal of the current integrator gradually increases. This sensing voltage Vout2 is sampled at the logic level inversion of the second and fifth switch control signals? 2 and? 5.

However, when the current Ioled flows through the organic light emitting diode OLED, the parasitic resistance value Rload existing in the data line 14 and the parasitic resistance value Rsw of the fifth switch TFT ST5 cause the IR drop And thus the voltage applied to the organic light emitting diode OLED is lower than the initialization voltage Vcm. Since the parasitic resistance value Rload increases in proportion to the length of the data line 14, even if the same initialization voltage Vcm is applied using the current integrator, the parasitic resistance value Rload is applied to the organic light emitting diode OLED And the voltage to be applied are different from each other. Therefore, in order to accurately compensate the degradation of the organic light emitting diodes, the parasitic resistance values Rload and Rsw must be extracted and reflected in the compensation value CD. The initialization voltage Vcm may be applied twice at a first level Vcm1 and at a second level Vcm2 higher than the first level Vcm1 in order to increase the accuracy of compensation. The sensing voltage Vout2 of the first level sampled by the initializing voltage of the first level Vcm1 and the sensing voltage Vout2 of the second level sampled by the initializing voltage of the second level Vcm2 are supplied to the ADC 122 To the second sensing information SD2 and then applied to the second compensating unit 112B. The second compensating unit 112B applies the second sensing information SD2 to an algorithm represented by the following equation (2) to extract the entire parasitic resistance value Rload + Rsw.

In the expression (1), " Ioled1 "denotes a current flowing in the organic light emitting diode when the initialization voltage of the first level (Vcm1) is applied and" Ioled2 & Va1 denotes the voltage actually applied to the organic light emitting diode when the initialization voltage of the first level (Vcm1) is applied, and Va2 denotes the initialization voltage of the second level (Vcm2) of the organic light emitting diode. "V _T " represents the thermal voltage constant of the organic light emitting diode, and "n" represents the emission coefficient of the organic light emitting diode.

"Ioled1" and "Ioled2" in Equation (1) can be easily found by the following Equation (2).

Quot; Cf " in the expression (2) represents the capacitance of the feedback capacitor Cfb, and "Vcf" represents the voltage across the feedback capacitor Cfb.

The extracted parasitic resistance value Rload + Rsw is stored in the second lookup table LUT2 by the second compensation unit 112B, and then used for determination of the compensation value (CD). The parasitic resistance value (Rload + Rsw) extraction process is performed for all the pixels (P).

Since the second compensation drive is performed once in the initial setting process of the display device, the information stored in the second lookup table LUT2 is fixed.

FIG. 11 is an application waveform diagram of control signals for the third compensation driving, and FIGS. 12A to 12C sequentially show operation states of the display device at the second compensation operation. The third compensation drive progresses in a first period CT1 for applying the initialization voltage, a second period CT2 for charging the feedback capacitor, and a third period CT3 for generating the sensing voltage. This third compensation drive may be performed for all of the pixels P for at least one frame synchronized with the on timing of the drive power source, or for at least one frame synchronized with the off timing of the drive power source. In addition, the third compensation driving can be performed for the pixels P in one horizontal line for each blank period between adjacent frames in the course of normal driving.

11 and 12A, during the first period CT1, the scan signal SCAN and the emission signal EM are generated at the high logic level H, so that the first to fourth switch TFTs (ST1 to ST4) are turned off. The sensing signal SEN is generated at the low logic level L during the first period CT1 to turn on the fifth switch TFT ST5 of the pixel P. [ During the first period CT1, the first and fourth switch control signals phi 1 and phi 4 are generated at the low logic level L and the first and fourth switches SW1 and SW4 in the data driving circuit 12 The second, third and fifth switch control signals? 2,? 3 and? 5 are generated at the high logic level H and the second, third and fifth switches SW2 , SW3, and SW5 are turned on.

Accordingly, the first input terminal (+) of the OP-AMP constituting the sensing & output unit 124 is connected to the initialization voltage supply source (VCM), the second input terminal (-) and the output terminal of the OP- , And the second input terminal (-) of the OP-AMP is connected to the organic light emitting diode OLED of the pixel P. The feedback capacitor Cfb is reset by the short circuit. According to the virtual ground characteristic of the OP-AMP, the potential of the second input terminal (-) of the OP-AMP is maintained at the initializing voltage (Vcm). The output terminal potential of the OP-AMP is also maintained at the initialization voltage (Vcm). The initialization voltage Vcm is applied to the anode electrode of the organic light emitting diode OLED while charging the data line 14 at a high speed. As a result, current flows through the organic light emitting diode OLED. The magnitude of the current flowing through the organic light emitting diode (OLED) varies depending on the degree of deterioration of the organic light emitting diode (OLED). For example, even if an initialization voltage Vcm of the same level is applied to two organic light emitting diodes (OLEDs) as shown in FIG. 13, the current Ib flowing in the organic light emitting diode OLED_B, Becomes lower than the current Ia flowing in the organic light emitting diode OLED_A having a small degree of deterioration.

11 and 12B, the scan signal SCAN and the emission signal EM are maintained at the high logic level (H) during the second period CT2 so that the first to fourth switch TFTs ST1 to ST4 are continuously turned off. The sensing signal SEN remains at the low logic level L during the second period CT2 to turn on the fifth switch TFT ST5 of the pixel P continuously. During the second period CT2, the first and fourth switch control signals phi 1 and phi 4 are held at the low logic level L and the first and fourth switches SW1 and SW4 in the data driving circuit 12 are The third switch control signal? 3 is inverted to the low logic level L to turn off the third switch SW3 in the data driving circuit 12, and the second and fifth switch control signals? and the second and fifth switches SW2 and SW5 in the data driving circuit 12 are kept turned on.

Accordingly, the first input terminal (+) of the OP-AMP constituting the sensing & output unit 124 is continuously connected to the initial voltage supply source VCM, and the second input terminal (-) of the OP- And the second input terminal (-) of the OP-AMP is continuously connected to the organic light emitting diode (OLED) of the pixel P. The sensing & output unit 124 functions as an integrator by canceling the shot. Since the current flowing in the organic light emitting diode OLED charges the feedback capacitor Cfb, the output terminal potential Vo of the OP-AMP linearly increases at the initializing voltage Vcm.

11 and 12C, the scan signal SCAN and the emission signal EM are maintained at the high logic level (H) during the third period CT3 so that the first to fourth switch TFTs ST1 to ST4 are continuously turned off. The sensing signal SEN remains at the low logic level L during the third period CT3 to turn on the fifth switch TFT ST5 of the pixel P continuously. During the third period CT3, the first and fourth switch control signals phi 1 and phi 4 are held at the low logic level L and the first and fourth switches SW1 and SW4 in the data driving circuit 12 are The third switch control signal? 3 is kept at the low logic level L so as to turn off the third switch SW3 in the data driving circuit 12 continuously and the second switch control signal? 2 is kept at the high logic level H to turn on the second switch SW2 in the data driving circuit 12 continuously. The fifth switch control signal phi 5 is inverted to the low logic level L to turn off the fifth switch SW5 in the data drive circuit 12. [

Accordingly, the voltage stored in the output terminal of the OP-AMP until the fifth switch SW5 is turned off is sampled at the sensing voltage Vout3. When the sampling time is kept constant, the level of the sampling voltage Vout3 sampled depends on the degree of deterioration of the organic light emitting diode OLED. 14, the sensing voltage Vout3 level Vb when the deterioration is large is smaller than the sensing voltage Vout3 level Va when the deterioration is small (for example, . This is a method of sampling a voltage obtained at a constant time and can be implemented through an ADC 122 such as a Pipe-Line type or SAR type. The magnitude of the sampled sensing voltage Vout3 is inversely proportional to the degree of deterioration of the organic light emitting diode OLED.

As another method of predicting the degree of deterioration of the organic light emitting diode (OLED), the amount of time it takes to reach a constant voltage and reach this voltage can be used. As in the above method, this method also utilizes the increase slope of the output voltage of the OP-AMP depending on the magnitude of the current flowing through the organic light emitting diode (OLED). For example, the target voltage Vc may be determined in advance as shown in FIG. 15, and the time taken for the level of the sensing voltage Vout3 to reach the target voltage Vc may be sampled. 15, the size of the sampled times Ts1 and Ts2 is proportional to the degree of deterioration of the organic light emitting diode OLED. Such a method may be implemented through an ADC 122 such as a Single-Slope type.

The sampled sensing voltages Vout3 (or sampled times) are converted into third sensing information SD3 via the ADC 122 and then sent to the third lookup table LUT3 via the third compensator 112C And is then used to determine the compensation value (CD).

Since this third compensation drive is repeatedly executed, the information stored in the third lookup table LUT3 is continuously updated.

FIG. 16 is an application waveform diagram of control signals for normal driving, and FIGS. 17A and 17B sequentially show operation states of the display device at the time of normal driving. The normal driving progresses in a first period DT1 for compensating the driving TFT deviation and the high potential driving voltage deviation, and a second period DT2 for programming and light emission.

16 and 17A, during a first period DT1, a scan signal SCAN is generated at a low logic level L to turn on the first and second switch TFTs ST1 and ST2 of the pixel P And the emission signal EM is generated at the high logic level H to turn off the third and fourth switch TFTs ST3 and ST4 of the pixel P and the sensing signal SEN is at the high logic level (H) to turn off the fifth switch TFT (ST5) of the pixel (P). During the first period DT1, the first, third and fifth switch control signals? 1,? 3,? 5 are generated at the high logic level (H) 5 switches SW1, SW3 and SW5 are turned on and the second and fourth switch control signals phi 2 and phi 4 are generated at a low logic level L and the second and fourth switches The switches SW2 and SW4 are turned off.

As a result, the sensing & output unit 124 functions as an output buffer to buffer the data voltage (Vdata) input from the DAC 123 and supply it to the data line 14. In the pixel P, the intermediate compensation value Vdd-Vth is applied to the first node N1 by the diode connection of the drive TFT DR (the gate electrode and the drain electrode of the drive TFT DR are short-circuited). The intermediate compensation value Vdd-Vth is determined by subtracting the threshold voltage Vth of the driving TFT DR from the high-potential driving voltage Vdd. And the data voltage Vdata is applied to the second node N2. The storage capacitor Cst holds the potential of the first node N1 at the intermediate compensation value Vdd-Vth and the potential at the second node N2 at the data voltage Vdata.

16 and 17B, during the second period DT2, the scan signal SCAN is inverted to the high logic level H to turn on the first and second switch TFTs ST1 and ST2 of the pixel P The emission signal EM is inverted to the low logic level L to turn on the third and fourth switch TFTs ST3 and ST4 of the pixel P and the sensing signal SEN is turned to the high logic level (H) to turn off the fifth switch TFT (ST5) of the pixel P continuously. During the second period DT2, the logic level state of the switch control signals phi 1 through phi 5 remains the same as the first period DT1.

The reference voltage Vref is applied to the second node N2 of the pixel P and the potential of the second node N2 is changed from the data voltage Vdata to the reference voltage Vref. Since the first node N1 is connected to the second node N2 via the storage capacitor Cst, the potential change amount Vdata-Vref of the second node is directly applied to the first node N1 N1). As a result, the potential of the first node N1 is the final compensation value {(Vdd-Vth) - (Vdata-Vref)} obtained by subtracting the potential change amount (Vdata-Vref) of the second node from the intermediate compensation value (Vdd- .

At this time, the driving current Ioled flowing through the organic light emitting diode OLED is expressed by the following equation (3).

In Equation 3, "k" represents a constant determined by mobility, parasitic capacitance, and channel size, and "Vsg" represents a source-gate voltage of the driving TFT DR.

The driving current Ioled according to the present invention depends on the data voltage Vdata and the reference voltage Vref that can be controlled by the user and can be controlled by the threshold voltage of the driving TFT DR, (Vth) applied to the driving TFT (DR) and the level of the high potential driving voltage (Vdd) applied to the driving TFT (DR). Therefore, even if the threshold voltage Vth of the driving TFT DR and the high-potential driving voltage Vdd are different for each of the pixels P, the luminance irregularity among the pixels P can be reduced by as much as a suitable voltage Vdata- Can be solved.

INDUSTRIAL APPLICABILITY As described above, the organic light emitting diode display and the driving method thereof according to the present invention can improve image quality by preventing deterioration of image by compensating for the deterioration of the organic light emitting diode between pixels.

Furthermore, the organic light emitting diode display device and the driving method thereof according to the present invention can significantly improve the image quality by compensating for the deviation of the electric characteristics of the driving TFTs between the pixels and the deviation of the high-potential driving voltage according to the position.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a view showing the principle of light emission of a general organic light emitting diode display device.

FIG. 2 is an equivalent view of one pixel in a conventional 2T1C structure organic light emitting diode display. FIG.

3 is a view illustrating an organic light emitting diode display device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a specific configuration of the timing controller, the data driving circuit, and the memory of FIG. 3; FIG.

5 is a detailed view of the sensing &

FIG. 6 is a detailed view of the pixel shown in FIG. 3; FIG.

7 shows an applied waveform of control signals for a first compensation drive;

8 is a view showing an operation state of the display device at the same time as the first compensation mechanism.

9 shows an applied waveform of control signals for a second compensation drive;

10 is a view showing an operation state of the display device at the same time as the second compensation mechanism.

11 shows an applied waveform of control signals for a third compensation drive;

12A to 12C are diagrams sequentially showing the operation states of the display device at the time of the second compensation operation.

13 is a view showing the relationship between the current flowing through the organic light emitting diode and the degree of deterioration of the organic light emitting diode.

FIGS. 14 and 15 are diagrams for explaining a method of sampling. FIG.

16 is a diagram showing an applied waveform of control signals for normal driving;

FIGS. 17A and 17B are diagrams sequentially showing the operation states of the display device at the time of normal operation. FIG.

Description of the Related Art

10: Display panel 11: Timing controller

12: data driving circuit 13: gate driving circuit

14: Data line 15: Gate line

16: memory 111: control signal generating circuit

112: Data processing circuit 121: Shift register

122: analog-to-digital converter 123: digital-to-analog converter

124: sensing and output section

Claims (14)

A display panel including a plurality of pixels arranged in a matrix form at intersecting regions of a plurality of gate lines and a plurality of data lines and each having an organic light emitting diode; A data driving circuit including a plurality of sensing and output units connected to the data lines, and an ADC for sampling and analog-to-digital converting a sensing result from the sensing and outputting units to generate sensing information; And And a data processing circuit for determining compensation values for compensating deterioration of the organic light emitting diode based on the sensing information and adding the compensated values to input digital video data to generate digital correction data, Wherein each of the sensing and outputting units operates as an output buffer during normal driving to apply the digital correction data to the display panel while operating as a current integrator during compensation driving to determine the compensation values, Light emitting diode display. The method according to claim 1, Wherein the data driving circuit further comprises a plurality of DACs for converting the digital correction data to a data voltage and supplying the data to the sensing and outputting units during the normal driving. 3. The method of claim 2, Each of the sensing & An OP-AMP having a first input, a second input, and an output coupled to the ADC; A feedback capacitor connected between the second input terminal and the output terminal; A first switch connected between the first input terminal and the DAC; A second switch connected between the first input and the initialization voltage source; A third switch connected in parallel with the feedback capacitor between the second input terminal and the output terminal; A fourth switch connected between the second input terminal and the reference current source; And And a fifth switch connected between the second input terminal and the pixel. The method of claim 3, Wherein each of the sensing and outputting units functions as the current integrator through a first compensation drive pertaining to the compensation driving to sense the degree of deterioration of the organic light emitting diodes of the pixels. 5. The method of claim 4, Wherein the first compensation drive proceeds to a first period, a second period subsequent to the first period, and a third period subsequent to the second period; During the first period, the second, third, and fifth switches are turned on to reset the feedback capacitor, and an initialization voltage from the initialization voltage source is applied to the organic light emitting diode Current flow; During the second period, the third switch is turned off and the second and fifth switches are continuously turned on to charge the feedback capacitor with a current flowing in the organic light emitting diode; And the third and fifth switches are turned off and the second switch is continuously turned on during the third period so that the voltage of the output terminal is sensed. 6. The method of claim 5, Wherein the ADC samples the voltage level of the output terminal at a certain point of time or samples the time taken for the voltage of the output terminal to reach a predetermined target voltage. The method of claim 3, Each of the sensing & outputs functions as the current integrator through a second compensation drive pertaining to the compensation drive to sense their feedback capacitor size; Wherein the first, third, and fifth switches are kept in a turned-off state and the second and fourth switches are turned off after being maintained in a turned-on state for a predetermined time during the second compensation driving. Light emitting diode display. The method of claim 3, Each of the sensing and outputting portions functions as the current integrator through a third compensation drive belonging to the compensation driving, and senses a parasitic resistance value between itself and the organic light emitting diode; Wherein the first, third and fourth switches are kept in a turn-off state and the second and fifth switches are turned off after being maintained in a turn-on state for a predetermined time during the third compensation driving, Wherein the organic light emitting diode display device generates the initialization voltage twice at different levels. The method of claim 3, Each of the sensing and outputting portions functions as the output buffer through the normal driving to supply a data voltage from the DAC to the data lines; Wherein during the normal driving, the first, third, and fifth switches are held in a turned-on state and the second and fourth switches are held in a turned-off state. 10. The method of claim 9, Each of the pixels includes: Organic light emitting diodes; A driving TFT connected between a high potential driving voltage source for generating a high potential driving voltage and the organic light emitting diode and controlling an amount of current flowing in the organic light emitting diode according to a voltage between the high potential driving voltage source and the first node; A first switch TFT connected between the high potential driving voltage source and the first node; A second switch TFT connected between the data line and a second node; A third switch TFT connected between the reference voltage source generating the reference voltage and the second node; A fourth switch TFT connected between the driving TFT and the organic light emitting diode; A fifth switch TFT connected between the data line and the organic light emitting diode; And And a storage capacitor connected between the first node and the second node. 11. The method of claim 10, The normal driving proceeds to a first period and a second period subsequent to the first period; During the first period, the first and second switch TFTs are turned on and the third to fifth switch TFTs are turned off, and the first node is supplied with the high-potential drive voltage minus the threshold voltage of the drive TFT An intermediate compensation value is applied, and a data voltage is applied to the second node; During the second period, the first, second and fifth switch TFTs are turned off and the third and fourth switch TFTs are turned on, and the potential of the second node changes from the data voltage to the reference voltage And the potential of the first node is determined as a final compensation value obtained by subtracting the potential change amount of the second node from the intermediate compensation value by the potential change of the second node. A method of driving an organic light emitting diode (OLED) display device including a plurality of pixels each having an organic light emitting diode, the plurality of pixels being arranged in a matrix form in intersecting regions of a plurality of gate lines and a plurality of data lines, Sensing a degree of deterioration of the organic light emitting diode using a plurality of sensing and output units connected to the data lines; Generating sensing information by sampling and analog-to-digital converting a sensing result from the sensing and outputting units; And Determining compensating values for compensating deterioration of the organic light emitting diode based on the sensing information, and adding the compensation values to input digital video data to generate digital correction data, Wherein each of the sensing and outputting units operates as an output buffer during normal driving to apply the digital correction data to the display panel while operating as a current integrator during compensation driving to determine the compensation values, A method of driving a diode display device. 13. The method of claim 12, The step of sensing the degree of degradation comprises: Applying an initialization voltage generated through the sensing & output unit to the organic light emitting diode to allow current to flow through the organic light emitting diode; Charging a feedback capacitor in the sensing & output unit with a current flowing through the organic light emitting diode; And And sensing a charge voltage of the feedback capacitor at an output terminal of the sensing and outputting unit. 14. The method of claim 13, The step of sampling the sensing result from the sensing and outputting units may include sampling the voltage level of the output terminal of the sensing & output unit at a certain point of time, or measuring the time taken for the voltage of the output terminal of the sensing & output unit to reach a predetermined target voltage Wherein the sampling is performed by using the sampling signal.

Images