CN114530133B - Display panel and display terminal - Google Patents
Display panel and display terminal Download PDFInfo
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- CN114530133B CN114530133B CN202210209455.9A CN202210209455A CN114530133B CN 114530133 B CN114530133 B CN 114530133B CN 202210209455 A CN202210209455 A CN 202210209455A CN 114530133 B CN114530133 B CN 114530133B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Abstract
The application relates to a display panel and a display terminal, wherein the display panel comprises a pixel unit array and a time division multiplexing unit, the time division multiplexing unit comprises a plurality of gating lines and a plurality of switching transistors, a plurality of first compensation capacitors are arranged at a first port and a third port of each of the partial switching transistors, and a second compensation capacitor is arranged at a first port of at least one switching transistor and a third port of other switching transistors; or a plurality of third compensation capacitors are arranged between the first port and the second port of the partial switch transistors, and the first port of at least one switch transistor and the second port of other switch transistors are provided with fourth compensation capacitors. Through establishing a plurality of first compensation electric capacity, second compensation electric capacity, third compensation electric capacity and fourth compensation electric capacity in the time-sharing multiplexing unit, this application can carry out the mixed compensation to the data signal on each data line, guarantees data signal's uniformity, avoids data signal on each data line to appear the difference, eliminates the phenomenon that the display picture shows inhomogeneous.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display terminal.
Background
In the field of liquid crystal displays (Liquid Crystal Display, LCD), a method of reducing driving chips or Demux (multiplexing) technology is generally used for cost saving. For example, the gate driver chip is removed in the GOA (Gate on Array) circuit, or the number of gate driver chips or source driver chips is reduced by time-division multiplexing using Demux technology.
However, in the related art, although the number of source driver chips can be reduced, coupling capacitances between different transistors in the Demux circuit are different, so that the data signals on the corresponding data lines are different, and adverse phenomena such as vertical lines and horizontal lines may occur in the display screen, thereby affecting the uniformity of the display screen.
Disclosure of Invention
In view of this, the present application provides a display panel and a display terminal, which can perform hybrid compensation on data signals on each data line output by a time division multiplexing unit, ensure consistency of the data signals on each data line, further avoid differences of the data signals on each data line, and eliminate a phenomenon that display images are unevenly displayed.
According to an aspect of the present application, there is provided a display panel, including a pixel unit array and a plurality of time division multiplexing units, each of the time division multiplexing units is electrically connected to the pixel unit array, each of the pixel units in the pixel unit array includes one or more sub-pixel units, each of the time division multiplexing units includes a plurality of gate lines and a plurality of switching transistors, wherein a first port of each of the switching transistors is electrically connected to one of the gate lines, and a second port of each of the switching transistors is electrically connected to a corresponding driving signal; the third ports of the at least two switching transistors are respectively and electrically connected to the sub-pixel units in different pixel units to form the intersection of the data lines corresponding to the at least two switching transistors; among the plurality of switch transistors, a plurality of first compensation capacitors are arranged between a first port of a part of the switch transistors and a third port of the switch transistor, wherein one or a plurality of second compensation capacitors are arranged between a first port of a switch transistor corresponding to at least one first compensation capacitor and the third port of other switch transistors; or, a plurality of third compensation capacitors are arranged between the first ports of some of the switch transistors and the second ports of the switch transistors, wherein one or a plurality of fourth compensation capacitors are arranged between the first ports of the switch transistors corresponding to at least one third compensation capacitor and the second ports of other switch transistors.
Further, the first port of each switching transistor is a gate of the switching transistor, the second port of each switching transistor is a source of the switching transistor, the third port of each switching transistor is a drain of the switching transistor, or the first port of each switching transistor is a gate of the switching transistor, the second port of each switching transistor is a drain of the switching transistor, and the third port of each switching transistor is a source of the switching transistor.
Further, each time-division multiplexing unit includes a first multiplexing unit and a second multiplexing unit, where the first multiplexing unit and the second multiplexing unit are electrically connected to the pixel unit array, and the number of gate lines and the number of switching transistors in the first multiplexing unit and the second multiplexing unit are both N, where N is a natural number greater than or equal to 2, and the number of compensation capacitors of the first multiplexing unit is different from the number of compensation capacitors of the second multiplexing unit.
Further, the number of the compensation capacitors of the first multiplexing unit is N-1, the N-1 compensation capacitors comprise a first compensation capacitor and N-2 second compensation capacitors, one end of the first compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the 1 st switching transistor in the first multiplexing unit; one end of the N-2 second compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the first multiplexing unit, and the other end of the N-2 second compensation capacitor is electrically connected with the third port of the N-1 st switching transistor in the first multiplexing unit.
Further, the number of the compensation capacitors of the second multiplexing unit is N, the N compensation capacitors include a first compensation capacitor and N-1 second compensation capacitors, one end of the first compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the 1 st switching transistor in the second multiplexing unit; one end of the N-1 second compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the second multiplexing unit, and the other end of the N-1 second compensation capacitor is electrically connected with the third port of the N switching transistor in the second multiplexing unit.
Further, the capacitance value of any one of the first compensation capacitors in the first multiplexing unit is different from the capacitance value of the first compensation capacitor in the second multiplexing unit, and the capacitance value of any one of the second compensation capacitors in the first multiplexing unit is different from the capacitance value of the second compensation capacitor in the second multiplexing unit.
Further, the number of the compensation capacitors of the first multiplexing unit is N-1, the N-1 compensation capacitors comprise a third compensation capacitor and N-2 fourth compensation capacitors, one end of the third compensation capacitor is electrically connected with the first port of the Nth switching transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the Nth switching transistor in the first multiplexing unit; one end of the N-2 fourth compensation capacitor is electrically connected with the first port of the N-1 switching transistor in the first multiplexing unit, and the other end of the N-2 fourth compensation capacitor is electrically connected with the third port of the N-1 switching transistor in the first multiplexing unit.
Further, the number of the compensation capacitors of the second multiplexing unit is N, the N compensation capacitors include a third compensation capacitor and N-1 fourth compensation capacitors, one end of the third compensation capacitor is electrically connected with the first port of the nth switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the nth switching transistor in the second multiplexing unit; one end of the N-1 fourth compensation capacitor is electrically connected with the first port of the N-1 switching transistor in the second multiplexing unit, and the other end of the N-1 fourth compensation capacitor is electrically connected with the third port of the N-1 switching transistor in the second multiplexing unit.
Further, the capacitance value of any one of the third compensation capacitors in the first multiplexing unit is different from the capacitance value of the third compensation capacitor in the second multiplexing unit, and the capacitance value of any one of the fourth compensation capacitors in the first multiplexing unit is different from the capacitance value of the fourth compensation capacitor in the second multiplexing unit.
According to another aspect of the present application, there is provided a display terminal including a terminal body and the display panel, the terminal body being connected with the display panel.
By arranging a plurality of first compensation capacitors between a first port of a switching transistor and a third port of the switching transistor in a plurality of switching transistors of a time division multiplexing unit with data lines crossing each other, arranging one or more second compensation capacitors between a first port of the switching transistor corresponding to at least one first compensation capacitor and a third port of other switching transistors, or arranging a plurality of third compensation capacitors between a first port of the switching transistor and a second port of the switching transistor, arranging one or more fourth compensation capacitors between a first port of the switching transistor corresponding to at least one third compensation capacitor and a second port of other switching transistors, the data signals on each data line output by the time division multiplexing unit can be subjected to mixed compensation according to aspects of the application, the consistency of the data signals on each data line is ensured, the difference of the data signals on each data line is further avoided, and the phenomenon of uneven display of pictures is eliminated.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a Demux driving architecture of the related art.
Fig. 2 shows a schematic diagram of a display panel according to an embodiment of the present application.
Fig. 3 shows a schematic diagram of a time division multiplexing unit according to an embodiment of the present application.
Fig. 4 shows a schematic diagram of a time division multiplexing unit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements or interaction relationship between the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials. In some instances, methods, means, elements, and circuits have not been described in detail as not to unnecessarily obscure the present application.
Fig. 1 shows a schematic diagram of a Demux driving architecture of the related art.
As shown in fig. 1, in the related art, the Demux circuit can switch on and off one driving Signal (i.e., signal 1) outputted from the Source Driver chip (i.e., source Driver IC) in a 1:3 manner sequentially through the transistor T1, the transistor T2 and the transistor T3, and time-division transmit the driving Signal to the 3 rows of data lines DL1, DL2 and DL3 in the display area; the other driving Signal (i.e., signal 2) output from the source driving chip can be turned on and off sequentially by the transistors T4, T5 and T6 in a 1:3 manner, and is transmitted to the 3 rows of data lines DL4, DL5 and DL6 in the display area in a time sharing manner.
In fig. 1, the display area may include a plurality of pixel units, each including a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit. The red sub-pixel unit 11, the green sub-pixel unit 12 and the blue sub-pixel unit 13 may be located in the same pixel unit of the display area of the display panel; the red sub-pixel unit 14, the green sub-pixel unit 15, and the blue sub-pixel unit 16 may be located in another pixel unit of the display area of the display panel. A corresponding thin film transistor may be disposed in each sub-pixel unit, and the thin film transistor in each sub-pixel unit may be electrically connected to a corresponding data line. For example, the drain of the thin film transistor in the red sub-pixel unit 11 may be electrically connected to the data line DL1, the drain of the thin film transistor in the green sub-pixel unit 12 may be electrically connected to the data line DL2, and the drain of the thin film transistor in the blue sub-pixel unit 13 may be electrically connected to the data line DL 3.
Referring to fig. 1, de2, and De3 may be different gate lines, and the gate lines GL1 may be electrically connected to the gates of the respective thin film transistors in a row of sub-pixel units, respectively. The drain of the first transistor T1 is electrically connected to the data line DL1, the drain of the fifth transistor T5 is electrically connected to DL2, the drain of the third transistor T3 is electrically connected to DL3, the drain of the fourth transistor T4 is electrically connected to DL4, the drain of the second transistor T2 is electrically connected to the data line DL5, and the drain of the sixth transistor T6 is electrically connected to DL6.
In actual operation, during the high level period of the gate line GL1, the De2 and the De3 may be pulse signals in sequence to control the transistors T1, T2 and T3 to be turned on in sequence, so as to transmit the data Signal1 to the data lines DL1, DL5 and DL3 in a time-sharing manner, and finally write the display data into the sub-pixel unit 11, the sub-pixel unit 15 and the sub-pixel unit 13 in a time-sharing manner, thereby realizing the display of the display screen. Similar operation is also possible for Signal 2.
However, in fig. 1, there is a coupling capacitance (or parasitic capacitance) Cp0 between the drain of the transistor T3 and the drain of the transistor T2 (or between the data line DL5 and the data line DL 3). Further, there is a coupling capacitance Cp21 between the drain of the transistor T2 and the gate of the transistor T1 (or between the data line DL5 and the gate line De 1); a coupling capacitor Cp31 exists between the drain of the transistor T3 and the gate of the transistor T1; there is a coupling capacitance Cp32 between the drain of transistor T3 and the gate of transistor T2. A coupling capacitance Cp54 exists between the drain of the transistor T5 and the gate of the transistor T4; a coupling capacitor Cp64 exists between the drain of the transistor T6 and the gate of the transistor T4; there is a coupling capacitance Cp65 between the drain of transistor T6 and the gate of transistor T5.
The coupling condition between the different data lines DL1 to DL6 is not uniform due to the coupling capacitance between the transistors. When the transistors T1-T6 are turned on or off by the gate lines, the data signals on the data lines DL1-DL6 are different, so that uneven display of vertical lines, horizontal lines and the like may occur on the display picture.
Therefore, in the case where the data lines corresponding to the sub-pixel units of the same color in the different pixel units in fig. 1 cross each other, the influence of the coupling capacitance between the transistor (e.g., T2 or T5) directly related to the crossing line and each gate line is large, and at the same time, the influence of the coupling capacitance between the transistor (e.g., T3 or T6) directly related to the crossing line and the coupling capacitance between the transistor adjacent to the next transistor and each gate line are also large. In addition, coupling capacitances (e.g., cp 0) also exist between different data lines, e.g., crossing data lines and adjacent data lines.
In view of this, the present application provides a display panel, where the display panel includes a pixel unit array and a plurality of time division multiplexing units, each of the time division multiplexing units is electrically connected to the pixel unit array, each of the pixel units in the pixel unit array includes one or more sub-pixel units, each of the time division multiplexing units includes a plurality of gate lines and a plurality of switching transistors, where a first port of each of the switching transistors is electrically connected to one of the gate lines, and a second port of each of the switching transistors is electrically connected to a corresponding driving signal; the third ports of the at least two switching transistors are respectively and electrically connected to the sub-pixel units in different pixel units to form the intersection of the data lines corresponding to the at least two switching transistors; among the plurality of switch transistors, a plurality of first compensation capacitors are arranged between a first port of a part of the switch transistors and a third port of the switch transistor, wherein one or a plurality of second compensation capacitors are arranged between a first port of a switch transistor corresponding to at least one first compensation capacitor and the third port of other switch transistors; or, a plurality of third compensation capacitors are arranged between the first ports of some of the switch transistors and the second ports of the switch transistors, wherein one or a plurality of fourth compensation capacitors are arranged between the first ports of the switch transistors corresponding to at least one third compensation capacitor and the second ports of other switch transistors.
By arranging a plurality of first compensation capacitors between a first port of a switching transistor and a third port of the switching transistor in a plurality of switching transistors of a time division multiplexing unit with data lines crossing each other, one or more second compensation capacitors are arranged between the first port of the switching transistor corresponding to at least one first compensation capacitor and the third ports of other switching transistors, or a plurality of third compensation capacitors are arranged between the first port of the switching transistor and the second port of the switching transistor, and one or more fourth compensation capacitors are arranged between the first port of the switching transistor corresponding to at least one third compensation capacitor and the second ports of other switching transistors.
Fig. 2 shows a schematic diagram of a display panel according to an embodiment of the present application.
As shown in FIG. 2, embodiments of the present application identify names or sequences in a left-to-right and top-to-bottom order. 1 may represent an array of pixel cells and 2 may represent any one of the time-division multiplexing units (also called Demux units). The time division multiplexing unit may have two paths of driving signals Signal1 and Signal2, and output corresponding data signals to different sub-pixel units through the first multiplexing unit and the second multiplexing unit respectively. The first multiplexing unit may include a 1 st switching transistor T1, a 2 nd switching transistor T2, and a 3 rd switching transistor T3; the second multiplexing unit may include a 1 st switching transistor T4, a 2 nd switching transistor T5, and a 3 rd switching transistor T6.
Further, the sub-pixel unit 11 may be a red sub-pixel unit, the sub-pixel unit 12 may be a green sub-pixel unit, and the sub-pixel unit 13 may be a blue sub-pixel unit. The sub-pixel unit 11, the sub-pixel unit 12 and the sub-pixel unit 13 are positioned in the same pixel unit; the sub-pixel unit 14 may be a red sub-pixel unit, the sub-pixel unit 15 may be a green sub-pixel unit, and the sub-pixel unit 16 may be a blue sub-pixel unit. The sub-pixel unit 14, the sub-pixel unit 15, and the sub-pixel unit 16 are located in another pixel unit.
Further, in fig. 2, de1, de2, and De3 may be different strobe signals. Wherein, C1 may be a first compensation capacitor in the first multiplexing unit, and C2 may be a second compensation capacitor in the first multiplexing unit; c3 may be a first compensation capacitance in the second multiplexing unit, and both C4 and C5 may be second compensation capacitances in the second multiplexing unit; c1 'may be a fourth compensation capacitance in the first multiplexing unit, and C2' may be a third compensation capacitance in the first multiplexing unit; both C3 'and C4' may be fourth compensation capacitances in the second multiplexing unit; c5' may be a third compensation capacitance in the second multiplexing unit. It should be noted that, in the present application, the switching transistors in a single multiplexing unit may be sequentially ordered from left to right. For example, in the second multiplexing unit, T4 may be a 1 st switching transistor, T5 may be a 2 nd switching transistor, and T6 may be a 3 rd switching transistor.
Further, the first port of each switching transistor is a gate of the switching transistor, the second port of each switching transistor is a source of the switching transistor, the third port of each switching transistor is a drain of the switching transistor, or the first port of each switching transistor is a gate of the switching transistor, the second port of each switching transistor is a drain of the switching transistor, and the third port of each switching transistor is a source of the switching transistor.
Note that, in the embodiments of the present application, the transistors, for example, the switching transistor and the thin film transistor, may be N-type or P-type, and the types of the transistors are not limited in this application. Hereinafter, the embodiment of the present application will be mainly described by taking N-type as an example.
Specifically, in the time division multiplexing unit in the embodiment of the present application, the driving signal input into the time division multiplexing unit may be represented by 1: n, the data on the data line is written into the corresponding sub-pixel unit by time-sharing transmission to the corresponding data line in the sub-pixel unit, so that each sub-pixel unit emits light, and the display of the display picture is realized. Wherein N is a natural number greater than or equal to 2.
Wherein, the time division multiplexing unit may be provided with a plurality of. And each time division multiplexing unit controls a preset number of sub-pixel units to emit light. It is understood that the present application is not limited to the structure between the respective time division multiplexing units.
Further, each time-division multiplexing unit includes a first multiplexing unit and a second multiplexing unit, where the first multiplexing unit and the second multiplexing unit are electrically connected to the pixel unit array, and the number of gate lines and the number of switching transistors in the first multiplexing unit and the second multiplexing unit are both N, where N is a natural number greater than or equal to 2, and the number of compensation capacitors of the first multiplexing unit is different from the number of compensation capacitors of the second multiplexing unit. For example, among the plurality of time-division multiplexing units, the number of gate lines and the number of switching transistors of one of the time-division multiplexing units may be 6, and 2 multiplexing units may be total. At this time, the number of compensation capacitors of the first multiplexing unit may be 2, and the number of compensation capacitors of the second multiplexing unit may be 3.
Further, the number of the compensation capacitors of the first multiplexing unit is N-1, the N-1 compensation capacitors comprise a first compensation capacitor and N-2 second compensation capacitors, one end of the first compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the 1 st switching transistor in the first multiplexing unit; one end of the N-2 second compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the first multiplexing unit, and the other end of the N-2 second compensation capacitor is electrically connected with the third port of the N-1 st switching transistor in the first multiplexing unit. Taking the switching transistors as N-type examples, there may be 1 first compensation capacitor and N-2 second compensation capacitors. One end of the first compensation capacitor can be electrically connected with the grid electrode of the corresponding switching transistor, and the other end of the first compensation capacitor can be electrically connected with the drain electrode of the corresponding switching transistor. It can be appreciated that in practical applications, the number of the first compensation capacitor and the second compensation capacitor can be set as required, and the number of the first compensation capacitor and the second compensation capacitor is not limited in this application.
Further, the number of the compensation capacitors of the second multiplexing unit is N, the N compensation capacitors include a first compensation capacitor and N-1 second compensation capacitors, one end of the first compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the 1 st switching transistor in the second multiplexing unit; one end of the N-1 second compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the second multiplexing unit, and the other end of the N-1 second compensation capacitor is electrically connected with the third port of the N switching transistor in the second multiplexing unit. For example, in fig. 2, C3 may be a first compensation capacitance, C4 may be a 1 st second compensation capacitance, and C5 may be a 2 nd second compensation capacitance.
Further, the capacitance value of any one of the first compensation capacitors in the first multiplexing unit is different from the capacitance value of the first compensation capacitor in the second multiplexing unit, and the capacitance value of any one of the second compensation capacitors in the first multiplexing unit is different from the capacitance value of the second compensation capacitor in the second multiplexing unit. The capacitance value of the first compensation capacitor and the capacitance value of the second compensation capacitor can also be calculated in other modes, and can be adjusted according to actual needs, which is not limited in the application.
Fig. 3 shows a schematic diagram of a time division multiplexing unit according to an embodiment of the present application.
As shown in fig. 3, one time division multiplexing unit of the embodiment of the present application may include 6 switching transistors, and the first multiplexing unit and the second multiplexing unit may include 3 switching transistors, respectively. For example, the first multiplexing unit includes a first switching transistor T1, a second switching transistor T2, and a switching transistor T3. Wherein, the grid electrode of the first switch transistor is electrically connected with the first gating line De1, and the drain electrode of the first switch transistor is electrically connected with the first data line DL 1; the grid electrode of the second switching transistor is electrically connected with the second gating line De2, and the drain electrode of the second switching transistor is electrically connected with the second data line DL 5; the gate of the third switching transistor is electrically connected to the third gate line De3, and the drain of the third switching transistor is electrically connected to the third data line DL 3. The source of the first switching transistor, the source of the second switching transistor and the source of the third switching transistor are electrically connected to the driving Signal 1.
Referring to fig. 3, C1 may be a first compensation capacitance in the first multiplexing unit, and C2 may be a second compensation capacitance in the first multiplexing unit; c3 may be the first compensation capacitance in the second multiplexing unit and both C4 and C5 may be the second compensation capacitance in the second multiplexing unit.
For example, the capacitance of the compensation capacitor may be set as follows:
C1＝Cp31+Cp32+2*Cp0；
C2＝Cp31+Cp32-Cp21-Cp0；
C3＝Cp64+Cp65；
C4＝Cp64+Cp65-Cp54-Cp0；
C5＝2*Cp0；
wherein Cp0 is a coupling capacitance between the drain of the 3 rd switching transistor T3 in the first multiplexing unit and the drain of the 2 nd switching transistor T2 in the first multiplexing unit; cp21 is the coupling capacitance between the drain of the 2 nd switching transistor T2 in the first multiplexing unit and the gate of the 1 st switching transistor T1 in the first multiplexing unit; cp31 is the coupling capacitance between the drain of the 3 rd switching transistor T3 in the first multiplexing unit and the gate of the 1 st switching transistor T1 in the first multiplexing unit; cp32 is the coupling capacitance between the drain of the 3 rd switching transistor T3 in the first multiplexing unit and the gate of the 2 nd switching transistor T2 in the first multiplexing unit.
Further, cp54 is a coupling capacitance between the drain of the 2 nd switching transistor T5 in the second multiplexing unit and the gate of the 1 st switching transistor T4 in the second multiplexing unit; cp64 is the coupling capacitance between the drain of the 3 rd switching transistor T6 in the second multiplexing unit and the gate of the 1 st switching transistor T4 in the second multiplexing unit; cp65 is the coupling capacitance between the drain of the 3 rd switching transistor T6 in the second multiplexing unit and the gate of the 2 nd switching transistor T5 in the second multiplexing unit.
Fig. 4 shows a schematic diagram of a time division multiplexing unit according to an embodiment of the present application.
As shown in fig. 4, one time division multiplexing unit of the embodiment of the present application may include 6 switching transistors, and the first multiplexing unit and the second multiplexing unit may include 3 switching transistors, respectively. For example, the first multiplexing unit includes a first switching transistor T1, a second switching transistor T2, and a switching transistor T3. Wherein, the grid electrode of the first switch transistor is electrically connected with the first gating line De1, and the drain electrode of the first switch transistor is electrically connected with the first data line DL 1; the grid electrode of the second switching transistor is electrically connected with the second gating line De2, and the drain electrode of the second switching transistor is electrically connected with the second data line DL 5; the gate of the third switching transistor is electrically connected to the third gate line De3, and the drain of the third switching transistor is electrically connected to the third data line DL 3. The source of the first switching transistor, the source of the second switching transistor and the source of the third switching transistor are electrically connected to the driving Signal 1.
Referring to fig. 4, C1 'may be a fourth compensation capacitance in the first multiplexing unit, and C2' may be a third compensation capacitance in the first multiplexing unit; c3 'may be the 1 st fourth compensation capacitance in the second multiplexing unit and C4' may be the 2 nd fourth compensation capacitance in the second multiplexing unit; c5' may be a third compensation capacitance in the second multiplexing unit.
For example, the capacitance of the compensation capacitor may be set as follows:
C1’＝Cp21+3*Cp0；
C2’＝Cp31+Cp32+2*Cp0；
C3’＝2*Cp0；
C4’＝Cp54+3*Cp0；
C5’＝Cp64+Cp65；
wherein Cp0 is a coupling capacitance between the drain of the 3 rd switching transistor T3 in the first multiplexing unit and the drain of the 2 nd switching transistor T2 in the first multiplexing unit; cp21 is the coupling capacitance between the drain of the 2 nd switching transistor T2 in the first multiplexing unit and the gate of the 1 st switching transistor T1 in the first multiplexing unit; cp31 is the coupling capacitance between the drain of the 3 rd switching transistor T3 in the first multiplexing unit and the gate of the 1 st switching transistor T1 in the first multiplexing unit; cp32 is the coupling capacitance between the drain of the 3 rd switching transistor T3 in the first multiplexing unit and the gate of the 2 nd switching transistor T2 in the first multiplexing unit.
Further, cp54 is a coupling capacitance between the drain of the 2 nd switching transistor T5 in the second multiplexing unit and the gate of the 1 st switching transistor T4 in the second multiplexing unit; cp64 is the coupling capacitance between the drain of the 3 rd switching transistor T6 in the second multiplexing unit and the gate of the 1 st switching transistor T4 in the second multiplexing unit; cp65 is the coupling capacitance between the drain of the 3 rd switching transistor T6 in the second multiplexing unit and the gate of the 2 nd switching transistor T5 in the second multiplexing unit.
It should be noted that, in the embodiment of the present application, the embodiment of fig. 3 and the embodiment of fig. 4 may be replaced with each other, or the embodiment of fig. 3 and the embodiment of fig. 4 may be used in combination with each other. Further, the setting of the capacitance values of the compensation capacitances described above is exemplary, and the capacitance values of the respective compensation capacitances may be set as needed in practical applications.
In one example, referring to fig. 3, signal1 Signal entering DL5 is pulled high by Signal compensation at C1 and C2, thereby canceling data Signal degradation caused by Cp0, cp21, cp31, and Cp32 coupling to DL1, DL3, and DL 5; signal2 signals entering DL2 are pulled high by Signal compensation at C3, C4, and C5, thereby canceling the data Signal degradation caused by coupling of Cp54, cp64, and Cp65 to DL2, DL4, and DL6. The magnitude of the compensation capacitor is equal to that of the coupling capacitor by setting different newly added compensation capacitors, so that the level of the compensation signal pulled up is the same as that of the coupling capacitor pulled down, and the compensation signal and the coupling capacitor are offset.
It should be noted that, for fig. 3, the first compensation capacitor and the second compensation capacitor are disposed at a side between the data line and the gate line where the cross line is less (i.e., a side far from the driving signal); for fig. 4, the third compensation capacitor and the fourth compensation capacitor are disposed on the more cross-line side (i.e., the side closer to the driving signal) between the data line and the gate line. Through setting up first compensation electric capacity and second compensation electric capacity in the one side of keeping away from drive signal or setting up third compensation electric capacity and fourth compensation electric capacity in the one side of being close to drive signal, this embodiment of the application can compensate the data signal on each data line of multiplexing unit output of dividing time, guarantees the uniformity of data signal on each data line, and then avoid the data signal on each data line appears the difference, eliminates the phenomenon that the display picture shows unevenly.
Further, the display panel further comprises a driving unit, and the plurality of time-sharing multiplexing units are respectively and electrically connected with the driving unit and are used for receiving driving signals output by the driving unit. For example, the driving signal may be generated using a source driver in the display panel. It is understood that the present application is not limited as to how the drive signal is generated.
Further, the sub-pixel unit array includes a plurality of sub-pixel units arranged in rows and columns, and each sub-pixel unit is provided with a thin film transistor, where the drain electrode of the thin film transistor in each sub-pixel unit is electrically connected to the data line corresponding to the sub-pixel unit. It is understood that the specific structure of the sub-pixel unit array is not limited in this application.
In addition, the application also provides a display terminal, which comprises a terminal main body and the display panel, wherein the terminal main body is connected with the display panel.
In summary, in the multiple switching transistors of the time division multiplexing unit having the data lines intersecting each other, a portion of the multiple switching transistors have multiple first compensation capacitors disposed between the first port of the switching transistor and the third port of the switching transistor, one or more second compensation capacitors disposed between the first port of the switching transistor corresponding to at least one first compensation capacitor and the third port of the other switching transistor, or a portion of the multiple third compensation capacitors disposed between the first port of the switching transistor and the second port of the switching transistor, and one or more fourth compensation capacitors disposed between the first port of the switching transistor corresponding to at least one third compensation capacitor and the second port of the other switching transistor.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The display panel and the display terminal provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and embodiments of the present application, and the description of the above embodiments is only used to help understand the technical solution and core ideas of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. The display panel is characterized by comprising a pixel unit array and a plurality of time division multiplexing units, wherein each time division multiplexing unit is respectively and electrically connected with the pixel unit array, each pixel unit in the pixel unit array comprises one or a plurality of sub-pixel units, each time division multiplexing unit comprises a plurality of gating lines and a plurality of switching transistors,
the first ports of the switching transistors are respectively and electrically connected with a gating line, and the second ports of the switching transistors are respectively and electrically connected with corresponding driving signals; the third ports of the at least two switching transistors are respectively and electrically connected to the sub-pixel units in different pixel units to form the intersection of the data lines corresponding to the at least two switching transistors;
among the plurality of switch transistors, a plurality of first compensation capacitors are arranged between a first port of a part of the switch transistors and a third port of the switch transistor, wherein one or a plurality of second compensation capacitors are arranged between a first port of a switch transistor corresponding to at least one first compensation capacitor and the third port of other switch transistors;
or, a plurality of third compensation capacitors are arranged between the first ports of some of the switch transistors and the second ports of the switch transistors, wherein one or a plurality of fourth compensation capacitors are arranged between the first ports of the switch transistors corresponding to at least one third compensation capacitor and the second ports of other switch transistors, so as to perform mixed compensation on the data signals on each data line output by the time division multiplexing unit.
2. The display panel of claim 1, wherein the first port of each of the switching transistors is a gate of the switching transistor, the second port of each of the switching transistors is a source of the switching transistor, the third port of each of the switching transistors is a drain of the switching transistor,
or, the first port of each switch transistor is the gate of the switch transistor, the second port of each switch transistor is the drain of the switch transistor, and the third port of each switch transistor is the source of the switch transistor.
3. The display panel of claim 2, wherein each of the time division multiplexing units includes a first multiplexing unit and a second multiplexing unit, the first multiplexing unit and the second multiplexing unit being electrically connected to the pixel cell array, respectively, wherein,
the number of the gate lines and the number of the switching transistors in the first multiplexing unit and the second multiplexing unit are N, wherein N is a natural number greater than or equal to 2, and the number of the compensation capacitors of the first multiplexing unit is different from the number of the compensation capacitors of the second multiplexing unit.
4. The display panel of claim 3, wherein the number of compensation capacitors of the first multiplexing unit is N-1, the N-1 compensation capacitors include a first compensation capacitor and N-2 second compensation capacitors, wherein,
one end of the first compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the 1 st switching transistor in the first multiplexing unit;
one end of the N-2 second compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the first multiplexing unit, and the other end of the N-2 second compensation capacitor is electrically connected with the third port of the N-1 st switching transistor in the first multiplexing unit.
5. The display panel of claim 3, wherein the number of compensation capacitors of the second multiplexing unit is N, the N compensation capacitors including a first compensation capacitor and N-1 second compensation capacitors, wherein,
one end of the first compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the 1 st switching transistor in the second multiplexing unit;
one end of the N-1 second compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the second multiplexing unit, and the other end of the N-1 second compensation capacitor is electrically connected with the third port of the N switching transistor in the second multiplexing unit.
6. The display panel according to claim 4 or 5, wherein a capacitance value of any one of the first compensation capacitors in the first multiplexing unit is different from a capacitance value of the first compensation capacitor in the second multiplexing unit, and a capacitance value of any one of the second compensation capacitors in the first multiplexing unit is different from a capacitance value of the second compensation capacitor in the second multiplexing unit.
7. The display panel of claim 3, wherein the number of compensation capacitors of the first multiplexing unit is N-1, the N-1 compensation capacitors include a third compensation capacitor and N-2 fourth compensation capacitors, wherein,
one end of the third compensation capacitor is electrically connected with the first port of the N-th switching transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the N-th switching transistor in the first multiplexing unit;
one end of the N-2 fourth compensation capacitor is electrically connected with the first port of the N-1 switching transistor in the first multiplexing unit, and the other end of the N-2 fourth compensation capacitor is electrically connected with the third port of the N-1 switching transistor in the first multiplexing unit.
8. The display panel of claim 3, wherein the number of compensation capacitors of the second multiplexing unit is N, the N compensation capacitors including a third compensation capacitor and N-1 fourth compensation capacitors, wherein,
one end of the third compensation capacitor is electrically connected with the first port of the Nth switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the Nth switching transistor in the second multiplexing unit;
one end of the N-1 fourth compensation capacitor is electrically connected with the first port of the N-1 switching transistor in the second multiplexing unit, and the other end of the N-1 fourth compensation capacitor is electrically connected with the third port of the N-1 switching transistor in the second multiplexing unit.
9. The display panel according to claim 7 or 8, wherein a capacitance value of any one of the third compensation capacitors in the first multiplexing unit is different from a capacitance value of the third compensation capacitor in the second multiplexing unit, and a capacitance value of any one of the fourth compensation capacitors in the first multiplexing unit is different from a capacitance value of the fourth compensation capacitor in the second multiplexing unit.
10. A display terminal comprising a terminal body and the display panel according to any one of claims 1 to 9, the terminal body being connected to the display panel.
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