CN110930889B - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- CN110930889B CN110930889B CN201911377223.9A CN201911377223A CN110930889B CN 110930889 B CN110930889 B CN 110930889B CN 201911377223 A CN201911377223 A CN 201911377223A CN 110930889 B CN110930889 B CN 110930889B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The embodiment of the application provides a display panel, a driving method thereof and a display device. The display panel is provided with a display area and a non-display area, the display area comprises a plurality of pixel columns arranged along a first direction, in the same pixel column, a plurality of first sub-pixels and a plurality of second sub-pixels are alternately arranged along a second direction, and a plurality of third sub-pixels are arranged along the second direction; the first sub-pixels positioned in the same pixel column are electrically connected with the same first data line, and the second sub-pixels positioned in the same pixel column are electrically connected with the same second data line; the non-display area comprises a plurality of first multi-path distribution circuits, and each first multi-path distribution circuit comprises a first signal input end, a first signal output end and a second signal output end; the first multi-path distribution circuits are arranged in one-to-one correspondence with the pixel columns, the first signal output ends are electrically connected with the first data lines, and the second signal output ends are electrically connected with the second data lines. Is beneficial to improving the image retention phenomenon and improving the display quality.
Description
[ technical field ] A
The present disclosure relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.
[ background ] A method for producing a semiconductor device
As the quality requirements of users for display devices are continuously increased, the existing display devices are moving toward high PPI and high frequency driving. PPIs of terminal display devices such as mobile phones, televisions, in-vehicle displays, etc. are increasing.
Referring to fig. 1, the display panel includes a pixel 01, and the pixel 01 includes a sub-pixel 011, a sub-pixel 012, and a sub-pixel 013. The sub-pixel 011 is electrically connected to the data line 021, the sub-pixel 012 is electrically connected to the data line 022, and the sub-pixel 013 is electrically connected to the data line 023. For a high-resolution display panel, the prior art uses a highpin mode for driving, that is, the number of pin pins electrically connected to data lines in the display panel is large, each data line is directly electrically connected to the pin, the pin is used for binding the chip 03 (or electrically connected to the chip by binding the FPC), and data signals of the chip 03 are transmitted to corresponding sub-pixels through the data lines.
For example, for a display panel with a resolution of 1920 x 1080 and a high frequency of 120HZ driving, the pixel scan time per row is 1/120/1920 ≈ 4us at maximum. Since the scan lines require a certain charging time (commonly referred to as a delay time) to reach a predetermined voltage, the effective turn-on time of each row of scan lines is about 2us except for the delay time. The scanning line open time is short, and the data signal that needs the higher voltage charges sub-pixel, and data signal voltage is too high, can bring serious image residual phenomenon, and display effect is not good enough, has reduced display panel's quality, has reduced user experience.
[ application contents ]
In view of the above, the present application provides a display panel, a driving method thereof and a display device to solve the technical problems in the background art.
In one aspect, embodiments of the present application provide a display panel having a display area and a non-display area, the display area including a plurality of pixel columns arranged along a first direction, a plurality of gate lines extending along the first direction, and a plurality of data lines extending along a second direction; the first direction and the second direction intersect; the pixel column comprises a plurality of pixels arranged along a second direction, and the pixels comprise first sub-pixels, second sub-pixels and third sub-pixels which are different in color; in the first part of pixel columns, a plurality of first sub-pixels and a plurality of second sub-pixels are alternately arranged along the second direction in the same pixel column, and in the second part of pixel columns, a plurality of third sub-pixels are arranged along the second direction in the same pixel column; the first sub-pixel is electrically connected with the first gate line, and the second sub-pixel is electrically connected with the second gate line; the first sub-pixels positioned in the same pixel column are electrically connected with the same first data line, and the second sub-pixels positioned in the same pixel column are electrically connected with the same second data line; the non-display area comprises a plurality of first multi-path distribution circuits, and each first multi-path distribution circuit comprises a first signal input end, a first signal output end and a second signal output end; the first multi-path distribution circuits are arranged in one-to-one correspondence with the pixel columns, the first signal output ends are electrically connected with the first data lines, and the second signal output ends are electrically connected with the second data lines.
On the other hand, an embodiment of the present application provides a driving method of a display panel, which is used for driving the display panel provided by the present application, at a first time, a first signal input terminal is turned on to a first signal output terminal, and a first signal input terminal is turned off to a second signal output terminal; a conducting signal is in the first gate line, and a stopping signal is in the second gate line; a first data signal of a first signal input end is written into the first sub-pixel through a first data line; at the second moment, the first signal input end is cut off from the first signal output end, and the first signal input end is conducted from the second signal output end; a conducting signal is in the first gate line, and a conducting signal is in the second gate line; the first data line maintains the first data signal at the previous moment and continuously writes the first data signal into the first sub-pixel; a second data signal of the first signal input end is written into the second sub-pixel through a second data line; at the third moment, the first signal input end is conducted to the first signal output end, and the first signal input end is cut off to the second signal output end; the first grid line is a cut-off signal, and the second grid line is a conducting signal; the second data line maintains the second data signal of the previous moment and continues to write into the second sub-pixel.
In another aspect, an embodiment of the present application provides another driving method for a display panel, for driving the display panel provided in the present application, at a first time, a second signal input terminal to a third signal output terminal are turned on, and a second signal input terminal to a fourth signal output terminal are turned off; the third gate line is a conducting signal, and the fourth gate line is a stopping signal; a third data signal of the second signal input end is written into the odd-numbered third sub-pixels through a third data line; at the second moment, the second signal input end is connected with the third signal output end, and the second signal input end is connected with the fourth signal output end; a conducting signal is in the third gate line, and a conducting signal is in the fourth gate line; the third data line maintains the third data signal at the previous moment and continuously writes the odd-numbered third sub-pixels; a fourth data signal of the second signal input end is written into an even third sub-pixel through a fourth data line; at a third moment, the second signal input end is connected with the third signal output end, and the second signal input end is connected with the fourth signal output end; the third gate line is a cut-off signal, and the fourth gate line is a conducting signal; the fourth data line maintains the fourth data signal at the previous moment and continuously writes the even third sub-pixels.
In another aspect, an embodiment of the present application further provides a display device, including the display panel provided in the embodiment of the present application.
In the display panel, the driving method thereof and the display device provided by the embodiment of the application, the display area includes a plurality of pixel columns arranged along a first direction, the pixel columns include a plurality of pixels arranged along a second direction, and the pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel which are different in color. The first sub-pixel and the second sub-pixel are electrically connected with different gate lines and different data lines, respectively, so that the first sub-pixel and the second sub-pixel can be controlled to emit light independently. In the VT test stage, the first subpixel and the second subpixel can be respectively lit, so that the display panel displays a picture with a corresponding color, and the aging picture and the aging time can be independently set, thereby improving the display quality and the display life of the display panel.
In addition, since the first multiplexing circuit is provided in the non-display area, the first data line and the second data line are electrically connected to the chip through one first signal input terminal to receive the data signal, so that the number of pin pins can be reduced.
Also, since the first multiplexing circuits are provided to control when the electrical signal of the first signal input terminal is transmitted to the first data line and the second data line, respectively, it is possible to supply a scan signal to the second gate line to charge the first subpixel in advance while the first data line is charged, and to control the electrical signal of the first signal input terminal to be transmitted to the second data line. That is, the first gate line and the second gate line may simultaneously receive the scan signal at a portion of time, thereby increasing the charging time of the gate lines and correspondingly increasing the effective turn-on time of the gate lines. When the first data line is charged to the first sub-pixel, the second gate line is charged to the predetermined scan signal voltage in advance, and the electrical signal of the first signal input terminal is controlled to be transmitted to the second data line to charge the second sub-pixel. Compared with the prior art, the sub-pixels can be charged without using a data signal with higher voltage, so that the image residual phenomenon is improved or avoided, the display quality of the display panel is improved, and the use experience of a user is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel provided in the prior art;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another display panel provided in the embodiment of the present application;
FIG. 4 is a schematic structural diagram of another display panel provided in the embodiment of the present application;
FIG. 5 is a schematic diagram of a display panel according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a display panel according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a pixel provided in an embodiment of the present application;
fig. 8 is a schematic structural diagram of another pixel provided in the embodiment of the present application;
fig. 9 is a timing diagram illustrating a driving method of a display panel according to an embodiment of the present disclosure;
fig. 10 is a timing diagram illustrating another driving method of a display panel according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
[ detailed description ] A
In order to better understand the technical solution of the present application, the following detailed description is made with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "approximately", "substantially" and the like in the claims and the examples are intended to be inclusive and mean that the term "substantially" may be interpreted as an alternative to an exact value within a reasonable process operating range or tolerance.
It should be understood that although the terms first, second, third, etc. may be used to describe the display regions in the embodiments of the present application, the display regions should not be limited to these terms. These terms are used only to distinguish the display regions from each other. For example, the first display region may also be referred to as a second display region, and similarly, the second display region may also be referred to as a first display region without departing from the scope of embodiments of the present application.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
The present embodiment provides a display panel having a display area AA and a non-display area NA, the display area AA including a plurality of pixel columns PX arranged in a first direction X, a plurality of gate lines GL extending in the first direction X, and a plurality of data lines DL extending in a second direction Y; the first direction X and the second direction Y intersect;
the pixel column PX includes a plurality of pixels P arranged in the second direction Y, the pixels P including first, second, and third sub-pixels SP1, SP2, and SP3, which are different in color; in the first partial pixel column PX, in the same pixel column PX, the plurality of first sub-pixels SP1 and the plurality of second sub-pixels SP2 are alternately arranged in the second direction Y, and in the second partial pixel column PX, in the same pixel column PX, the plurality of third sub-pixels SP3 are arranged in the second direction Y;
the first subpixel SP1 is electrically connected to the first gate line GL1, and the second subpixel SP2 is electrically connected to the second gate line GL 2; the first sub-pixels SP1 located in the same pixel column PX are electrically connected to the same first data line DL1, and the second sub-pixels SP2 located in the same pixel column PX are electrically connected to the same second data line DL 2;
the non-display area NA includes a plurality of first demultiplexing circuits DE1, the first demultiplexing circuit DE1 including a first signal input terminal IN1, a first signal output terminal O1 and a second signal output terminal O2;
the first multiplexing circuits DE1 are provided in one-to-one correspondence with the pixel columns PX, the first signal output terminal O1 is electrically connected to the first data line DL1, and the second signal output terminal O2 is electrically connected to the second data line DL 2.
In the display panel provided in this embodiment, the display area AA has a function of displaying image information. The non-display area NA does not have a display function, and is generally used for disposing signal traces and electronic components.
The display area AA includes a plurality of pixel columns PX repeatedly arranged in the first direction X. The pixel columns PX extend in the second direction Y. Wherein, in some alternative embodiments, the first direction X and the second direction Y are perpendicular or substantially perpendicular. It is to be understood that the number of pixel columns PX in fig. 1, and the number of pixels P included in each pixel column PX should not limit the present application.
In practical implementation, the number of pixel columns PX and the number of pixels P included in each pixel column PX may be set according to practical situations, and when the size of the display panel is fixed, the greater the number of pixels P, the higher the resolution of the display panel, and the finer the displayed image generally.
The pixel P includes three sub-pixels of different colors, i.e., a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP 3. The three sub-pixels with different colors can be mixed to display a plurality of different colors. The more colors that can be displayed after the color mixing of the three sub-pixels in the pixel P, the richer the colors of the image displayed by the display panel and the higher the quality of the picture.
The same pixel column PX includes a first portion and a second portion, both of which are elongated portions extending in the second direction Y, and are arranged in the first direction X. For the same pixel column PX, the plurality of first sub-pixels SP1 and the plurality of second sub-pixels SP2 are alternately arranged in the second direction Y to form the first section, and the plurality of third sub-pixels SP3 are arranged in the second direction Y to form the second section.
Alternatively, for the same pixel column PX, the plurality of first sub-pixels SP1 and the plurality of second sub-pixels SP2 are alternately arranged in the second direction Y as one sub-pixel column PX1, and the plurality of third sub-pixels SP3 are arranged in the second direction Y as another sub-pixel column PX 2. A sub-pixel column PX1 composed of the first sub-pixel SP and the plurality of second sub-pixels SP and a sub-pixel column PX2 composed of the plurality of third sub-pixels SP are alternately arranged in the first direction X.
In the display panel provided in the present embodiment, the first sub-pixel SP1 and the second sub-pixel SP2 are electrically connected to different gate lines and different data lines, respectively. Specifically, the first sub-pixels SP1 located in the same pixel column PX are electrically connected to the same first data line DL1, and the second sub-pixels SP2 located in the same pixel column PX are electrically connected to the same second data line DL 2. It should be noted that, in the display panel illustrated in fig. 2, the arrangement positions of the gate lines and the data lines are only exemplary and should not be construed as a specific limitation to the embodiments of the present application.
Since the first and second sub-pixels SP1 and SP2 are electrically connected to different gate lines and different data lines, respectively, the first and second sub-pixels SP1 and SP2 can be controlled to emit light individually. In the VT testing stage, the first sub-pixel SP1 and the second sub-pixel SP2 can be respectively turned on to make the display panel display the pictures with the corresponding colors, and the aging picture and the aging time can be set independently, thereby improving the display quality and the display life of the display panel.
IN the display panel provided by this embodiment, a plurality of first demultiplexing circuits DE1 are disposed IN the non-display area NA, and the first demultiplexing circuits DE1 can time-share the electrical signal of the first signal input terminal IN1 and output the electrical signal from the first signal output terminal O1 and the second signal output terminal O2, respectively.
The number of the first demultiplexing circuits DE1 and the pixel columns PX is the same, and one first demultiplexing circuit DE1 is provided for each pixel column PX. For one pixel column PX and the first demultiplexing circuit DE1 circuit provided in correspondence thereto, the first signal output terminal O1 and the first data line DL1 of the first demultiplexing circuit DE1 are electrically connected, and the second signal output terminal O2 and the second data line DL2 are electrically connected. The electrical signal of the first signal input terminal IN1 may be transmitted to the first data line DL1 and the second data line DL2, respectively, at different periods of time.
IN the display panel provided by this embodiment, since the first demultiplexer DE1 is provided, the first data line DL1 and the second data line DL2 are electrically connected to a chip (not shown) through a first signal input terminal IN1 to receive data signals, so that the number of pin pins can be reduced. Also, since the first multiplexing circuit DE1 is provided, it is possible to control when the electric signal of the first signal input terminal IN1 is transmitted to the first data line DL1 and the second data line DL2, respectively, and thus, it is possible to supply a scan signal to the second gate line GL2 IN advance to charge the first subpixel SP1 while the first data line DL1 charges the same, and to control the electric signal of the first signal input terminal IN1 to be transmitted to the second data line DL 2. That is, the first gate line GL1 and the second gate line GL2 may simultaneously receive the scan signal at a portion of the time, thereby increasing the charging time of the gate lines and correspondingly increasing the effective on-time of the gate lines. After the first data line DL1 is charged to the first subpixel SP1, since the second gate line GL2 is charged to the preset scan signal voltage IN advance, the electric signal of the first signal input terminal IN1 can be controlled to be transmitted to the second data line DL2 to charge the second subpixel SP 2.
The display panel that this embodiment provided, owing to increase the charge time of gate line, the corresponding effectual opening time of gate line that has increased for prior art, can need not to charge to the sub-pixel with the higher data signal of voltage to improve or avoid the image to remain the phenomenon, improve display panel's display quality, promote user's use and experience.
In some alternative embodiments, one of the first and second sub-pixels SP1 and SP2 is red, the other is green, and the third sub-pixel SP is blue. On one hand, red, green and blue are three primary colors of light, and all colors can be obtained by mixing the three colors, so that the display panel has rich colors and higher display quality. On the other hand, the inventor finds that the image sticking phenomenon of the red sub-pixel and the green sub-pixel in the display panel provided by the prior art is relatively serious. In this implementation, the charging time of the gate lines corresponding to the red sub-pixel and the green sub-pixel is increased, and compared with the prior art, the charging of the red sub-pixel and the green sub-pixel can be performed without using a data signal with higher voltage, so that the image sticking phenomenon of the red sub-pixel and the green sub-pixel can be effectively improved, and the display quality is improved.
In the display panel provided in the embodiments of the present application, there may be various electrical connection manners for the third sub-pixel SP3 and the gate line and the data line, and the following exemplary embodiments are provided to specifically describe this.
In some optional embodiments, please refer to fig. 3, wherein fig. 3 is a schematic structural diagram of another display panel provided in the embodiments of the present application.
In the present embodiment, the third sub-pixel SP3 located in the same pixel column PX is electrically connected to the same fifth data line DL 5; the third subpixel SP3 is electrically connected to the first gate line GL1 or the second gate line GL 2. In fig. 3, only the third subpixel SP3 and the second gate line GL2 are electrically connected. The fifth data line DL5 may be directly electrically connected to a chip (not shown) to receive data signals, that is, a separate pin may be provided in the display panel to be directly electrically connected to the fifth data line DL 5. When the first and second subpixels SP1 and SP2 are charged, respectively, the third subpixel SP3 is independently controlled by the fifth data line DL5, and the fifth data line DL5 directly supplies a data signal to the third subpixel SP 3. The third subpixel SP3 is electrically connected to the first gate line GL1 or the second gate line GL2, and since the charging time of the first gate line GL1 and the second gate line GL2 is increased in the embodiment of the present application, the image retention of the third subpixel SP3 is further improved, so that the display quality is further improved, and the user experience is improved. In addition, since the third sub-pixel SP3 located in the same pixel column PX is electrically connected to the same fifth data line DL5, and the fifth data line DL5 can be directly electrically connected to a chip (not shown) to receive data signals, there is no need to provide a multiplexing circuit corresponding to the third sub-pixel SP3, so that the space of the non-display area NA can be saved, which is beneficial to narrow frames of the display panel.
In some optional embodiments, please refer to fig. 4, and fig. 4 is a schematic structural diagram of another display panel provided in the embodiments of the present application.
In this embodiment, the odd-numbered third sub-pixels SP3 and the third data line DL3 located in the same pixel column PX are electrically connected, and the even-numbered third sub-pixels SP3 and the fourth data line DL4 are electrically connected; (ii) a The third subpixel SP3 is electrically connected to the first gate line GL1 or the second gate line GL 2; in fig. 4, only the third subpixel SP3 and the second gate line GL2 are electrically connected for illustration;
the non-display area NA includes a plurality of second demultiplexing circuits DE2, the second demultiplexing circuit DE2 including a second signal input terminal IN2, a third signal output terminal O3 and a fourth signal output terminal O4;
the second multiplexing circuits DE2 are provided in one-to-one correspondence with the pixel columns PX, the third signal output terminal O3 is electrically connected to the third data line DL3, and the fourth signal output terminal O4 is electrically connected to the fourth data line DL 4.
In the display panel illustrated in fig. 4, one end of the display region far from the second demultiplexing circuit DE2 is an upper end, and one end close to the second demultiplexing circuit DE2 is a lower end. The third subpixels SP3 in the same pixel column PX are arranged from top to bottom, the odd number of third subpixels SP3 are electrically connected to the third data line DL3 and the third gate line GL3, and the even number of third subpixels SP3 are electrically connected to the fourth data line DL4 and the fourth gate line GL 4. It will be appreciated by those skilled in the art that in other alternative embodiments, the odd number of third sub-pixels SP3 and the even number of third sub-pixels SP3 are defined by arranging the third sub-pixels SP3 in the same pixel column PX from bottom to top. This embodiment does not specifically limit this.
The display panel provided by the present embodiment can control when the electrical signal of the second signal input terminal IN2 is transmitted to the three data lines DL3 and the fourth data line DL4 respectively because the second demultiplexing circuit DE2 is provided. The third data line DL3 and the fourth data line DL4 are electrically connected to a chip (not shown) through a second signal input terminal IN2 to receive data signals, so that the number of pin pins can be further reduced.
In the display panel provided in the embodiment of the present application, there may be a plurality of specific circuit structures of the first demultiplexing circuit, and the present invention is described below with reference to specific circuit structures of the first demultiplexing circuit.
In some optional embodiments, please refer to fig. 5, and fig. 5 is a schematic structural diagram of another display panel provided in the embodiments of the present application.
In this embodiment, the first demultiplexing circuit DE1 includes: a first switch T1 and a second switch T2, an input terminal of the first switch T1 and an input terminal of the second switch T2 each being electrically connected to the first signal input terminal IN 1;
an output terminal of the first switch T1 is electrically connected to the first signal output terminal O1, and an output terminal of the second switch T2 is electrically connected to the second signal output terminal O2. Optionally, the first demultiplexing circuit DE1 includes: a first control signal line CK1, a second control signal line CK 2; the first control signal line CK1 is electrically connected to a control terminal of the first switch T1, and the second control signal line CK2 is electrically connected to a control terminal of the second switch T2. Optionally, the first switch T1 and the second switch T2 are both thin film transistors.
In this embodiment, the thin film transistors are used as the first switch T1 and the second switch T2 for controlling the distribution of signals in the first demultiplexing circuit DE1, and the circuit structure is simple and easy to implement.
Optionally, please refer to fig. 6, where fig. 6 is a schematic structural diagram of another display panel provided in the embodiment of the present application. In this embodiment, the second demultiplexing circuit DE2 includes: a third switch T3 and a fourth switch T4, an input terminal of the third switch T3 and an input terminal of the fourth switch T4 are electrically connected to the second signal input terminal IN 2;
an output terminal of the third switch T3 is electrically connected to the third signal output terminal O3, and an output terminal of the fourth switch T4 is electrically connected to the fourth signal output terminal O4. Optionally, the second multiplexing circuit DE2 multiplexes the first control signal line CK1 and the second control signal line CK 2; the first control signal line CK1 is electrically connected to a control terminal of the third switch T3, and the second control signal line CK2 is electrically connected to a control terminal of the fourth switch T4. Optionally, the third switch T3 and the fourth switch T4 are both thin film transistors. In this embodiment, the thin film transistors are used as the third switch T3 and the fourth switch T4 for controlling the distribution of signals in the second demultiplexing circuit DE2, and the circuit structure is simple and easy to implement.
It should be noted that, in the display panel provided in each embodiment of the present application, there may be a plurality of arrangement structures of the three sub-pixels of the pixel, and the present invention is described below by providing an exemplary embodiment.
In some optional embodiments, please refer to fig. 7, and fig. 7 is a schematic structural diagram of a pixel provided in the embodiments of the present application.
In the present embodiment, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 are arranged in a triangle. Specifically, the triangular arrangement may be understood as that, since the actual area of the sub-pixel is very small, the sub-pixel may be abstracted into one "point", and the connection line of three "points" of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 may form a triangle. The lengths of the first, second and third sub-pixels SP1, SP2 and SP3 in the second direction Y are substantially the same.
In some optional embodiments, please refer to fig. 8, where fig. 8 is a schematic structural diagram of another pixel provided in the embodiments of the present application.
In this embodiment, along the second direction Y, a side of the first sub-pixel SP1 away from the second sub-pixel SP2 is a first sub-edge SE1, a side of the second sub-pixel SP2 away from the first sub-pixel SP1 is a second sub-edge SE2, a distance between the first sub-edge SE1 and the second sub-edge SE2 is D1, and a length of the third sub-pixel SP3 along the second direction Y is D2, where D1 is D2. In this embodiment, the length of the third subpixel SP3 in the second direction Y is longer than or equal to the sum of the lengths of the first subpixel SP1 and the second subpixel SP2 in the second direction Y. Accordingly, the width of the third sub-pixel SP3 along the first direction X may be smaller, so that space may be saved to arrange more pixel columns, which is beneficial to improve the resolution of the display panel.
An embodiment of the present application further provides a driving method of a display panel, please refer to fig. 2 in combination, where the driving method provided in this embodiment includes:
at the first time, the first signal input terminal IN1 to the first signal output terminal O1 are turned on, and the first signal input terminal IN1 to the second signal output terminal O2 are turned off; an on signal is present in the first gate line GL1, and an off signal is present in the second gate line GL 2; the first data signal from the first signal input terminal IN1 is written into the first sub-pixel SP1 through the first data line DL1, and at this time, the first data line DL1 charges the first sub-pixel SP1 directly.
At the second time, the first signal input terminal IN1 is turned off to the first signal output terminal O1, and the first signal input terminal IN1 is turned on to the second signal output terminal O2; the first gate line GL1 is a turn-on signal, and the second gate line GL2 is a turn-on signal; the first data line DL maintains the first data signal at the previous time, and continues to write into the first subpixel SP1, at this time, the first data line DL1 charges the first subpixel SP1 in a line charge manner; when the second data signal from the first signal input terminal IN1 is written into the second sub-pixel SP2 through the second data line DL2, the second data line DL2 charges the second sub-pixel SP2 directly;
at the third time, the first signal input terminal IN1 to the first signal output terminal O1 are turned on, and the first signal input terminal IN1 to the second signal output terminal O2 are turned off; an off signal is present on the first gate line GL1, and an on signal is present on the second gate line GL 2; the second data line DL2 maintains the second data signal at the previous time, and continues to write into the second subpixel SP2, and at this time, the second data line DL2 charges the second subpixel SP2 in a line charge manner.
Next, in this embodiment, the display panel shown in fig. 5 is taken as an example to exemplarily explain a driving method, please refer to fig. 5 and fig. 9 in combination, and fig. 9 is a timing chart of the driving method of the display panel provided in the embodiment of the present application.
At a first time F1, the first control signal line CK1 is a low voltage signal, and the second control signal line CK2 is a high voltage signal; a low voltage signal is present in the first gate line GL1, and a high voltage signal is present in the second gate line GL 2; the first data signal from the first signal input terminal IN1 is written into the first subpixel SP1 through the first data line DL1, and at this time, the first data line DL1 charges the first subpixel SP1 directly.
At a second time F2, the first control signal line CK1 is a high voltage signal, and the second control signal line CK2 is a low voltage signal; a low voltage signal is present on the first gate line GL1 and on the second gate line GL 2; the first data line DL maintains the first data signal at the previous time, and continues to write into the first subpixel SP1, at this time, the first data line DL1 charges the first subpixel SP1 in a line charge manner; when the second data signal from the first signal input terminal IN1 is written into the second sub-pixel SP2 through the second data line DL2, the second data line DL2 charges the second sub-pixel SP2 directly;
at a third time F3, the first control signal line CK1 is a low voltage signal, and the second control signal line CK2 is a high voltage signal; a high voltage signal is present on the first gate line GL1, and a low voltage signal is present on the second gate line GL 2; the second data line DL2 maintains the second data signal at the previous time, and continues to write into the second subpixel SP2, and at this time, the second data line DL2 charges the second subpixel SP2 in a line charging manner.
In this embodiment, the on signal of the gate line is a low voltage signal, and the off signal is a high voltage signal, and the on signal of the control signal line is a low voltage signal, and the off signal is a high voltage signal. It is understood that in other alternative embodiments, the on signal of the gate line may be a high voltage signal, the off signal may be a low voltage signal, and the electrical signal of the control signal line may be the same.
In the display panel shown in fig. 2 or 5, the third data line DL3 may be directly electrically connected to a chip in the display device, and the chip may directly transmit data signals without a demultiplexer circuit.
The driving method provided by the embodiment can effectively increase the charging time of the gate line, and correspondingly increase the effective opening time of the gate line. Specifically, at the second timing, the first data line DL1 charges the first subpixel SP1 while the scan signal is supplied to the second gate line GL2 IN advance to charge it, and the electric signal controlling the first signal input terminal IN1 is transmitted to the second data line DL 2. That is, the first gate line GL1 and the second gate line GL2 can simultaneously receive the scan signal at the second time T2, so as to increase the charging time of the gate lines, and accordingly increase the effective turn-on time of the gate lines. After the first data line DL1 is charged to the first subpixel SP1, since the second gate line GL2 is charged to the preset scan signal voltage IN advance, the electric signal of the first signal input terminal IN1 can be controlled to be transmitted to the second data line DL2 to charge the second subpixel SP 2.
Taking a display panel with a resolution of 1920 × 1080 and a high-frequency 120HZ driving as an example, the charging time of each row of gate lines is (1/120/1920) × 2 (2/3) ≈ 5.3 us. Compared with the prior art, the charging time of the gate line is effectively increased.
The display panel that this embodiment provided, owing to increase the charge time of gate line, the corresponding effectual opening time of gate line that has increased for prior art, can need not to charge with the higher data signal of voltage to sub-pixel to improve or avoid the image to remain the phenomenon, improve display panel's display quality, promote user's use and experience.
An embodiment of the present application further provides another driving method of a display panel, please refer to fig. 4, where the driving method provided in this embodiment includes:
at the first time, the second signal input terminal IN2 to the third signal output terminal O3 are turned off, and the second signal input terminal IN2 to the fourth signal output terminal O4 are turned on; the gate lines electrically connected to the odd-numbered third sub-pixels SP3 are on signals, and the gate lines electrically connected to the even-numbered third sub-pixels SP3 are off signals; the third data signal of the second signal input terminal IN2 is written IN the odd-numbered third sub-pixels SP3 through the third data line GL 3;
at the second time, the second signal input terminal IN2 to the third signal output terminal O3 are turned on, and the second signal input terminal IN2 to the fourth signal output terminal O4 are turned off; on signals are provided in the gate lines electrically connected to the odd-numbered third sub-pixels SP3, and off signals are provided in the gate lines electrically connected to the even-numbered third sub-pixels SP 3;
at the third time, the second signal input terminal IN2 to the third signal output terminal O3 are turned off, and the second signal input terminal IN2 to the fourth signal output terminal O4 are turned on; an off signal is provided in the gate line electrically connected to the odd-numbered third subpixel SP3, and an on signal is provided in the gate line electrically connected to the even-numbered third subpixel SP 3;
at the fourth time, the second signal input terminal IN2 to the third signal output terminal O3 are turned on, and the second signal input terminal IN2 to the fourth signal output terminal O4 are turned off; an off signal is provided in the gate line electrically connected to the odd-numbered third subpixel SP3, and an on signal is provided in the gate line electrically connected to the even-numbered third subpixel SP 3; the fourth data signal of the second signal input terminal IN2 is written into the even-numbered third sub-pixels SP3 through the fourth data line GL 4.
Next, in this embodiment, the display panel shown in fig. 6 is taken as an example to exemplarily explain a driving method, please refer to fig. 6 and fig. 10 in combination, and fig. 10 is a timing chart of another driving method of a display panel provided in this embodiment of the present application. For the sake of clarity, in fig. 10, the four data lines at the upper end of the display panel are labeled as G01, G02, G03, and G04, respectively.
At a first time F01, the first control signal line CK1 is a high voltage signal, and the second control signal line CK2 is a low voltage signal; a low voltage signal on gate line G02 and a high voltage signal on gate line G04; the third data signal of the second signal input terminal IN2 is written into the odd-numbered third sub-pixels SP3 through the third data line GL 3;
at a second time F02, the first control signal line CK1 is a low voltage signal, and the second control signal line CK2 is a high voltage signal; a low voltage signal on gate line G02 and a high voltage signal on gate line G04; at this time, the data signal in the third data line GL3 is turned off, and charging to the odd-numbered third sub-pixels SP3 is stopped;
at a third time F03, the first control signal line CK1 is a high voltage signal, and the second control signal line CK2 is a low voltage signal; a high voltage signal on gate line G02 and a low voltage signal on gate line G04; the fourth data line DL4 is turned off to prevent charging to the even-numbered third sub-pixels SP 3;
at a fourth time F04, the first control signal line CK1 is a low voltage signal, and the second control signal line CK2 is a high voltage signal; a high voltage signal on gate line G02 and a low voltage signal on gate line G04; the fourth data signal from the second signal input terminal IN2 is written to the even-numbered third sub-pixels SP3 through the fourth data line DL 4.
In the driving method provided in this embodiment, the third subpixel SP3 in the same column is charged using the second demultiplexer DE2, so that the number of pins can be further reduced. Further, the first and second demultiplexing circuits DE1 and DE2 can share the first and second control signal lines CK1 and CK2, which is advantageous in simplifying the driving signals.
In this embodiment, only the on signal of the gate line is taken as a low voltage signal, and the off signal is taken as a high voltage signal. It is understood that in other alternative embodiments, the on signal of the gate line may be a high voltage signal, and the off signal may be a low voltage signal.
An embodiment of the present application further provides a display device, as shown in fig. 11, fig. 11 is a schematic structural diagram of the display device provided in the embodiment of the present application, and the display device includes the display panel provided in any one of the embodiments. The specific structure of the display panel has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 11 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (1)
1. A driving method of a display panel for driving the display panel, characterized by:
the display panel is provided with a display area and a non-display area;
the display area comprises a plurality of pixel columns arranged along a first direction, a plurality of gate lines extending along the first direction, and a plurality of data lines extending along a second direction; the first direction and the second direction intersect;
the pixel column comprises a plurality of pixels arranged along the second direction, and the pixels comprise first sub-pixels, second sub-pixels and third sub-pixels which are different in color; in a first part of the pixel columns, a plurality of the first sub-pixels and a plurality of the second sub-pixels are alternately arranged along the second direction in the same pixel column, and in a second part of the pixel columns, a plurality of the third sub-pixels are arranged along the second direction in the same pixel column;
the first sub-pixel is electrically connected with the first gate line, and the second sub-pixel is electrically connected with the second gate line; the first sub-pixels positioned in the same pixel column are electrically connected with the same first data line, and the second sub-pixels positioned in the same pixel column are electrically connected with the same second data line;
the non-display area comprises a plurality of first multi-path distribution circuits, and each first multi-path distribution circuit comprises a first signal input end, a first signal output end and a second signal output end;
the first multi-path distribution circuits are arranged in one-to-one correspondence with the pixel columns, the first signal output ends are electrically connected with the first data lines, and the second signal output ends are electrically connected with the second data lines;
the odd-numbered third sub-pixels positioned in the same pixel column are electrically connected with the third data line, and the even-numbered third sub-pixels are electrically connected with the fourth data line; the third sub-pixel is electrically connected with the first gate line or the second gate line;
the non-display area comprises a plurality of second multi-way distribution circuits, and each second multi-way distribution circuit comprises a second signal input end, a third signal output end and a fourth signal output end;
the second multi-path distribution circuits are arranged in one-to-one correspondence with the pixel columns, the third signal output ends are electrically connected with the third data lines, and the fourth signal output ends are electrically connected with the fourth data lines;
the driving method includes: at a first moment, the second signal input end is connected to the third signal output end, and the second signal input end is connected to the fourth signal output end; the gate lines electrically connected with the odd-numbered third sub-pixels are on signals, and the gate lines electrically connected with the even-numbered third sub-pixels are off signals; a third data signal of the second signal input end is written into the odd-numbered third sub-pixels through the third data line;
at a second moment, the second signal input end is connected to the third signal output end, and the second signal input end is connected to the fourth signal output end; the gate lines electrically connected with the odd-numbered third sub-pixels are on signals, and the gate lines electrically connected with the even-numbered third sub-pixels are off signals;
at a third moment, the second signal input end is disconnected with the third signal output end, and the second signal input end is connected with the fourth signal output end; the gate lines electrically connected with the odd-numbered third sub-pixels are cut-off signals, and the gate lines electrically connected with the even-numbered third sub-pixels are conducting signals;
at a fourth moment, the second signal input end is connected to the third signal output end, and the second signal input end is connected to the fourth signal output end; an off signal is used in the gate lines electrically connected with the odd-numbered third sub-pixels, and an on signal is used in the gate lines electrically connected with the even-numbered third sub-pixels; and a fourth data signal of the second signal input end is written into the even third sub-pixels through the fourth data line.
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