CN114530133A - Display panel and display terminal - Google Patents
Display panel and display terminal Download PDFInfo
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- CN114530133A CN114530133A CN202210209455.9A CN202210209455A CN114530133A CN 114530133 A CN114530133 A CN 114530133A CN 202210209455 A CN202210209455 A CN 202210209455A CN 114530133 A CN114530133 A CN 114530133A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Abstract
The application relates to a display panel and a display terminal, wherein the display panel comprises a pixel unit array and a time-sharing multiplexing unit, the time-sharing multiplexing unit comprises a plurality of gate lines and a plurality of switching transistors, a plurality of first compensation capacitors are arranged at first ports and third ports of part of the switching transistors, and a second compensation capacitor is arranged at the first port of at least one switching transistor and the third ports of other switching transistors; or a plurality of third compensation capacitors are arranged between the first ports and the second ports of part of the switch transistors, and fourth compensation capacitors are arranged between the first port of at least one switch transistor and the second ports of other switch transistors. Through setting up a plurality of first compensation capacitance, second compensation capacitance, third compensation capacitance and fourth compensation capacitance in time sharing multiplex unit, this application can carry out hybrid compensation to the data signal on each data line, guarantees data signal's uniformity, avoids the data signal on each data line to appear the difference, eliminates the inhomogeneous phenomenon of display screen display.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display terminal.
Background
In the field of Liquid Crystal Display (LCD), in order to save cost, a mode of reducing a driving chip or a Demux (multiplex) technology is generally adopted. For example, the gate driving chips are removed from the goa (gate on array) circuit, or the number of gate driving chips or source driving chips is reduced by time-division multiplexing using Demux technology.
However, although the Demux circuit is adopted in the related art, the number of source driver chips can be reduced, the difference of data signals on corresponding data lines occurs due to different coupling capacitances existing between different transistors in the Demux circuit, so that the display image may have adverse phenomena such as vertical stripes and horizontal stripes, which affect the uniformity of the display image.
Disclosure of Invention
In view of this, the present application provides a display panel and a display terminal, which can perform hybrid compensation on data signals on each data line output by a time division multiplexing unit, so as to ensure consistency of the data signals on each data line, further avoid difference of the data signals on each data line, and eliminate non-uniform display of a display screen.
According to an aspect of the present application, there is provided a display panel, including a pixel cell array and a plurality of time-sharing multiplexing units, each of the time-sharing multiplexing units being electrically connected to the pixel cell array, each of the pixel cells in the pixel cell array including one or more sub-pixel cells, each of the time-sharing multiplexing units including a plurality of gate lines and a plurality of switching transistors, wherein a first port of each of the switching transistors is electrically connected to one of the gate lines, and a second port of each of the switching transistors is electrically connected to a corresponding driving signal; the third ports of the at least two switching transistors are respectively and electrically connected to the sub-pixel units in different pixel units to form the intersection of the data lines corresponding to the at least two switching transistors; among the plurality of switching transistors, a plurality of first compensation capacitors are arranged between the first ports of part of the switching transistors and the third ports of the switching transistors, wherein one or more second compensation capacitors are arranged between the first port of the switching transistor corresponding to at least one first compensation capacitor and the third ports of other switching transistors; or, in the plurality of switch transistors, a plurality of third compensation capacitors are arranged between the first ports of some of the switch transistors and the second ports of the switch transistors, and one or more fourth compensation capacitors are arranged between the first port of the switch transistor corresponding to at least one third compensation capacitor and the second ports of other switch transistors.
Further, the first port of each switch transistor is a gate of the switch transistor, the second port of each switch transistor is a source of the switch transistor, and the third port of each switch transistor is a drain of the switch transistor, or the first port of each switch transistor is a gate of the switch transistor, the second port of each switch transistor is a drain of the switch transistor, and the third port of each switch transistor is a source of the switch transistor.
Further, each time division multiplexing unit includes a first multiplexing unit and a second multiplexing unit, and the first multiplexing unit and the second multiplexing unit are respectively electrically connected to the pixel cell array, wherein the number of gate lines and the number of switching transistors in the first multiplexing unit and the second multiplexing unit are both N, N is a natural number greater than or equal to 2, and the number of compensation capacitors of the first multiplexing unit is different from the number of compensation capacitors of the second multiplexing unit.
Furthermore, the number of the compensation capacitors of the first multiplexing unit is N-1, and the N-1 compensation capacitors include a first compensation capacitor and N-2 second compensation capacitors, wherein one end of the first compensation capacitor is electrically connected to the first port of the 1 st switching transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected to the third port of the 1 st switching transistor in the first multiplexing unit; one end of the (N-2) th second compensation capacitor is electrically connected with the first port of the (1) th switching transistor in the first multiplexing unit, and the other end of the (N-2) th second compensation capacitor is electrically connected with the third port of the (N-1) th switching transistor in the first multiplexing unit.
Furthermore, the number of compensation capacitors of the second multiplexing unit is N, and the N compensation capacitors include a first compensation capacitor and N-1 second compensation capacitors, where one end of the first compensation capacitor is electrically connected to the first port of the 1 st switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected to the third port of the 1 st switching transistor in the second multiplexing unit; one end of the (N-1) th second compensation capacitor is electrically connected with the first port of the 1 st switch transistor in the second multiplexing unit, and the other end of the (N-1) th second compensation capacitor is electrically connected with the third port of the Nth switch transistor in the second multiplexing unit.
Furthermore, a capacitance value of any one of the first compensation capacitors in the first multiplexing unit is different from a capacitance value of the first compensation capacitor of the second multiplexing unit, and a capacitance value of any one of the second compensation capacitors in the first multiplexing unit is different from a capacitance value of the second compensation capacitor of the second multiplexing unit.
Furthermore, the number of the compensation capacitors of the first multiplexing unit is N-1, and the N-1 compensation capacitors include a third compensation capacitor and N-2 fourth compensation capacitors, wherein one end of the third compensation capacitor is electrically connected to the first port of the nth switching transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected to the third port of the nth switching transistor in the first multiplexing unit; one end of the (N-2) th fourth compensation capacitor is electrically connected with the first port of the (N-1) th switching transistor in the first multiplexing unit, and the other end of the (N-2) th fourth compensation capacitor is electrically connected with the third port of the (N-1) th switching transistor in the first multiplexing unit.
Furthermore, the number of compensation capacitors of the second multiplexing unit is N, and the N compensation capacitors include a third compensation capacitor and N-1 fourth compensation capacitors, where one end of the third compensation capacitor is electrically connected to the first port of the nth switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected to the third port of the nth switching transistor in the second multiplexing unit; one end of the (N-1) th fourth compensation capacitor is electrically connected with the first port of the (N-1) th switching transistor in the second multiplexing unit, and the other end of the (N-1) th fourth compensation capacitor is electrically connected with the third port of the (N-1) th switching transistor in the second multiplexing unit.
Furthermore, a capacitance value of any one third compensation capacitor in the first multiplexing unit is different from a capacitance value of a third compensation capacitor in the second multiplexing unit, and a capacitance value of any one fourth compensation capacitor in the first multiplexing unit is different from a capacitance value of a fourth compensation capacitor in the second multiplexing unit.
According to another aspect of the present application, there is provided a display terminal including a terminal body and the display panel, the terminal body being connected with the display panel.
In a plurality of switching transistors of a time division multiplexing unit with data lines crossing each other, a plurality of first compensation capacitors are arranged between a first port of a part of the switching transistors and a third port of the switching transistors, one or more second compensation capacitors are arranged between a first port of the switching transistor corresponding to at least one first compensation capacitor and a third port of another switching transistor, or a plurality of third compensation capacitors are arranged between a first port of a part of the switching transistors and a second port of the switching transistor, one or more fourth compensation capacitors are arranged between a first port of the switching transistor corresponding to at least one third compensation capacitor and a second port of another switching transistor, and data signals on each data line output by the time division multiplexing unit can be mixed and compensated according to aspects of the present application, so that the consistency of the data signals on each data line can be ensured, and further, the data signals on the data lines are prevented from being different, and the phenomenon of uneven display of a display picture is eliminated.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a related art Demux drive architecture.
Fig. 2 shows a schematic diagram of a display panel according to an embodiment of the present application.
Fig. 3 shows a schematic diagram of a time division multiplexing unit according to an embodiment of the present application.
Fig. 4 shows a schematic diagram of a time division multiplexing unit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other suitable relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present application.
Fig. 1 shows a schematic diagram of a related art Demux drive architecture.
As shown in fig. 1, in the related art, the Demux circuit may sequentially turn on and off a driving Signal (i.e., Signal 1) output by a Source Driver IC (i.e., Source Driver IC) in a 1:3 manner through a transistor T1, a transistor T2 and a transistor T3, and time-share the driving Signal to 3 columns of data lines DL1, DL2 and DL3 in the display area; the other driving Signal (i.e., Signal 2) output by the source driver chip may be turned on and off sequentially through the transistor T4, the transistor T5 and the transistor T6 in a 1:3 manner, and then transmitted to the 3-column data lines DL4, DL5 and DL6 in the display area in a time-sharing manner.
In fig. 1, the display region may include a plurality of pixel units, each including a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit. The red sub-pixel unit 11, the green sub-pixel unit 12, and the blue sub-pixel unit 13 may be located in the same pixel unit of the display area of the display panel; the red sub-pixel unit 14, the green sub-pixel unit 15 and the blue sub-pixel unit 16 may be located in another pixel unit of the display area of the display panel. A corresponding thin film transistor may be disposed in each sub-pixel unit, and the thin film transistor in each sub-pixel unit may be electrically connected to a corresponding data line. For example, the drain electrode of the thin film transistor in the red sub-pixel unit 11 may be electrically connected to the data line DL1, the drain electrode of the thin film transistor in the green sub-pixel unit 12 may be electrically connected to the data line DL2, and the drain electrode of the thin film transistor in the blue sub-pixel unit 13 may be electrically connected to the data line DL 3.
Referring to fig. 1, De1, De2 and De3 may be different gate lines, and the gate lines GL1 may be electrically connected to the gates of the tfts in a row of sub-pixel units, respectively. The drain of the first transistor T1 is electrically connected to the data line DL1, the drain of the fifth transistor T5 is electrically connected to DL2, the drain of the third transistor T3 is electrically connected to DL3, the drain of the fourth transistor T4 is electrically connected to DL4, the drain of the second transistor T2 is electrically connected to the data line DL5, and the drain of the sixth transistor T6 is electrically connected to DL 6.
In actual operation, during the high level period of the gate line GL1, the De1, the De2 and the De3 may be sequentially pulsed to control the transistor T1, the transistor T2 and the transistor T3 to be sequentially turned on, and further, the data Signal1 is transmitted to the data lines DL1, DL5 and DL3 in a time-sharing manner, and finally, the display data is written into the sub-pixel unit 11, the sub-pixel unit 15 and the sub-pixel unit 13 in a time-sharing manner, so as to realize the display of the display screen. Similar work is done for Signal 2.
However, in fig. 1, a coupling capacitor (or parasitic capacitor) Cp0 exists between the drain of the transistor T3 and the drain of the transistor T2 (or between the data line DL5 and the data line DL 3). Further, a coupling capacitance Cp21 exists between the drain of the transistor T2 and the gate of the transistor T1 (or between the data line DL5 and the gate line De 1); a coupling capacitance Cp31 exists between the drain of the transistor T3 and the gate of the transistor T1; a coupling capacitance Cp32 exists between the drain of the transistor T3 and the gate of the transistor T2. A coupling capacitance Cp54 exists between the drain of the transistor T5 and the gate of the transistor T4; a coupling capacitance Cp64 exists between the drain of the transistor T6 and the gate of the transistor T4; a coupling capacitance Cp65 exists between the drain of the transistor T6 and the gate of the transistor T5.
Due to the existence of the coupling capacitance between the transistors, the coupling conditions between the different data lines DL1-DL6 are inconsistent. When the gate line turns on or off the transistors T1-T6, the data signals on the data lines DL1-DL6 are different, so that the display image may have non-uniform display phenomena such as vertical stripes and horizontal stripes.
Therefore, in the case where the data lines corresponding to the sub-pixel cells of the same color in different pixel cells cross each other in fig. 1, the coupling capacitance between the transistor (e.g., T2 or T5) directly related to the cross line and each gate line has a large influence, and the coupling capacitance between the transistor (e.g., T3 or T6) adjacent to the transistor directly related to the cross line and each gate line has a large influence. In addition, coupling capacitance (e.g., Cp0) also exists between different data lines, such as between crossing data lines and adjacent data lines.
In view of the above, the present application provides a display panel, which includes a pixel cell array and a plurality of time-sharing multiplexing units, each of the time-sharing multiplexing units is electrically connected to the pixel cell array, each of the pixel cells in the pixel cell array includes one or more sub-pixel cells, each of the time-sharing multiplexing units includes a plurality of gate lines and a plurality of switching transistors, wherein a first port of each of the switching transistors is electrically connected to one of the gate lines, and a second port of each of the switching transistors is electrically connected to a corresponding driving signal; the third ports of the at least two switching transistors are respectively and electrically connected to the sub-pixel units in different pixel units to form the intersection of the data lines corresponding to the at least two switching transistors; among the plurality of switching transistors, a plurality of first compensation capacitors are arranged between the first ports of part of the switching transistors and the third ports of the switching transistors, wherein one or more second compensation capacitors are arranged between the first port of the switching transistor corresponding to at least one first compensation capacitor and the third ports of other switching transistors; or, in the plurality of switch transistors, a plurality of third compensation capacitors are arranged between the first ports of some of the switch transistors and the second ports of the switch transistors, and one or more fourth compensation capacitors are arranged between the first port of the switch transistor corresponding to at least one third compensation capacitor and the second ports of other switch transistors.
In a plurality of switching transistors of a time division multiplexing unit with data lines crossed with each other, a plurality of first compensation capacitors are arranged between the first ports of part of the switching transistors and the third ports of the switching transistors, one or more second compensation capacitors are arranged between the first port of the switching transistor corresponding to at least one first compensation capacitor and the third ports of other switching transistors, or a plurality of third compensation capacitors are arranged between the first port of part of the switching transistors and the second port of the switching transistor, one or more fourth compensation capacitors are arranged between the first port of the switching transistor corresponding to at least one third compensation capacitor and the second ports of other switching transistors, so that the data signals on each data line output by the time division multiplexing unit can be mixed and compensated, and the consistency of the data signals on each data line can be ensured, and further, the data signals on the data lines are prevented from being different, and the phenomenon of uneven display of a display picture is eliminated.
Fig. 2 shows a schematic diagram of a display panel according to an embodiment of the present application.
As shown in fig. 2, the embodiments of the present application identify names or sequences in left-to-right and top-to-bottom order. 1 may denote a pixel cell array, and 2 may denote any one of the time-division multiplexing units (also referred to as Demux units). The time-sharing multiplexing unit can have two paths of driving signals Signal1 and Signal2, and corresponding data signals are output to different sub-pixel units through the first multiplexing unit and the second multiplexing unit respectively. The first multiplexing unit may include a 1 st switching transistor T1, a 2 nd switching transistor T2, and a 3 rd switching transistor T3; the second multiplexing unit may include a 1 st switching transistor T4, a 2 nd switching transistor T5, and a 3 rd switching transistor T6.
Further, the sub-pixel unit 11 may be a red sub-pixel unit, the sub-pixel unit 12 may be a green sub-pixel unit, and the sub-pixel unit 13 may be a blue sub-pixel unit. The sub-pixel unit 11, the sub-pixel unit 12 and the sub-pixel unit 13 are located in the same pixel unit; sub-pixel element 14 may be a red sub-pixel element, sub-pixel element 15 may be a green sub-pixel element, and sub-pixel element 16 may be a blue sub-pixel element. The sub-pixel unit 14, the sub-pixel unit 15, and the sub-pixel unit 16 are located at another pixel unit.
Further, in fig. 2, De1, De2, and De3 may be different strobe signals. Wherein C1 may be a first compensation capacitor in the first multiplexing unit, and C2 may be a second compensation capacitor in the first multiplexing unit; c3 may be a first compensation capacitor in the second multiplexing unit, and C4 and C5 may be second compensation capacitors in the second multiplexing unit; c1 'may be a fourth compensation capacitor in the first multiplexing unit, and C2' may be a third compensation capacitor in the first multiplexing unit; c3 'and C4' may be fourth compensation capacitors in the second multiplexing unit; c5' may be a third compensation capacitance in the second multiplexing unit. It should be noted that, in the present application, the switching transistors in a single multiplexing unit may be sequentially ordered from left to right. For example, in the second multiplexing unit, T4 may be a 1 st switching transistor, T5 may be a 2 nd switching transistor, and T6 may be a 3 rd switching transistor.
Further, the first port of each switch transistor is a gate of the switch transistor, the second port of each switch transistor is a source of the switch transistor, and the third port of each switch transistor is a drain of the switch transistor, or the first port of each switch transistor is a gate of the switch transistor, the second port of each switch transistor is a drain of the switch transistor, and the third port of each switch transistor is a source of the switch transistor.
Note that the transistors in the embodiments of the present application, such as the switching transistor and the thin film transistor, may be N-type or P-type, and the types of the transistors in the present application are not limited. Hereinafter, the examples of the present application will be described mainly by taking N-type as an example.
Specifically, in the time division multiplexing unit in the embodiment of the present application, the driving signal input to the time division multiplexing unit may be divided into 1: and in the N mode, the data are transmitted to the corresponding data lines in the sub-pixel units in a time-sharing manner so as to write the data on the data lines into the corresponding sub-pixel units, so that each sub-pixel unit emits light and the display of a display picture is realized. Wherein N is a natural number greater than or equal to 2.
The time division multiplexing unit may be provided in plurality. And each time division multiplexing unit controls a preset number of sub-pixel units to emit light. It is to be understood that the structure between the time division multiplexing units is not limited in the present application.
Further, each time division multiplexing unit includes a first multiplexing unit and a second multiplexing unit, and the first multiplexing unit and the second multiplexing unit are respectively electrically connected to the pixel cell array, wherein the number of gate lines and the number of switching transistors in the first multiplexing unit and the second multiplexing unit are both N, N is a natural number greater than or equal to 2, and the number of compensation capacitors of the first multiplexing unit is different from the number of compensation capacitors of the second multiplexing unit. For example, in the plurality of time division multiplexing units, the number of gate lines and the number of switching transistors of one of the time division multiplexing units may be both 6, and there are 2 multiplexing units in total. At this time, the number of compensation capacitors of the first multiplexing unit may be 2, and the number of compensation capacitors of the second multiplexing unit may be 3.
Further, the number of the compensation capacitors of the first multiplexing unit is N-1, where the N-1 compensation capacitors include a first compensation capacitor and N-2 second compensation capacitors, one end of the first compensation capacitor is electrically connected to the first port of the 1 st switch transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected to the third port of the 1 st switch transistor in the first multiplexing unit; one end of the (N-2) th second compensation capacitor is electrically connected with the first port of the (1) th switching transistor in the first multiplexing unit, and the other end of the (N-2) th second compensation capacitor is electrically connected with the third port of the (N-1) th switching transistor in the first multiplexing unit. Taking the switching transistors as N-type, the number of the first compensation capacitors may be 1, and the number of the second compensation capacitors may be N-2. One end of the first compensation capacitor can be electrically connected with the grid electrode of the corresponding switch transistor, and the other end of the first compensation capacitor can be electrically connected with the drain electrode of the corresponding switch transistor. It can be understood that, in practical applications, the number of the first compensation capacitor and the second compensation capacitor may be set as required, and the application is not limited to the number of the first compensation capacitor and the second compensation capacitor.
Furthermore, the number of compensation capacitors of the second multiplexing unit is N, and the N compensation capacitors include a first compensation capacitor and N-1 second compensation capacitors, where one end of the first compensation capacitor is electrically connected to the first port of the 1 st switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected to the third port of the 1 st switching transistor in the second multiplexing unit; one end of the (N-1) th second compensation capacitor is electrically connected with the first port of the 1 st switch transistor in the second multiplexing unit, and the other end of the (N-1) th second compensation capacitor is electrically connected with the third port of the Nth switch transistor in the second multiplexing unit. For example, in fig. 2, C3 may be a first compensation capacitor, C4 may be a 1 st second compensation capacitor, and C5 may be a 2 nd second compensation capacitor.
Further, a capacitance value of any one of the first compensation capacitors in the first multiplexing unit is different from a capacitance value of the first compensation capacitor of the second multiplexing unit, and a capacitance value of any one of the second compensation capacitors in the first multiplexing unit is different from a capacitance value of the second compensation capacitor of the second multiplexing unit. The capacitance value of the first compensation capacitor and the capacitance value of the second compensation capacitor may also be calculated in other manners, and may be adjusted according to actual needs, which is not limited in the present application.
Fig. 3 shows a schematic diagram of a time division multiplexing unit according to an embodiment of the present application.
As shown in fig. 3, one time division multiplexing unit according to the embodiment of the present application may include 6 switching transistors, and the first multiplexing unit and the second multiplexing unit may include 3 switching transistors, respectively. For example, the first multiplexing unit includes a first switching transistor T1, a second switching transistor T2, and a switching transistor T3. Wherein, the gate of the first switching transistor is electrically connected with the first gate line De1, and the drain of the first switching transistor is electrically connected with the first data line DL 1; a gate electrode of the second switching transistor is electrically connected to the second gate line De2, and a drain electrode of the second switching transistor is electrically connected to the second data line DL 5; a gate electrode of the third switching transistor is electrically connected to the third gate line De3, and a drain electrode of the third switching transistor is electrically connected to the third data line DL 3. The source of the first switching transistor, the source of the second switching transistor, and the source of the third switching transistor are all electrically connected to the driving Signal 1.
Referring to fig. 3, C1 may be a first compensation capacitor in the first multiplexing unit, and C2 may be a second compensation capacitor in the first multiplexing unit; c3 may be a first compensation capacitor in the second multiplexing unit, and C4 and C5 may each be a second compensation capacitor in the second multiplexing unit.
Illustratively, the capacitance value of the compensation capacitor can be set as follows:
C1＝Cp31+Cp32+2*Cp0；
C2＝Cp31+Cp32-Cp21-Cp0；
C3＝Cp64+Cp65；
C4＝Cp64+Cp65-Cp54-Cp0；
C5＝2*Cp0；
cp0 is a coupling capacitance between the drain of the 3 rd switching transistor T3 in the first multiplexing unit and the drain of the 2 nd switching transistor T2 in the first multiplexing unit; cp21 is the coupling capacitance between the drain of the 2 nd switch transistor T2 in the first multiplexing unit and the gate of the 1 st switch transistor T1 in the first multiplexing unit; cp31 is the coupling capacitance between the drain of the 3 rd switch transistor T3 in the first multiplexing unit and the gate of the 1 st switch transistor T1 in the first multiplexing unit; cp32 is the coupling capacitance between the drain of the 3 rd switch transistor T3 in the first multiplexing unit and the gate of the 2 nd switch transistor T2 in the first multiplexing unit.
Further, Cp54 is a coupling capacitance between the drain of the 2 nd switch transistor T5 in the second multiplexing unit and the gate of the 1 st switch transistor T4 in the second multiplexing unit; cp64 is the coupling capacitance between the drain of the 3 rd switch transistor T6 in the second multiplexing unit and the gate of the 1 st switch transistor T4 in the second multiplexing unit; cp65 is the coupling capacitance between the drain of the 3 rd switch transistor T6 in the second multiplexing unit and the gate of the 2 nd switch transistor T5 in the second multiplexing unit.
Fig. 4 shows a schematic diagram of a time division multiplexing unit according to an embodiment of the present application.
As shown in fig. 4, one time division multiplexing unit according to the embodiment of the present application may include 6 switching transistors, and the first multiplexing unit and the second multiplexing unit may include 3 switching transistors, respectively. For example, the first multiplexing unit includes a first switching transistor T1, a second switching transistor T2, and a switching transistor T3. Wherein, the grid of the first switch transistor is electrically connected with first strobe line De1, the drain-source resistance of the first switch transistor is electrically connected with first data link DL 1; a gate electrode of the second switching transistor is electrically connected to the second gate line De2, and a drain electrode of the second switching transistor is electrically connected to the second data line DL 5; a gate electrode of the third switching transistor is electrically connected to the third gate line De3, and a drain electrode of the third switching transistor is electrically connected to the third data line DL 3. The source of the first switching transistor, the source of the second switching transistor, and the source of the third switching transistor are all electrically connected to the driving Signal 1.
Referring to fig. 4, C1 'may be a fourth compensation capacitor in the first multiplexing unit, and C2' may be a third compensation capacitor in the first multiplexing unit; c3 'may be the 1 st fourth compensation capacitor in the second multiplexing unit, and C4' may be the 2 nd fourth compensation capacitor in the second multiplexing unit; c5' may be a third compensation capacitance in the second multiplexing unit.
Illustratively, the capacitance value of the compensation capacitor can be set as follows:
C1’＝Cp21+3*Cp0；
C2’＝Cp31+Cp32+2*Cp0；
C3’＝2*Cp0；
C4’＝Cp54+3*Cp0；
C5’＝Cp64+Cp65；
cp0 is a coupling capacitance between the drain of the 3 rd switching transistor T3 in the first multiplexing unit and the drain of the 2 nd switching transistor T2 in the first multiplexing unit; cp21 is the coupling capacitance between the drain of the 2 nd switch transistor T2 in the first multiplexing unit and the gate of the 1 st switch transistor T1 in the first multiplexing unit; cp31 is the coupling capacitance between the drain of the 3 rd switch transistor T3 in the first multiplexing unit and the gate of the 1 st switch transistor T1 in the first multiplexing unit; cp32 is the coupling capacitance between the drain of the 3 rd switch transistor T3 in the first multiplexing unit and the gate of the 2 nd switch transistor T2 in the first multiplexing unit.
Further, Cp54 is a coupling capacitance between the drain of the 2 nd switch transistor T5 in the second multiplexing unit and the gate of the 1 st switch transistor T4 in the second multiplexing unit; cp64 is the coupling capacitance between the drain of the 3 rd switch transistor T6 in the second multiplexing unit and the gate of the 1 st switch transistor T4 in the second multiplexing unit; cp65 is the coupling capacitance between the drain of the 3 rd switch transistor T6 in the second multiplexing unit and the gate of the 2 nd switch transistor T5 in the second multiplexing unit.
It should be noted that, in the embodiment of the present application, the embodiment of fig. 3 and the embodiment of fig. 4 may be replaced with each other, or the embodiment of fig. 3 and the embodiment of fig. 4 may be used in combination with each other. In addition, the setting of the capacitance values of the compensation capacitors is exemplary, and the capacitance values of the respective compensation capacitors may be set as needed in practical applications.
In one example, referring to fig. 3, Signal1 Signal entering DL5 is pulled high by Signal compensation through C1 and C2, so as to counteract the data Signal reduction caused by Cp0, Cp21, Cp31 and Cp32 coupling DL1, DL3 and DL 5; by performing Signal compensation through C3, C4 and C5, a Signal2 Signal entering DL2 is pulled high, so that the reduction of data signals caused by the coupling of Cp54, Cp64 and Cp65 to DL2, DL4 and DL6 is counteracted. By setting different newly-added compensation capacitors, the size of the compensation capacitor is equal to that of the coupling capacitor, so that the level of the raised compensation signal is the same as that of the lowered compensation signal, and the raised compensation signal and the lowered compensation signal are mutually offset.
Note that, with regard to fig. 3, the first compensation capacitor and the second compensation capacitor are disposed on a side where there is less crossover (i.e., a side away from the driving signal) between the data line and the gate line; with respect to fig. 4, the third compensation capacitor and the fourth compensation capacitor are disposed between the data line and the gate line on more sides (i.e., on the side close to the driving signal) across the lines. Through set up first compensation capacitance and second compensation capacitance or set up third compensation capacitance and fourth compensation capacitance in the one side of keeping away from drive signal, this application embodiment can compensate the data signal on each data line of timesharing multiplex unit output, guarantees the uniformity of data signal on each data line, and then avoids data signal on each data line appears the difference, eliminates the inhomogeneous phenomenon of display screen demonstration.
Furthermore, the display panel further comprises a driving unit, and the plurality of time division multiplexing units are respectively electrically connected with the driving unit and used for receiving the driving signals output by the driving unit. For example, the driving signal may be generated using a source driver in the display panel. It is to be understood that the present application is not limited as to how the drive signal is generated.
Furthermore, the sub-pixel unit array comprises a plurality of sub-pixel units arranged in a row and column mode, a thin film transistor is arranged in each sub-pixel unit, and the drain electrode of the thin film transistor in each sub-pixel unit is electrically connected with the data line corresponding to the sub-pixel unit. It is to be understood that the present application is not limited to the specific structure of the sub-pixel unit array.
In addition, this application still provides a display terminal, display terminal include the terminal main part with display panel, the terminal main part with display panel is connected.
In summary, in the embodiments of the present application, in a plurality of switching transistors of a time division multiplexing unit having data lines intersecting each other, a plurality of first compensation capacitors are disposed between a first port of a part of the switching transistors and a third port of the switching transistors, one or more second compensation capacitors are disposed between a first port of a switching transistor corresponding to at least one of the first compensation capacitors and a third port of another switching transistor, or a plurality of third compensation capacitors are disposed between a first port of a part of the switching transistors and a second port of the switching transistor, and one or more fourth compensation capacitors are disposed between a first port of a switching transistor corresponding to at least one of the third compensation capacitors and a second port of another switching transistor, so that data signals on the data lines output by the time division multiplexing unit can be mixed and compensated, and consistency of the data signals on the data lines can be ensured, and further, the data signals on the data lines are prevented from being different, the phenomenon of uneven display of a display picture is eliminated, and the display panel is suitable for various display panels.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display panel and the display terminal provided in the embodiments of the present application are described in detail above, and a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the embodiments above is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display panel, comprising a pixel cell array and a plurality of time-sharing multiplexing units, each time-sharing multiplexing unit being electrically connected to the pixel cell array, each pixel cell in the pixel cell array comprising one or more sub-pixel cells, each time-sharing multiplexing unit comprising a plurality of gate lines and a plurality of switching transistors, wherein,
the first port of each switch transistor is electrically connected with one gate line, and the second port of each switch transistor is electrically connected with a corresponding driving signal; the third ports of the at least two switching transistors are respectively and electrically connected to the sub-pixel units in different pixel units to form the intersection of the data lines corresponding to the at least two switching transistors;
among the plurality of switching transistors, a plurality of first compensation capacitors are arranged between the first ports of part of the switching transistors and the third ports of the switching transistors, wherein one or more second compensation capacitors are arranged between the first port of the switching transistor corresponding to at least one first compensation capacitor and the third ports of other switching transistors;
or, in the plurality of switch transistors, a plurality of third compensation capacitors are arranged between the first ports of some of the switch transistors and the second ports of the switch transistors, and one or more fourth compensation capacitors are arranged between the first port of the switch transistor corresponding to at least one third compensation capacitor and the second ports of other switch transistors.
2. The display panel according to claim 1, wherein the first port of each of the switching transistors is a gate of the switching transistor, the second port of each of the switching transistors is a source of the switching transistor, the third port of each of the switching transistors is a drain of the switching transistor,
or, the first port of each switch transistor is a gate of the switch transistor, the second port of each switch transistor is a drain of the switch transistor, and the third port of each switch transistor is a source of the switch transistor.
3. The display panel according to claim 2, wherein each of the time-division multiplexing units includes a first multiplexing unit and a second multiplexing unit, the first multiplexing unit and the second multiplexing unit being electrically connected to the pixel cell array, respectively, wherein,
the number of the gate lines and the number of the switching transistors in the first multiplexing unit and the second multiplexing unit are both N, wherein N is a natural number greater than or equal to 2, and the number of the compensation capacitors of the first multiplexing unit is different from the number of the compensation capacitors of the second multiplexing unit.
4. The display panel according to claim 3, wherein the number of the compensation capacitors of the first multiplexing unit is N-1, the N-1 compensation capacitors include a first compensation capacitor and N-2 second compensation capacitors, wherein,
one end of the first compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the 1 st switching transistor in the first multiplexing unit;
one end of the (N-2) th second compensation capacitor is electrically connected with the first port of the (1) th switching transistor in the first multiplexing unit, and the other end of the (N-2) th second compensation capacitor is electrically connected with the third port of the (N-1) th switching transistor in the first multiplexing unit.
5. The display panel according to claim 3, wherein the number of the compensation capacitors of the second multiplexing unit is N, the N compensation capacitors include a first compensation capacitor and N-1 second compensation capacitors, wherein,
one end of the first compensation capacitor is electrically connected with the first port of the 1 st switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the 1 st switching transistor in the second multiplexing unit;
one end of the (N-1) th second compensation capacitor is electrically connected with the first port of the 1 st switch transistor in the second multiplexing unit, and the other end of the (N-1) th second compensation capacitor is electrically connected with the third port of the Nth switch transistor in the second multiplexing unit.
6. The display panel according to claim 4 or 5, wherein a capacitance value of any one of the first compensation capacitors in the first multiplexing unit is different from a capacitance value of the first compensation capacitor in the second multiplexing unit, and a capacitance value of any one of the second compensation capacitors in the first multiplexing unit is different from a capacitance value of the second compensation capacitor in the second multiplexing unit.
7. The display panel according to claim 3, wherein the number of the compensation capacitors of the first multiplexing unit is N-1, the N-1 compensation capacitors include a third compensation capacitor and N-2 fourth compensation capacitors, wherein,
one end of the third compensation capacitor is electrically connected with the first port of the Nth switching transistor in the first multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the Nth switching transistor in the first multiplexing unit;
one end of the (N-2) th fourth compensation capacitor is electrically connected with the first port of the Nth switching transistor in the first multiplexing unit, and the other end of the (N-2) th fourth compensation capacitor is electrically connected with the third port of the (N-1) th switching transistor in the first multiplexing unit.
8. The display panel according to claim 3, wherein the number of the compensation capacitors of the second multiplexing unit is N, the N compensation capacitors include a third compensation capacitor and N-1 fourth compensation capacitors, wherein,
one end of the third compensation capacitor is electrically connected with the first port of the Nth switching transistor in the second multiplexing unit, and the other end of the first compensation capacitor is electrically connected with the third port of the Nth switching transistor in the second multiplexing unit;
one end of the (N-1) th fourth compensation capacitor is electrically connected with the first port of the (N-1) th switching transistor in the second multiplexing unit, and the other end of the (N-1) th fourth compensation capacitor is electrically connected with the third port of the (N-1) th switching transistor in the second multiplexing unit.
9. The display panel according to claim 7 or 8, wherein a capacitance value of any one of the third compensation capacitors in the first multiplexing unit is different from a capacitance value of the third compensation capacitor in the second multiplexing unit, and a capacitance value of any one of the fourth compensation capacitors in the first multiplexing unit is different from a capacitance value of the fourth compensation capacitor in the second multiplexing unit.
10. A display terminal characterized in that the display terminal comprises a terminal body and a display panel according to any one of claims 1 to 9, the terminal body being connected to the display panel.
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