KR20080041089A - Liquid crystal display and apparatus for driving the same - Google Patents

Abstract

An LCD device and an operating method thereof are provided to form data lines along the short axis of an LCD panel to reduce the number of data lines, thereby reducing the number of expensive ICs(Integrated Circuits) necessary to operate data lines, and miniaturizing and simplifying an FPC(Flexible Printed Circuit) and a PCB(Printed Circuit Board). An LCD panel(Liquid Crystal Display)(6) has plural data lines(D1~Dn) and plural gate lines(G1~Gm). The data lines are formed along the y axis of a substrate. The gate lines are formed along the x axis of the substrate to cross the data lines. A data driving circuit supplies a data voltage to the data lines. A gate driving circuit(2) supplies a scan pulse to the gate lines. A timing controller(3) supplies video data to the data driving circuit and controls the data driving circuit and the gate driving circuit. The gate driving circuit generates a scan pulse having a pulse width shorter than 1 horizontal period.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND APPARATUS FOR DRIVING THE SAME}

1 is a block diagram showing a conventional liquid crystal display device.

FIG. 2 is an enlarged view of a 4 × 4 liquid crystal cell matrix in the liquid crystal panel of FIG. 1; FIG.

FIG. 3 is a waveform diagram illustrating signals supplied to data lines and gate lines shown in FIG. 1. FIG.

4 shows an example where source / gate drive integrated circuits are bonded onto a glass substrate in a tape automated manner.

FIG. 5 shows an example in which source / gate drive integrated circuits are bonded onto a glass substrate in a chip on glass manner.

FIG. 6 is a diagram illustrating an example in which data lines and a common electrode cross each other in a storage on come-on method. FIG.

7 is a diagram illustrating an example in which data lines and a common electrode intersect in an in-plane switching mode.

8 is a block diagram illustrating a liquid crystal display according to a first embodiment of the present invention.

FIG. 9 shows a first embodiment of the pixel array shown in FIG. 8; FIG.

FIG. 10 is a waveform diagram illustrating a data voltage and a scan pulse for driving a pixel array as shown in FIG. 9.

FIG. 11 shows an example of a timing controller for aligning digital video data to the signal wiring and subpixel arrangement of FIGS. 9 and 10.

12 is a block diagram illustrating in detail a source drive integrated circuit according to a first embodiment of the present invention for supplying data as shown in FIG.

FIG. 13 shows a second embodiment of the pixel array shown in FIG. 8; FIG.

FIG. 14 is a waveform diagram illustrating a data voltage and a scan pulse for driving a pixel array as shown in FIG. 13.

FIG. 15 is a detailed block diagram illustrating a source drive integrated circuit according to a second exemplary embodiment of the present invention for generating a data voltage as shown in FIG.

FIG. 16 illustrates a common electrode for supplying a common voltage to a common electrode of a liquid crystal cell in a liquid crystal display device and a driving method thereof according to an embodiment of the present invention.

17 illustrates a data line and a source drive integrated circuit of a liquid crystal display according to another exemplary embodiment of the present invention.

18 and 20 show a third embodiment of the pixel array shown in FIG.

FIG. 19 is a waveform diagram illustrating a data voltage and a scan pulse for driving a pixel array as shown in FIG. 18.

FIG. 21 is a waveform diagram illustrating a data voltage and a scan pulse for driving a pixel array as shown in FIG. 19.

FIG. 22 illustrates an example of a timing controller for aligning digital video data according to the signal wiring and subpixel arrangement of FIGS. 18 and 19.

FIG. 23 is a view for explaining the configuration and operation of a source drive IC for generating a data voltage as shown in FIG. 22;

24 is a diagram illustrating an example of a timing controller for aligning digital video data according to the signal wiring and subpixel arrangement of FIGS. 20 and 21.

FIG. 25 is a view for explaining the configuration and operation of a source drive IC for generating a data voltage as shown in FIG. 24;

<Description of Symbols for Main Parts of Drawings>

1a to 1d, 51, 61: source drive ICs 2 and 13: gate driving circuit

3, 11: Timing controller 4, 53, 57, 63: PCB

5, 54, 62: FPC 6, 14: liquid crystal panel

7: level shifter 12: data driving circuit

31,131,231: memory 50, 60: pixel array

52, 56: TCP 55, 65: gate drive IC

71, 81: common electrode 101,201,301,401: shift register

102, 202, 302, 402: first latch 103, 203, 303, 403: second latch 104, 204, 304, 404: DAC 105, 205, 305, 405: output buffer 106, 206, 306, 406: register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and in particular, reduces the number of source drive integrated circuits (hereinafter referred to as " IC ") for supplying data to data lines and supplies signals to the source drive ICs. In order to reduce the size of a flexible printed circuit (FPC) and a printed circuit board (hereinafter referred to as "PCB") and a driving method thereof will be. In addition, the present invention relates to a liquid crystal display and a driving method thereof to prevent a change in the common voltage caused by the intersection of the data line and the common voltage line. The present invention also relates to a liquid crystal display device and a method of driving the same, which reduce the number of gate lines to ensure sufficient charging time of the data voltage.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. In an active matrix type liquid crystal display, switching elements are formed in each liquid crystal cell, which is advantageous for displaying a moving image. As the switching device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

1 schematically shows an active matrix type liquid crystal display device. FIG. 2 is an equivalent circuit diagram equivalently showing a TFT array substrate for a 4 × 4 liquid crystal cell matrix of the liquid crystal panel shown in FIG. 1. 3 is a waveform diagram illustrating signals supplied to signal wires of the liquid crystal cell matrix illustrated in FIG. 2.

1 to 3, in an active matrix type liquid crystal display, data lines D1 to Dm and gate lines G1 to Gn intersect each other and drive liquid crystal cells Clc at intersections thereof. Liquid crystal panel 14 having TFTs formed therein, a data driving circuit 12 for driving the data lines D1 to Dm of the liquid crystal panel 14, and gate lines G1 to Gn of the liquid crystal panel 14. ) And a timing controller 11 for controlling the data driving circuit 12 and the gate driving circuit 13.

The data driving circuit 12 includes a plurality of source drive ICs to convert the digital data into analog data voltages R1 to R4, G1 to G4, and B1 to B4 by using the analog gamma compensation voltage under the control of the timing controller 11. The conversion is supplied to the data lines D1 to Dm.

The gate driving circuit 13 sequentially supplies the scan pulses SP1 to SP4 to the gate lines G1 to Gn under the control of the timing controller 11 including a plurality of gate drive ICs.

Each of the scan pulses SP1 to SP4 is generated for approximately one horizontal period, and the data voltages R1 to R4, G1 to G4, and B1 to B4 are synchronized with the scan pulses SP1 to SP4 and the data lines D1. To Dm). The TFTs are turned on in response to the scan pulses SP1 to SP4 to supply the data voltages from the data lines D1 to Dm to the pixel electrode PIX of the liquid crystal cells Clc. In the liquid crystal cells Clc, liquid crystal molecules are disposed between the pixel electrode PIX supplied with the data voltage and the common electrode supplied with the common voltage Vcom. The liquid crystal molecules rotate according to an electric field applied by the pixel electrode PIX and the common electrode COM by dielectric anisotropy to modulate the polarization component of incident light.

The timing controller 11 controls the gate control signal GDC and the data driver circuit 12 for controlling the gate driver circuit 13 using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, a polarity control signal POL, and the like. The gate control signal GDC includes a gate shift clock (GSC), a gate output signal (GOE), a gate start pulse (GSP), and the like.

In FIG. 1, 'Cst' connected to the liquid crystal cell Clc is a storage capacitor for maintaining the voltage of the liquid crystal cell Clc. The storage capacitor Cst is a storage on gate connected between the front gate line and the pixel electrode PIX or a storage on comon connected between the separate common electrode COM and the pixel electrode PIX. On Common).

The source drive ICs and gate drive ICs are referred to as Tape Automated Bonding (TAB), as shown in FIG. 4, or Chip On Glass (hereinafter referred to as "COG") as shown in FIG. Adhesive) onto the substrate.

In the TAB method, as shown in FIG. 4, each of the source drive ICs 51 and the gate drive ICs 55 are mounted in a tape carrier package (hereinafter, referred to as “TCP”) 52 and 56. Output pads of TCPs 52 and 56 are bonded to a data pad or gate pad of a glass substrate with an anisotropic conductor film (ACF). The input pads of the source TCPs 52 are bonded to the output pads of the source PCB 53 on which the timing controller 11 and the gamma reference voltage generation circuits (not shown) are mounted. Input pads of gate TCPs 56 are bonded to output pads of gate PCB 57. The source PCB 53 and the gate PCB 57 are connected to the FPC 54. The drive voltages and control signals required for the gate drive ICs are supplied from the source PCB 53 to the gate PCB 57 through the FPC 54.

The COG method directly bonds the source drive ICs 61 and the gate drive ICs 65 onto the glass substrate as shown in FIG. 5 using conductive bumps. In FIG. 5, reference numeral '62' denotes an FPC that is attached to a glass substrate to supply signals and voltages necessary for the source drive ICs 61 and the gate drive ICs 65 generated from the source PCB 63.

4 and 5, reference numerals '50' and '60' denote pixels in which the data lines D1 to Dm and the gate lines G1 to Gn intersect and the liquid crystal cells Clc are arranged in a matrix form. Represents an array.

The liquid crystal display device has a larger number of data lines than the gate lines because the data lines are arranged in the long axis (x-axis) direction of the liquid crystal panel 14. Thus, the number of source drive ICs 51 and 61 for driving the data lines increases. Since the source drive ICs 51 and 61 have a higher cost than the gate drive ICs 55 and 65, the source drive ICs 51 and 61 increase the manufacturing cost of the liquid crystal display. Currently, in the liquid crystal panel 14 having the XGA resolution (1024 * 768), five source drive ICs are required when the source drive ICs 51 and 61 have 618 output channels. In addition, the cost of the liquid crystal display is further increased because the PCBs and the FPC are relatively large.

In addition, the liquid crystal display has a problem in that the image quality is deteriorated because the common voltage Vcom is changed. 6 and 7, the common electrodes 71 and 81 to which the common voltage Vcom is supplied and the data lines D1 to Dm to which the data voltage is supplied cross each other, thereby causing a load. There is a cause for it. FIG. 6 is a diagram illustrating an example in which data lines and a common electrode 71 cross each other in a storage-on-communication method overlapping the pixel electrode PIX. FIG. 7 illustrates that the pixel electrode PIX and the common electrode COM are disposed. An example in which the data lines and the common electrode 81 intersect in an in-plane switching mode (hereinafter, referred to as "IPS mode") formed on the same substrate to form a horizontal electric field in liquid crystal molecules. The figure shows. 6 and 7, when the data lines D1 to Dm and the common electrodes 71 and 81 cross each other, electrical coupling of the data lines D1 to Dm and the common electrodes 71 and 81 is performed by the intersections thereof. Coupling occurs and the common voltage Vcom fluctuates by data lines supplied with a data voltage in units of one horizontal period by the coupling.

Accordingly, an object of the present invention is to reduce the number of source drive ICs for supplying data to data lines and to reduce the size of FPC and PCB for supplying signals to the source drive ICs, and a driving method thereof. To provide.

Another object of the present invention is to provide a liquid crystal display and a driving method thereof to prevent a change in the common voltage caused by the intersection of the data line and the common voltage line.

It is still another object of the present invention to provide a liquid crystal display device and a driving method thereof to reduce the number of gate lines to ensure charging time of data voltage.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of data lines formed along a long axis direction of a substrate, and a plurality of gate lines formed along a short axis direction of the substrate to intersect the data lines. Liquid crystal panel having; A data driver circuit for supplying a data voltage to the data line; A gate driving circuit supplying a scan pulse to the gate line; And a timing controller for supplying digital video data to the data driving circuit and controlling the data driving circuit and the gate driving circuit.

The liquid crystal panel may include a plurality of red subpixels disposed along a short direction of the substrate; A plurality of green subpixels disposed along the minor axis of the substrate; And a plurality of blue subpixels disposed along the minor axis of the substrate.

The gate driving circuit generates the scan pulse with a pulse width smaller than one horizontal period.

The data driving circuit supplies a red data voltage corresponding to the red digital video data to the data lines for 1/3 horizontal period, and then the green corresponding to the green digital video data for the 1/3 horizontal period. After supplying a data voltage to the data lines, a blue data voltage corresponding to blue digital video data is supplied to the data lines during the 1/3 horizontal period.

The liquid crystal panel may include a plurality of red subpixels disposed along a long axis direction of the substrate; A plurality of green subpixels disposed along a long axis of the substrate; And a plurality of blue subpixels disposed along the long axis of the substrate.

The gate driving circuit generates the scan pulse with a pulse width of one horizontal period.

The data driving circuit supplies red, green, and blue data voltages to different data lines during the one horizontal period.

A liquid crystal panel having a plurality of odd and even data lines formed along a long axis direction of a substrate, and a plurality of gate lines formed along a short axis direction of the substrate so as to intersect the data lines; A data driver circuit for supplying a data voltage to the data line; A gate driving circuit supplying a scan pulse to the gate line; And a timing controller for supplying digital video data to the data driving circuit and controlling the data driving circuit and the gate driving circuit. Two subpixels disposed at the left and right sides of the gate line share the gate line.

Among the plurality of red, green, and blue subpixels, the subpixels disposed on the left side of the gate line with the gate line interposed therebetween receive the data voltage from the odd data line, and the gate with the gate line interposed therebetween. Subpixels disposed on the right side of the line receive the data voltage from the even data line.

The gate driving circuit generates the scan pulse with a pulse width of 1/2 horizontal period.

The data driving circuit supplies a red data voltage corresponding to red digital video data and a green data voltage corresponding to green digital video data to the odd and even data lines, respectively, for a half horizontal period. During the 1/2 horizontal period, the blue data voltage corresponding to the blue digital video data and the red data voltage corresponding to the red digital video data are supplied to the odd and even data lines, respectively. The green data voltage corresponding to the green digital video data and the blue data voltage corresponding to the blue digital video data are supplied to the odd and even data lines, respectively.

Among the plurality of red, green, and blue subpixels, 4i + 1 (i is 0 or a natural number) and 4i + 2th subpixels disposed on the left side of the gate line with the gate line interposed therebetween. The data voltage is supplied from and the 4i + 3th and 4i + 4th subpixels are supplied with the data voltage from the even data line.

Among the plurality of red, green, and blue subpixels, 4i + 1 (i is 0 or a natural number) and 4i + 2th subpixels disposed on the right side of the gate line with the gate line interposed therebetween. The data voltage is supplied from and the 4i + 3th and 4i + 4th subpixels are supplied with the data voltage from the odd data line.

The data driving circuit supplies a red data voltage corresponding to the red digital video data and a green data voltage corresponding to the green digital video data to the odd and even data lines, respectively, during the 1/2 horizontal period. Supplying the blue data voltage corresponding to the blue digital video data and the red data voltage corresponding to the red digital video data to the odd and even data lines, respectively, for 1/2 horizontal period, During the period, the green data voltage corresponding to the green digital video data and the blue data voltage corresponding to the blue digital video data are supplied to the even and odd data lines, respectively.

The liquid crystal display according to the exemplary embodiment of the present invention further includes a common electrode supplying the same common voltage to the common electrodes of the subpixels; The common electrode may be parallel to the data line and not cross the data line.

The timing controller stores the red, green and blue digital video data, supplies the red digital video data for one line to the data driving circuit, and then supplies the green digital video data for one line. And a memory for supplying the blue digital video data for one line to the data driving circuit after being supplied to the data driving circuit.

The timing controller stores the red, green, and blue digital video data, supplies one line of the red and green digital video data to the data driving circuit, and then stores one line of the blue and red digital video data. And supplying digital video data to the data driving circuit, and then supplying the green and blue digital video data for one line to the data driving circuit.

A liquid crystal display according to an exemplary embodiment of the present invention is formed at an intersection of the data lines and the gate lines, and supplies a data voltage from the data lines to pixel electrodes of the subpixels in response to the scan pulse. A plurality of thin film transistors are further provided, and elements of the gate driving circuit are formed on the substrate simultaneously with the thin film transistors.

In order to achieve the above object, a driving method of a liquid crystal display according to an exemplary embodiment of the present invention includes forming a plurality of data lines in the substrate along a long axis direction of the substrate and forming a plurality of gate lines in the substrate to intersect the data lines. Forming on the substrate along a major axis direction; Supplying a data voltage to the data line; And supplying a scan pulse to the gate line.

In order to achieve the above object, a driving method of a liquid crystal display device according to an exemplary embodiment of the present invention includes forming a plurality of odd and even data lines in the substrate along a long axis direction of the substrate and forming a plurality of gate lines to intersect the data lines. Forming on the substrate along a longitudinal direction of the substrate; Disposing subpixels such that two subpixels disposed at left and right sides with the gate line share the gate line; Supplying a data voltage to the data line; And supplying a scan pulse to the gate line.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 25.

Referring to FIG. 8, the liquid crystal display according to the exemplary embodiment of the present invention may include m gate lines G1 to G1 arranged side by side in the long axis direction (x-axis direction) of the pixel array 10 of the liquid crystal panel 6. Gm and n (n is an integer smaller than m) arranged side by side along the short axis direction (y-axis direction) in the pixel array 10 of the liquid crystal panel 6 so as to cross the gate lines G1 to Gm. Data lines D1 to Dn, the gate driving circuit 2 directly formed on the glass substrate of the liquid crystal panel 6, and the data driving circuit bonded to the glass substrate of the liquid crystal panel 6 in the form of COG or TCP. Source drive ICs 1a and 1b, and FPC 5 connected between the liquid crystal panel 6 and the source PCB 4, respectively.

In the pixel array 10, m × n liquid crystal cells are formed in pixel regions defined by the intersection of the gate lines G1 to Gm and the data lines D1 to Dn.

In the liquid crystal panel 6, liquid crystal is injected between two glass substrates. Of the two glass substrates, the data lines D1 to Dn and the gate lines G1 to Gm are orthogonal to each other on the TFT array substrate.

TFTs formed at the intersections of the data lines D1 to Dn and the gate lines G1 to Gm may receive data from the data lines D1 to Dn in response to a scan pulse from the gate lines G1 to Gm. Is supplied to the liquid crystal cells. 9 and 13, the TFTs are connected to gate electrodes connected to the gate lines G1 to Gm, source electrodes connected to the data lines D1 to Dn, and pixel electrodes of the liquid crystal cells Clc. A drain electrode is included.

In addition, a storage capacitor connected to each of the liquid crystal cells is formed on the TFT array substrate. The storage capacitor includes a front gate line for selecting a front vertical line by a previous scan pulse, a storage on gate connected between a pixel electrode supplied with a data voltage, or a common electrode 8 supplied with a common voltage Vcom. The storage device may be formed in a storage on-com mode connected between pixel electrodes to which a data voltage is supplied.

Among the two glass substrates, a color filter, a black matrix, and the like are formed on the color filter array substrate facing the TFT array substrate with the liquid crystal cell interposed therebetween.

On each of the TFT array substrate and the color filter array substrate, an alignment film for determining pretilt of liquid crystal molecules, a polarizer for passing light of a specific linearly polarized light, and the like are formed. A common electrode facing the pixel electrode and supplied with a common voltage may be formed on a TFT array substrate or a color filter array substrate.

The gate driving circuit 2 is not bonded to a glass substrate in a COG or TAB manner, but elements inside thereof are TFTs, gate lines G1 to Gm, and data lines of the pixel array in the manufacturing process of the TFT array substrate. It is formed simultaneously with (D1 to Dn). The method of mounting the gate driving circuit 2 is known as a "gate in panel". The gate driving circuit 2 includes a shift register, an output buffer, and the like, and sequentially supplies scan pulses to the gate lines G1 to Gm in response to the control signal GDC from the timing controller 3. The gate driving circuit 2 supplies the scan pulses sequentially from left to right or vice versa because the gate lines G1 to Gm are arranged side by side along the major axis direction of the liquid crystal panel 6.

If each of the red, green, and blue subpixels is arranged along the short axis direction of the liquid crystal panel 6 as shown in FIG. 9, the scan supplied to the k + 1 (k is a positive integer of 0 or more) gate line as shown in FIG. 10. The period between the generation of the pulse and the generation of the scan pulse supplied to the k + 4th gate line satisfies approximately one horizontal period (1H), and the scan pulses generated within the period secure the charging time of the liquid crystal cell. In order to achieve the precharge effect of data, the data may be overlapped or non-overlapping. Here, the size of one horizontal period 1H is substantially the same as the period of supplying the data voltage to one horizontal line in the prior art having the same resolution. One horizontal period 1H to be described below has this value.

When each of the red, green and blue subpixels is arranged along the major axis direction of the liquid crystal panel 6 as shown in FIG. 13, the pulse width of each of the scan pulses is approximately 1 horizontal period (1H) as shown in FIG. Pulses can be overlapping or non-overlapping.

If each of the red, green, and blue subpixels are arranged along the short axis direction of the liquid crystal panel 6 as shown in FIGS. 18 and 20, and two adjacent subpixels share a gate line, respectively, each of FIG. And the period between the generation of the scan pulse supplied to the k + 1 th gate line and the generation of the scan pulse supplied to the k + 3 th gate line is approximately one horizontal as shown in FIG. 21. The scan pulses satisfying the period 1H and generated within the period may be superimposed and non-overlapping to obtain a pre-charge effect of data in order to secure the charging time of the liquid crystal cell.

The source drive ICs 1a and 1b include a register, a shift register, a latch 102, a digital to analog converter (hereinafter referred to as a "DAC"), an output buffer, and the like. Sampling and latching the digital video data RGB inputted through the &lt; RTI ID = 0.0 &gt;), &lt; / RTI &gt; The source drive ICs 1a and 1b are disposed below the data of the pixels disposed above the pixel array 10 because the data lines D1 to Dn are arranged along the short axis direction of the liquid crystal panel 6. Data is sampled in the order of the data of the acquired pixels, or vice versa. The data voltages output from the source drive ICs 1a and 1b are generated in units of 1/3 horizontal period or 1/2 horizontal period or 1 horizontal period in synchronization with the scan pulse.

The source PCB 4 is mounted with a timing controller 3, a level shifter 7, a DC-DC converter and a gamma reference voltage generator circuit (not shown).

The timing controller 3 controls the gate control signal GDC and the data driving circuit 32 for controlling the gate driving circuit 33 by using the vertical / horizontal synchronization signals Vsync and Hsync and the clock CLK. To generate a data control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity control signal POL, and the like. The gate control signal GDC includes a gate shift clock, a gate output signal, a gate start pulse, and the like.

As shown in Fig. 10, the timing controller 3 has a horizontal pulse width of one scan pulse in a condition that the period between the occurrence of the k + 1th scan pulse and the occurrence of the k + 4th scan pulse satisfies one horizontal period. If less than the period 1H, the frequencies of the gate control signal GDC and the data control signal DDC are modulated faster than the reference frequency. As shown in Fig. 19, the timing controller 3 has a horizontal pulse width of one scan pulse in a condition that the period between the occurrence of the k + 1 th scan pulse and the occurrence of the k + 3 th scan pulse satisfies one horizontal period. If less than the period 1H, the frequencies of the gate control signal GDC and the data control signal DDC are modulated faster than the reference frequency. In addition, the timing controller 3 selects the digital video data RGB in accordance with the data sampling order of the data line of the pixel array 10, the liquid crystal cell, and the source drive ICs 1a and 1b. Realign. The level shifter 7 receives the low potential / high potential DC input voltage and shifts the voltages to increase the swing width to the TFT operation voltage of the pixel array 10 and the gate high voltage (VGH) and the gate low. Generates a low voltage (VLH).

The FPC 5 is connected to signal pads of the liquid crystal panel 6 and output pads of the source PCB 5 electrically connected to the gate driving circuit 2 and the input terminals of the source drive ICs 1a and 1b. The data voltage, gate high / low voltage, and various control signals from the source PCB 5 are transmitted to the gate driving circuit 2 and the source drive ICs 1a and 1b.

FIG. 9 shows a first embodiment of the pixel array shown in FIG. 8.

Referring to FIG. 9, in the pixel array 10, data lines D1 to Dn are formed along a major axis direction x of the liquid crystal panel 6 on the TFT array substrate, and gate lines G1 to Gm. The liquid crystal panel 6 is formed along the short axis direction y. Each of the red color filter, the green color filter, and the blue color filter formed on the color filter array substrate of the pixel array 10 is disposed along the minor axis direction y of the liquid crystal panel 6. Therefore, each of the red subpixel, the green subpixel, and the blue subpixel in the pixel array 10 is disposed along the minor axis direction y of the liquid crystal panel 6.

FIG. 10 illustrates a data voltage and a scan pulse for driving the pixel array 10 as shown in FIG. 9.

Referring to FIG. 10, the gate driving circuit 2 sequentially generates scan pulses smaller than one horizontal period 1H and supplies the scan pulses to the gate lines G1 to Gm. The pulse width of the scan pulses is less than one horizontal period (1H) within the condition that the period between the occurrence of the k + 1th scan pulse and the occurrence of the k + 4th scan pulse satisfies one horizontal period.

The source drive ICs 1a and 1b are synchronized with the scan pulses and the red data voltages R1 to R4 for one line for approximately 1/3 horizontal period (1/3 H) in each of the data lines D1 to Dn. After outputting all of them, output all the green data voltages G1 to G4 for one line for approximately 1/3 horizontal period (1/3 H), and then output for approximately 1/3 horizontal period (1/3 H). The blue data voltages B1 to B4 for one line are all output.

In the driving method of the liquid crystal display according to the first exemplary embodiment of the present invention, as described above, the data lines D1 to Dn are arranged along the short axis direction y of the liquid crystal panel 6, and the red, green, and blue colors Since the subpixels are arranged along the major axis direction (x) of the liquid crystal panel 6 as shown in FIG. 9, a data voltage of a color corresponding to each of the red, green, and blue subpixels can be supplied during one horizontal period. Reduce the frequency of data voltage generation to less than 1/3

In order to supply the data voltages to the data lines D1 to Dn as shown in FIG. 10, the data order supplied to the source drive ICs 1a and 1b must be different from the order in which the data lines are supplied to the signal lines as shown in FIG. 2. . To this end, the driving method of the liquid crystal display device according to the first embodiment of the present invention is a timing controller 3 or a graphics card of an external system for supplying digital video data to the timing controller 3 from the outside through an interface circuit. It is necessary to rearrange the data based on the arrangement of signal lines and subpixels as shown in FIG. 9.

Among graphic cards currently on the market, based on the signal wiring and sub-pixel arrangement of the prior art as shown in FIG. There is a graphics card that supports the so-called Pivot function to align the. If the pivot is selected as the "vertical view" option on such a graphics card, data output as shown in FIG. 10 is possible.

FIG. 11 shows an example of a timing controller 3 that aligns digital video data to the signal wiring and subpixel arrangement of FIGS. 9 and 10.

Referring to FIG. 11, the timing controller 3 includes a memory 31.

The memory 31 is red digital video data inputted in the order of R1, R2, R3 ... through the first data input line, and green digital inputted in order of G1, G2, G3 ... through the second data input line. Video data and blue digital video data input in the order of B1, B2, B3 ... are received through the third data input line. The memory 31 rearranges the data under the control of a memory controller (not shown), and R1, R2, R3 ... Rn, G1, G2, G3 ... Gn, B1, B2, B3. Output in .Bn order. The digital video data output from this memory 31 is tripled, so that the period compared to the input data of the timing controller 3 is shortened by 1/3.

FIG. 12 is a view for explaining the configuration and operation of the source drive ICs 1a and 1b for supplying data as shown in FIG. 10, and shows the first source drive IC 1a in detail.

Referring to FIG. 12, the first source drive IC 1a may include a shift register 101, a first latch 102, a second latch 103, a DAC 104, an output buffer 105, and a register 106. ).

The register 106 temporarily stores the digital video data RGB from the timing controller 3 and supplies the digital video data RGB to the first latch 102.

The shift register 101 shifts the source start pulse SSP from the timing controller 3 in accordance with the source shift clock signal SSC to generate a sampling signal. In addition, the shift register 101 shifts the source start pulse SSP to transfer the carry signal CAR to the integrated circuit of the next stage.

The first latch 102 sequentially samples and latches the digital video data RGB according to the sampling signal input from the shift register 101, and then simultaneously latches the latched digital video data RGB to the second latch 103. Supplies).

The second latch 103 latches the data from the first latch 102 until the last data of one line, that is, the nth data, is latched in the second latch of the second source drive IC 1a, and then 3 In response to the assigned source output signal SOE, the latched digital video data is output simultaneously with the second latch of the second source drive ICs 1a.

The DAC 104 converts the digital video data RGB from the second latch 104 into a positive / negative analog data voltage using gamma reference voltages GMA1 to GMA6.

The output buffer 105 is connected to each of the data lines D1 to D n / 2 to provide an output buffer for reducing the loss of data voltages supplied from the DAC 104 to the data lines D1 to D n / 2. Include.

FIG. 13 shows a second embodiment of the pixel array shown in FIG.

Referring to FIG. 13, in the pixel array 10, data lines D1 to Dn are formed along the major axis direction x of the liquid crystal panel 6 on the TFT array substrate, and gate lines G1 to Gm. The liquid crystal panel 6 is formed along the short axis direction y. Each of the red color filter, the green color filter, and the blue color filter formed on the color filter array substrate of the pixel array 10 is disposed along the major axis direction x of the liquid crystal panel 6. Therefore, each of the red subpixel, the green subpixel, and the blue subpixel in the pixel array 10 is disposed along the major axis direction x of the liquid crystal panel 6.

FIG. 14 illustrates a data voltage and a scan pulse for driving the pixel array 10 as shown in FIG. 13.

Referring to FIG. 14, the gate driving circuit 2 sequentially generates scan pulses having a pulse width of approximately one horizontal period 1H, and supplies the scan pulses to the gate lines G1 to Gm.

The source drive ICs 1a and 1b output a red data voltage, a green data voltage and a blue data voltage for one line to each of the data lines D1 to Dn in approximately one horizontal period 1H in synchronization with the scan pulse. After that, the red data voltage, the green data voltage, and the blue data voltage for one line of the next line are output.

In the driving method of the liquid crystal display according to the second exemplary embodiment of the present invention, as described above, the data lines D1 to Dn are arranged along the minor axis direction y of the liquid crystal panel 6 and have red, green and blue colors. Since the subpixels are arranged along the short axis direction y of the liquid crystal panel 6 as shown in FIG. 13, the pulse width of the scan pulse and the generation period of the data voltage are controlled to approximately one horizontal period 1H.

Since the data supply method as shown in FIG. 14 is substantially the same as that of FIG. 3, there is no need to rearrange data or change a driving frequency.

FIG. 15 is a diagram for describing the configuration and operation of the source drive ICs 1a and 1b for generating the data voltage as shown in FIG. 14, and illustrates the first source drive IC 1a in detail.

Referring to FIG. 15, the first source drive IC 1a may include a shift register 201, a first latch 202, a second latch 203, a DAC 204, an output buffer 205, and a register 206. ). Since the digital video data input from the timing controller 3 is supplied to the first source drive IC 1a in the order of R1, G1, B1 ... R2, G2, B2 ... In each of the two latches 202 and 203, digital video data are arranged in order of R, G and B from left to right.

FIG. 16 illustrates a common electrode COM for supplying a common voltage Vcom to a common electrode of a liquid crystal cell in a liquid crystal display and a driving method thereof according to an exemplary embodiment of the present invention.

Referring to FIG. 16, the common voltage supply line COML is disposed along the same direction as the data lines D1 to Dn, that is, along the short axis direction y of the liquid crystal panel 6, and thus the data lines D1 to Dn. Are formed on the TFT array substrate of the liquid crystal panel 6 in parallel with each other and do not cross the data lines D1 to Dn. Therefore, the common voltage COML is not affected by the data voltage and thus does not change due to the data voltage.

In the liquid crystal display according to the exemplary embodiment of the present invention, n data lines D1 to Dn are arranged side by side along the short axis direction y of the liquid crystal panel 6, and each data line D1 to Dn is a liquid crystal. It is disposed long along the major axis direction x of the panel 6. Therefore, as the data lines D1 to Dn become longer, the resistance of the data line and the parasitic capacitance of the data line may increase, thereby increasing the RC delay of the data voltage. In order to reduce the RC delay, the data lines D1 to Dn are formed of low resistance metal, for example, copper (Cu), or the data lines D1 to Dn are divided and divided as shown in FIG. 17. There is a method of dividing each of the left and right sides of each of them into different source drive ICs 1a to 1d. Even if the method shown in FIG. 17 is applied, the present invention can reduce the number of source drive ICs at the same resolution as compared with the related art. For example, if a conventional liquid crystal display as shown in FIG. 1 has five source drive ICs having 618 output channels if data lines are arranged at XGA resolution (1024 * 768), the present invention is similar to that of FIG. Four source drive ICs are required.

18 and 20 show a third embodiment of the pixel array shown in FIG.

Referring to FIG. 18, the pixel array 10 according to the third exemplary embodiment of the present invention may include data lines D1 to D2n formed along a major axis direction x of the liquid crystal panel 6 on a TFT array substrate, and a liquid crystal. Gate lines G1 to G3m / 2 are formed along the minor axis y of the panel 6. The color filter array substrate of the pixel array 10 according to the third embodiment of the present invention includes a red color filter, a green color filter, and a blue color filter, and each of the red color filter, the green color filter, and the blue color filter The liquid crystal panel 6 is disposed along the minor axis direction y. Therefore, each of the red subpixel, the green subpixel, and the blue subpixel in the pixel array 10 is disposed along the minor axis direction y of the liquid crystal panel 6. Among the two subpixels sharing one gate line, the subpixels R11 to Rn1, B11 to Bn1, G12 to Gn2, and R13 to the left of the shared gate lines G1 to G (3m / 2) are included. Rn3, ... G1m to Gnm) are each supplied with data from radix data lines D1, D3, ... D (2n-1).

Among the two subpixels sharing one gate line, the subpixels G11 to Gn1, R12 to Rn2, B12 to Bn2, and G13 to disposed on the right side of the shared gate lines G1 to G (3m / 2). Gn3, ... B1m to Bnm) are each supplied with data from even data lines D2, D4, ... D2n.

To this end, a thin film transducer is formed in a region on the left side of the intersection point of the shared gate line and the odd data line to switch data from the odd data line into subpixels arranged on the left side of the shared gate lines.

A thin film transducer is formed in a region on the right side of the intersection point of the shared gate line and the even data line to switch data from the even data line to subpixels disposed on the right side of the shared gate lines.

In the pixel array 10 according to the third exemplary embodiment of the present invention, two of the R, G, and B sub-pillars constituting one pixel receive data from an odd (or even) data line, and the other one Receive data from even (or odd) data lines. Therefore, the pixel array 10 according to the third embodiment of the present invention is not limited to FIG. 18 but may be configured in various forms, for example, as shown in FIG. 20. As shown in FIG. 20, in the pixel array 10 according to the third exemplary embodiment of the present invention, data lines D1 to D2n are formed along a long axis direction x of the liquid crystal panel 6 on a TFT array substrate. Lines G1 to G3m / 2 are formed along the short axis direction y of the liquid crystal panel 6. Each of the red color filter, the green color filter, and the blue color filter formed on the color filter array substrate of the pixel array 10 is disposed along the minor axis direction y of the liquid crystal panel 6. Therefore, each of the red subpixel, the green subpixel, and the blue subpixel in the pixel array 10 is disposed along the minor axis direction of the liquid crystal panel 6. Here, 4i + 1 (i is 0 or a natural number) and 4i + 2th disposed on the left side of the shared gate lines G1 to G (3m / 2) among two subpixels sharing one gate line. The subpixels R11 to Rn1, B11 to Bn1, ... R1 (m-2) to Rn (m-2) receive data from the odd data lines, respectively, and are the 4i + 3th and 4i + 4th subs. The pixels G12 to Gn2, R13 to Rn3, ... G1m to Gnm are respectively supplied with data from the even data line. Also, 4i + 1st and 4i + 2th subpixels G11 to Gn1 disposed on the right side of the shared gate lines G1 to G (3m / 2) among two subpixels sharing one gate line. , R12 to Rn2, ... G1 (m-2) to Gn (m-2) are respectively supplied with data from the even data line, and 4i + 3rd and 4i + 4th subpixels B12 to Bn2, G13 to Gn3, ... B1m to Bnm) are each supplied with data from the radix data line.

To this end, a thin film transducer formed at the left region of the intersection point of the shared gate line and the odd data line switches the data from the odd data line to 4i + 1 and 4i + 2th subpixels disposed to the left of the shared gate lines. . The thin film transformer formed at the right side of the intersection point of the shared gate line and the odd data line switches the data from the odd data line to 4i + 3 and 4i + 4th subpixels disposed on the right side of the shared gate lines.

The thin film transformer formed at the right side of the intersection of the shared gate line and the even data line switches the data from the even data line to 4i + 1 and 4i + 2th subpixels disposed on the right side of the shared gate lines. The thin film transformer formed at the left side of the intersection of the shared gate line and the even data line switches the data from the even data line to 4i + 3 and 4i + 4th subpixels disposed to the left of the shared gate lines.

FIG. 19 illustrates a data voltage and a scan pulse for driving the pixel array 10 as shown in FIG. 18. FIG. 21 illustrates a data voltage and a scan pulse for driving the pixel array 10 as shown in FIG. 19.

19 and 21, the gate driving circuit 2 sequentially generates scan pulses smaller than one horizontal period 1H, and supplies the scan pulses to the gate lines G1 to G (3m / 2). do. The pulse width of the scan pulses is smaller than one horizontal period 1H within the condition that the period between the occurrence of the k + 1th scan pulse and the occurrence of the k + 3th scan pulse satisfies one horizontal period 1H.

The source drive ICs 1a and 1b output a data voltage to each of the data lines D1 to D2n in synchronization with the scan pulse. For example, the source drive ICs 1a and 1b output about one line of red and green data voltages R11 to Gn1 for approximately one half horizontal period (1/2 H), and then approximately one half horizontal. During the period (1/2 H), both the blue and red data voltages B11 to Rn1 for one line are output.

According to the driving method of the liquid crystal display according to the third exemplary embodiment of the present invention, as described above, the data lines D1 to Dn are arranged along the major axis direction x of the liquid crystal panel 6, and the red, green, and blue Subpixels are arranged along the major axis direction x of the liquid crystal panel 6 in order. In addition, two subpixels disposed between the shared gate lines are simultaneously synchronized with the scan pulses from the gate lines so as to receive data voltages from odd or even data lines. Therefore, the driving method of the liquid crystal display according to the third exemplary embodiment of the present invention provides a generation period of the data voltage so that the data voltage of the color corresponding to each of the red, green, and blue subpixels can be supplied during one horizontal period. Reduce to half the contrast. Table 1 compares this third embodiment of the present invention with the prior art and the first and second embodiments.

Prior art First and second embodiment Third embodiment Number of data lines 1024 * + = 3072 768 768 * 2 = 1536 Gate line number 768 1024 * 3 = 3072 1024 * 3/2 = 1536

As shown in Table 1, the liquid crystal display according to the third embodiment of the present invention reduces the number of data lines by half and the number of gate lines by half compared to the first and second embodiments. Accordingly, the liquid crystal display according to the third embodiment of the present invention can reduce the number of source drive ICs at the same resolution as compared with the conventional one, and the number of source drive ICs is increased even though the number of data lines is increased than the first and second embodiments. Even if increases, the number of gate lines can be reduced to easily secure the charging time of the data lines.

In order to supply the data voltages to the data lines D1 to D2n as shown in FIGS. 19 and 21, the data order supplied to the source drive ICs 1a and 1b is different from the order in which the data lines are supplied to the signal lines as shown in FIG. 2. You must do it differently. To this end, the driving method of the liquid crystal display device according to the third embodiment of the present invention is a timing controller 3 or a graphics card of an external system for supplying digital video data to the timing controller 3 from the outside through an interface circuit. It is necessary to rearrange the data based on the arrangement of signal lines and subpixels as shown in FIGS. 18 and 20.

FIG. 22 shows an example of a timing controller 3 that aligns digital video data to the signal wiring and subpixel arrangement of FIGS. 18 and 19.

Referring to FIG. 22, the timing controller 3 includes a memory 131.

The memory 131 may include red digital video data inputted in an order of R11 to Rnm through a first data input line, green digital video data inputted in an order of G11 to Gnm through a second data input line, and a third data input line. Blue digital video data is input through B11 to Bnm. The memory 131 rearranges the data under the control of a memory controller (not shown) and passes through the data output lines R11, G11, R21, G21 ... Gn1, B11, R12, B21, R22 ... Rn2, G12, Outputs B12, G22, B22 ... Bn2, R13, G13, R23, G23 ... Gn3. The digital video data output from the memory 131 is doubled so that the period compared to the input data of the timing controller 3 is shortened by half.

FIG. 23 is a view for explaining the configuration and operation of the source drive ICs 1a and 1b for generating the data voltage as shown in FIG. 22, and shows the first source drive IC 1a in detail.

Referring to FIG. 23, a first source drive IC 1a according to an exemplary embodiment of the present invention may include a shift register 301, a first latch 302, a second latch 303, a DAC 304, and an output buffer ( 305, and a register 306. The first source drive IC 1a is connected to the timing controller 3 by R11, G11, R21, G21 ... Gn1, B11, R12, B21, R22 ... Rn2, G12, B12, G22, B22 ... Digital video data input in the order of Bn2, R13, G13, R23, G23 ... Gn3 is supplied to the respective data lines D1 to Dn via the first and second latches 302 and 303.

24 shows an example of a timing controller 3 that aligns digital video data to the signal wiring and subpixel arrangement of FIGS. 20 and 21.

Referring to FIG. 24, the timing controller 3 includes a memory 231.

The memory 231 may include red digital video data input in the order of R11 to Rnm through the first data input line, green digital video data input in the order of G11 to Gnm through the second data input line, and the third data input line. Blue digital video data is input through B11 to Bnm. The memory 231 rearranges the data under the control of a memory controller (not shown) and through the data output lines R11, G11, R21, G21 ... Gn1, B11, R12, B21, R22 ... Rn2, B12, Outputs G12, B22, G22 ... Gn2, G13, R13, G23, R23 ... Rn3. The digital video data output from this memory 231 is doubled, so that the period compared to the input data of the timing controller 3 is shortened by half.

FIG. 25 is a diagram for describing the configuration and operation of the source drive ICs 1a and 1b for generating the data voltage as shown in FIG. 24, and shows the first source drive IC 1a in detail.

Referring to FIG. 25, the first source drive IC 1a may include a shift register 401, a first latch 402, a second latch 403, a DAC 404, an output buffer 405, and a register 406. ). This first source drive IC 1a is connected to the timing controller 3 by R11, G11, R21, G21 ... Gn1, B11, R12, B21, R22 ... Rn2, B12, G12, B22, G22 ... Digital video data input in the order of Gn2, G13, R13, G23, R23 ... Rn3 is supplied to the respective data lines D1 to Dn via the first and second latches 402 and 403.

As described above, the liquid crystal display and the driving method thereof according to the present invention can reduce the number of expensive source drive ICs required for driving the data lines by forming the data lines in the short axis direction of the liquid crystal panel to reduce the number of data lines. In addition, the FPC and PCB can be made small and simple. In addition, the liquid crystal display and the driving method thereof according to the present invention can prevent the fluctuation of the common voltage caused by the intersection of the signal lines because the data line and the common voltage line are parallel. In addition, the liquid crystal display and the driving method thereof according to the present invention reduce the number of data lines and share one gate line with two subpixels, thereby reducing the number of gate lines to easily secure the charging time of the data voltage. can do.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (38)

A liquid crystal panel having a plurality of data lines formed along a long axis direction of a substrate and a plurality of gate lines formed along a short axis direction of the substrate to intersect the data lines; A data driver circuit for supplying a data voltage to the data line; A gate driving circuit supplying a scan pulse to the gate line; And And a timing controller for supplying digital video data to the data driving circuit and controlling the data driving circuit and the gate driving circuit. The method of claim 1, The liquid crystal panel, A plurality of red subpixels disposed along a short axis of the substrate; A plurality of green subpixels disposed along the minor axis of the substrate; And And a plurality of blue subpixels arranged along a short axis direction of the substrate. The method of claim 2, And the gate driving circuit generates the scan pulse with a pulse width smaller than one horizontal period. The method of claim 3, wherein The data driving circuit After supplying the red data voltage corresponding to the red digital video data to the data lines for 1/3 horizontal period, the data voltage of the green corresponding to the green digital video data is supplied to the data lines during the 1/3 horizontal period. And supplying blue data voltages corresponding to blue digital video data to the data lines during the 1/3 horizontal period. The method of claim 1, The liquid crystal panel, A plurality of red subpixels disposed along a long axis of the substrate; A plurality of green subpixels disposed along a long axis of the substrate; And And a plurality of blue subpixels disposed along the long axis of the substrate. The method of claim 5, wherein And the gate driving circuit generates the scan pulse with a pulse width of one horizontal period. The method of claim 6, The data driving circuit And red, green, and blue data voltages supplied to different data lines during the one horizontal period. A liquid crystal panel having a plurality of odd and even data lines formed along a long axis direction of a substrate, and a plurality of gate lines formed along a short axis direction of the substrate so as to intersect the data lines; A data driver circuit for supplying a data voltage to the data line; A gate driving circuit supplying a scan pulse to the gate line; And A timing controller for supplying digital video data to the data driving circuit and controlling the data driving circuit and the gate driving circuit; And two subpixels disposed at the left and right sides of the gate line share the gate line. The method of claim 8, The liquid crystal panel, A plurality of red subpixels disposed along a short axis of the substrate; A plurality of green subpixels disposed along the minor axis of the substrate; And And a plurality of blue subpixels arranged along a short axis direction of the substrate. The method of claim 9, Among the plurality of red, green, and blue subpixels, the subpixels disposed on the left side of the gate line with the gate line interposed therebetween receive the data voltage from the odd data line, and the gate with the gate line interposed therebetween. And the subpixels disposed on the right side of the line receive the data voltage from the even data line. The method of claim 10, And the gate driving circuit generates the scan pulse with a pulse width of 1/2 horizontal period. The method of claim 11, The data driving circuit 1/2 horizontal period after supplying the red data voltage corresponding to the red digital video data and the green data voltage corresponding to the green digital video data to the odd and even data lines, respectively, during the 1/2 horizontal period. While the blue data voltage corresponding to the blue digital video data and the red data voltage corresponding to the red digital video data are supplied to the odd and even data lines, respectively, and then the green digital video for 1/2 horizontal period. And a green data voltage corresponding to data and a blue data voltage corresponding to blue digital video data to the odd and even data lines, respectively. The method of claim 9, Among the plurality of red, green, and blue subpixels, 4i + 1 (i is 0 or a natural number) and 4i + 2th subpixels disposed on the left side of the gate line with the gate line interposed therebetween. And the 4i + 3th and 4i + 4th subpixels receive the data voltage from the even data line. The method of claim 9, Among the plurality of red, green, and blue subpixels, 4i + 1 (i is 0 or a natural number) and 4i + 2th subpixels disposed on the right side of the gate line with the gate line interposed therebetween. And the 4i + 3th and 4i + 4th subpixels receive the data voltage from the odd data line. The method according to claim 13 or 14, And the gate driving circuit generates the scan pulse with a pulse width of 1/2 horizontal period. The method of claim 15, The data driving circuit, 1/2 horizontal period after supplying the red data voltage corresponding to the red digital video data and the green data voltage corresponding to the green digital video data to the odd and even data lines, respectively, during the 1/2 horizontal period. While the blue data voltage corresponding to the blue digital video data and the red data voltage corresponding to the red digital video data are supplied to the odd and even data lines, respectively, and then the green digital video for 1/2 horizontal period. And a green data voltage corresponding to data and a blue data voltage corresponding to blue digital video data to the even and odd data lines, respectively. The method according to any one of claims 2, 5 and 9, A common electrode for supplying the same common voltage to the common electrodes of the subpixels; And the common electrode is parallel to the data line and does not cross the data line. The method of claim 4, wherein The timing controller, Storing the red, green and blue digital video data, supplying the red digital video data for one line to the data driving circuit, and then supplying the green digital video data for one line to the data driving circuit. And a memory for supplying the blue digital video data for one line to the data driving circuit after the supply. The method of claim 12, The timing controller, Storing the red, green, and blue digital video data, supplying one line of the red and green digital video data to the data driving circuit, and storing one line of the blue and red digital video data. And a memory for supplying the green and blue digital video data for one line to the data driving circuit after being supplied to the data driving circuit. The method according to any one of claims 2, 5 and 9, A plurality of thin film transistors formed at the intersections of the data lines and the gate lines and supplying data voltages from the data lines to the pixel electrodes of the subpixels in response to the scan pulse; And the elements of the gate driving circuit are formed on the substrate simultaneously with the thin film transistor. Forming a plurality of data lines in the substrate along a long axis direction of the substrate and forming a plurality of gate lines in the substrate along the minor axis direction of the substrate so as to intersect the data lines; Supplying a data voltage to the data line; And And supplying a scan pulse to the gate line. The method of claim 21, Disposing a plurality of red subpixels along a short axis of the substrate; Disposing a plurality of green subpixels along a short axis of the substrate; And And arranging a plurality of blue subpixels along a short axis direction of the substrate. The method of claim 22, And the scan pulses are generated with a pulse width less than one horizontal period. The method of claim 23, The step of supplying the data voltage, Supplying red data voltages corresponding to red digital video data to the data lines during a 1/3 horizontal period; Supplying green data voltages corresponding to the green digital video data to the data lines during the 1/3 horizontal period; And And supplying blue data voltages corresponding to blue digital video data to the data lines during the 1/3 horizontal period. The method of claim 21, Arranging a plurality of red subpixels along a long axis of the substrate; Disposing a plurality of green subpixels along a long axis of the substrate; And And arranging a plurality of blue subpixels along a long axis direction of the substrate. The method of claim 25, And the scan pulses are generated with a pulse width of one horizontal period. The method of claim 26, The step of supplying the data voltage, And supplying red, green, and blue data voltages to different data lines during the one horizontal period. Forming a plurality of odd and even data lines on the substrate along the major axis of the substrate and forming a plurality of gate lines on the substrate along the minor axis of the substrate to intersect the data lines; Disposing subpixels such that two subpixels disposed at left and right sides with the gate line share the gate line; Supplying a data voltage to the data line; And And supplying a scan pulse to the gate line. The method of claim 28, Arranging the subpixels, Disposing a plurality of red subpixels along a short axis of the substrate; Disposing a plurality of green subpixels along a short axis of the substrate; And And arranging a plurality of blue subpixels along a short axis direction of the substrate. The method of claim 29, Among the plurality of red, green, and blue subpixels, the subpixels disposed on the left side of the gate line with the gate line interposed therebetween receive the data voltage from the odd data line, and the gate with the gate line interposed therebetween. And the subpixels disposed on the right side of the line are supplied with the data voltage from the even data line. The method of claim 30, And the scan pulses are generated with a pulse width of 1/2 horizontal period. The method of claim 31, wherein The step of supplying the data voltage, Supplying the red data voltage corresponding to the red digital video data and the green data voltage corresponding to the green digital video data to the odd and even data lines, respectively, during a 1/2 horizontal period; Supplying the blue data voltage corresponding to the blue digital video data and the red data voltage corresponding to the red digital video data to the odd and even data lines, respectively, during a 1/2 horizontal period; And Supplying the green data voltage corresponding to the green digital video data and the blue data voltage corresponding to the blue digital video data to the odd and even data lines, respectively, for a 1/2 horizontal period. A method of driving a liquid crystal display device. The method of claim 29, Among the plurality of red, green, and blue subpixels, 4i + 1 (i is 0 or a natural number) and 4i + 2th subpixels disposed on the left side of the gate line with the gate line interposed therebetween. And the 4i + 3th and 4i + 4th subpixels receive the data voltage from the even data line. The method of claim 29, Among the plurality of red, green, and blue subpixels, 4i + 1 (i is 0 or a natural number) and 4i + 2th subpixels disposed on the right side of the gate line with the gate line interposed therebetween. And the 4i + 3th and 4i + 4th subpixels are supplied with the data voltages from the odd data lines. The method of claim 33 or 34, And the scan pulses are generated with a pulse width of 1/2 horizontal period. 36. The method of claim 35 wherein The step of supplying the data voltage, Supplying the red data voltage corresponding to the red digital video data and the green data voltage corresponding to the green digital video data to the odd and even data lines, respectively, during a 1/2 horizontal period; Supplying the blue data voltage corresponding to the blue digital video data and the red data voltage corresponding to the red digital video data to the odd and even data lines, respectively, during a 1/2 horizontal period; And Supplying the green data voltage corresponding to the green digital video data and the blue data voltage corresponding to the blue digital video data to the even and odd data lines, respectively, for a 1/2 horizontal period. A method of driving a liquid crystal display device. The method according to any one of claims 22, 25 and 29, Forming a common electrode on the substrate, the common electrode being parallel to the data line; The same common voltage is supplied to each of the subpixels through the common electrode, and the common electrode does not cross the data line. The method according to any one of claims 22, 25 and 29, Forming a plurality of thin film transistors at the intersections of the data lines and the gate lines for supplying data voltages from the data lines to the pixel electrodes of the subpixels in response to the scan pulse; And a gate driving circuit for generating the scan pulse on the substrate at the same time as the thin film transistor.

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