KR20220069675A - Data driving circuit, controller and display device - Google Patents

Abstract

Embodiments of the present invention relate to a data driving circuit, a controller, and a display device, wherein the display device performs display driving by outputting fewer internal data enable signals than external data enable signals, thus preventing an increase in the load of data driving circuit caused by high-speed driving. In addition, some internal data enable signals are output during a blank period to prevent a decrease in an interval between the internal data enable signals and increase the number of the internal data enable signals, and thus, image quality displayed through a display panel can be improved while preventing an increase in the load of the data driving circuit.

Description

DATA DRIVING CIRCUIT, CONTROLLER AND DISPLAY DEVICE

Embodiments of the present invention relate to a data driving circuit, a controller, and a display device.

As the information society develops, the demand for a display device for displaying an image is increasing, and various types of display devices such as a liquid crystal display device and an organic light emitting display device are utilized.

The display device may include a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels are disposed, and various driving circuits and a controller for driving the display panel.

The display device may display an image by driving a plurality of gate lines and a plurality of data lines during one frame period and controlling the brightness of a plurality of sub-pixels.

As the driving frequency of the display device increases, the number of frames for displaying images per unit time increases, so that smoother image display is possible and good image quality can be provided.

On the other hand, as the driving frequency of the display device increases, problems may occur due to heat generation of the driving circuit and increase in power consumption. In addition, as the amount of computation increases for high-speed driving, there is a problem in that the size of the controller for controlling the driving circuit increases.

Embodiments of the present invention provide a method for preventing an increase in the temperature and power consumption of a data driving circuit included in a display device driven at a high speed with a high driving frequency and an increase in the size of the controller.

Embodiments of the present invention provide a method for reducing the load of a data driving circuit and the amount of computation of a controller when a display device is driven at a high speed, and preventing deterioration of image quality of an image displayed through a display panel.

Embodiments of the present invention control a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are disposed, a data driving circuit supplying a data voltage to the plurality of data lines, and a data driving circuit A display device including a controller is provided.

The controller may receive a plurality of external data enable signals from the outside and output the plurality of internal data enable signals to the data driving circuit.

At least one of the number and interval at which the plurality of internal data enable signals are output during one frame period may be different from at least one of the number and interval at which the plurality of external data enable signals are input during one frame period.

The number of times that the plurality of internal data enable signals are output during one frame period may be smaller than the number of times that the plurality of external data enable signals are input.

An interval at which the plurality of internal data enable signals are output during one frame period may be greater than an interval at which the plurality of external data enable signals are input.

At least one of the plurality of internal data enable signals may be output in a blank period included in one frame period. A scan signal may be supplied to at least one of the plurality of gate lines in response to at least one internal data enable signal output in the blank period.

In another aspect, in the display device according to the embodiments of the present invention, the number and interval at which the plurality of internal data enable signals are output during one frame period during the period in which the display panel is driven at the first driving frequency is determined by the plurality of external data The number and interval at which the enable signals are input are the same, and at least one of the number and interval at which the plurality of internal data enable signals are output during one frame period during the period in which the display panel is driven at the second driving frequency is the plurality of external data It may be different from at least one of the number and interval at which the enable signals are input.

Here, the second driving frequency may be greater than the first driving frequency.

In another aspect, embodiments of the present invention provide a data driving circuit that receives a plurality of internal data enable signals and outputs a data voltage during one frame period, wherein data corresponding to each of the plurality of internal data enable signals is provided. A data driving circuit that outputs a voltage and input at least one of the plurality of internal data enable signals in a blank period of one frame period is provided.

In another aspect, embodiments of the present invention provide a controller that receives a plurality of external data enable signals from the outside and outputs the plurality of internal data enable signals to a data driving circuit, wherein the plurality of internal data enable signals are At least one of the number of times and the interval output during one frame period is different from at least one of the number and interval at which the plurality of external data enable signals are input during one frame period.

According to the embodiments of the present invention, when the display device is driven at a high speed, the number of scans of the data driving circuit is reduced and an image is displayed, thereby reducing the increase in the load of the data driving circuit and the increase in the amount of calculation of the controller according to the high speed driving of the display device. can

According to embodiments of the present invention, by changing the scanning method of the data driving circuit according to the characteristics of the image displayed by the display panel, it is possible to reduce the number of scans of the data driving circuit and maintain image quality according to high-speed driving of the display device. .

1 is a diagram schematically illustrating a configuration included in a display device according to an embodiment of the present invention.
2 is a diagram illustrating an example of a circuit structure of a sub-pixel included in a display device according to embodiments of the present invention.
3 is a diagram schematically illustrating an example of a configuration of a controller included in a display apparatus according to embodiments of the present invention.
4A to 4C are diagrams illustrating examples of displaying an image according to a driving method when a display device according to embodiments of the present invention is driven at a high speed.
5 is a diagram illustrating an example of a signal input or output from the display device when the display device is driven according to the driving method shown in FIG. 4A .
6 is a diagram illustrating an example of a signal input or output from the display device when the display device is driven according to the driving method shown in FIG. 4B .
7 is a diagram illustrating an example of a signal input or output from the display device when the display device is driven according to the driving method shown in FIG. 4C .
8 to 10 are diagrams illustrating other examples of signals input or output from the display apparatus when the display apparatus is driven at a high speed according to embodiments of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted. When "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it may include a case in which the plural is included unless otherwise explicitly stated.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms.

In the description of the positional relationship of the components, when it is described that two or more components are "connected", "coupled" or "connected", two or more components are directly "connected", "coupled" or "connected" ", but it will be understood that two or more components and other components may be further "interposed" and "connected," "coupled," or "connected." Here, other components may be included in one or more of two or more components that are “connected”, “coupled” or “connected” to each other.

In the description of the temporal relationship or flow relationship of the components, for example, a temporal precedence or flow precedence relationship is When described, cases that are not continuous unless "immediately" or "directly" are used may also be included.

On the other hand, when numerical values or corresponding information (eg, level, etc.) for a component are mentioned, even if there is no separate explicit description, the numerical value or the corresponding information is based on various factors (eg, process factors, internal or external shock, Noise, etc.) may be interpreted as including an error range that may occur.

1 is a diagram schematically illustrating a configuration included in a display apparatus 100 according to embodiments of the present invention.

Referring to FIG. 1 , the display device 100 includes a display panel 110 , a gate driving circuit 120 for driving the display panel 110 , a data driving circuit 130 , a controller 140 , and the like. can do.

The display panel 110 may include an active area AA in which a plurality of subpixels SP are disposed, and a non-active area NA positioned outside the active area AA.

A plurality of gate lines GL and a plurality of data lines DL may be disposed on the display panel 110 . The subpixel SP may be positioned in a region where the gate line GL and the data line DL intersect.

The gate driving circuit 120 is controlled by the controller 140 , and sequentially outputs scan signals to the plurality of gate lines GL disposed on the display panel 110 to drive timing of the plurality of subpixels SP. to control

The gate driving circuit 120 may include one or more gate driver integrated circuits (GDICs), and may be located on only one side or both sides of the display panel 110 depending on the driving method. may be

Each gate driver integrated circuit (GDIC) is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, or a gate (GIP) method. In Panel) type and may be directly disposed on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases. In addition, each gate driver integrated circuit (GDIC) may be implemented in a chip on film (COF) method mounted on a film connected to the display panel 110 .

The data driving circuit 130 receives a data signal from the controller 140 and converts the data signal into an analog data voltage Vdata. In addition, the data voltage Vdata is output to each data line DL according to the timing at which the scan signal is applied through the gate line GL so that each subpixel SP expresses the brightness according to the data signal. .

The data driving circuit 130 may include one or more source driver integrated circuits (SDICs).

Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

Each source driver integrated circuit (SDIC) may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method, or may be directly disposed on the display panel 110 , , in some cases, may be integrated and disposed on the display panel 110 . In addition, each source driver integrated circuit SDIC may be implemented in a chip-on-film (COF) method. In this case, each source driver integrated circuit SDIC is mounted on a film connected to the display panel 110 and , may be electrically connected to the display panel 110 through wires on the film.

The controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130 , and controls operations of the gate driving circuit 120 and the data driving circuit 130 .

The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the gate driving circuit 120 and the data driving circuit 130 through the printed circuit board, the flexible printed circuit, etc. .

The controller 140 causes the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and converts image data received from the outside to match the signal format used by the data driving circuit 130 , The converted data signal may be output to the data driving circuit 130 .

The controller 140 externally transmits various timing signals including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), and a clock signal (CLK) together with the image data. Receive from (eg host system).

The controller 140 may generate various control signals using various timing signals received from the outside and output them to the gate driving circuit 120 and the data driving circuit 130 .

For example, in order to control the gate driving circuit 120 , the controller 140 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE: Gate Output Enable) and the like, and output various gate control signals (GCS).

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits GDIC constituting the gate driving circuit 120 . The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits GDIC, and controls the shift timing of the scan signal. The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits GDIC.

In addition, in order to control the data driving circuit 130 , the controller 140 includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Source). Output Enable) and output various data control signals DCS.

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits SDIC constituting the data driving circuit 130 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source driver integrated circuits SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130 .

The display device 100 supplies various voltages or currents to the display panel 110 , the gate driving circuit 120 , the data driving circuit 130 , or the like, or a power management integrated circuit for controlling various voltages or currents to be supplied. may include

Each subpixel SP may be a region defined by the intersection of the gate line GL and the data line DL, and at least one circuit element including a light emitting element may be disposed thereon.

For example, when the display device 100 is a liquid crystal display device, the display panel 110 may include a liquid crystal layer. In addition, the arrangement of the liquid crystal may be adjusted according to the electric field formed by each of the plurality of sub-pixels SP, the brightness of the sub-pixels SP may be adjusted, and an image may be displayed.

As another example, when the display device 100 is an organic light emitting display device, an organic light emitting diode (OLED) and various circuit elements may be disposed in the plurality of subpixels SP. By controlling the current supplied to the organic light emitting diode (OLED) disposed in the subpixel (SP) by various circuit elements, each subpixel (SP) may display brightness corresponding to image data.

Alternatively, in some cases, a light emitting diode (LED) or a micro light emitting diode (μLED) may be disposed in the subpixel SP.

2 is a diagram illustrating an example of a circuit structure of a sub-pixel SP included in the display apparatus 100 according to embodiments of the present invention.

FIG. 2 shows an example of a circuit structure of a sub-pixel SP when the display apparatus 100 is an organic light emitting display apparatus, but embodiments of the present invention may be applied to other types of display apparatuses.

Referring to FIG. 2 , a light emitting device ED and a driving transistor DRT for driving the light emitting device ED may be disposed in the subpixel SP. In addition, at least one circuit element other than the light emitting element ED and the driving transistor DRT may be further disposed in the subpixel SP.

For example, as illustrated in FIG. 2 , a switching transistor SWT, a sensing transistor SENT, and a storage capacitor Cstg may be further disposed in the subpixel SP.

Accordingly, the example shown in FIG. 2 illustrates a 3T1C structure in which three thin film transistors and one capacitor are disposed in the subpixel SP in addition to the light emitting device ED as an example, but embodiments of the present invention are not limited thereto. does not Also, in the example shown in FIG. 2 , the thin film transistors are all N-type, but in some cases, the thin film transistors disposed in the sub-pixel SP may be P-type.

The switching transistor SWT may be electrically connected between the data line DL and the first node N1 .

The data voltage Vdata may be supplied to the subpixel SP through the data line DL. The first node N1 may be a gate node of the driving transistor DRT.

The switching transistor SWT may be controlled by a scan signal supplied to the gate line GL. The switching transistor SWT may control that the data voltage Vdata supplied through the data line DL is applied to the gate node of the driving transistor DRT.

The driving transistor DRT may be electrically connected between the driving voltage line DVL and the light emitting device ED.

The first driving voltage EVDD may be supplied to the third node N3 of the driving transistor DRT through the driving voltage line DVL. The first driving voltage EVDD may be a high potential driving voltage. The third node N3 may be a drain node or a source node of the driving transistor DRT.

The driving transistor DRT may be controlled by a voltage applied to the first node N1 . In addition, the driving transistor DRT may control the driving current supplied to the light emitting device ED.

The sensing transistor SENT may be electrically connected between the reference voltage line RVL and the second node N2 .

The reference voltage Vref may be supplied to the second node N2 through the reference voltage line RVL. The second node N2 may be a source node or a drain node of the driving transistor DRT.

The sensing transistor SENT may be controlled by a scan signal supplied to the gate line GL. The gate line GL controlling the sensing transistor SENT may be the same as or different from the gate line GL controlling the switching transistor SWT.

The sensing transistor SENT may control that the reference voltage Vref is applied to the second node N2 . Also, in some cases, the sensing transistor SENT may control sensing the voltage of the second node N2 through the reference voltage line RVL.

The storage capacitor Cstg may be electrically connected between the first node N1 and the second node N2 . The storage capacitor Cstg may maintain the data voltage Vdata applied to the first node N1 for one frame.

The light emitting device ED may be electrically connected between the second node N2 and a line to which the second driving voltage EVSS is supplied. The second driving voltage EVSS may be a low potential driving voltage.

The light emitting device ED may exhibit brightness according to a driving current supplied through the driving transistor DRT.

In this way, the display apparatus 100 may display an image while controlling the driving of the plurality of sub-pixels SP disposed on the display panel 110 . In order to improve the quality of an image displayed through the display panel 110 , the display apparatus 100 may be driven at a high driving frequency.

When the display apparatus 100 is driven at a high driving frequency, an effect of improving image quality may be provided, but an increase in the load of the data driving circuit 130 for driving the display panel 110 or an increase in the size of the controller 140 Problems such as

In embodiments of the present invention, the data driving circuit included in the display device 100 is changed by changing the scanning method of the data driving circuit 130 included in the display device 100 according to the image displayed by the display panel 110 . A method for reducing an increase in the load of 130 or an increase in the size of the controller 140 and enabling high-speed driving of the display apparatus 100 is provided.

For example, the data driving circuit 130 included in the display apparatus 100 may vary the number of times the data voltage Vdata is output during one frame period according to an input image.

In addition, varying the number of times the data driving circuit 130 outputs the data voltage Vdata during one frame period may be controlled by the controller 140 .

When the controller 140 receives image data and various control signals from the outside, it analyzes the image, and controls the data driving circuit 130 and the gate driving circuit 120 differently according to the analyzed image, thereby providing a constant value during high-speed driving. It is possible to reduce the load of the data driving circuit 130 while maintaining a high level of image quality.

In addition, it is possible to prevent an increase in the size of the controller 140 by reducing the amount of computation required for the controller 140 to process data.

3 is a diagram schematically illustrating an example of the configuration of the controller 140 included in the display apparatus 100 according to embodiments of the present invention.

Referring to FIG. 3 , the controller 140 includes, for example, an analysis unit 141 , a frame memory 142 , a still image determination unit 143 , a frame memory control unit 144 , a data processing unit 145 , and a gate control unit. (146).

The controller 140 may receive image data and various control signals from the host system 200 .

The analyzer 141 of the controller 140 may analyze an image based on image data received from the host system 200 and control a driving method for displaying the image in each frame.

For example, the analysis unit 141 may control an image driving method differently depending on whether the image according to the image data is a still image or a moving image. As another example, the analyzer 141 may control the driving method of the image differently according to a foreground region in which an object is displayed and a background region other than the foreground region in the image.

The frame memory 142 may store image data input from the host system 200 .

The still image determination unit 143 may determine a still image by comparing input/output data of the frame memory 142 .

The frame memory control unit 144 may control the frame memory 142 according to the analysis result of the analysis unit 141 . Data read by the data processing unit 145 from the frame memory 142 may vary according to the control of the frame memory control unit 144 .

The data processing unit 145 may output a data signal converted from image data and various control signals to the data driving circuit 130 according to the analysis result of the analysis unit 141 .

The gate control unit 146 may control the gate driving circuit 120 according to the analysis result of the analysis unit 141 .

The gate control unit 146 may control the gate driving circuit 120 to output a scan signal according to the method in which the data driving circuit 130 supplies the data voltage Vdata according to the output signal of the data processing unit 145 . have.

Here, the analysis unit 141 of the controller 140 may analyze the input image and reduce the number of times the data driving circuit 130 outputs the data voltage Vdata during one frame period according to the characteristics of the image. .

The analyzer 141 may reduce the load on the data driving circuit 130 by reducing the number of times the data voltage Vdata is output by the data driving circuit 130 without degrading the image quality.

Even when the display apparatus 100 is driven at a high speed such as 120 Hz or 240 Hz, for example, the load on the data driving circuit 130 is reduced by reducing the number of times the data voltage Vdata is output by the data driving circuit 130 . can do it

In addition, even if the length of the frame period is shortened due to high-speed driving, the charging rate of the display panel 110 may be improved due to a decrease in the number of times of outputting the data voltage Vdata.

The analyzer 141 may determine whether to decrease the number of times the data voltage Vdata is output according to whether the input image data is a still image. When the image data is a still image, only some gate lines GL are driven in each frame and the data voltage Vdata is supplied, thereby reducing the number of times the data voltage Vdata is output.

As another example, the analyzer 141 may adjust the number of times of outputting the data voltage Vdata during each frame period in consideration of the similarity of adjacent lines, a region in which an object is disposed, and the like.

The analyzer 141 may calculate a difference between adjacent lines and calculate a similarity score. The analysis unit 141 may generalize the calculated similarity score.

The analyzer 141 may detect an object. The analyzer 141 may detect an object by, for example, applying a high weight to a central region of the image, a region corresponding to a human skin color, or a bright region in the image data. The analysis unit 141 may detect an object and calculate a score for each line. The analysis unit 141 may generalize the calculated score for each line.

The analysis unit 141 may generate a new score by synthesizing the generalized similarity score.

The analysis unit 141 may select a priority according to the generated new score.

The analysis unit 141 may determine a driving method for displaying an image for each region according to priority.

For example, when the similarity of images displayed on adjacent lines is high and the priority is low as a static image, the analysis unit 141 may drive only some lines or drive a plurality of lines simultaneously.

Driving some lines may mean that only some gate lines GL are driven and the data voltage Vdata is supplied during one frame period.

Driving the plurality of lines simultaneously may mean driving two or more gate lines GL at the same time and supplying the data voltage Vdata.

The analysis unit 141 may individually drive each line for a high-priority region.

Driving each line individually may mean driving one gate line GL and supplying the data voltage Vdata.

The load on the data driving circuit 130 in the display device 100 performing high-speed driving is reduced by adjusting the number of times the data voltage Vdata is supplied during one frame period according to the analysis result of the analysis unit 141 . can do it

In addition, by varying the driving method of the data driving circuit 130 according to the characteristics of the image, it is possible to prevent image quality deterioration, increase the load of the data driving circuit 130 and increase the amount of computation of the controller 140 .

4A to 4C are diagrams illustrating examples of displaying an image according to a driving method when the display apparatus 100 according to embodiments of the present invention is driven at a high speed.

Referring to FIG. 4A , when the display apparatus 100 displays a still image, some lines may be driven during each frame period to display the image (Case A).

For example, the display apparatus 100 may display an image while driving an odd-numbered line during the first frame period. Also, the display apparatus 100 may display an image while driving an even-numbered line during the second frame period.

The image displayed during the first frame period and the image during the second frame period may be merged to be recognized as one image.

Since the display apparatus 100 drives at high speed and displays a still image, some lines may be driven during each frame period to display an image. In addition, since the number of times of outputting the data voltage Vdata in each frame period is reduced, the load of the data driving circuit 130 may be reduced.

In addition, since the number of times the gate driving circuit 120 outputs a scan signal in each frame period is also reduced, the load of the gate driving circuit 120 may also be reduced.

Referring to FIG. 4B , when the display apparatus 100 displays a moving picture, an image may be displayed while driving all lines during each frame period (Case B).

The display apparatus 100 drives all lines during one frame period, but may drive two or more lines with one data voltage Vdata.

For example, the scan signal may be simultaneously supplied to two adjacent lines. The data voltage Vdata may be supplied at a timing when the scan signal is supplied to the two lines.

Here, the data voltage Vdata may be a value corresponding to an average of image data corresponding to each of two adjacent lines. Alternatively, in some cases, a weight may be applied according to the characteristics of the image data corresponding to each of the two adjacent lines, and thus the value may be within a predetermined range from the average.

By simultaneously driving two adjacent lines and supplying the data voltage Vdata, the number of times of supplying the data voltage Vdata during one frame period may be reduced.

When the similarity of several adjacent lines in the moving picture displayed by the display apparatus 100 is very high, three or more lines may be simultaneously driven and the data voltage Vdata may be supplied.

Alternatively, a plurality of lines may be simultaneously driven in some areas, and one line may be individually driven in the remaining areas, based on a priority selected according to similarity for each area in the moving picture.

Referring to FIG. 4C , the display apparatus 100 may differently control the driving method of the data driving circuit 130 for each foreground region where an object is located and a background region other than the foreground region (Case C).

For example, when the display apparatus 100 displays an object in the center of an image, two lines may be simultaneously driven in an upper region and a lower region of the image corresponding to the background region, and the data voltage Vdata may be supplied. In addition, in the central region including the region where the object is located, one line is individually driven and the data voltage Vdata may be supplied.

Alternatively, a region in which one line is driven and a region in which a plurality of lines are driven may be adjusted based on the similarity of images indicated by adjacent lines, not the presence or absence of an object.

As described above, by differently controlling the number of lines driven for each region, the number of times the data voltage Vdata is output by the data driving circuit 130 can be reduced and image quality deterioration can be prevented.

The controller 140 may differently control the driving methods of the data driving circuit 130 and the gate driving circuit 120 for each frame period according to the characteristics of the image.

The controller 140 may, for example, adjust a driving method of the data driving circuit 130 by varying the control signal output to the data driving circuit 130 .

FIG. 5 is a diagram illustrating an example of a signal input or output from the display apparatus 100 when the display apparatus 100 is driven according to the driving method illustrated in FIG. 4A .

Referring to FIG. 5 , the controller 140 may receive an external data enable signal ODE from the host system 200 . The external data enable signal ODE is a signal input to the controller 140 for data output, and may refer to the aforementioned input data enable signal DE.

The controller 140 may output an internal data enable signal IDE to the data driving circuit 130 using the received external data enable signal ODE. The internal data enable signal IDE is a signal for controlling the data driving circuit 130 to output the data voltage Vdata, and may refer to the above-described source output enable signal SOE.

The controller 140 may receive a plurality of external data enable signals ODEs during the active period of one frame period. In addition, the controller 140 may output a plurality of internal data enable signals IDE during the active period of one frame period.

Here, the number or interval of the external data enable signals ODE received by the controller 140 during one frame period is the number or interval of the internal data enable signals IDE output by the controller 140 during one frame period. may be different.

The number of internal data enable signals IDE output by the controller 140 during one frame period may be smaller than the number of external data enable signals ODEs input during one frame period. For example, the controller 140 may receive 2N external data enable signals ODE and output N internal data enable signals IDE.

In addition, the interval Tb between the internal data enable signals IDE output by the controller 140 during one frame period may be greater than the interval Ta between the external data enable signals ODE received by the controller 140 during one frame period. have.

The data driving circuit 130 included in the display device 100 driven at high speed by outputting a number of internal data enable signals IDE that is smaller than the number of external data enable signals ODE received by the controller 140 . ) may reduce the number of times the data voltage Vdata is output during one frame period.

Also, since the interval between the internal data enable signals IDE increases, the charging time of the display panel 110 may increase.

Any one of the plurality of gate lines GL may be driven according to the timing at which the data voltage Vdata is output according to the internal data enable signal IDE output from the controller 140 .

For example, during one frame period, 2N 1/2, which is the number of external data enable signals ODE, N internal data enable signals IDE may be output. An odd-numbered gate line GL among the plurality of gate lines GL may receive a scan signal in response to the internal data enable signal IDE.

Accordingly, the odd-numbered gate line GL may be driven and the data voltage Vdata may be supplied during one frame period.

In addition, during the next frame period, N internal data enable signals IDE may be output, an even-numbered gate line GL among the plurality of gate lines GL may be driven, and the data voltage Vdata may be supplied.

The load of the data driving circuit 130 in the display device 100 performing high-speed driving is reduced by reducing the number of outputs of the internal data enable signal IDE and the number of the gate lines GL driven during each frame period. reduced, and an image can be displayed.

6 is a diagram illustrating an example of a signal input or output from the display apparatus 100 when the display apparatus 100 is driven according to the driving method illustrated in FIG. 4B .

Referring to FIG. 6 , the controller 140 may receive 2N external data enable signals ODEs from the host system 200 during one frame period.

When the display apparatus 100 performs high-speed driving, the length of one frame period may be short. Also, as the resolution increases, the number of external data enable signals ODEs input during one frame period increases, so that the interval between the external data enable signals ODEs may be small.

The controller 140 may output a smaller number of internal data enable signals IDE than the number of external data enable signals ODEs received in one frame period to the data driving circuit 130 . The interval between the internal data enable signals IDE may be greater than the interval between the external data enable signals ODE.

Two or more gate lines GL may be driven in response to each internal data enable signal IDE.

For example, two adjacent gate lines GL may be driven in response to one internal data enable signal IDE. Accordingly, the data voltage Vdata output according to the internal data enable signal IDE may be supplied to a line driven by the two gate lines GL.

Since two adjacent lines are driven with one data voltage Vdata, the number of times the data voltage Vdata is output during one frame period may decrease. In addition, two adjacent lines may be simultaneously driven to display an image.

Also, the number of lines driven for each region may be adjusted according to image characteristics.

7 is a diagram illustrating an example of a signal input or output from the display apparatus 100 when the display apparatus 100 is driven according to the driving method illustrated in FIG. 4C .

Referring to FIG. 7 , a smaller number of internal data enable signals IDE than the number of external data enable signals ODE input in one frame period may be output.

As indicated by parts 701 and 703 , the two gate lines GL may be driven in response to some of the plurality of internal data enable signals IDE.

As indicated by 702 , one gate line GL may be driven in response to the remaining internal data enable signals IDE among the plurality of internal data enable signals IDE.

As described above, an area in which a plurality of lines are simultaneously driven and an area in which one line is driven may be divided according to the similarity of images displayed by adjacent lines or the presence or absence of an object.

By adjusting the number of lines simultaneously driven for each region according to the characteristics of the image displayed by the display panel 110 , the number of data voltages Vdata output during one frame period can be reduced while maintaining image quality.

Also, when the number of lines simultaneously driven for each region is adjusted, the number of internal data enable signals IDE required to supply the data voltage Vdata may increase.

In this case, by reducing the interval between the internal data enable signals IDE, the number of internal data enable signals IDE output during the active period may be increased.

Alternatively, by outputting some of the plurality of internal data enable signals IDE during a blank period of one frame period, a reduction in the interval between the internal data enable signals IDE is prevented and internal data enable required for driving a display The number of signals IDE may be increased.

8 to 10 are diagrams illustrating another example of a signal input or output from the display apparatus 100 when the display apparatus 100 is driven at a high speed according to embodiments of the present invention.

Referring to FIG. 8 , the controller 140 may receive 2N external data enable signals ODEs in one frame period.

When the display apparatus 100 drives only some lines during one frame period as in Case A or drives a plurality of lines in response to one internal data enable signal IDE as in Case B, the data voltage Vdata The number of internal data enable signals IDE required for output of may be N.

As in Case C, when some regions drive a plurality of lines and a remaining region drives a single line during one frame period, the number of internal data enable signals IDE required to output the data voltage Vdata may be (N+α).

Some of the (N+α) internal data enable signals IDE may be output in a blank period of one frame period.

The gate line GL may be driven in response to the internal data enable signal IDE output during the blank period.

There may be one gate line GL driven in response to one internal data enable signal IDE output during the blank period, or there may be more than one gate line GL.

Since the internal data enable signal IDE is output during the blank period to increase the internal data enable signal IDE, a reduction in the interval between the internal data enable signals IDE can be prevented.

While the number of times the data driving circuit 130 outputs the data voltage Vdata in one frame period is reduced, the interval at which the data voltage Vdata is output may be prevented from being reduced.

Accordingly, the load of the data driving circuit 130 may be reduced and the charging time may be increased.

In addition, by adjusting the number of lines simultaneously driven for each region according to the characteristics of the image, the increase in the load on the data driving circuit 130 in the display device 100 performing high-speed driving is reduced and image quality above a constant level is provided. can

Also, when an increase in the internal data enable signal IDE is required according to the characteristics of the image, the interval between the internal data enable signals IDE may be reduced.

Referring to FIG. 9 , when the controller 140 receives 2N external data enable signals ODEs in one frame period, in Case A or Case B, the controller 140 receives N internal data enable signals in one frame period. An enable signal IDE may be output.

The load of the data driving circuit 130 may be reduced by driving the display apparatus 100 performing high-speed driving according to the N internal data enable signals IDE.

As in Case C, when adjusting the number of lines driven for each region, the controller 140 may output (N+β) internal data enable signals IDE in one frame period. Here, β may be a value greater than α described with reference to FIG. 8 .

When the number of lines driven for each region is adjusted, the number of required internal data enable signals IDE may increase when the driving ratio of one line increases according to the characteristics of the image.

The controller 140 may output the internal data enable signal IDE by reducing the interval between the internal data enable signals IDE because the period may be insufficient even if the partial internal data enable signal IDE is output during the blank period.

For example, the interval between the internal data enable signals IDE output by the controller 140 may be Tc. In case of Case A or Case B, Tc may be smaller than the interval Tb between the internal data enable signals IDE output by the controller 140 .

Also, Tc may be greater than the interval Ta between the external data enable signals ODE received by the controller 140 .

Even if the interval between the internal data enable signals IDE is reduced, since the interval between the external data enable signals ODE is larger than the interval between the internal data enable signals IDE, the charging time of the display panel 110 may increase.

One or more lines may be driven according to each of the (N+β) internal data enable signals IDE, and the data voltage Vdata may be supplied according to each of the internal data enable signals IDE. .

In addition, at least one line is driven according to the internal data enable signal IDE output during the blank period, and the data driving circuit 130 outputs the data voltage Vdata according to the internal data enable signal IDE. can

Since the number (N+β) of the internal data enable signals IDE is smaller than the number of 2N external data enable signals ODE, the data driving circuit ( 130) may reduce the number of times the data voltage Vdata is output.

By outputting the internal data enable signal IDE during the blank period to secure the supply timing of the data voltage Vdata, an image may be displayed according to the characteristics of the image. In addition, since the number of times the data voltage Vdata is output is reduced and the interval at which the data voltage Vdata is output is maintained at a predetermined level or more, an increase in the load of the data driving circuit 130 due to high-speed driving can be reduced.

In addition, embodiments of the present invention may be applied to a case where the driving frequency of the display apparatus 100 is changed and display driving is performed.

Referring to FIG. 10 , the display device 100 may perform low-speed driving or high-speed driving according to the driving state or driving period of the display device 100 . The low-speed driving and the high-speed driving may have a relative meaning, and the display apparatus 100 may be driven at the first driving frequency or the second driving frequency, for example.

The display apparatus 100 may be driven at a relatively low first driving frequency, such as 30 Hz or 60 Hz, for example.

When the display apparatus 100 is driven at the first driving frequency, as shown in frame A of FIG. 10 , display driving may be performed.

The controller 140 may receive 2N external data enable signals ODE and output 2N internal data enable signals IDE in one frame period.

Since the first driving frequency is relatively low, the length of one frame period may be relatively long.

Accordingly, the controller 140 may perform display driving while maintaining the same number of external data enable signals ODE and internal data enable signals IDE.

The display apparatus 100 may be driven at a second driving frequency greater than the first driving frequency according to a driving state or driving period. The second driving frequency may be, for example, a relatively high frequency such as 120Hz or 240Hz.

When the display apparatus 100 is driven at the second driving frequency, as shown in frame B of FIG. 10 , display driving may be performed.

The controller 140 may receive 2N external data enable signals ODEs in one frame period and may output N internal data enable signals IDE that are less than 2N.

Since the display driving is performed according to the N internal data enable signals IDE, the number of times the data driving circuit 130 outputs the data voltage Vdata in one frame period may be reduced.

And, as in the above example, by driving different lines for each frame or driving a plurality of lines in response to one internal data enable signal IDE, the internal data enable signal IDE is reduced and a constant level of the internal data enable signal IDE is reduced. quality can be maintained.

The number and interval of the internal data enable signals IDE are adjusted according to the period during which the display apparatus 100 performs low-speed driving and the period during which high-speed driving is performed, thereby preventing degradation of the display apparatus 100 and performing high-speed driving. driving can be performed.

According to the above-described embodiments of the present invention, by adjusting the number of internal data enable signals IDE output by the controller 140 in response to the external data enable signals ODE, the data driving circuit ( An increase in the load of 130 and an increase in the amount of computation of the controller 140 can be prevented.

By adjusting the number of lines driven in response to the internal data enable signal IDE according to the characteristics of the image, a certain level of image quality may be provided.

In addition, when the required internal data enable signal IDE increases, some internal data enable signals IDE are output during the blank period, thereby minimizing reduction in the interval between the internal data enable signals IDE and driving the display. can be done

Accordingly, while preventing an increase in the load of the data driving circuit 130 or an increase in the size of the controller 140 due to high-speed driving, the image quality of the display device 100 performing high-speed driving can be maintained at a certain level or higher.

The above description is merely illustrative of the technical spirit of the present invention, and various modifications and variations will be possible without departing from the essential characteristics of the present invention by those skilled in the art to which the present invention pertains. In addition, since the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device 110: display panel
120: gate driving circuit 130: data driving circuit
140: controller 141: analysis unit
142: frame memory 143: still image determination unit
144: frame memory control unit 145: data processing unit
146: gate control unit 200: host system

Claims (20)

a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels are disposed;
a data driving circuit supplying a data voltage to the plurality of data lines; and
a controller for controlling the data driving circuit;
The controller is
receiving a plurality of external data enable signals from the outside, and outputting a plurality of internal data enable signals to the data driving circuit;
At least one of the number and interval at which the plurality of internal data enable signals are output during one frame period is different from at least one of the number and interval at which the plurality of external data enable signals are input during the one frame period.
According to claim 1,
The number of times that the plurality of internal data enable signals are output during the one frame period is smaller than the number of times that the plurality of external data enable signals are input.
According to claim 1,
An interval at which the plurality of internal data enable signals are output during the one frame period is greater than an interval at which the plurality of external data enable signals are input.
According to claim 1,
At least one of the plurality of internal data enable signals is output in a blank period included in the one frame period.
5. The method of claim 4,
A display device in which a scan signal is supplied to at least one of the plurality of gate lines in response to the at least one internal data enable signal output during the blank period.
5. The method of claim 4,
A display device in which the plurality of internal data enable signals are output in a period excluding the blank period during a first frame period, and some of the plurality of internal data enable signals are output in the blank period during a second frame period.
7. The method of claim 6,
An interval at which the plurality of internal data enable signals are output during the second frame period is smaller than an interval at which the plurality of internal data enable signals are output during the first frame period.
8. The method of claim 7,
An interval at which the plurality of internal data enable signals are output during the second frame period is greater than an interval at which the plurality of external data enable signals are input during the second frame period.
According to claim 1,
a scan signal is supplied to one of the plurality of gate lines in correspondence with each of the plurality of internal data enable signals;
A gate line to which the scan signal is supplied in a first frame period among successive frame periods and a gate line to which the scan signal is supplied in a second frame period are different from each other.
According to claim 1,
a scan signal is simultaneously supplied to at least two of the plurality of gate lines in correspondence with each of the plurality of internal data enable signals;
The two or more gate lines to which the scan signal is simultaneously supplied are located adjacent to each other.
According to claim 1,
During the one frame period, a scan signal is supplied to one of the plurality of gate lines in correspondence with some of the plurality of internal data enable signals;
A display device in which a scan signal is simultaneously supplied to at least two of the plurality of gate lines in correspondence with the rest of the plurality of internal data enable signals.
a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels are disposed;
a data driving circuit supplying a data voltage to the plurality of data lines; and
a controller for controlling the data driving circuit;
The controller is
receiving a plurality of external data enable signals from the outside, and outputting a plurality of internal data enable signals to the data driving circuit;
The number and interval at which the plurality of internal data enable signals are output during one frame period during a period in which the display panel is driven at the first driving frequency are the same as the number and interval at which the plurality of external data enable signals are input;
In a period in which the display panel is driven at the second driving frequency, at least one of the number and interval at which the plurality of internal data enable signals are output during the one frame period is the number and interval at which the plurality of external data enable signals are input a display device different from at least one of
13. The method of claim 12,
The second driving frequency is greater than the first driving frequency.
14. The method of claim 13,
In a period in which the display panel is driven at the second driving frequency, the number of times the plurality of internal data enable signals are output during the one frame period is smaller than the number of times the plurality of external data enable signals are input.
14. The method of claim 13,
In a period in which the display panel is driven at the second driving frequency, an interval at which the plurality of internal data enable signals are output during the one frame period is greater than an interval at which the plurality of external data enable signals are input.
14. The method of claim 13,
During a period in which the display panel is driven at the second driving frequency, at least one of the plurality of internal data enable signals is output in a blank period included in the one frame period.
17. The method of claim 16,
A display device in which a scan signal is supplied to at least one of the plurality of gate lines in response to the at least one internal data enable signal output during the blank period.
A data driving circuit for receiving a plurality of internal data enable signals and outputting a data voltage during one frame period, the data driving circuit comprising:
The data driving circuit outputs the data voltage corresponding to each of the plurality of internal data enable signals, and at least one of the plurality of internal data enable signals is input in a blank period of the one frame period.
19. The method of claim 18,
A data driving circuit wherein the number of times the plurality of internal data enable signals are received during one frame period is different from the number of times the plurality of internal data enable signals are received during another frame period.
A controller for receiving a plurality of external data enable signals from the outside and outputting a plurality of internal data enable signals to a data driving circuit, the controller comprising:
At least one of the number and interval at which the plurality of internal data enable signals are output during one frame period is different from at least one of the number and interval at which the plurality of external data enable signals are input during the one frame period.

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